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Verilog HDL Module 1 Notes

This document provides information about a Verilog HDL course offered in the Electronics and Communication Engineering department at SAI Vidya Institute of Technology. The course is offered in the 5th semester as part of the Choice Based Credit System. The first module covers an overview of digital design with Verilog HDL, including the evolution of CAD tools and HDLs, typical HDL design flows, and why Verilog HDL is used. It also discusses hierarchical modeling concepts like top-down and bottom-up design methodologies. The referenced study material is a book on Verilog HDL by Samir Palnitkar. The document is compiled by an assistant professor in the ECE department who provides contact details.

Uploaded by

Abdullah Gubbi
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
610 views

Verilog HDL Module 1 Notes

This document provides information about a Verilog HDL course offered in the Electronics and Communication Engineering department at SAI Vidya Institute of Technology. The course is offered in the 5th semester as part of the Choice Based Credit System. The first module covers an overview of digital design with Verilog HDL, including the evolution of CAD tools and HDLs, typical HDL design flows, and why Verilog HDL is used. It also discusses hierarchical modeling concepts like top-down and bottom-up design methodologies. The referenced study material is a book on Verilog HDL by Samir Palnitkar. The document is compiled by an assistant professor in the ECE department who provides contact details.

Uploaded by

Abdullah Gubbi
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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SAI VIDYA INSTITUTE OF TECHNOLOGY

(Affiliated to VTU, Belgaum, Approved by AICTE, New Delhi and Govt. of Karnataka)
Rajanukunte, Doddaballapur Road, Bangalore-560064
Tel: 080-2846 8196, Fax: 2846 8193 / 98, Web: www.svit.co.in

DEPARTMENT
OF
ELECTRONICS AND COMMUNICATION ENGINEERING

Verilog HDL (15EC53)


(As per Choice based Credit System (CBCS) Scheme)
VTH SEMESTER

MODULE-1

Syllabus:

Overview of Digital Design with Verilog HDL Evolution of CAD,


emergence of HDLs, typical HDL-flow, why Verilog HDL?, trends in
HDLs. Hierarchical Modelling Concepts Top-down and bottom-up
design methodology, differences between modules and module
instances, parts of a simulation, design block, stimulus block.

Study Material Referred:

 Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and


Synthesis”, Pearson Education, Second Edition.

Compiled By:
Prashanth N
Assistant professor
Dept. of ECE, SVIT
Mail : Prashanth09827@gmail.com
Prashanth.n@saividya.ac.in

Phone: +91-9538766317
   

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