Logic Design

Dinesh Sharma
Microelectronics group
EE Department, IIT Bombay

August 10, 2017

2
Contents

1 Beyond Static CMOS 7

1.1 Pseudo nMOS Design Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.1 Static Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1.2 Noise margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1.3 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1.4 Pseudo nMOS design Flow . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.5 Conversion of pseudo nMOS Inverter to other logic . . . . . . . . . . . 11
1.2 Complementary Pass gate Logic . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.1 Basic Multiplexer Structure . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.2 Logic Design using CPL . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.3 Buffer Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3 Cascade Voltage Switch Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.4 Dynamic Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.1 Problem with Cascading CMOS dynamic logic . . . . . . . . . . . . . . 18
1.4.2 Four Phase Dynamic Logic . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4.3 Domino Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.4.4 Zipper logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3
4 CONTENTS
List of Figures

1.1 ‘high’ to ‘low’ transition on the output . . . . . . . . . . . . . . . . . . . . . . 10

1.2 Pseudo NMOS implementation of A.B + C.(D + E) . . . . . . . . . . . . . . . 12
1.3 Basic Multiplexer with logic restoring inverters . . . . . . . . . . . . . . . . . . 13
1.4 Implementation of XOR and XNOR by CPL logic. . . . . . . . . . . . . . . . 13
1.5 Implementation of (a) AND-NAND and (b) OR-NOR functions using comple-
mentary passgate logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.6 High leakage current in inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.7 Pull up pMOS to avoid leakage in the inverter . . . . . . . . . . . . . . . . . . 15
1.8 Problem with a low to high transition on the output . . . . . . . . . . . . . . . 15
1.9 Pseudo-nMOS NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.10 Pseudo-nMOS OR from complemented inputs . . . . . . . . . . . . . . . . . . 16
1.11 OR-NOR implementation in Cascade Voltage Switch Logic . . . . . . . . . . . 17
1.12 CMOS dynamic gate to implement (A + B).C. . . . . . . . . . . . . . . . . . . 18
1.13 Dynamic gate for (A + B).C cascaded with an inverter. . . . . . . . . . . . . . 18
1.14 CMOS 4 phase dynamic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.15 CMOS 4 phase dynamic logic drive constraints . . . . . . . . . . . . . . . . . . 20
1.16 CMOS domino logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.17 Zipper logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5
6 LIST OF FIGURES
Chapter 1

Beyond Static CMOS

1.1 Pseudo nMOS Design Style

CMOS design style ensures that the logic consumes no static power. This is because the pull
down and pull up networks are never ‘on’ simultaneously. However, this requires that signals
have to be routed to the n pull down network as well as to the p pull up network. This means
that the load presented to every driver is high. This fact is exacerbated by the fact that n
and p channel transistors cannot be placed close together as these are in different wells which
have to be kept well separated in order to avoid latchup.

Pseudo nMOS design style reduces dynamic power (by reducing capacitive loading) at
the cost of having non-zero static power by replacing the pull up network by a single pMOS
transistor with its gate terminal grounded. The pseudo nMOS inverter is shown below.

Vdd

Out

in

Gnd

Notice that since the pMOS is not driven by signals, it is always ‘on’. The effective gate
voltage seen by the pMOS transistor is VDD . Thus the overvoltage on the p channel gate is
always VDD - VT p . When the nMOS is turned ‘on’, a direct path between supply and ground
exists and static power will be drawn.

7
8 CHAPTER 1. BEYOND STATIC CMOS

1.1.1 Static Characteristics

As we sweep the input voltage from ground to VDD , we encounter the following regimes of
operation:

nMOS ‘off’
This is the case when the input voltage is less than VT n . The output is ‘high’ and no current
is drawn from the supply.

nMOS saturated, pMOS linear

As the input voltage is raised above VT n , we enter this region. The input voltage is assumed to
be sufficiently low that the output voltage exceeds the saturation voltage Vi − VT n . Normally,
this voltage will be higher than VT p , so the p channel transistor is in linear mode of operation.
Equating currents through the n and p channel transistors, we get

1 Kn
 
Kp (VDD − VT p )(VDD − Vo ) − (VDD − Vo )2 = (Vi − VT n )2 (1.1)
2 2
defining V1 ≡ VDD − Vo and V2 ≡ VDD − VT p , we get

1 2 β
V1 − V2 V1 + (Vi − VT n )2 = 0 (1.2)
2 2
with solutions q
V1 = V2 ± V22 − β(Vi − VT n )2
substituting the values of V1 and V2 and choosing the sign which puts Vo in the correct range,
we get q
Vo = VT p + (VDD − VT p )2 − β(Vi − VT n )2 (1.3)

nMOS linear, pMOS linear

As the input voltage is increased, the output voltage will decrease in accordance with equation(1.3).
At some point, the output voltage will fall below Vi − VT n . It can be shown that this will
happen when q
VT p + VT2p + (β + 1)VDD (VDD − 2VT p )
Vi > VT n + .
β+1
The nMOS is now in its linear mode of operation. We shall not derive the expression for the
output voltage in this mode of operation in the discussion here. The solution is straightfor-
ward, though algebraically tedious.
1.1. PSEUDO NMOS DESIGN STYLE 9

nMOS linear, pMOS saturated

As the input voltage is raised still further, the output voltage will fall below VT p . The pMOS
transistor is now in saturation regime. Equating currents, we get
1 Kp
 
Kn (Vi − VT n )Vo − Vo2 = (VDD − VT p )2
2 2
which gives
1 2 (VDD − VT p )2
Vo − (Vo − VT n )Vo +
2 2β
This can be solved to get
q
Vo = (Vi − VT n ) − (Vi − VT n )2 − (VDD − VT p )2 /β (1.4)

1.1.2 Noise margins

As in the case of CMOS inverter, we find points on the transfer curve where the slope is -1.

When the input is low and output high, we should use eq(1.3). Differentiating this equation
with respect to Vi and setting the slope to -1, we get
VDD − VT p
ViL = VT n + q (1.5)
β(β + 1)

and s
β
VoH = VT p + (VDD − VT p ) (1.6)
β+1
When the input is high and the output low, we use eq(1.4). Again, differentiating with respect
to Vi and setting the slope to -1, we get
2
ViH = VT n + √ (VDD − VT p ) (1.7)
3β
and
(VDD − VT p )
VoL = √ (1.8)
3β
To make the output ‘low’ value lower than VT n , we get the condition
2
1 VDD − VT p

β>
3 VT n
This condition on values of β places a requirement on the ratios of widths of n and p channel
transistors. The logic gates work properly only when this equation is satisfied. Therefore this
10 CHAPTER 1. BEYOND STATIC CMOS

kind of logic is also called ‘ratioed logic’. In contrast, CMOS logic is called ratioless logic
because it does not place any restriction on the ratios of widths of n and p channel transistors
for static operation. The noise margin for pseudo nMOS can be determined easily from the
expressions for ViL , VoL , ViH , VoH .

1.1.3 Dynamic characteristics

In the sections above, we have derived the behaviour of a pseudo nMOS inverter in static
conditions. In the sections below, we discuss the dynamic behaviour of this inverter.

Rise Time
When the input is low and the output rises from ‘low’ to ‘high’, the nMOS is off. The situation
is identical to the charge up condition of a CMOS gate with the pMOS being biased with its
gate at 0V. This gives
" #
C 2VT p VDD + VoH − 2VT p
τrise = + ln (1.9)
Kp (VDD − VT p ) VDD − VT p VDD − VoH

Fall Time
Analytical calculation of fall time is complicated by the fact that the pMOS load continues to
dump current in the output node, even as the nMOS tries to discharge the output capacitor.

Vdd

Out

in

Gnd

Figure 1.1: ‘high’ to ‘low’ transition on the output

Thus the nMOS should sink the discharge current as well as the drain current of the
pMOS transistor. We make the simplifying assumption that the pMOS current remains
constant at its saturation value through the entire discharge process. (This will result in a
slightly pessimistic value of discharge time). Then,
Kp
Ip = (VDD − VT p )2
2
1.1. PSEUDO NMOS DESIGN STYLE 11

. We can write the KCL equation at the output node as:

dVo
In − Ip + C =0
dt
which gives
τf all VoL dVo
Z
=−
C VDD In − Ip
We define V1 ≡ Vi − VT n and V2 ≡ VDD − VT p . The integration range can be divided into two
regimes. nMOS is saturated when V1 ≤ Vo < VDD and is in linear regime when VoL < Vo < V1 .
Therefore,
τf all dVo dVo
Z V1 Z VoL
=− 1 −
C 2
VDD 2 Kn V1 − Ip V1 Kn (V1 Vo − 21 Vo2 ) − Ip
so,
τf all VDD − V1 Z V1
dVo
= 1 2
+ 1
C K V − Ip
2 n 1 VoL Kn (V1 Vo − 2 Vo2 ) − Ip

1.1.4 Pseudo nMOS design Flow

We design the basic inverter first and then map the inverter design to other logic circuits.
The load device size is calculated from the rise time. From eq. 1.9 we have
" #
C 2VT p VDD + VoH − 2VT p
τrise = + ln
Kp (VDD − VT p ) VDD − VT p VDD − VoH
Given a value of τrise , operating voltages and technological constants, Kp and hence, the ge-
ometry of the p channel transistor can be determined.

Geometry of the n channel transistor in the reference inverter design can be determined
from static considerations. Using eq. 1.4, the output ‘low’ level is given by:
q
Vo = (Vi − VT n ) − (Vi − VT n )2 − (VDD − VT p )2 /β

If the desired value of the output ‘low’ level is given, we can calculate β. But β ≡ Kn /Kp and
Kp is already known. This evaluates Kn and hence, the geometry of the n channel transistor.

1.1.5 Conversion of pseudo nMOS Inverter to other logic

Once the basic pseudo nMOS inverter is designed, other logic gates can be derived from
it. The procedure is the same as that for CMOS, except that it is applied only to nMOS
transistors. The p channel transistor is kept at the same size as that for an inverter.
The logic is expressed as a sum of products with a bar (inversion) on top. For every ‘.’ in
the expression, we put the corresponding n channel transistors in series and for every ‘+’, we
12 CHAPTER 1. BEYOND STATIC CMOS

Vdd

Out

A C

D
B E

Figure 1.2: Pseudo NMOS implementation of A.B + C.(D + E)

put the n channel transistors in parallel. We scale the transistor widths up by the number of
devices put in series. The geometries are left untouched for devices put in parallel. Fig.1.2
shows the implementation of A.B + C.(D + E) in pseudo NMOS logic design style.

1.2 Complementary Pass gate Logic

This logic family is based on multiplexer logic.

Given a Boolean function F(x1, x2, . . . , xn), we can express it as:

F (x1, x2, . . . , xn) = xi · f 1 + xi · f 2

where f1 and f2 are reduced expressions for F with xi forced to ‘1’ and ‘0’ respectively. Thus,
F can be implemented with a multiplexer controlled by xi which selects f1 or f2 depending on
xi. f1 and f2 can themselves be decomposed into simpler expressions by the same technique.
To implement a multiplexer, we need both xi and xi. Therefore, this logic family needs
all inputs in true as well as in complement form. In order to drive other gates of the same
type, it must produce the outputs also in true and complement forms. Thus each signal is
carried by two wires. This logic style is called “Complementary Passgate Logic” or CPL for
short.

1.2.1 Basic Multiplexer Structure

Pure passgate logic contains no ‘amplifying’ elements. Therefore, it has zero or negative
noise margin. (Each logic stage degrades the logic level). Therefore, multiple logic stages
cannot be cascaded. We shall assume that each stage includes conventional CMOS inverters
to restore the logic level. Ideally, the multiplexer should be composed of complementary pass
1.2. COMPLEMENTARY PASS GATE LOGIC 13

xi xi
F
f1
F
f2
f1 F
F
f2
Figure 1.3: Basic Multiplexer with logic restoring inverters

gate transistors. However, we shall use just n channel transistors as switches for simplicity.
This gives us the multiplexer structure shown in fig.1.3.

1.2.2 Logic Design using CPL

Since both true and complement outputs are generated by CPL, we do not need separate gates
for AND and NAND functions. The same applies to OR-NOR, and XOR-XNOR functions.

To take an example, let us consider the XOR-XNOR functions. Because of the inverter,

A A
A+B
B
A+B
B
A+B
B
A+B
B
XOR−XNOR
Figure 1.4: Implementation of XOR and XNOR by CPL logic.

the multiplexer for the XOR output first calculates the XNOR function given by A.B + A.B.
14 CHAPTER 1. BEYOND STATIC CMOS

If we put A =‘1’, this reduces to B and for A = ‘0’, it reduces to B. Similarly, for the XNOR
output, we generate the XOR expression = A.B + A.B which will be inverted by the logic
level restoring inverter. The expression reduces to B for A = ‘1’ and to B for A = ‘0’. This
leads to an implementation of XOR-XNOR as shown in fig.1.4

A A A A
A.B
B A+B
A
A.B A+B
A B

B A.B A+B
A
A.B A+B
A B
AND−NAND OR−NOR

Figure 1.5: Implementation of (a) AND-NAND and (b) OR-NOR functions using comple-
mentary passgate logic.

Implementation of AND and OR functions is similar. In case of AND, the multiplexer

should output A.B to be inverted by the buffer. This reduces to B when A =‘1’. When A
= ‘0’, it evaluates to 1 = A. For NAND output, the multiplexer should output A.B, which
evaluates to B for A = ‘1’ and to ‘0’ (or A) when A = ‘0’.

1.2.3 Buffer Leakage Current

The circuit configuration described above uses nMOS multiplexers. This limits the ‘high’

xi xi
f1
y=F
F
f2

Figure 1.6: High leakage current in inverter

output of the multiplexer (node y - which is the input for the inverter) to VDD - VT n . Conse-
quently, the pMOS transistor in the buffer inverter never quite turns off. This results in static
power consumption in the inverter. This can be avoided by adding a pull up pMOS as shown
1.2. COMPLEMENTARY PASS GATE LOGIC 15

xi xi
f1
y=F
F
f2

Figure 1.7: Pull up pMOS to avoid leakage in the inverter

in fig. 1.7. When the multiplexer output (y) is ‘low’, the inverter output is high. The pMOS
is therefore off and has no effect. When the multiplexer output goes ‘high’, the inverter input
charges up, the output starts falling and turns the pMOS on. Now, as the multiplexer output
(y) approaches VDD - VT n , the nMOS switch in the multiplexer turns off. However, the pMOS
pull up remains ‘on’ and takes the inverter input all the way to VDD . This avoids leakage in
the inverter.

However, this solution brings up another problem. Consider the equivalent circuit when
the inverter output is ‘low’ and the pMOS is ‘on’. Now if the multiplexer output wants to go

Vdd
0 ->1 ‘0’

‘0’ ‘1’ ‘0’

Figure 1.8: Problem with a low to high transition on the output

‘low’, it has to fight the pMOS pullup - which is trying to keep this node ‘high’.

In fact, the multiplexer n transistor and the pull up p transistor constitute a pseudo
nMOS inverter. Therefore, the multiplexer output cannot be pulled low unless the transistor
geometries are appropriately ratioed.
16 CHAPTER 1. BEYOND STATIC CMOS

1.3 Cascade Voltage Switch Logic

We can understand this logic configuration as an attempt to improve pseudo-nMOS logic
circuits. Consider the NOR gate shown below: Static power is consumed by this NOR circuit

Vdd

Out

A B

Figure 1.9: Pseudo-nMOS NOR

whenever the output is ‘LOW’. This happens when A OR B is TRUE. We wish that the
pMOS could be turned off for just this combination of inputs.

To turn the pMOS transistor off, we need to apply a ‘HIGH’ voltage level to its gate
whenever A OR B is true. This obviously requires an OR gate. Non-inverting gates cannot
be made in a single stage. However, We can create the OR function by using a NAND of
A and B as shown in figure 1.10. But then what about the pMOS drive of this circuit?

Vdd

Out
A

Figure 1.10: Pseudo-nMOS OR from complemented inputs

We want to turn the pMOS of this OR circuit off when both A and B are ‘HIGH’; i.e.
when A = B = 0. This means we would like to turn the pMOS of this circuit off when the
NOR of A and B is ‘TRUE’.
1.4. DYNAMIC LOGIC 17

Vdd

Out Out

A B B

Figure 1.11: OR-NOR implementation in Cascade Voltage Switch Logic

But we already have this signal as the output of the first (NOR) circuit! So the two
circuits can drive each other’s pMOS transistors and avoid static power consumption. This
kind of logic is called Cascade Voltage Switch Logic (CVSL). It can use any network f and its
complementary network f in the two cross-coupled branches. The complementary network is
constructed by changing all series connections in f to parallel and all parallel connections to
series, and complementing all input signals.

CVSL shares many characteristics with static CMOS, CPL and pseudo-nMOS.

• Like CMOS static logic, there is no static power consumption.

• Like CPL, this logic requires both True and Complement signals. It also provides both
True and complement outputs. (Dual Rail Logic).

• Like pseudo nMOS, the inputs present a single transistor load to the driving stage.

• The circuit is self latching. This reduces ratioing requirements.

1.4 Dynamic Logic

In this style of logic, some nodes are required to hold their logic value as a charge stored on a
capacitor. These nodes are not connected to their ‘drivers’ permanently. The ‘driver’ places
the logic value on them, and is then disconnected from the node. Due to leakage etc., the
logic value cannot be held indefinitely. Dynamic circuits therefore require a minimum clock
frequency to operate correctly. Use of dynamic circuits can reduce circuit complexity and
power consumption substantially, compared to pseudo NMOS. When the clock is low, pMOS
is on and the bottom nMOS is off. The output is ‘pre-charged’ to ‘1’ unconditionally. When
the clock goes high, the pMOS turns off and the bottom nMOS comes on. The circuit then
conditionally discharges the output node, if (A+B).C is TRUE. This implements the function
(A + B).C.
18 CHAPTER 1. BEYOND STATIC CMOS

Vdd

Out

A B

C CL

Ck

Figure 1.12: CMOS dynamic gate to implement (A + B).C.

1.4.1 Problem with Cascading CMOS dynamic logic

The dynamic circuit described above can run into problems when several dynamic gates are
cascaded. Consider the case when the circuit described in Fig. 1.12 is followed by an inverter.
Let us take two cases – when (A+B).C is FALSE and when it is TRUE.

Vdd

A B X Out

C CL

Ck

Figure 1.13: Dynamic gate for (A + B).C cascaded with an inverter.

When (A+B).C is FALSE, There is no problem X pre-charges to ‘1’ and remains at ‘1’.
1.4. DYNAMIC LOGIC 19

Therefore the inverter sees the correct logic value at its input all the time and discharges the
output to ‘0’, which is the expected output.

Ck

(A+B).C = FALSE
X

Out

However, When (A+B).C is TRUE, there is a problem.

The correct value for X is now ‘0’. After the pre-charge cycle, X takes some time to discharge

Ck

(A+B).C = TRUE

Out

to ‘0’. So for some time after pre-charge, its output is held at the wrong value of ‘1’ During
this time, charge placed on the output leaks away as the input to nMOS of the inverter is not
‘0’. This can lead to a wrong evaluation of the logic function!

1.4.2 Four Phase Dynamic Logic

The problem can be solved by introducing additional clock phases. We use different phases
for pre-charge, evaluation and for holding a valid output. Now we can sample the previous
stage only in the clock phase when evaluation is complete and it is valid.

For the circuit shown in Fig. 1.14, we have a 4 phase clock. Combined clock signals of the
type Ckmn are generated as required. Ckmn is high during the m and n phases of the clock.
Now, for the gate shown in the figure,

1. In phase 1, node P is pre-charged.

20 CHAPTER 1. BEYOND STATIC CMOS

Ck1
Ck2
Ck3
Ck4

Ck23
P Out

A B

C
Ck12

Figure 1.14: CMOS 4 phase dynamic logic

2. In phase 2, P as well as the output are pre-charged.

3. In phase 3, The gate evaluates.

4. In phases 4 and 1, the output is isolated from the driver and remains valid.

This is called a type 3 gate. It evaluates in phase 3 and is valid in phases 4 and 1. Similarly,
we can have type 4, type 1 and type 2 gates. A type 3 gate can drive a type 4 or a type 1

Drive Sequences

Type 1 Type 2

Type 4 Type 3

Figure 1.15: CMOS 4 phase dynamic logic drive constraints

gate. Similarly, type 4 will drive types 1 and 2; type 1 will drive types 2 and 3; and type 2
1.4. DYNAMIC LOGIC 21

will drive types 3 and 4. We can use a 2 phase clock if we stick to type 1 and type 3 gates
(or type 2 and type 4 gates) as these can drive each other.

1.4.3 Domino Logic

A B

C
Ck

Figure 1.16: CMOS domino logic

Another way to eliminate the problem with cascading logic stages is to use a static in-
verter after the CMOS dynamic gate. Recall that cascading of dynamic CMOS stage causes
problems because the output is pre-charged to VDD . If the final value of a stage is meant to
be zero, the next stage nMOS to which this output is connected erroneously sees a one till
the pre-charged output is brought down to zero. During this time, it ends up discharging its
own pre-charged output, which it was not supposed to do.

If an inverter is added, the output is held ‘low’ before logic evaluation. Now, if the final
output of this gate is ‘0’, there is no problem anyway. If the final output was supposed be
’1’, the next stage is erroneously held at zero for some time. However, this does not result in
a false evaluation by the next stage. The only effect it can have is that the next stage starts
its evaluation a little later.

Domino logic is fast, because the pre-charge cycle is common to all stages. Once pre-charge
is done, each stage evaluates one after the other (hence the name - domino logic). Thus for
n stage logic, there is only one cycle of pre-charge and n cycles of evaluation, rather than n
cycles of pre-charge and n of evaluation.

However, the addition of an inverter means that the logic is non-inverting. Therefore, it
cannot be used to implement any arbitrary logic function. In synchronous digital circuits,
combinational logic alternates with clocked latches. If inversion is required, we insert a latch
at that place and take the Q output of the latch to the next group of domino logic.
22 CHAPTER 1. BEYOND STATIC CMOS

1.4.4 Zipper logic

Vdd

A B E

C D

Ck Ck
Gnd
A, B, C must be from p stages.
D and E must be from n stages.

Figure 1.17: Zipper logic

Instead of using an inverter, we can alternate n and p evaluation stages. The n stage is
pre-charged high, but it drives a p stage. A high pre-charged stage will keep the p evaluation
stage off, which will not cause any malfunction. The p stage will be pre-discharged to ‘low’,
which is safe for driving n stages. This kind of logic is called zipper logic.