Verilog 2012 PDF

Synthesizable Coding of
Verilog
REF:
•Verilog Training Manual, CIC, July, 2008
•Reuse Methodology Manual – For System-ON-A-Chip Design, Third Edition 2002
•Logic Synthesis with Design Complier, CIC , July, 2008
Speaker: Y. –X. Chen Nov. 2012
Advanced Reliable 1
Systems (ARES) Lab.
11/21
 課程主題: Synthesizable Verilog & Coding
 學習目標
 Synthesizable coding style in Verilog
 Syntax check with nLint
 LAB1簡介-撰寫simple 8-bit microprocessor之Verilog code
 步驟一:RTL coding並使用nLint確定為可合成之code
 步驟二:使用修正好的RTL netlist跑simulation，並觀察波型
Advanced Reliable Systems (ARES) Lab. 2

Outline
 Basic of Logic Synthesis Concept
 Basic Concept of Verilog HDL
 Synthesizable Verilog
 LAB 1-1: Design Rule Check with nLint
 Tips for Verilog Design
 LAB 1-2: RTL Simulation

Basic Concept of the Synthesis

Cell-Based Design Flow
Spec.
System Level MATLAB/ C/ C++/ System C/ Memory Generator

ADS/ Covergen (MaxSim)
RTL Level Verilog/ VHDL NC-Verilog/ ModelSim Syntest

Debussy (Verdi)/ VCS
Logic Synthesis Conformal/ Design/ Power Compiler
Magma Blast Fusion

Physical Compiler/
Formality
Design for Test DFT Compiler/ TetraMAX
Gate Level NC-Verilog/ ModelSim

Debussy (Verdi)/ VCS
Layout Level SOC Encounter/ Astro

GDS II
Post-Layout DRC/ LVS (Calibre)
Verification
PVS: Calibre xRC/ NanoSim
(Time/ Power Mill)
Tape Out
What is Synthesis
 Synthesis = translation + optimization + mapping
if(high_bits == 2’b10)begin
residue = state_table[i];
end
else begin
residue = 16’h0000;
end Translate (HDL Compiler)
HDL Source
(RTL)
No Timing Info.
Optimize + Mapping
(HDL Compiler)
Generic Boolean
(GTECT)
Timing Info.
The synthesis is constraint driven

and technology independent !! Target Technology
Notice Before Synthesis
Area
Better
 Your RTL design Cycle
 Functional verification by some high-level language Time
 Also, the code coverage of your test benches should be verified (i.e. VN)
 Coding style checking (i.e. n-Lint)
 Good coding style will reduce most hazards while synthesis
 Better optimization process results in better circuit performance
 Easy debugging after synthesis
 Constraints
 The area and timing of your circuit are mainly determined by your
circuit architecture and coding style
 There is always a trade-off between the circuit timing and area
 In fact, a super tight timing constraint may be worked while synthesis,
but failed in the Place & Route (P&R) procedure

Basic Concept of Verilog HDL

Verilog Model
 Key features of Verilog
 Supports various level of abstraction
 Switch level model or transistor level model
 Gate level model
 Data flow model or register transfer model
 Behavioral model

Register Transfer Level (RTL)

Gate Level Model
 Model consists of basic logic
 Ex. AND, NAND, OR, NOR, XOR, NOT, etc.

Verilog Module
/* This is sample code.

The function is ALU.
*/
module module_name(port_names); module ALU(a,b,sel,out);
•Port declaration input [7:0] a,b; //Data in
output[7:0]out; //Data out
•Data type declaration input [2:0]sel; //Control select
•Task & function declaration
•Module functionality or structure reg [7:0]out;
•Timing Specification wire …
…
endmodule always@(...)begin
…
end
…
endmodule

Verilog Syntax
 Verilog consists of a series token
 Comment: //, /* */
 operators: unary, binary, ternary
 A=~B;
 A=B&C;
 C=SEL?A:B;
 Numbers: size, unsized
 Sized: 4’b0010, 8’ha
 Identifiers: $, #, etc.
 Keywords
 …

Verilog Syntax (Cont’d)
 always@ statement
 Blocking
always @ (posedge clk) begin
 Non-blocking x_temp<=x;
end
always @ (a or x_temp)begin
if (a) begin
x= x_temp+1’b1;
end
else begin
x= x_temp;
end

Verilog Syntax (Cont’d)
 Case statement
 If-else statement always @ (d) begin
case (d)
2'b00: z=1'b1;
2'b01: z=1'b0;
default : z=1'b0;
endcase
end
if (a) begin
x= x_temp+1’b1;
end
else begin
x= x_temp;
end

Connection Manners
net/register
net
net/register net
input net output
inout
net

Synthesizable Verilog

Importance of Coding Style
 Make sure your code is readable, modifiable,
and reusable
 Good coding style helps to achieve better results
in synthesis and simulation

Concept of Clocks and Reset
Synchronous Mixed Clock Edges

D Q D Q D Q CBL D Q
CBL
clk clk
Gated Clocks
Combination Feedback
D Q D Q
CBL
clk

Asynchronous and Synchronous Reset
 Synchronous reset
always@(posedge clock)begin
if (rst) begin
…………….
end
…
end
 Asynchronous reset
always@(posedge clock or negedge reset)
if (!rst) begin
………………
end
…
end
Synthesizable Verilog
 Not all kinds of Verilog constructs can be
synthesized
 Only a subset of Verilog constructs can be
synthesized and the code containing only this
subset is synthesizable

Synthesizable Verilog (Cont’)
 Verilog Basis  Synthesizable Verilog
 parameter declarations primitives cells
 wire, wand, wor  and, or, not, nand, nor, xor,
declarations xnor
 reg declarations  bufif0, bufif1, notif0, notif1
 input, output, inout
 Can not use for Synthesis
 continuous assignment
=== delay
 module instructions !== Initial
 gate instructions / (division) repeat
 always blocks % (modulus) forever
 task statement wait
 function definitions fork
 for, while loop join
event
Synthesizable Verilog (Cont’)
 Operators precedence
 Concatenation ( { }, {{}} ) highest
 Unary reduction ( !, ~, &, |, ^ )
 2’s complement arithmetic ( +, -, *)
 Logic shift ( >>, << )
 Relational ( >, <, >=, <= )
 Equality ( ==, != )
 Binary bit-wise ( &, |, ^, ~^ )
 Logical ( &&, || )
 Conditional ( ?: ) lowest

Coding for Synthesis
 Combinational Blocks  Sequential Blocks
always @ (d) begin always @ (posedge clk )begin
case (d) if (a) begin
2'b00: z=1'b1; z<=1’b1;
2'b01: z=1'b0; end
default : z=1'b0; else begin
endcase z<=1’b0;
end end
end
if (a) begin
x= x_temp+1’b1;
end
else begin
x= x_temp;
end

Coding for Synthesis (Cont’)
 Avoid Combinational Feedback
always @ (a or x)begin always @ (posedge clk) begin

if (a) begin x_temp<=x;
x= x+1’b1; end
end
else begin always @ (a or x_temp)begin
x= x; if (a) begin
end x= x_temp+1’b1;
end
else begin
x= x_temp;
end

 Blocking Assignment  Non-Blocking Assignment
always @ (posedge clk )begin always @ (posedge clk )begin
b=a; b<=a;
c=b; c<=b;
end end
Just like “a=c;” Just like “shift register”
a b c a b c
D Q D Q D Q
clk clk

 Avoid Latches
always @ (d) begin
x=1’b0;
always @ (d) begin
z=1’b0;
case (d)
case (d)
2'b00: z=1'b1;
2'b00: begin z=1'b1; x=1’b1; end
2'b01: z=1'b0;
2'b01: begin z=1'b0; end
default : z=1'b0;
default : begin z=1'b0; end
endcase
endcase
end
end
always @ (d)begin always @ (posedge clk )begin
if (a) begin if (a) begin
............ z<=1b1;
end end
else begin else begin
........... z<=1’b0;
end end
end end
 Sensitivity List
always @ (d) begin always @ (a or b or c or d)begin

case (d) if (a) begin
2'b00: z=1'b1; ............
2'b01: z=1'b0; end
default : z=1'b0; else begin
endcase if (b)begin
end z=c;
end
else begin
z=d;
end
end
end

 Case statements  if – else statements
always @ ( sel or a or b or c or always @ ( sel or a or b or c or d)
d)begin begin
case (sel) if (sel==2'b00) out=a;
2'b00:out=a; else if (sel==2'b01) out=b;
2'b01:out=b; else if (sel==2'b10) out=c;
2'b10:out=c; else out=d;
2'b11:out=d; end
endcase
end
sel
a 00
d 0
b 01 out
c 1
c 10 0
0 out
d 11 1
b 1
a
sel
Lab 1-1
Design Rule Check with nLint

Design Rule Check
 Use nLint tool (include by Debussy) and the
Verilog Coding Guideline to check your design
and modify parts of code to match the coding
guidelines

Start nLint
 Unix% nLint –gui &

Load Verilog Code (1/2)

Load Verilog Code (2/2)

Run nLint Check
Compile

nLint Check Result (1/2)

nLint Check Results (2/2)

Lab Time

11/28
 課程主題: Synthesizable Verilog & Coding
 學習目標
 Tips for Verilog Design
 RTL simulation
 Waveform viewer – nWave / Debussy
 LAB1簡介-撰寫simple 8-bit microprocessor之Verilog code
並模擬結果
 步驟一:RTL coding並使用nLint確定為可合成之code
 步驟二:使用修正好的RTL netlist跑simulation，並觀察波型

Outline
 Basic of Logic Synthesis Concept
 Basic Concept of Verilog HDL
 Synthesizable Verilog
 LAB 1-1: Design Rule Check with nLint
 Tips for Verilog Design
 LAB 1-2: RTL Simulation

Tips for Verilog Design

Pre-RTL Preparation Checklist
 Communicate design issues with your team
 Naming conventions, revision control, directory tree
and other design organizations
 Have a specification for your design
 Everyone should have a specification before they start
coding
 Design partition
 Follow the specification’s recommendations for
partition
 Break the design into major function blocks

RTL Coding Style
 Create a block level drawing of your design
before you begin coding
 Draw a block diagram of the function and sub-function
of your design
 Always think of the poor guy who has to read
your RTL code
 Correlate “top to bottom in the RTL description” with
left to right in block diagram
 Comments and headers
 Hierarchy design

Basic Coding Practices
 Naming Conventions
 Use lowercase letters for all signal names, and port
names, versus uppercase letters for names of
constants and user-defined types
 Use meaningful names
 For active low signals, end the signal name with an
underscore followed by a lowercase character (e.g.,
rst_ or rst_n)
 Recommend using “bus[X:0]” for multi-bit signals

Basic Coding Practices (Cont’)
 Include Headers in Source Files and Comments

 Indentation  Port Maps and Generic
Maps

 Use Functions or Tasks
 Which Instead of repeating the same sections of code

Write Efficient HDL Code
 Use parentheses control complex structure
of a design
 Resource Sharing
 Scalable design and propagate constant value
 Use operator bit-width efficiently
 Timescale

Use Parentheses Properly
 out=a+b+c+d+e  out=((a+(b+c))+(d+e));
a b b
c
c a d e
out
out

Resource Sharing
 Operations can be shared if they lie in the same
always blocks

Scalable Design & Constant
parameter size=8;
wire [3:0] a,b,c,d,e;
assign a=size+2; Constant

assign b=a+1; Increaser
assign c=d+e; Adder

Use Operator Bit-width Efficiently
module fixed_multiplier(a,b,c);
input [8:0] a, b;
output [8:0] c;
reg [15:0] tmp;
reg [8:0] c;
assign tmp = a*b;
assign c = tmp(15,8);
endmodule

Timescale
 `timescale: which declares the time unit and precision.
 `timescale <time_unit> / <time_precision>
 e.g. : `timescale 1s/1ps, to advance 1 sec, the timewheel scans its queues
1012 times versus a `timescale 1s/1ms, where it only scans the queues
103 times.
 The time_precision must be at least as precise as the time_unit.
 Keep precision as close in scale to the time units as is practical.
 If not specified, the simulator may assign a default timescale
unit.
 The smallest precision of all the timescale directive determines
the “simulation time unit ” of the simulation.

Omit for Synthesis
 Omit the Wait for XX ns Statement
 Do not use “#XX;”
 Omit the ...After XX ns or Delay Statement
 Do not use “assign #XX Q=0;”
 Omit initial values
 Do not use “initial sum = 1’b0;”

Non-Synthesizable Style
 Either non-synthesizable or incorrect after
synthesis
 initial block is forbidden (non-synthesizable)
 Multiple assignments (multiple driving sources)
 Mixed blocking and non-blocking assignment

Summary
 No initial in the RTL code
 Avoid unnecessary latches
 Avoid combinational feedback
 For sequential blocks, use non-blocking
statement
 For combinational blocks, use blocking
statements

Lab 1-2
RTL Simulation

Tools
 Simulators
 Verilog-XL, NC-Verilog, Altera Quartus, ModelSim and
etc.
 Synthesizers
 Design vision, Ambit, and etc.
 Debugger and verification tools
 Debussy, nWave, nLint, and etc.
 nLint can check the correctness of your code’s syntax
58
Verilog Simulator

Run Verilog Simulation(1/2)
 Method 1:
 unix% verilog alu.v t_alu.v
 unix% ncverilog +access+r alu.v t_alu.v
 Method 2:
 Using additional file alu.f
alu.v
t_alu.v
 unix% verilog -f alu.f
 unix% ncverilog +access+r -f alu.f
 Method 3:
 Using additional description `include “module_file”
Run Verilog Simulation(2/2)

Testbench
 Compare this with your design
module testfixture;
•Declare signals
•Instantiate modules
•Applying stimulus
•Monitor signals
endmodule

FSDB File
 Waveform file format
 Add commands in testbench
// testbench.v
module …();
…
initial begin
$fsdbDumpfile(“abcd.fsdb”);
$fsdbDumpvars;
End
…
endmodule

Example of Testbench
//t_alu.v
/* This is testbench of sample code.
The function is ALU.
*/
module test_ALU;
reg [7:0] A,B;
reg[2:0]SEL;
//alu.v wire[7:0] OUT;
/* This is sample code.
The function is ALU. ALU U0(.a(A),.b(B),.sel(SEL),.out(OUT));
*/ always #5 B=~B;
initial
module ALU(a,b,sel,out);
begin
input [7:0] a,b; //Data in A=0;B=0;SEL=0;
output[7:0]out; //Data out #10 A=0;SEL=1;
input [2:0]sel; //Control select #10 SEL=0;
…..
reg [7:0]out; #10 SEL=1;
#10 $finish;
wire …
end
… initial begin
always@(...)begin $fsdbDumpfile(“ALU.fsdb”);
… $fsdbDumpvars;
end end
… endmodule
endmodule

Debussy – Getting Start
 Using nWave or Debussy
 unix% nWave&
 unix% debussy&

Get Signals
 Select “Signal” -> “Get Signal”

Observe Waveform

Change Radix

Save Waveform

LAB Time

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Synthesizable Coding of

Speaker: Y. –X. Chen Nov. 2012

Advanced Reliable Systems (ARES) Lab. 2

Advanced Reliable Systems (ARES) Lab. 3

Advanced Reliable Systems (ARES) Lab. 4

System Level MATLAB/ C/ C++/ System C/ Memory Generator

RTL Level Verilog/ VHDL NC-Verilog/ ModelSim Syntest

Logic Synthesis Conformal/ Design/ Power Compiler

Magma Blast Fusion

Gate Level NC-Verilog/ ModelSim

Layout Level SOC Encounter/ Astro

The synthesis is constraint driven

Advanced Reliable Systems (ARES) Lab. 7

Advanced Reliable Systems (ARES) Lab. 8

Advanced Reliable Systems (ARES) Lab. 9

Advanced Reliable Systems (ARES) Lab. 10

Advanced Reliable Systems (ARES) Lab. 11

/* This is sample code.

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Synchronous Mixed Clock Edges

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always @ (a or x)begin always @ (posedge clk) begin

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Just like “a=c;” Just like “shift register”

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always @ (d) begin always @ (a or b or c or d)begin

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assign a=size+2; Constant

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