CECS 201 Computer Logic Design © 2013 R. W.

Allison

Xilinx Verilog Lab #3 – Spring 2013  Name ______________________________

General Statement: You are to create a structural verilog module of a 4-to-16 decoder (named dec_4to16) using five
instances of a verilog module for a 2-to-4 decoder (named dec_2to4). Your verilog module for the 4-to-16 decoder will
have a 4-bit data input, (d[3:0]) and a 1-bit enable input (en). There will be one 16-bit output (y[15:0]). The 4-to-16
decoder is to be created using ONLY 2-to-4 decoders, having two 1-bit data inputs, a 1-bit enable input and four 1-bit
outputs. The purpose of this lab is to use “structural modeling” techniques with verilog. The “unconnected” structure of
the 4-to-16 decoder components, along with global/local inputs and outputs is illustrated in the diagram below:

Structural Diagram of
4‐to‐16 Decoder 
dec_2to4 
Components 
  d1      y3
  d0      y2
      y1
  en      y0

dec_2to4 
  d1      y3
  d0      y2
      y1
dec_2to4    en      y0

4 16 global
  d1      y3 
  d0      y2  outputs 
d[3:0]
      y1  dec_2to4  y[15:0]
  en      y0 
  d1      y3
global    d0      y2
inputs        y1
  en      y0

dec_2to4 
en   d1      y3
local local 
  d0      y2
inputs        y1 outputs 
  en      y0
Note: the “local” data inputs of the individual
2-to-4 decoder's (d1, d0) must be connected to
the appropriate “global” data inputs of the
4-to-16 decoder (d3, d2, d1, d0).

Deliverables: You are to turn in (1) this cover sheet, followed by (2) a printout of three verilog modules: the “top level”
(given on page 3), dec_4to16 and dec_2to4 modules, followed by (3) a printout of the simulation waveform (see p. 2).

Due Date:  Thursday, April 11, 2013 {Thur. of week 11}

Verilog Lab # 3 – Page 1

CECS 201 Computer Logic Design © 2013 R. W. Allison

As mentioned previously, since the 4-to-16 decoder will be constructed with instances of a 2-to-4 decoder module which
you are to produce. The 2-to-4 decoder module may be designed either behaviorally or structurally. My suggestion is to
design it behaviorally, using a “case statement,” similar to what was done in the last lab assignment, (i.e. Verilog Lab 2).
Since the proper operation of the 4-to-16 decoder is dependent upon the proper operation of the 2-to-4 decoder, it will
save time to write a “throw-away” testbench to verify to operation of the 2-to-4 decoder before depending on it.

Once you are assured the 2-to-4 decoder module works correctly, write the verilog module for the 4-to-16 decoder
module, again, using five instances of module dec_2to4. Once you save the verilog file for the 4-to-16 decoder, the Xilinx
Project Navigator window should look something like below (depending on the name of your instances):

To verify the operation of the 4-to-16 decoder, create a testbench that assigns the four data inputs d[3:0] with all possible
combinations (0000 to 1111) while to enable input (en) is asserted (i.e. en=1). Following those 16 values, deasserted the
enable and set the data inputs to “xxxx.” Conclude the test vectors with the enable deasserted (i.e. en=0) and the data
inputs set to 0000. The correct output from the ISE Simulator is shown below.

Note that the 16-bit output, y[15:0], is being display in hexadecimal format for the sake of readability. In the graphic
above, the cursor (706.6 ns) is placed when to input to the decoder is binary “0111,” which should assert output y[7]. By
converting the output 0x0080 to binary  0000_0000_1000_0000, we verify that, in fact, only the y[7] output is asserted
while all other 15 outputs are deasserted.

Also note in the last two test vectors, when the enable input is deasserted (i.e. 0) none of the 16 outputs is asserted.

Verilog Lab # 3 – Page 2

CECS 201 Computer Logic Design © 2013 R. W. Allison

Top‐Level Verilog Module for FPGA Board Test 

Unfortunately, the Nexys2 FPGA board does not have 16 LED’s to connect to the 4-to-16 decoder outputs. Thus, your
project is to include the following “top-level” module that will instantiate the dec_4to16 module and select either the
upper 8 outputs (i.e. y[15:8]) or lower 8 outputs (i.e. y[7:0]) to go to the 8 LED’s that are on the Nexys2 board:

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////
// Company: CSULB_CECS_Dept
// Engineer: R. W. Allison
//
// Create Date: 19:56:32 01/15/2013
// Design Name: Verilog_Lab3_Spring2013
// Module Name: Verilog_Lab3_Top_Level
//
// Description: This purpose of this top-level module is to
// instantiate the 4-to-16 decoder and then select either
// the lower 8 outputs y[7:0] or upper 8 outputs of the
// (since we don't have 16 LED's) 4-to-16 decoder.
//
//////////////////////////////////////////////////////////////////////////
module Verilog_Lab3_Top_Level( d, enable, up8_lo8, leds );
input [3:0] d;
input enable, up8_lo8;
output wire [7:0] leds;

// used when instantiating the 4-to 16

wire [15:0] y;

//instantiate the 4-to-16 decoder module

dec_4to16 uut ( d, enable, y );

//the conditional assignment acts like a 2-to-1 MUX

// if (up8_lo8==1) leds = y[15:8] else leds = y[7:0]
assign leds = (up8_lo8 == 1) ? y[15:8] : y[7:0];

endmodule

Obviously, you must change the “Engineer,” “Create Date,” and “Design Name” fields in the comment header
appropriately, but the rest of the module must be typed in exactly as shown above, including the formatting.

Use the following specifications for the creation of your “constraints” file for the Nexys2 boards:
The inputs to the “top-level” module (d[3:0]) are to be connected to switches SW3 to SW0, respectively.
The enable input “enable” is to be connected to switch SW4.
The up8_lo8 select input is to be connected to switch SW7.
The outputs from the “top-level” module (leds[7:0]) are to be connected to LD7 to LD0, respectively.

Verilog Lab # 3 – Page 3