A B C D E

1 1

NWQAA
2
Marseille 10 2

LA-6061P REV 2.0 Schematic

3
Intel Processor(ARD) /PCH(HM55) 3

2010-03-24 Rev 2.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 1 of 45
A B C D E
 A B C D E

Fan Control Clock Generator

APL5607 RTM890N
Intel Arrandale page 6 page 13

rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1

Dual Channel BANK 0, 1, 2, 3 page 11,12

page 5,6,7,8,9,10 1.5V DDRIII 800/1066/1333 MT/s

CRT USB/B Right Left USB FingerPrinter

FDI X8 DMI X4 USB port 0,1 USB port 2 USB port 8
page 14 page 25 page 25 page 26
2.7GHz 2.5GHz

BT conn Felica Int. Camera

USB port 5 USB port 9 USB port 11
USB page 26 page 26 page 13
5V 480MHz
LVDS Conn.
page 13
PCIeMini Card PCIeMini Card Express Card
2
USB WiMax USB port 13 3G/TV#1
TV#2
USB port 12
USB port 10
USB USB port 4 2

5V 480MHz page 27 page 27 page 27

EC SMBus HDMI-CEC Level Shifter
HDMI Conn. PCIe 1x PCIeMini Card PCIeMini Card Express Card
page 15 page 15 1.5V 2.5GHz(250MB/s)
WLAN PCIe port 2 JET PCIe port 4
PCIe PCIe port 3
page 15 page 27 page 27 page 27
Intel Ibex Peak

RTL8105E 10/100M SATA port 1 SATA HDD B-CAS SIM

RJ45 PCIe 1x 5V 3GHz(300MB/s) page 26 page 27
SATA port 1
page 28 RTL8111E 1G PCIe port 1 1.5V 2.5GHz(250MB/s) page 25
page 28
BGA-951
SATA port 4 SATA ODD
5V 3GHz(300MB/s) SATA port 4
Cardreader PCIe 1x page 25
JMB385C/389C 1.5V 2.5GHz(250MB/s) SATA port 5
PCIe port5 page 16,17,18,19,20,21,22,23,24
page 29 5V 3GHz(300MB/s) eSATA USB
3 3
USB port 3 SATA port 5 USB port 3
page 25 page 25
5V 480MHz

LPC BUS HD Audio 3.3V/1.5V 24MHz

3.3V 33 MHz
Light Pipe/B
LS-6061P page 33
MDC 1.5 Conn HDA Codec
ALC269
Cap Sensor SPI ROM Debug Port ENE KB926 D3/E0 page 26 page 30
page 32 page 31
& Light Sensor/B (4MB)
page 16
RTC CKT. LS-6062P page 33
page 16
Touch Pad Int.KBD EC ROM CIR G-Sensor Int. SPK Conn JPIO
page 30
LED/B page 33 page 32 page 31 page 32 MIC Conn (HP &page
MIC)
DC/DC Interface CKT. LS-6063P page 33
(256KB)
page 32
page 13 25

page 34 EC SMBus
Audio & USB/B
4 4

Power Circuit DC/DC LS-6064P page 25

page 35,36,37,38,39,40
41,42,43 Finger Printer/B
LS-6065P page 26 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

Power On/Off CKT. Power/B_FPC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
page 33 DA300006F00 page 33 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B 2.0

Date: Tuesday, March 23, 2010 Sheet 2 of 45

A B C D E
 5 4 3 2 1

DESIGN CURRENT 0.1A +3VL

DESIGN CURRENT 0.1A +5VL
B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW
SUSP#

DESIGN CURRENT 2A +1.8VS

MP2121DQ
SUSP
D D

N-CHANNEL DESIGN CURRENT 4A +5VS

SI4800 BCPWON
DESIGN CURRENT 0.5A +5VS_L_BCAS
P-CHANNEL
AO-3413
KB_LED
RT8205EGQW DESIGN CURRENT 400mA +5VS_LED
P-CHANNEL
AO-3413
+5VS
DESIGN CURRENT 300mA +3VS_HDP
LDO
G9191
ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413

Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW

WOL_EN#

P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

SUSP AO-3413
C C
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800 LCD_ENVDD

P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD

AO-3415
BT_PWR#
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413
FELICA_PWR
DESIGN CURRENT 0.5A +FLICA_VCC
P-CHANNEL
AO-3413
VR_ON

DESIGN CURRENT 48A +CPU_CORE

ISL62883HRZ

GFXVR_EN

DESIGN CURRENT 15A +GFX_CORE

ADP3211AMNR2G

VTTP_EN
B B

Ipeak=18A, Imax=12.6A, Iocp min=19.8 DESIGN CURRENT 18A +VTT

APW7138NITRL
SUSP#

Ipeak=7A, Imax=4.9A, Iocp min=7.7 DESIGN CURRENT 7A +1.05VS

RT8209BGQW

SUSP#
Ipeak=15A, Imax=10.5A, Iocp min=16.5 DESIGN CURRENT 15A +1.5V
RT8209BGQW SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5V_CPU

FDS6676AS
SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5VS

FDS6676AS

SUSP or 0.75VR_EN#

DESIGN CURRENT 1.5A +0.75VS

A G2992F1U A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Tuesday, March 23, 2010 Sheet 3 of 45
5 4 3 2 1
 A B C D E

( O MEANS ON X MEANS OFF )

Voltage Rails
+RTCVCC +B +5VL +5VALW +1.5V +5VS
+3VL +3VALW +3VS
+VSB +1.5VS
power
+VGA_CORE
1 plane BTO Option Table 1

+CPU_CORE
+VTT
Function MINI PCI-E SLOT LAN Fingerprint Modem CIR KB Light
+1.05VS
+1.8VS description SLOT2 SLOT1 LAN Fingerprint Modem CIR KB Light
+1.1VS
explain 3G TV Tuner WIMAX 10/100M Giga Fingerprint Modem CIR KB Light
State +0.75VS
BTO 3G@ TV@ WIMAX@ 8105E@ 8111E@ FP@ MDC@ CIR@ KBL@

Function Felica BLUE TOOTH G-SENSOR Camera & Mic HDMI Card reader

description Felica BLUE TOOTH G-SENSOR Camera & Mic HDMI JMB385C/389C
S0
O O O O O O explain Felica BLUE TOOTH G-SENSOR Camera & Mic UMA CEC JMB385C JMB389C

S1 BTO FELICA@ BT@ GSENSOR@ CAM@ IHDMI@ CEC@ JMB385@ JMB389@

O O O O O O
2 2
S3 O O O O O X Function S3 Power Saving New Card

S5 S4/AC description S3 Power Saving New Card

O O O O X X
explain No Power Saving Power Saving New Card
S5 S4/ Battery only
O O O X X X
BTO NOPS@ PS@ NEW@
S5 S4/AC & Battery
don't exist
O X X X X X

PCH SM Bus Address

Power Device HEX Address

+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
3
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b 3
SIGNAL
+3VS Clock Generator D2 H 1101 0010 b STATE SLP_S3# SLP_S4# SLP_S5#
+3VS New Card
Full ON HIGH HIGH HIGH
+3VS WLAN/WIMAX
+3VS Clock Generator S1(Power On Suspend) HIGH HIGH HIGH
+3VS 3G
S3 (Suspend to RAM) LOW HIGH HIGH

S4 (Suspend to Disk) LOW LOW HIGH

S5 (Soft OFF) LOW LOW LOW

EC SM Bus1 Address EC SM Bus2 Address
G3 LOW LOW LOW
Power Device HEX Address Power Device HEX Address
+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b
+3VL HDMI-CEC 34 H 0011 0100 b +3VS G-Sensor 40 H 0100 0000 b
+3VS Light Sensor 52 H 0101 0010 b

4
Power Device HEX Address 4

+3VL Cap. Sensor Virtual I2C

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Tuesday, March 23, 2010 Sheet 4 of 45
A B C D E
 5 4 3 2 1

JCPUB
@ 1 2 H_COMP3 AT23
1000P_0402_50V7K 2 DRAMPWROK COMP3
1 C487 R1 20_0402_1%
BCLK A16 CLK_CPU_BCLK <21>

MISC
1 2 H_COMP2 AT24 B16 CLK_CPU_BCLK# <21>
@ R2 20_0402_1% COMP2 BCLK#
1000P_0402_50V7K 2 1 C488 VTTPWROK_CPU H_COMP1 G16 CLK_CPU_XDP_R 1 CLK_CPU_XDP

CLOCKS
1 2 COMP1 BCLK_ITP AR30 2
R4 49.9_0402_1% AT30 CLK_CPU_XDP#_R 1 R41 @ 2 0_0402_5% CLK_CPU_XDP#
H_COMP0 AT26 BCLK_ITP# R42 @ 0_0402_5%
1 2 COMP0
R3 49.9_0402_1% E16 CLK_PEG <17>
PEG_CLK +VTT
PEG_CLK# D16 CLK_PEG# <17>
PAD T41 TP_SKTOCC# AH24
+VTT SKTOCC#
DPLL_REF_SSCLK A18 Unused by Clarksfield rPGA989
D A17 PM_EXTTS#0 R15 2 1 10K_0402_5% D
CATERR# DPLL_REF_SSCLK#
1 2 AK14 CATERR#

THERMAL
R18 49.9_0402_1% PM_EXTTS#_R R13 2 1 10K_0402_5%
+VTT F6 SM_DRAMRST#_CPU
SM_DRAMRST#
<21> PECI AT15 PECI
SM_RCOMP[0] AL1 SM_RCOMP_0 R6 1 2 100_0402_1%
Power has removed VR_TT# AM1 SM_RCOMP_1 R7 1 2 24.9_0402_1% DDR3 Compensation Signals
SM_RCOMP[1]
2

Layout Note:Please these

SM_RCOMP[2] AN1 SM_RCOMP_2 R8 1 2 130_0402_1% resistors near Processor
R10 1 2 H_PROCHOT#_D AN26
+VTT PROCHOT#
68_0402_5% R9 68_0402_5% AN15 PM_EXTTS#0

DDR3
MISC
PM_EXT_TS#[0]
@ PM_EXT_TS#[1] AP15 PM_EXTTS#_R 2 1 PM_EXTTS# <11,12>
R12 0_0402_5%
1

<21> H_THERMTRIP# AK15 THERMTRIP#

H_CPURST#

AT28 XDP_PRDY#
PRDY# XDP_PREQ# XDP_TDI_R XDP_TDI
PREQ# AP27 1 2
R20 0_0402_5%
AN28 XDP_TCK
XDP_RST#_R H_CPURST# TCK XDP_TMS XDP_TDO_M XDP_TDO
1 2 AP26 RESET_OBS# TMS AP28 1 @ 2

PWR MANAGEMENT
R36 1K_0402_5% AT27 XDP_TRST# Routed as a single daisy chain R21 0_0402_5%
TRST#

1
JTAG & BPM
AL15 AT29 XDP_TDI_R R23
<18> PMSYNCH PM_SYNC TDI
AR27 XDP_TDO_R 0_0402_5%
TDO XDP_TDI_M
TDI_M AR29 2 1 +3VS
2 1 H_PWRGOOD1_R AN14 AP29 XDP_TDO_M R312 1K_0402_5%

2
+1.5V_CPU 0_0402_5% R25 VCCPW RGOOD_1 TDO_M XDP_TDI_M 1 @ 2
AN25 XDP_DBRESET# R26 0_0402_5%
DBR# XDP_DBRESET# <18>
C H_PWRGOOD AN27 C
<21> H_PWRGOOD VCCPW RGOOD_0 @ XDP_TDO_R 1 2
2

AJ22 XDP_BPM#0 XDP_PRDY# R358 1 2 0_0402_5% XDP_PRDY#_R R27 0_0402_5%

R28 DRAMPWROK AK13 BPM#[0] XDP_BPM#1 @
<18> DRAMPWROK SM_DRAMPW ROK BPM#[1] AK22
1.1K_0402_1% AK24 XDP_BPM#2 XDP_PREQ# R359 1 2 0_0402_5% XDP_PREQ#_R
NOPS@ BPM#[2] XDP_BPM#3 @
BPM#[3] AJ24
<39> VTTPWROK_CPU VTTPWROK_CPU AM15 AJ25 XDP_TCK R360 1 2 0_0402_5% XDP_TCK_R
1

VTTPW RGOOD BPM#[4] @

BPM#[5] AH22
DRAMPWROK AK23 XDP_TMS R367 1 2 0_0402_5% XDP_TMS_R JTAG MAPPING
TAPPWRGD BPM#[6] @
AM26 TAPPW RGOOD BPM#[7] AH23
XDP_TRST# R370 1 2 0_0402_5% XDP_TRST#_R
2

@ Scan Chain STUFF -> R20, R23, R27

NOPS@ R29 BUF_PLT_RST#_R AL14 XDP_BPM#0 R371 1 2 0_0402_5% XDP_BPM#0_R (Default) NO STUFF -> R21, R26
<20> BUF_PLT_RST# RSTIN#
3K_0402_1% 1.5K_0402_1% R30 @
XDP_BPM#1 R373 1 2 0_0402_5% XDP_BPM#1_R
R31 @ CPU Only STUFF -> R20, R21
1

PS@ 750_0402_1% IC,AUB_CFD_rPGA,R0P9 XDP_BPM#2 R374 1 2 0_0402_5% XDP_BPM#2_R NO STUFF -> R23, R26, R27
R29 @ @
750_0402_1% XDP_BPM#3 R375 1 2 0_0402_5% XDP_BPM#3_R
@ GMCH Only STUFF -> R26, R27
XDP_DBRESET# R390 1 2 0_0402_5% XDP_DBRESET#_R NO STUFF -> R20, R21, R23

EMI request, close to JCPU

NOPS@
B
2
R19
1
0_0402_5%
XDPSFF-24Pin
Connector B

For S3 CPU Power Saving

JXDP
PS@ XDP_PREQ#_R 1 1
S

SM_DRAMRST#_CPU 3 1 XDP_PRDY#_R 2
SM_DRAMRST# <11,12> 2
3 3
1

Q41 XDP_BPM#0_R 4
PS@ BSS138_NL_SOT23-3 XDP_BPM#1_R 4
5
G
2

R127 5
6 6
100K_0402_5% RST_GATE <21> XDP_BPM#2_R 7
XDP_BPM#3_R 7
8
2

@ R32 1K_0402_5% 8
9 9
1 H_PWRGOOD 1 2 H_PWRGOOD_R 10
C140 TAPPWRGD TAPPWRGD_R 10
1 2 11 11
0.047U_0402_25V6K @ R35 0_0402_5% CLK_CPU_XDP 12
PS@ CLK_CPU_XDP# 12
13 13
2 14
+VTT 14
XDP_RST#_R 15
+3VALW XDP_DBRESET#_R 15
16 16
PS@ 17
XDP_TDO 17
1 2 1 2 1 18 18
C163 0.1U_0402_16V4Z 51_0402_5% R14 XDP_TRST#_R 19 19

1
PS@ C1 XDP_TDI 20 20
5

U16 0.1U_0402_10V6K XDP_TMS_R 21

VTTPWROK @ 2 R11 21
1 22
P

<34,39> VTTPWROK IN1 22

4 PS@ DRAMPWROK 51_0402_5% 23 25
O R33 1.5K_0402_1% XDP_TCK_R 23 GND
2 24 26

2
IN2 24 GND
G

A A
SN74AHC1G08DCKR_SC70-5 MOLEX_52435-2472
3

2 @ 1
0_0402_5% R84
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU CLK/MISC/JTAG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 5 of 45
5 4 3 2 1
 5 4 3 2 1

D D

JCPUA
B26 PEG_COMP 1 2
PEG_ICOMPI R38 49.9_0402_1%
PEG_ICOMPO A26
<18> DMI_PTX_CRX_N0 A24 DMI_RX#[0] PEG_RCOMPO B27
C23 A25 PEG_RBIAS 1 2
<18> DMI_PTX_CRX_N1 DMI_RX#[1] PEG_RBIAS
B22 R39 750_0402_1%
<18> DMI_PTX_CRX_N2 DMI_RX#[2]
<18> DMI_PTX_CRX_N3 A21 DMI_RX#[3] PEG_RX#[0] K35
PEG_RX#[1] J34
<18> DMI_PTX_CRX_P0 B24 DMI_RX[0] PEG_RX#[2] J33
<18> DMI_PTX_CRX_P1 D23 DMI_RX[1] PEG_RX#[3] G35

DMI
<18> DMI_PTX_CRX_P2 B23 DMI_RX[2] PEG_RX#[4] G32
<18> DMI_PTX_CRX_P3 A22 DMI_RX[3] PEG_RX#[5] F34
PEG_RX#[6] F31
<18> DMI_CTX_PRX_N0 D24 DMI_TX#[0] PEG_RX#[7] D35
<18> DMI_CTX_PRX_N1 G24 DMI_TX#[1] PEG_RX#[8] E33
<18> DMI_CTX_PRX_N2 F23 DMI_TX#[2] PEG_RX#[9] C33
<18> DMI_CTX_PRX_N3 H23 DMI_TX#[3] PEG_RX#[10] D32
PEG_RX#[11] B32
<18> DMI_CTX_PRX_P0 D25 DMI_TX[0] PEG_RX#[12] C31
<18> DMI_CTX_PRX_P1 F24 DMI_TX[1] PEG_RX#[13] B28
<18> DMI_CTX_PRX_P2 E23 DMI_TX[2] PEG_RX#[14] B30
<18> DMI_CTX_PRX_P3 G23 DMI_TX[3] PEG_RX#[15] A31

PEG_RX[0] J35
PEG_RX[1] H34
PEG_RX[2] H33
<18> FDI_CTX_PRX_N0 E22 FDI_TX#[0] PEG_RX[3] F35
C D21 G33 C
<18> FDI_CTX_PRX_N1 FDI_TX#[1] PEG_RX[4]
<18> FDI_CTX_PRX_N2 D19 FDI_TX#[2] PEG_RX[5] E34
<18> FDI_CTX_PRX_N3 D18 FDI_TX#[3] PEG_RX[6] F32
<18> FDI_CTX_PRX_N4 G21 FDI_TX#[4] PEG_RX[7] D34

PCI EXPRESS -- GRAPHICS

<18> FDI_CTX_PRX_N5 E19 FDI_TX#[5] PEG_RX[8] F33
<18> FDI_CTX_PRX_N6 F21 FDI_TX#[6] PEG_RX[9] B33
<18> FDI_CTX_PRX_N7 G18 FDI_TX#[7] Intel(R) FDI PEG_RX[10] D31
A32
PEG_RX[11]
PEG_RX[12] C30
<18> FDI_CTX_PRX_P0 D22 FDI_TX[0] PEG_RX[13] A28
<18> FDI_CTX_PRX_P1 C21 FDI_TX[1] PEG_RX[14] B29
<18> FDI_CTX_PRX_P2 D20 FDI_TX[2] PEG_RX[15] A30
C18
<18>
<18>
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4 G22
FDI_TX[3]
FDI_TX[4] PEG_TX#[0] L33
+5VS
FAN Control Circuit
<18> FDI_CTX_PRX_P5 E20 FDI_TX[5] PEG_TX#[1] M35
<18> FDI_CTX_PRX_P6 F20 FDI_TX[6] PEG_TX#[2] M33
<18> FDI_CTX_PRX_P7 G19 FDI_TX[7] PEG_TX#[3] M30 1A
PEG_TX#[4] L31
<18> FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32
<18> FDI_FSYNC1 E17 FDI_FSYNC[1] PEG_TX#[6] M29
PEG_TX#[7] J31
<18> FDI_INT C17 FDI_INT PEG_TX#[8] K29 2
PEG_TX#[9] H30
C3 JFAN
<18> FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29
<18> FDI_LSYNC1 D17 F29 10U_0805_10V4Z +FAN1 1
FDI_LSYNC[1] PEG_TX#[11] 1 1
PEG_TX#[12] E28 2 2
PEG_TX#[13] D29 2 3 3
D27 U1
PEG_TX#[14] C4
PEG_TX#[15] C26 1 EN GND 8 4 GND
B @ 1000P_0402_25V8J B
2 VIN GND 7 5 GND
+FAN1 1
PEG_TX[0] L34 3 VOUT GND 6
PEG_TX[1] M34 <31> EN_DFAN1 4 VSET GND 5 ACES_85204-0300N
M32 1 @
PEG_TX[2] APL5607KI-TRG_SO8
PEG_TX[3] L30 10mil
M31 C5
PEG_TX[4] R34 10K_0402_5%
PEG_TX[5] K31 10U_0805_10V4Z
2
PEG_TX[6] M28 2 1 +3VS
PEG_TX[7] H31
PEG_TX[8] K28 FAN_SPEED1 <31>
PEG_TX[9] G30
PEG_TX[10] G29
F28 C6
PEG_TX[11] @ @ 0.01U_0402_25V7K
PEG_TX[12] E27
D28 EN_DFAN1 2 1 FAN_SPEED1 2 1
PEG_TX[13]
PEG_TX[14] C27
C25 C339 0.1U_0402_16V7K C374 0.1U_0402_16V7K
PEG_TX[15] @ @
2 1 2 1

IC,AUB_CFD_rPGA,R0P9 C372 0.1U_0402_16V7K C432 0.1U_0402_16V7K

@ @
2 1

C373 0.1U_0402_16V7K

A A
For ESD request at PVT

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU DMI/FDI/PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 6 of 45
5 4 3 2 1
 5 4 3 2 1

JCPUC JCPUD

<11> DDR_A_D[0..63] <12> DDR_B_D[0..63]

SA_CK[0] AA6 DDRA_CLK0 <11> SB_CK[0] W8 DDRB_CLK0 <12>

SA_CK#[0] AA7 DDRA_CLK0# <11> SB_CK#[0] W9 DDRB_CLK0# <12>
P7 DDR_B_D0 B5 M3
SA_CKE[0] DDRA_CKE0 <11> SB_DQ[0] SB_CKE[0] DDRB_CKE0 <12>
DDR_A_D0 A10 DDR_B_D1 A5
DDR_A_D1 SA_DQ[0] DDR_B_D2 SB_DQ[1]
C10 SA_DQ[1] C3 SB_DQ[2]
D DDR_A_D2 C7 DDR_B_D3 B3 V7 D
SA_DQ[2] SB_DQ[3] SB_CK[1] DDRB_CLK1 <12>
DDR_A_D3 A7 Y6 DDR_B_D4 E4 V6
SA_DQ[3] SA_CK[1] DDRA_CLK1 <11> SB_DQ[4] SB_CK#[1] DDRB_CLK1# <12>
DDR_A_D4 B10 Y5 DDR_B_D5 A6 M2
SA_DQ[4] SA_CK#[1] DDRA_CLK1# <11> SB_DQ[5] SB_CKE[1] DDRB_CKE1 <12>
DDR_A_D5 D10 P6 DDR_B_D6 A4
SA_DQ[5] SA_CKE[1] DDRA_CKE1 <11> SB_DQ[6]
DDR_A_D6 E10 DDR_B_D7 C4
DDR_A_D7 SA_DQ[6] DDR_B_D8 SB_DQ[7]
A8 SA_DQ[7] D1 SB_DQ[8]
DDR_A_D8 D8 DDR_B_D9 D2
DDR_A_D9 SA_DQ[8] DDR_B_D10 SB_DQ[9]
F10 SA_DQ[9] SA_CS#[0] AE2 DDRA_SCS0# <11> F2 SB_DQ[10] SB_CS#[0] AB8 DDRB_SCS0# <12>
DDR_A_D10 E6 AE8 DDR_B_D11 F1 AD6
SA_DQ[10] SA_CS#[1] DDRA_SCS1# <11> SB_DQ[11] SB_CS#[1] DDRB_SCS1# <12>
DDR_A_D11 F7 DDR_B_D12 C2
DDR_A_D12 SA_DQ[11] DDR_B_D13 SB_DQ[12]
E9 SA_DQ[12] F5 SB_DQ[13]
DDR_A_D13 B7 DDR_B_D14 F3
DDR_A_D14 SA_DQ[13] DDR_B_D15 SB_DQ[14]
E7 SA_DQ[14] SA_ODT[0] AD8 DDRA_ODT0 <11> G4 SB_DQ[15] SB_ODT[0] AC7 DDRB_ODT0 <12>
DDR_A_D15 C6 AF9 DDR_B_D16 H6 AD1
SA_DQ[15] SA_ODT[1] DDRA_ODT1 <11> SB_DQ[16] SB_ODT[1] DDRB_ODT1 <12>
DDR_A_D16 H10 DDR_B_D17 G2
DDR_A_D17 SA_DQ[16] DDR_B_D18 SB_DQ[17]
G8 SA_DQ[17] J6 SB_DQ[18]
DDR_A_D18 K7 DDR_B_D19 J3
DDR_A_D19 SA_DQ[18] DDR_B_D20 SB_DQ[19]
J8 SA_DQ[19] G1 SB_DQ[20] DDR_B_DM[0..7] <12>
DDR_A_D20 G7 DDR_B_D21 G5 D4 DDR_B_DM0
SA_DQ[20] DDR_A_DM[0..7] <11> SB_DQ[21] SB_DM[0]
DDR_A_D21 G10 DDR_B_D22 J2 E1 DDR_B_DM1
DDR_A_D22 SA_DQ[21] DDR_A_DM0 DDR_B_D23 SB_DQ[22] SB_DM[1] DDR_B_DM2
J7 SA_DQ[22] SA_DM[0] B9 J1 SB_DQ[23] SB_DM[2] H3
DDR_A_D23 J10 D7 DDR_A_DM1 DDR_B_D24 J5 K1 DDR_B_DM3
DDR_A_D24 SA_DQ[23] SA_DM[1] DDR_A_DM2 DDR_B_D25 SB_DQ[24] SB_DM[3] DDR_B_DM4
L7 SA_DQ[24] SA_DM[2] H7 K2 SB_DQ[25] SB_DM[4] AH1
DDR_A_D25 M6 M7 DDR_A_DM3 DDR_B_D26 L3 AL2 DDR_B_DM5
DDR_A_D26 SA_DQ[25] SA_DM[3] DDR_A_DM4 DDR_B_D27 SB_DQ[26] SB_DM[5] DDR_B_DM6
M8 SA_DQ[26] SA_DM[4] AG6 M1 SB_DQ[27] SB_DM[6] AR4
DDR_A_D27 L9 AM7 DDR_A_DM5 DDR_B_D28 K5 AT8 DDR_B_DM7
DDR_A_D28 SA_DQ[27] SA_DM[5] DDR_A_DM6 DDR_B_D29 SB_DQ[28] SB_DM[7]
L6 SA_DQ[28] SA_DM[6] AN10 K4 SB_DQ[29]
DDR_A_D29 K8 AN13 DDR_A_DM7 DDR_B_D30 M4
DDR_A_D30 SA_DQ[29] SA_DM[7] DDR_B_D31 SB_DQ[30]
N8 SA_DQ[30] N5 SB_DQ[31]
C DDR_A_D31 P9 DDR_B_D32 AF3 C
DDR_A_D32 SA_DQ[31] DDR_B_D33 SB_DQ[32]
AH5 SA_DQ[32] AG1 SB_DQ[33] DDR_B_DQS#[0..7] <12>
DDR_A_D33 AF5 DDR_B_D34 AJ3 D5 DDR_B_DQS#0
SA_DQ[33] DDR_A_DQS#[0..7] <11> SB_DQ[34] SB_DQS#[0]
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR SYSTEM MEMORY A

DDR_A_D35 SA_DQ[34] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2

AK7 SA_DQ[35] SA_DQS#[1] F8 AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D36 AF6 J9 DDR_A_DQS#2 DDR_B_D37 AG3 L4 DDR_B_DQS#3
DDR_A_D37 SA_DQ[36] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D38 SB_DQ[37] SB_DQS#[3] DDR_B_DQS#4
AG5 N9 AJ4 AH2

DDR SYSTEM MEMORY - B

DDR_A_D38 SA_DQ[37] SA_DQS#[3] DDR_A_DQS#4 DDR_B_D39 SB_DQ[38] SB_DQS#[4] DDR_B_DQS#5
AJ7 SA_DQ[38] SA_DQS#[4] AH7 AH4 SB_DQ[39] SB_DQS#[5] AL4
DDR_A_D39 AJ6 AK9 DDR_A_DQS#5 DDR_B_D40 AK3 AR5 DDR_B_DQS#6
DDR_A_D40 SA_DQ[39] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D41 SB_DQ[40] SB_DQS#[6] DDR_B_DQS#7
AJ10 SA_DQ[40] SA_DQS#[6] AP11 AK4 SB_DQ[41] SB_DQS#[7] AR8
DDR_A_D41 AJ9 AT13 DDR_A_DQS#7 DDR_B_D42 AM6
DDR_A_D42 SA_DQ[41] SA_DQS#[7] DDR_B_D43 SB_DQ[42]
AL10 SA_DQ[42] AN2 SB_DQ[43]
DDR_A_D43 AK12 DDR_B_D44 AK5
DDR_A_D44 SA_DQ[43] DDR_B_D45 SB_DQ[44]
AK8 SA_DQ[44] AK2 SB_DQ[45]
DDR_A_D45 AL7 DDR_B_D46 AM4
SA_DQ[45] DDR_A_DQS[0..7] <11> SB_DQ[46]
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D47 AM3
SA_DQ[46] SA_DQS[0] SB_DQ[47] DDR_B_DQS[0..7] <12>
DDR_A_D47 AL8 F9 DDR_A_DQS1 DDR_B_D48 AP3 C5 DDR_B_DQS0
DDR_A_D48 SA_DQ[47] SA_DQS[1] DDR_A_DQS2 DDR_B_D49 SB_DQ[48] SB_DQS[0] DDR_B_DQS1
AN8 SA_DQ[48] SA_DQS[2] H9 AN5 SB_DQ[49] SB_DQS[1] E3
DDR_A_D49 AM10 M9 DDR_A_DQS3 DDR_B_D50 AT4 H4 DDR_B_DQS2
DDR_A_D50 SA_DQ[49] SA_DQS[3] DDR_A_DQS4 DDR_B_D51 SB_DQ[50] SB_DQS[2] DDR_B_DQS3
AR11 SA_DQ[50] SA_DQS[4] AH8 AN6 SB_DQ[51] SB_DQS[3] M5
DDR_A_D51 AL11 AK10 DDR_A_DQS5 DDR_B_D52 AN4 AG2 DDR_B_DQS4
DDR_A_D52 SA_DQ[51] SA_DQS[5] DDR_A_DQS6 DDR_B_D53 SB_DQ[52] SB_DQS[4] DDR_B_DQS5
AM9 SA_DQ[52] SA_DQS[6] AN11 AN3 SB_DQ[53] SB_DQS[5] AL5
DDR_A_D53 AN9 AR13 DDR_A_DQS7 DDR_B_D54 AT5 AP5 DDR_B_DQS6
DDR_A_D54 SA_DQ[53] SA_DQS[7] DDR_B_D55 SB_DQ[54] SB_DQS[6] DDR_B_DQS7
AT11 SA_DQ[54] AT6 SB_DQ[55] SB_DQS[7] AR7
DDR_A_D55 AP12 DDR_B_D56 AN7
DDR_A_D56 SA_DQ[55] DDR_B_D57 SB_DQ[56]
AM12 SA_DQ[56] DDR_A_MA[0..15] <11> AP6 SB_DQ[57]
DDR_A_D57 AN12 DDR_B_D58 AP8
DDR_A_D58 SA_DQ[57] DDR_A_MA0 DDR_B_D59 SB_DQ[58]
AM13 SA_DQ[58] SA_MA[0] Y3 AT9 SB_DQ[59]
DDR_A_D59 AT14 W1 DDR_A_MA1 DDR_B_D60 AT7
B DDR_A_D60 SA_DQ[59] SA_MA[1] DDR_A_MA2 DDR_B_D61 SB_DQ[60] B
AT12 SA_DQ[60] SA_MA[2] AA8 AP9 SB_DQ[61]
DDR_A_D61 AL13 AA3 DDR_A_MA3 DDR_B_D62 AR10
SA_DQ[61] SA_MA[3] SB_DQ[62] DDR_B_MA[0..15] <12>
DDR_A_D62 AR14 V1 DDR_A_MA4 DDR_B_D63 AT10 U5 DDR_B_MA0
DDR_A_D63 SA_DQ[62] SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[0] DDR_B_MA1
AP14 SA_DQ[63] SA_MA[5] AA9 SB_MA[1] V2
V8 DDR_A_MA6 T5 DDR_B_MA2
SA_MA[6] DDR_A_MA7 SB_MA[2] DDR_B_MA3
SA_MA[7] T1 SB_MA[3] V3
Y9 DDR_A_MA8 R1 DDR_B_MA4
SA_MA[8] DDR_A_MA9 SB_MA[4] DDR_B_MA5
<11> DDR_A_BS0 AC3 SA_BS[0] SA_MA[9] U6 <12> DDR_B_BS0 AB1 SB_BS[0] SB_MA[5] T8
AB2 AD4 DDR_A_MA10 W5 R2 DDR_B_MA6
<11> DDR_A_BS1 SA_BS[1] SA_MA[10] <12> DDR_B_BS1 SB_BS[1] SB_MA[6]
U7 T2 DDR_A_MA11 R7 R6 DDR_B_MA7
<11> DDR_A_BS2 SA_BS[2] SA_MA[11] <12> DDR_B_BS2 SB_BS[2] SB_MA[7]
U3 DDR_A_MA12 R4 DDR_B_MA8
SA_MA[12] DDR_A_MA13 SB_MA[8] DDR_B_MA9
SA_MA[13] AG8 SB_MA[9] R5
T3 DDR_A_MA14 AC5 AB5 DDR_B_MA10
SA_MA[14] <12> DDR_B_CAS# SB_CAS# SB_MA[10]
AE1 V9 DDR_A_MA15 Y7 P3 DDR_B_MA11
<11> DDR_A_CAS# SA_CAS# SA_MA[15] <12> DDR_B_RAS# SB_RAS# SB_MA[11]
AB3 AC6 R3 DDR_B_MA12
<11> DDR_A_RAS# SA_RAS# <12> DDR_B_W E# SB_WE# SB_MA[12]
AE9 AF7 DDR_B_MA13
<11> DDR_A_W E# SA_WE# SB_MA[13]
P5 DDR_B_MA14
SB_MA[14] DDR_B_MA15
SB_MA[15] N1

IC,AUB_CFD_rPGA,R0P9
@

A A
IC,AUB_CFD_rPGA,R0P9
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 7 of 45
5 4 3 2 1
 5 4 3 2 1

Material Note (+VTT):

JCPUF
390uF/ 10mohm, number are 3,
power x1, HW x2

+CPU_CORE Clarksfield: 65A Clarksfield: 21A (Place these capacitors under CPU socket Edge, top layer) (Place these capacitors between inductor and socket on Bottom)
+VTT
Auburndale:48A Auburndale:18A +CPU_CORE
AG35 AH14
VCC1 VTT0_1 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
AG34 AH12
D VCC2 VTT0_2 D
AG33 AH11
VCC3 VTT0_3
AG32 AH10 1 1 1 1 1 1 1 1 1
VCC4 VTT0_4 C144 1 2 390U_2.5V_M_R10 C81 1 2 10U_0805_10V4K

+
AG31 J14
VCC5 VTT0_5
AG30 J13
VCC6 VTT0_6 C267 1 2 390U_2.5V_M_R10 C83 1 2 10U_0805_10V4K C71 C72 C73 C74 C75 C76 C77 C78 C79

+
AG29 H14
VCC7 VTT0_7 2 2 2 2 2 2 2 2 2
AG28 H12
VCC8 VTT0_8 C85 1
AG27
VCC9 VTT0_9
G14 2 10U_0805_10V4K
AG26 G13 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC10 VTT0_10 C87 1
AF35 G12 2 10U_0805_10V4K
VCC11 VTT0_11
AF34 G11
VCC12 VTT0_12 C89 1
AF33
VCC13 VTT0_13
F14 2 22U_0805_6.3V6M C88 1 2 10U_0805_10V4K
AF32 VCC14 VTT0_14 F13
AF31 F12 C91 1 2 22U_0805_6.3V6M C90 1 2 10U_0805_10V4K
VCC15 VTT0_15
AF30 VCC16 VTT0_16 F11 (Place these capacitors under CPU socket, top layer)
AF29 E14 C92 1 2 10U_0805_10V4K
VCC17 VTT0_17
AF28 VCC18 VTT0_18 E12
AF27 D14 C94 1 2 10U_0805_10V4K@ +CPU_CORE
VCC19 VTT0_19
AF26 VCC20 VTT0_20 D13

1.1V RAIL POWER

AD35 D12 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC21 VTT0_21
AD34 VCC22 VTT0_22 D11
AD33 VCC23 VTT0_23 C14 1 1 1 1 1 1 1
AD32 VCC24 VTT0_24 C13
AD31 VCC25 VTT0_25 C12
AD30 C11 C98 C99 C100 C101 C102 C103 C104
VCC26 VTT0_26 2 2 2 2 2 2 2
AD29 VCC27 VTT0_27 B14
AD28 VCC28 VTT0_28 B12
AD27 A14 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K 10U_0805_10V4K
VCC29 VTT0_29
AD26 VCC30 VTT0_30 A13
AC35 VCC31 VTT0_31 A12
AC34 VCC32 VTT0_32 A11
AC33 VCC33
C
AC32 VCC34 (Place these capacitors on CPU cavity, Bottom Layer) C
AC31 VCC35 Add on 5/25 for power team request
AC30 VCC36 VTT0_33 AF10
AC29 AE10 +CPU_CORE
VCC37 VTT0_34 +CPU_CORE
AC28 VCC38 VTT0_35 AC10
CPU CORE SUPPLY

AC27 AB10 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

VCC39 VTT0_36 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AC26 VCC40 VTT0_37 Y10
AA35 VCC41 VTT0_38 W10 1 1 1 1 1 1
AA34 U10 1 1 1 1 1 1 1 C105 C106 C107 C108 C109 C110
VCC42 VTT0_39 C114 C179 C131 C116 C132 C129 C149
AA33 T10
VCC43 VTT0_40
AA32 J12
VCC44 VTT0_41 2 2 2 2 2 2
AA31 J11
VCC45 VTT0_42 2 2 2 2 2 2 2
AA30 J16
VCC46 VTT0_43 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AA29 J15
VCC47 VTT0_44 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AA28
VCC48
AA27
VCC49
AA26
VCC50 +CPU_CORE
Y35
VCC51
Y34
VCC52 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
Y33
VCC53
Y32
VCC54
Y31 1 1 1 1 1 1
VCC55 C111 C112 C113 C130 C115 C148
Y30
VCC56
Y29
VCC57
Y28
VCC58 2 2 2 2 2 2
Y27
VCC59
Y26
V35
VCC60
AN33
CRB default setting: 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC61 PSI# H_PSI# <42>
V34 VID[6:0]=[0100111]
POWER

VCC62
V33
VCC63
V32 AK35 CPU_VID0 <42>
VCC64 VID[0]
V31 AK33 CPU_VID1 <42>
VCC65 VID[1]
V30 AK34 CPU_VID2 <42>
B VCC66 VID[2] B
V29
VCC67 VID[3]
AL35 CPU_VID3 <42> VTT Rail
CPU VIDS

V28
VCC68 VID[4]
AL33 CPU_VID4 <42> TOP side (under inductor)
V27 AM33 CPU_VID5 <42>
VCC69 VID[5]
V26
VCC70 VID[6]
AM35 CPU_VID6 <42> Auburndale +1.1VS_VTT=1.05V
U35 AM34 H_DPRSLPVR_R 1 2
U34
VCC71 PROC_DPRSLPVR R62 0_0402_5%
H_DPRSLPVR <42> Clarksfield +1.1VS_VTT=1.1V
VCC72 +CPU_CORE
U33
VCC73
U32
VCC74 H_VTTSELECT 330U_D2_2.5VM_R9M 330U_D2_2.5VM_R9M
U31 G15 T3 PAD
VCC75 VTT_SELECT
U30
VCC76 H_VTTSELECT = low, 1.1V 1 1 1 1
U29
VCC77 C121 + C122 + C123 + C124 +
U28
VCC78 H_VTTSELECT = high, 1.05V
U27
VCC79 330U_D2_2.5VM_R9M 330U_D2_2.5VM_R9M
U26
VCC80 2 2 2 2
R35
VCC81
R34
VCC82
R33
VCC83
R32 AN35 IMVP_IMON <42>
VCC84 ISENSE
R31
VCC85
R30 1 2 +CPU_CORE
VCC86 R64 100_0402_1%
R29
VCC87 VCCSENSE_R R65 VCCSENSE
2 0_0402_5%
SENSE LINES

R28 AJ34 1
R27
VCC88 VCC_SENSE
AJ35 VSSSENSE_R R66 1 2 0_0402_5% VSSSENSE VCCSENSE <42> Check list:
VCC89 VSS_SENSE VSSSENSE <42>
R26
VCC90
P35
P34
VCC91
B15 R67
1 2
100_0402_1%
+CPU_CORE: 6x 470uF, 12x 22uF, 17x 10uF
VCC92 VTT_SENSE VTT_SENSE <39>
P33 A15 VSS_SENSE_VTT <39>
VCC93 VSS_SENSE_VTT
P32
VCC94 near CPU +VTT: 4x 330uF, 7x 22uF, 8x 10uF
P31
VCC95
P30
VCC96
P29
VCC97
P28 VCC98
A A
P27 VCC99
P26 VCC100

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title
IC,AUB_CFD_rPGA,R0P9
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU POWER-1
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 8 of 45
5 4 3 2 1
 5 4 3 2 1

For S3 CPU Power Saving

For EMI request +1.5V_CPU +1.5V
3A Q33 PS@
1 S D 8
+GFX_CORE 2 7
S D

2
3 S D 6
R424 1 4 5
47P_0402_50V8J 47P_0402_50V8J 470_0805_5% C273 G D
1 PS@ FDS6676AS_SO8

1
C97 C118 C119 C93 10U_0805_10V4K 1 R418 2 +VSB

1
@ @ @ @ 2 PS@ 220K_0402_5%
PS@
2

6
D 1 D
47P_0402_50V8J 47P_0402_50V8J Q46B R417 Q46A PS@

0.1U_0402_25V6
C472
820K_0402_5%
SUSP 5 PS@ 2 SUSP
2 SUSP <34,41>
PS@

2
2N7002DW -T/R7_SOT363-6 PS@ 2N7002DW -T/R7_SOT363-6

1
Change C271 to 4.5mm height OS-CON at PVT
+GFX_CORE JCPUG
1 2 +GFX_CORE
22U_0805_6.3V6M 1U_0402_6.3V4Z AT21 R69 100_0402_1%
VAXG1 R365 1
AT19 VAXG2 VAXG_SENSE AR22 2 0_0402_5% VCC_AXG_SENSE <43>
R384 1 2 0_0402_5%

SENSE
LINES
1 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE <43>
1 1 1 1 1 1 AT16 VAXG4
C271 + C95 C127 C117 C96 C120 C86 AR21 1 2
330U_2.5V_M_R17 10U_0805_6.3V6M VAXG5 For Power request R82 100_0402_1%
AR19 VAXG6
2 2 2 2 2 2 2
AR18 VAXG7 near CPU
AR16 VAXG8 GFX_VID[0] AM22 GFXVR_VID_0 <43>
AP21 VAXG9 GFX_VID[1] AP22 GFXVR_VID_1 <43>

GRAPHICS VIDs
22U_0805_6.3V6M 1U_0402_6.3V4Z 10U_0805_6.3V6M AP19 AN22 C230 1 2 0.1U_0402_16V4Z
VAXG10 GFX_VID[2] GFXVR_VID_2 <43>
AP18 VAXG11 GFX_VID[3] AP23 GFXVR_VID_3 <43>
AP16 AM23 Change R136 to 470 ohm C314 1 2 0.1U_0402_16V4Z
VAXG12 GFX_VID[4] GFXVR_VID_4 <43>
AN21 AP24
VAXG13 GFX_VID[5] GFXVR_VID_5 <43> for GFX issue

GRAPHICS
AN19 AN24 C205 1 2 0.1U_0402_16V4Z
VAXG14 GFX_VID[6] GFXVR_VID_6 <43>
Add C496 Co-Layout with C271 AN18 VAXG15
AN16 GFXVR_EN 1 2 C186 1 2 0.1U_0402_16V4Z
VAXG16 R50 470_0402_5%
AM21 VAXG17 GFX_VR_EN AR25 GFXVR_EN <43>
C +GFX_CORE AM19 AT25 GFXVR_DPRSLPVR C
VAXG18 GFX_DPRSLPVR T8 PAD
AM18 AM24 GFXVR_IMON
VAXG19 GFX_IMON GFXVR_IMON <43>
AM16 PJ30 @
VAXG20 R687 2
1 AL21 VAXG21 1 1K_0402_5% 2 2 1 1
AL19 @
C496 + VAXG22 +1.5V_CPU JUMP_43X79
AL18 VAXG23
330U_D2_2VM_R6M AL16 PJ31 @
@ VAXG24 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
AK21 VAXG25 VDDQ1 AJ1 2 2 1 1 +1.5V
2
AK19 VAXG26 VDDQ2 AF1 1
AK18 AE7 JUMP_43X79

- 1.5V RAILS
VAXG27 VDDQ3 1 1 1 1 1 1 1
+ C216
AK16 VAXG28 Clarksfield: 5A VDDQ4 AE4
C133 C134 C135 C136 C137 C138 C139 390U_2.5V_M_R10
AJ21 VAXG29 VDDQ5 AC1
AJ19 VAXG30 Auburndale:3A VDDQ6 AB7
2 2 2 2 2 2 2 2 PJ30,PJ31 need to open for
AJ18 AB4
AJ16
VAXG31 VDDQ7
Y1
S3 CPU Power Saving
VAXG32 VDDQ8
AH21 VAXG33 VDDQ9 W7

POWER
AH19 W4 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
VAXG34 VDDQ10
AH18 VAXG35 VDDQ11 U1
AH16 VAXG36 VDDQ12 T7
VDDQ13 T4
+VTT Auburndale:22A VDDQ14 P1
VDDQ15 N7
VDDQ16 N4

DDR3
VDDQ17 L1
J24 VTT1_45 VDDQ18 H1
FDI
J23 VTT1_46
H25 +VTT
1 1 VTT1_47
C141 C142
B
(Place these capacitors under CPU socket Edge, top layer) B
22U_0805_6.3V6M 22U_0805_6.3V6M P10 1
2 2 VTT0_59 C143
VTT0_60 N10
VTT0_61 L10
K10 10U_0805_10V4K
VTT0_62 2
Clarksfield: 21A
+VTT
+VTT Auburndale:18A
1.1V

VTT1_63 J22
K26 VTT1_48 VTT1_64 J20
J27 VTT1_49 VTT1_65 J18 1
PEG & DMI

1 1 J26 H21 C145

C146 C147 VTT1_50 VTT1_66
J25 VTT1_51 VTT1_67 H20
H27 H19 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_52 VTT1_68 2
G28 VTT1_53
2 2
G27 VTT1_54 (Place these capacitors under CPU socket, top layer)
G26 VTT1_55
F26 +1.8VS
VTT1_56
E26 VTT1_57 VCCPLL1 L26
1.8V

E25 VTT1_58 VCCPLL2 L27

M26 +1.8VS_H_PLL 1U_0402_6.3V4Z 4.7U_0603_6.3V6K 2 1
VCCPLL3 R71 0_0805_5%
1 1 1 1
(Place these capacitors under CPU socket, top layer) Clarksfield: 0.6A C151 C152 C153 C154 C155
Auburndale:1.35A 1U_0402_6.3V4Z
2 2 2 2 22U_0805_6.3V6M

A
IC,AUB_CFD_rPGA,R0P9 2.2U_0603_6.3V4Z A
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU POWER-2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 9 of 45
5 4 3 2 1
 5 4 3 2 1

JCPUI JCPUH JCPUE

AT20 VSS1 VSS81 AE34 RSVD32 AJ13

AT17 VSS2 VSS82 AE33 RSVD33 AJ12
K27 VSS161 AR31 VSS3 VSS83 AE32
K9 VSS162 AR28 VSS4 VSS84 AE31 AP25 RSVD1
K6 VSS163 AR26 VSS5 VSS85 AE30 AL25 RSVD2 RSVD34 AH25
D K3 VSS164 AR24 VSS6 VSS86 AE29 AL24 RSVD3 RSVD35 AK26 D
J32 VSS165 AR23 VSS7 VSS87 AE28 AL22 RSVD4
J30 VSS166 AR20 VSS8 VSS88 AE27 AJ33 RSVD5 RSVD36 AL26
J21 VSS167 AR17 VSS9 VSS89 AE26 AG9 RSVD6 RSVD_NCTF_37 AR2
J19 VSS168 AR15 VSS10 VSS90 AE6 M27 RSVD7
H35 VSS169 AR12 VSS11 VSS91 AD10 L28 RSVD8 RSVD38 AJ26
H32 VSS170 AR9 VSS12 VSS92 AC8 J17 RSVD9 (SA_DIMM_VREF) RSVD39 AJ27
H28 VSS171 AR6 VSS13 VSS93 AC4 H17 RSVD10(SB_DIMM_VREF)
H26 VSS172 AR3 VSS14 VSS94 AC2 G25 RSVD11
H24 VSS173 AP20 VSS15 VSS95 AB35 G17 RSVD12
H22 VSS174 AP17 VSS16 VSS96 AB34 E31 RSVD13 RSVD_NCTF_40 AP1
H18 VSS175 AP13 VSS17 VSS97 AB33 E30 RSVD14 RSVD_NCTF_41 AT2
H15 VSS176 AP10 VSS18 VSS98 AB32
H13 VSS177 AP7 VSS19 VSS99 AB31 RSVD_NCTF_42 AT3
H11 VSS178 AP4 VSS20 VSS100 AB30 RSVD_NCTF_43 AR1
H8 AP2 AB29 WW41 Recommend not pull down
VSS179 VSS21 VSS101
H5 VSS180 AN34 VSS22 VSS102 AB28 PCIE2.0 Jitter is over on ES1
H2 VSS181 AN31 VSS23 VSS103 AB27
G34 VSS182 AN23 VSS24 VSS104 AB26 RSVD45 AL28
G31 AN20 AB6 3.01K_0402_1% 1 @ R74 2 AM30 AL29
VSS183 VSS25 VSS105 CFG[0] RSVD46
G20 VSS184 AN17 VSS26 VSS106 AA10 AM28 CFG[1] RSVD47 AP30
G9 VSS185 AM29 VSS27 VSS107 Y8 AP31 CFG[2] RSVD48 AP32
G6 AM27 Y4 3.01K_0402_1% 1 @ R75 2 AL32 AL27
VSS186 VSS28 VSS108 3.01K_0402_1% 1 @ R76 CFG[3] RSVD49
G3 VSS187 AM25 VSS29 VSS109 Y2 2 AL30 CFG[4] RSVD50 AT31
F30 VSS188 AM20 VSS30 VSS110 W35 AM31 CFG[5] RSVD51 AT32
F27 VSS189 AM17 VSS31 VSS111 W34 AN29 CFG[6] RSVD52 AP33
F25 VSS190 AM14 VSS32 VSS112 W33 AM32 CFG[7] RSVD53 AR33
F22 VSS191 AM11 VSS33 VSS113 W32 AK32 CFG[8] RSVD_NCTF_54 AT33
F19 AM8 W31 AK31 AT34

RESERVED
C VSS192 VSS34 VSS114 CFG[9] RSVD_NCTF_55 C
F16 VSS193 AM5 VSS35 VSS115 W30 AK28 CFG[10] RSVD_NCTF_56 AP35
E35 VSS194 AM2 VSS36 VSS116 W29 AJ28 CFG[11] RSVD_NCTF_57 AR35
E32 AL34 W28 AN30 AR32
E29
E24
VSS195
VSS196
VSS197
VSS AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
AN32
AJ32
CFG[12]
CFG[13]
CFG[14]
RSVD58

E21 VSS198 AL20 VSS40 VSS120 W6 AJ29 CFG[15] RSVD_TP_59 E15

E18 VSS199 AL17 VSS41 VSS121 V10 AJ30 CFG[16] RSVD_TP_60 F15
E13 VSS200 AL12 VSS42 VSS122 U8 AK30 CFG[17] KEY A2
E11 VSS201 AL9 VSS43 VSS123 U4 H16 RSVD_TP_86 RSVD62 D15
E8 VSS202 AL6 VSS44 VSS124 U2 RSVD63 C15
E5 VSS203 AL3 VSS45 VSS125 T35 RSVD64 AJ15
E2 AT35 H_NCTF1 PAD T4 AK29 T34 AH15
VSS204 VSS_NCTF1 H_NCTF2 VSS46 VSS126 RSVD65
D33 VSS205 VSS_NCTF2 AT1 PAD T5 AK27 VSS47 VSS127 T33
D30 VSS206 VSS_NCTF3 AR34 AK25 VSS48 VSS128 T32 B19 RSVD15
D26 VSS207 VSS_NCTF4 B34 AK20 VSS49 VSS129 T31 A19 RSVD16
D9 B2 AK17 T30
NCTF

VSS208 VSS_NCTF5 H_NCTF6 VSS50 VSS130

D6 VSS209 VSS_NCTF6 B1 PAD T6 AJ31 VSS51 VSS131 T29 A20 RSVD17
D3 A35 H_NCTF7 PAD T7 AJ23 T28 B20
VSS210 VSS_NCTF7 VSS52 VSS132 RSVD18
C34 VSS211 AJ20 VSS53 VSS133 T27 RSVD_TP_66 AA5
C32 VSS212 AJ17 VSS54 VSS134 T26 U9 RSVD19 RSVD_TP_67 AA4
C29 VSS213 AJ14 VSS55 VSS135 T6 T9 RSVD20 RSVD_TP_68 R8
C28 VSS214 AJ11 VSS56 VSS136 R10 RSVD_TP_69 AD3
C24 VSS215 AJ8 VSS57 VSS137 P8 AC9 RSVD21 RSVD_TP_70 AD2
C22 VSS216 AJ5 VSS58 VSS138 P4 AB9 RSVD22 RSVD_TP_71 AA2
C20 VSS217 AJ2 VSS59 VSS139 P2 CFG0 - PCI-Express Configuration Select RSVD_TP_72 AA1
C19 VSS218 AH35 VSS60 VSS140 N35 RSVD_TP_73 R9
C16 VSS219 AH34 VSS61 VSS141 N34 RSVD_TP_74 AG7
B31 AH33 N33 *1:Single PEG C1 AE3
VSS220 VSS62 VSS142 RSVD_NCTF_23 RSVD_TP_75
B25 VSS221 AH32 VSS63 VSS143 N32 0:Bifurcation enabled A3 RSVD_NCTF_24
B B
B21 VSS222 AH31 VSS64 VSS144 N31
B18 VSS223 AH30 VSS65 VSS145 N30 RSVD_TP_76 V4
B17 VSS224 AH29 VSS66 VSS146 N29 RSVD_TP_77 V5
B13 VSS225 AH28 VSS67 VSS147 N28 RSVD_TP_78 N2
B11 VSS226 AH27 VSS68 VSS148 N27 CFG3 - PCI-Express Static Lane Reversal J29 RSVD26 RSVD_TP_79 AD5
B8 VSS227 AH26 VSS69 VSS149 N26 J28 RSVD27 RSVD_TP_80 AD7
B6 VSS228 AH20 VSS70 VSS150 N6 RSVD_TP_81 W3
B4 VSS229 AH17 VSS71 VSS151 M10 *1 :Normal Operation A34 RSVD_NCTF_28 RSVD_TP_82 W2
A29 VSS230 AH13 VSS72 VSS152 L35 0 :Lane Numbers Reversed A33 RSVD_NCTF_29 RSVD_TP_83 N3
A27 VSS231 AH9 VSS73 VSS153 L32 15 -> 0, 14 -> 1, ... RSVD_TP_84 AE5
A23 VSS232 AH6 VSS74 VSS154 L29 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
A9 VSS233 AH3 VSS75 VSS155 L8 B35 RSVD_NCTF_31
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2 VSS AP34
AF4 VSS78 VSS158 K34 CFG4 - Display Port Presence
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30
*1:Disabled; No Physical Display Port
attached to Embedded Display Port IC,AUB_CFD_rPGA,R0P9
0:Enabled; An external Display Port @

IC,AUB_CFD_rPGA,R0P9 IC,AUB_CFD_rPGA,R0P9
device is connected to the Embedded
@ @ Display Port

*:Default

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU GND/RESERVED/XDP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Tuesday, March 23, 2010 Sheet 10 of 45
5 4 3 2 1
 5 4 3 2 1

+1.5V +1.5V

1
JDDRL
2
DDR3 SO-DIMM A M1 Circuit
+VREF_DQA
DDR_A_D0
3
5
VREF_DQ
VSS
VSS
DQ4 4
6
DDR_A_D4
DDR_A_D5
Standard Type <7> DDR_A_DQS[0..7] +1.5V
2 1

0.1U_0402_16V4Z

2.2U_0603_6.3V4Z
DQ0 DQ5 <7> DDR_A_DQS#[0..7] +VREF_DQB
1 1 DDR_A_D1 7 8 R78 0_0402_5%
DQ1 VSS

1
9 10 DDR_A_DQS#0 <7> DDR_A_D[0..63]
VSS DQS0# +1.5V
C156

C157
DDR_A_DM0 11 12 DDR_A_DQS0 R79
DM0 DQS0 1K_0402_1%
13 VSS VSS 14 <7> DDR_A_DM[0..7]
2 2 DDR_A_D2 DDR_A_D6 +V_DDR3_DIMM_REF
15 DQ2 DQ6 16

1
DDR_A_D3 17 18 DDR_A_D7 <7> DDR_A_MA[0..15]

2
DQ3 DQ7 R83
19 VSS VSS 20 2 1 +VREF_DQA
DDR_A_D8 21 22 DDR_A_D12 1K_0402_1% R80 0_0402_5%
DQ8 DQ12

1
D DDR_A_D9 23 24 DDR_A_D13 PS@ D
DQ9 DQ13 R81
25 26

2
DDR_A_DQS#1 VSS VSS DDR_A_DM1 1K_0402_1%
close to JDDRL.1 27 DQS1# DM1 28
DDR_A_DQS1 29 30
DQS1 RESET# SM_DRAMRST# <5,12>
31 32

2
DDR_A_D10 VSS VSS DDR_A_D14
33 DQ10 DQ14 34
DDR_A_D11 35 36 DDR_A_D15
DQ11 DQ15
37 VSS VSS 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_A_D22
DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS DDR_A_D28
55 VSS DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_A_DQS#3
DDR_A_DM3 VSS DQS3# DDR_A_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS VSS 72

<7> DDRA_CKE0 73 CKE0 CKE1 74 DDRA_CKE1 <7>

75 VDD VDD 76
C 77 78 DDR_A_MA15 C
NC A15 DDR_A_MA14
<7> DDR_A_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD VDD 100
<7> DDRA_CLK0 101 CK0 CK1 102 DDRA_CLK1 <7>
<7> DDRA_CLK0# 103 CK0# CK1# 104 DDRA_CLK1# <7>
105 VDD VDD 106
DDR_A_MA10 107 108
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# <7>
111 VDD VDD 112
<7> DDR_A_W E# 113 WE# S0# 114 DDRA_SCS0# <7>
<7> DDR_A_CAS# 115 CAS# ODT0 116 DDRA_ODT0 <7>
117 VDD VDD 118
DDR_A_MA13 +V_DDR3_DIMM_REF
119 A13 ODT1 120 DDRA_ODT1 <7>
<7> DDRA_SCS1# 121 S1# NC 122
123 124 R89
VDD VDD +DDR_VREF_CA_DIMMA
125 TEST VREF_CA 126 1 2
127 128 0_0402_5%
DDR_A_D32 VSS VSS DDR_A_D36
129 DQ32 DQ36 130
DDR_A_D33 131 132 DDR_A_D37
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

DQ33 DQ37
133 VSS VSS 134
B DDR_A_DQS#4 DDR_A_DM4 B
135 DQS4# DM4 136
DDR_A_DQS4 137 138 1 1 Layout Note: Layout Note: Place these 4 Caps near Layout Note:
DQS4 VSS DDR_A_D38
139 VSS DQ38 140
Place near JDDRL Command and Control signals of DIMMA Place near JDDRL1.203 and 204
C161

C162

DDR_A_D34 141 142 DDR_A_D39

DDR_A_D35 DQ34 DQ39
143 DQ35 VSS 144
DDR_A_D44 2 2
145 VSS DQ44 146
DDR_A_D40 147 148 DDR_A_D45 +1.5V
DDR_A_D41 DQ40 DQ45 C218 1 +1.5V +0.75VS
2 390U_2.5V_M_R10

+
149 DQ41 VSS 150
151 152 DDR_A_DQS#5
DDR_A_DM5 VSS DQS5# DDR_A_DQS5
153 DM5 DQS5 154 close to JDDRL.126
155 156 C164 1 2 0.1U_0402_16V4Z C165 1 2 10U_0805_6.3V6M
DDR_A_D42 VSS VSS DDR_A_D46 C166 1
157 DQ42 DQ46 158 2 10U_0805_6.3V6M
DDR_A_D43 159 160 DDR_A_D47 C167 1 2 0.1U_0402_16V4Z
DQ43 DQ47 C168 1
161 VSS VSS 162 2 10U_0805_6.3V6M C169 2 1 1U_0402_6.3V4Z
DDR_A_D48 163 164 DDR_A_D52 C170 1 2 0.1U_0402_16V4Z
DDR_A_D49 DQ48 DQ52 DDR_A_D53 C171 1
165 DQ49 DQ53 166 2 10U_0805_6.3V6M C172 2 1 1U_0402_6.3V4Z
167 168 C173 1 2 0.1U_0402_16V4Z
DDR_A_DQS#6 VSS VSS DDR_A_DM6 C174 1
169 DQS6# DM6 170 2 10U_0805_6.3V6M C175 2 1 1U_0402_6.3V4Z
DDR_A_DQS6 171 172
DQS6 VSS DDR_A_D54 C176 1
173 VSS DQ54 174 2 10U_0805_6.3V6M C177 2 1 1U_0402_6.3V4Z
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 DQ50 DQ55 C178 1
177 DQ51 VSS 178 2 10U_0805_6.3V6M
179 180 DDR_A_D60
DDR_A_D56 VSS DQ60 DDR_A_D61
181 DQ56 DQ61 182
DDR_A_D57 183 184
DQ57 VSS DDR_A_DQS#7
185 VSS DQS7# 186
DDR_A_DM7 187 188 DDR_A_DQS7
DM7 DQS7
189 VSS VSS 190
A
DDR_A_D58 191 192 DDR_A_D62 A
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
R90 1 2 195 196
10K_0402_5% VSS VSS
197 SA0 EVENT# 198 PM_EXTTS# <5,12>
+3VS 199 VDDSPD SDA 200 PM_SMBDATA <12,13,17,27>
201 202
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

SA1 SCL PM_SMBCLK <12,13,17,27>

10K_0402_5%

203 204
1 1 +0.75VS VTT VTT +0.75VS Security Classification Compal Secret Data Compal Electronics, Inc.
1

C182
C181 205 206 2009/10/05 2010/01/23 Title
GND1 BOSS1 Issued Date Deciphered Date
R91

207 208
2 2 GND2 BOSS2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM0
Size Document Number Rev
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FOX_AS0A626-U2SN-7F_204P Custom 2.0
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 11 of 45
5 4 3 2 1
 A B C D E

+1.5V +1.5V

1
JDDRH
2
Standard Type
+VREF_DQB
DDR_B_D0
3
5
VREF_DQ
VSS
VSS
DQ4 4
6
DDR_B_D4
DDR_B_D5
DDR3 SO-DIMM B
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS 8 <7> DDR_B_DQS#[0..7]
9 10 DDR_B_DQS#0

0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
DDR_B_DM0 VSS DQS0# DDR_B_DQS0
11 DM0 DQS0 12 <7> DDR_B_DQS[0..7]
1 1 13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6 <7> DDR_B_D[0..63]
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
C183

C184
19 VSS VSS 20 <7> DDR_B_DM[0..7]
2 2 DDR_B_D8 DDR_B_D12
21 DQ8 DQ12 22
1 DDR_B_D9 23 24 DDR_B_D13 <7> DDR_B_MA[0..15] 1
DQ9 DQ13
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS1# DM1
29 DQS1 RESET# 30 SM_DRAMRST# <5,11>
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
close to JDDRH.1 35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS DDR_B_D28
55 VSS DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS DQS3# DDR_B_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72

<7> DDRB_CKE0 73 CKE0 CKE1 74 DDRB_CKE1 <7>

75 VDD VDD 76
2 77 78 DDR_B_MA15 2
NC A15 DDR_B_MA14
<7> DDR_B_BS2 79 BA2 A14 80
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
<7> DDRB_CLK0 101 CK0 CK1 102 DDRB_CLK1 <7>
<7> DDRB_CLK0# 103 CK0# CK1# 104 DDRB_CLK1# <7>
105 VDD VDD 106
DDR_B_MA10 107 108
A10/AP BA1 DDR_B_BS1 <7>
<7> DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# <7>
111 VDD VDD 112
<7> DDR_B_W E# 113 WE# S0# 114 DDRB_SCS0# <7>
<7> DDR_B_CAS# 115 CAS# ODT0 116 DDRB_ODT0 <7>
117 VDD VDD 118
DDR_B_MA13 119 120
A13 ODT1 DDRB_ODT1 <7> +V_DDR3_DIMM_REF
<7> DDRB_SCS1# 121 S1# NC 122
123 124 R97
VDD VDD +DDR_VREF_CA_DIMMB
125 TEST VREF_CA 126 1 2 0_0402_5% Layout Note: Layout Note: Place these 4 Caps near Layout Note:
127 VSS VSS 128
DDR_B_D32 129 130 DDR_B_D36 Place near JDDRH Command and Control signals of DIMMB Place near JDDRH.203 and 204
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

DDR_B_D33 DQ32 DQ36 DDR_B_D37

131 DQ33 DQ37 132
133 VSS VSS 134 1 1
3 DDR_B_DQS#4 DDR_B_DM4 +1.5V 3
135 DQS4# DM4 136
DDR_B_DQS4 137 138 @ +1.5V +0.75VS
DQS4 VSS
C187

C188

DDR_B_D38 C189 1 2 330U_B2_2.5VM_R15M

+
139 VSS DQ38 140
DDR_B_D34 DDR_B_D39 2 2
141 DQ34 DQ39 142
DDR_B_D35 143 144 C190 1 2 0.1U_0402_16V4Z C191 1 2 10U_0805_6.3V6M
DQ35 VSS DDR_B_D44 C192 1
145 VSS DQ44 146 2 10U_0805_6.3V6M
DDR_B_D40 147 148 DDR_B_D45 C193 1 2 0.1U_0402_16V4Z
DDR_B_D41 DQ40 DQ45 C194 1
149 DQ41 VSS 150 2 10U_0805_6.3V6M C195 2 1 1U_0402_6.3V4Z
151 152 DDR_B_DQS#5 C196 1 2 0.1U_0402_16V4Z
DDR_B_DM5 VSS DQS5# DDR_B_DQS5 C197 1
153 DM5 DQS5 154 close to JDDRH.126 2 10U_0805_6.3V6M C198 2 1 1U_0402_6.3V4Z
155 156 C199 1 2 0.1U_0402_16V4Z
DDR_B_D42 VSS VSS DDR_B_D46 C200 1
157 DQ42 DQ46 158 2 10U_0805_6.3V6M C201 2 1 1U_0402_6.3V4Z
DDR_B_D43 159 160 DDR_B_D47
DQ43 DQ47 C202 1
161 VSS VSS 162 2 10U_0805_6.3V6M C203 2 1 1U_0402_6.3V4Z
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53 C204 1
165 DQ49 DQ53 166 2 10U_0805_6.3V6M
167 VSS VSS 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
DDR_B_D50 VSS DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS DDR_B_D60
179 VSS DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS 184
185 186 DDR_B_DQS#7
DDR_B_DM7 VSS DQS7# DDR_B_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
4
DDR_B_D58 191 192 DDR_B_D62 4
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
R98 1 2 195 196
10K_0402_5% VSS VSS
197 SA0 EVENT# 198 PM_EXTTS# <5,11>
+3VS 199 VDDSPD SDA 200 PM_SMBDATA <11,13,17,27>
201 SA1 SCL 202 PM_SMBCLK <11,13,17,27>
2.2U_0603_6.3V4Z 1 R99 2 203 204
1 1
10K_0402_5%
+0.75VS VTT VTT +0.75VS Security Classification Compal Secret Data Compal Electronics, Inc.
205 GND1 BOSS1 206 Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title
C207 C208 207 208
2 2 GND2 BOSS2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM1
0.1U_0402_16V4Z Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
FOX_AS0A626-UASN-7F_204P Custom 2.0
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 12 of 45
A B C D E
 A B C D E F G H

Clock Generator For SED For SED

+3VS_CK505

1
For SED For SED
FBMH1608HM601-T_0603 FBMH1608HM601-T_0603 R110
+3VS 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CK505 +1.05VS 1 2 10U_0805_10V4Z 0.1U_0402_16V4Z +1.05VS_CK505 10K_0402_5%
R100 1 1 1 1 R101 1 1 1 1

1
C252

2
2
C209 C210 C211 C212 C251 C219 C220 C221 C222 47P_0402_50V8J CK_PW RGD
@ R401 47P_0402_50V8J

2
0_0603_5% 2 2 2 2 2 2 2 2

3
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1

1
FBMH1608HM601-T_0603 Q35B
+1.5VS 1 2 0.1U_0402_16V4Z +1.5VS_CK505 5
R126 2N7002DW -T/R7_SOT363-6 CLK_ENABLE# <42>
1 1 1

4
For SED C213 C214 C215 For RF
2 2 2
Change C213 to 1U for NALAA 1U_0402_6.3V4Z 0.1U_0402_16V4Z C484
CPU_SEL 1 2 +3VS_CK505
ESATA issue at pre-MP Silego Have Internal Pull-Up
+1.05VS_CK505 100P_0402_50V8J

+3VS_CK505 H_STP_CPU# 10K_0402_5% 2 1 R105

+1.5VS_CK505

+1.05VS_CK505 U5

+3VS_CK505 1 32
VDD_USB_48 SCL PM_SMBCLK <11,12,17,27>
2 VSS_48M SDA 31 PM_SMBDATA <11,12,17,27>
3 30 CPU_SEL 1 2
<17> CLK_DOT DOT_96 REF_0/CPU_SEL CLK_14M_PCH <17>
4 29 33_0402_5% R102
<17> CLK_DOT# DOT_96# VDD_REF
5 28 CLK_XTAL_IN 10K_0402_5% 2 @ 1 R119 +1.05VS
VDD_27 XTAL_IN CLK_XTAL_OUT
6 27MHZ XTAL_OUT 27
7 27MHZ_SS VSS_REF 26
8 25 CK_PW RGD
USB_48 CKPWRGD/PD# CPU_SEL 10K_0402_5% 2 1 R106
9 VSS_27M VDD_CPU 24
<17> CLK_SATA 10 SATA CPU_0 23 CLK_BCLK <17> IDT Have Internal Pull-Down
2 11 22 2
<17> CLK_SATA# SATA# CPU_0# CLK_BCLK# <17>
12 VSS_SRC VSS_CPU 21
<17> PCH_CLK_DMI 13 SRC_1 CPU_1 20
<17> PCH_CLK_DMI# 14 SRC_1# CPU_1# 19 CPU_SEL CPU_0/0# CPU_1/1#
15 VDD_SRC_IO VDD_CPU_IO 18
H_STP_CPU# 16 17 +1.5VS_CK505 CLK_XTAL_OUT
CPU_STOP# VDD_SRC
0 (Default) 133MHz 133MHz
33 Y1
TGND CLK_XTAL_IN 1 2
RTM890N-631-GRT QFN 32P 2 2 1 100MHz 100MHz
14.318MHZ_16PF_7A14300083
C223 C224
22P_0402_50V8J 22P_0402_50V8J
1 1

@
BKOFF# 1 2
Reserve for EMI request +LCD_INV B+ B+ Top layer near H12,
L2 For EMI request C485 330P_0402_50V7K
LCD/PANEL BD. Conn. R93 0_0402_5% 2 1 @
1 2 1 1 FBMA-L11-201209-221LMA30T_0805
1 1 2

0.1U_0402_16V4Z
CAM@ 1
L55 @ C234 C235 @ C236 C268 C489 330P_0402_50V7K
68P_0402_50V8J 0.1U_0402_25V6 680P_0402_50V7K @
USB20_N11_R 2 2 2 @ BKOFF#_R
<20> USB20_N11 1 1 2 2 1 2
EMI 2
C486 0.1U_0402_16V4Z
3 USB20_P11_R 3
<20> USB20_P11 4 4 3 3
1 1
W CM-2012-900T_0805 For ESD request at PVT
C871 C872 W=20mils D84
R92 0_0402_5% 10P_0402_50V8J 10P_0402_50V8J 0_0603_5% 0.1U_0402_16V4Z 2
2 @ 2 @ R388 1 +3VS_LVDS_CAM
1 2 +3VS 2 1 2 1
CAM@ C225 CAM@ 3
CAM@ JLVDS @
For RF request 1 PACDN042Y3R_SOT23-3
USB20_P11_R 1 2 2 LCD_EDID_CLK <19>
3 3 4 4 LCD_EDID_DATA <19>
USB20_N11_R 5 INT_MIC_CLK
5 6 6 INT_MIC_DATA
INT_MIC_CLK <30>
7 7 8 8 INT_MIC_DATA <30>
+LCD_VDD +3VS LCD_TXOUT0+ LED_PW M_R R387 2 FBMA-10-100505-301T
<19> LCD_TXOUT0+ 9 9 10 10 1 PCH_PW M <19>
LCD_TXOUT0- 11 12 BKOFF#_R 2 1
<19> LCD_TXOUT0- 11 12 BKOFF# <31>
LCD_TXOUT1+ 13 14 33_0402_5% R103
<19> LCD_TXOUT1+ 13 14
1

LCD_TXOUT1- 15
R107 +3VS <19> LCD_TXOUT1-
LCD_TXOUT2+ 15 16 16 R113
1 2
10K_0402_5%
<19> LCD_TXOUT2+ 17 17 18 18
150_0603_5% R108 W=60mils LCD_TXOUT2- 19
100K_0402_5%
<19> LCD_TXOUT2-
LCD_TXCLK+ 19 20 20 +3VS
<19> LCD_TXCLK+ 21 21 22 22 1.5A
LCD_TXCLK- 23
<19> LCD_TXCLK- 24 24 +LCD_VDD
6 2

23
2 25 25 26 26 1 1
C228 27
0.1U_0402_16V7K 27 28 28 +LCD_INV
C226 C227
1 1
29 29 30 30
3

S
Q1A 0.1U_0402_16V4Z 4.7U_0805_10V4Z @ C231 C232
2N7002DW -T/R7_SOT363-6 1 G
Q17 2 2 680P_0402_50V7K 0.1U_0402_16V4Z
2 1 2 2 31 GND1
R109 47K_0402_5% AO3413_SOT23 EMI 2 2
1 32 GND2
3

C229 D
1

0.01U_0402_25V7K +LCD_VDD ACES_87242-3001-09

4 2 W=60mils 4
<19> UMA_ENVDD 5
Q1B
2N7002DW -T/R7_SOT363-6 1
4
2

C233
R112 0.1U_0402_16V4Z
100K_0402_5% 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator (CK505)/ LVDS CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 13 of 45
A B C D E F G H
 A B C D E

CRT CONNECTOR

1
D3 D4 D5

+3VS
1 DAN217_SC59 DAN217_SC59 DAN217_SC59 1

3
@ @ @

L3
1 2 CRT_R_L
<19> UMA_CRT_R
NBQ100505T-800Y_0402

L4
1 2 CRT_G_L
<19> UMA_CRT_G
NBQ100505T-800Y_0402

L5
1 2 CRT_B_L
<19> UMA_CRT_B
NBQ100505T-800Y_0402

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
150_0402_1%

150_0402_1%

150_0402_1%
1 1 1 1 1 1
1

1
R138 R139 R140 C238 C239 C240 C241 C242 C243
2 2 2 2 2 2 +5VS
D6 +CRT_VCC_R +CRT_VCC
2

2
2 F1 30mil
1 1 2
3 RB491D_SOT23-3 1
1.1A_6V_MINISMDC110F-2
If=1A C237
@ 0.1U_0402_16V4Z
2 2 2

+CRT_VCC

1 2 2 1 JCRT
C244 0.1U_0402_16V4Z R141 10K_0402_5% 6 6
5
1

11 11
CRT_R_L 1
OE#
P

D_CRT_HSYNC HSYNC 1
<19> UMA_CRT_HSYNC 2 A Y 4 1 2 7 7
L6 10_0402_5% CRT_DDC_DAT 12 12
G

U6 CRT_G_L 2
SN74AHCT1G125GW _SOT353-5 D_CRT_VSYNC VSYNC 2
1 2 8
3

L7 10_0402_5% HSYNC 8
13 13
CRT_B_L 3

10P_0402_50V8J

10P_0402_50V8J
+CRT_VCC 3
1 1 +CRT_VCC 9 9
VSYNC 14 16
C245 C246 14 G
4 4 G 17
5
1

@ @ 10
2 2 CRT_DDC_CLK 10
15
OE#
P

15
<19> UMA_CRT_VSYNC 2 A Y 4 5 5
G

U7 ALLTO_C10532-11505-L_15P-T
SN74AHCT1G125GW _SOT353-5 @
3

3 3

+3VS

+CRT_VCC
2

R146 R147
4.7K_0402_5% 4.7K_0402_5%
2

Q2A
1

<19> UMA_CRT_DATA 1 6 CRT_DDC_DAT

5

Q2B 2N7002DW -T/R7_SOT363-6

<19> UMA_CRT_CLK 4 3 CRT_DDC_CLK

1 1
1 1 2N7002DW -T/R7_SOT363-6
C249 C250
C247 C248 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title
CRT\TV\LVDS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 14 of 45
A B C D E
 5 4 3 2 1

HDMI CEC Controller U17 Address:0011010X

<31,36> EC_SMB_CK1 1 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 11 CEC_INT# <31>+3VL
+3VL +3VL

+3VL 2 12 CEC_TEST 1 CEC@2

P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# R171 4.7K_0402_5%

2
R190 D9 2 1CEC_RST# 3 RESET# P1_4/TXD0 13 CEC_FSHUPD1 CEC@2
10K_0402_5% CH751H-40PT_SOD323-2 R172 4.7K_0402_5% R174 4.7K_0402_5%
CEC@ CEC@ CEC@ CEC_FSHUPD (Pin13)
2 2 1CEC_XOUT 4 14 Low= Force to update flash. +3VL

1 1
HDMI_CECIN R178 47K_0402_5% XOUT/P4_7 P1_3/KI3#/AN11/TZOUT
D D
+3VL
CEC@
R581 5 15 +3VL
VSS/AVSS P1_2/KI2#/AN10/CMP0_2

1
27K_0402_5% 1 CEC@2 R192
1

Q49 D CEC@ C848 1U_0402_6.3V4Z 4.7K_0402_5% R193

2 2 1CEC_XIN 6 16 1 CEC@2 CEC@ 4.7K_0402_5%

2
XIN/P4_6 P4_2/VREF

2
G HDMI_CEC R179 47K_0402_5% C319 0.1U_0402_16V4Z CEC@
2N7002_SOT23-3 S CEC@

G
3

2
CEC@ 7 17 HDMI_CLK
VCC/AVCC P1_1/KI1#/AN9/CMP0_1 HDMI_SCLK HDMI_CLK
1 3
1

2
D Q50 Q51
HDMI_CECOUT 1 R191 HDMI_DATA +3VL Q47 BSH111_SOT23-3

G
2 2 2 1 8 MODE P1_0/KI0#/AN8/CMP0_0 18
27K_0402_5% G R176 4.7K_0402_5% BSH111_SOT23-3 CEC@
CEC@ S 2N7002_SOT23-3 C317 1 CEC@ HDMI_SDATA CEC@ 1 3 HDMI_DATA
3
1

CEC@ 0.1U_0402_16V4Z HDMI_CECIN 9 19 HDMI_HPD_R 2 CEC@ 1

R181 CEC@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0 R570

S
100K_0402_5% 10K_0402_5%
CEC@ 2 HDMI_CECOUT 10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA1 <31,36>
2

10/14 HDMI_HPD_R pull-up to +3VL

R5F211A4C33SP-W 4_LSSOP20
CEC@

10/14 Remove R691 and change BOM Structure to CEC@

+3VS 10/15 Add circuit to control +3VS
OE# pin for save power consumption
+5VL CEC@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1
R145 1 1 1 1 1 1 1 1
HDMI_HPD_U 1 2 HDMI_HPD R1429 C256 C266 C257 C258 C262 C263 C261 C260
2 1K_0402_5% 10K_0402_5% IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@ IHDMI@
C264 IHDMI@ 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2

2
5

C 0.1U_0402_16V4Z U9 OE# U10 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C

CEC@ 1
P

OE#

2 4 HDMI_HPD_R
A Y

6
+3VS 25 OE# 2 @ 1
G

CEC@ OE* R159 10K_0402_5% +HDMI_5V_OUT

Q6A 2
3

2N7002KDW _SOT363-6 HDMI_HPD VCC3V HDMI_SCLK

2 11 VCC3V SCL_SINK 28 1 IHDMI@ 2
74AHCT1G125GW _SOT353-5 1 15 R122 2.2K_0402_5%
VCC3V

2
R170 C430 21 29 HDMI_SDATA 1 IHDMI@ 2

1
IHDMI@ IHDMI@ VCC3V SDA_SINK R123 2.2K_0402_5%
26 VCC3V
100K_0402_5% 0.1U_0402_16V4Z 33
2 VCC3V HDMI_HPD 10/14 HDMI_HPD connect to U10.30
40 VCC3V HPD_SINK 30
46

1
VCC3V DDC_EN R168 2
DDC_EN 32 1 4.7K_0402_5% +3VS
IHDMI@
D53
PMEG2010AEH_SOD123 F2 IHDMI@ +3VS R167 1 IHDMI@ 2 2.2K_0402_5% 3 34 R162 2 IHDMI@ 1 2.2K_0402_5%
+HDMI_5V_OUT_F R158 IHDMI@ 2 2.2K_0402_5% FUNCTION1 FUNCTION3 R165 @ 0_0402_5%
+5VS 2 1 2 1 +HDMI_5V_OUT 1 4 FUCNTION2 FUNCTION4 35 2 1 +3VS
1 R163 1 @ 2 0_0402_5% R166 1 @ 2 0_0402_5%
IHDMI@ 1.1A_6V_MINISMDC110F-2 C259 R154 1 @ 2 0_0402_5% R164 1 @ 2 0_0402_5%
IHDMI@ IHDMI@ 2 R160 1 6
D54 0.1U_0402_16V4Z 3.48K_0402_1% ANALOG1(REXT)
2
+5VL 2 1 <19,21> PCH_HDMI_HPD 7 HPD_SOURCE
PMEG2010AEH_SOD123 8
<19> UMA_HDMI_DATA SDA_SOURCE
IHDMI@ HDMI_R_CK- R157 2 1 UMA_DVI_TXC-
0_0402_5% IHDMI@ 9
<19> UMA_HDMI_CLK SCL_SOURCE
Add D54 for HDMI CEC issue at pre-MP L8
2 1 R689
2 1
1 2 IHDMI@ 10 ANALOG2
2.2K_0402_5%
B 3 4 IHDMI@ B
3 4 UMA_DVI_TXC+ HDMI_TXC+ C279 1
13 OUT_D4+ IN_D4+ 48 2 0.1U_0402_16V7K UMA_HDMI_TXC+ <19>
W CM-2012-900T_0805 @ UMA_DVI_TXC- 14 47 HDMI_TXC- C280 1 2 0.1U_0402_16V7K
OUT_D4- IN_D4- UMA_HDMI_TXC- <19>
HDMI_R_CK+ R173 2 1 UMA_DVI_TXC+ IHDMI@ IHDMI@
0_0402_5% IHDMI@ UMA_DVI_TXD2+ 16 45 HDMI_TX2+ C281 1 2 0.1U_0402_16V7K
OUT_D3+ IN_D3+ UMA_HDMI_TX2+ <19>
UMA_DVI_TXD2- 17 44 HDMI_TX2- C282 1 2 0.1U_0402_16V7K
OUT_D3- IN_D3- UMA_HDMI_TX2- <19>
IHDMI@ IHDMI@
HDMI_R_D0+ R175 2 1 UMA_DVI_TXD0+ UMA_DVI_TXD1+ 19 42 HDMI_TX1+ C283 1 2 0.1U_0402_16V7K
HDMI Connector 0_0402_5% IHDMI@
L9
UMA_DVI_TXD1- 20
OUT_D2+
OUT_D2-
IN_D2+
IN_D2- 41 HDMI_TX1- C284 1
IHDMI@
2 0.1U_0402_16V7K
IHDMI@
UMA_HDMI_TX1+ <19>
UMA_HDMI_TX1- <19>
2 1 UMA_DVI_TXD0+ 22 39 HDMI_TX0+ C285 1 2 0.1U_0402_16V7K
2 1 OUT_D1+ IN_D1+ UMA_HDMI_TX0+ <19>
JHDMI @ UMA_DVI_TXD0- 23 38 HDMI_TX0- C286 1 2 0.1U_0402_16V7K
OUT_D1- IN_D1- UMA_HDMI_TX0- <19>
19 HDMI_HPD IHDMI@
HP_DET
+5V 18 +HDMI_5V_OUT 3 3 4 4
DDC/CEC_GND 17 Add R130 for AOC monitor
16 HDMI_SDATA W CM-2012-900T_0805 @ 1
SDA
15 HDMI_SCLK HDMI_R_D0- R180 2 1 UMA_DVI_TXD0- 5
GND issue at PVT
SCL 0_0402_5% IHDMI@ GND
Reserved 14 12 GND
13 HDMI_CEC 18
CEC HDMI_R_CK- GND HDMI_TXC-
20 GND CK- 12 24 GND
21 GND CK_shield 11 27 GND THERMAL_PAD 49

1
22 10 HDMI_R_CK+ HDMI_R_D1- R182 2 1 UMA_DVI_TXD1- 31
GND CK+ HDMI_R_D0- 0_0402_5% IHDMI@ GND R130
23 GND D0- 9 36 GND
8 L10 37 2.2K_0402_5%
D0_shield HDMI_R_D0+ GND IHDMI@
D0+ 7 2 2 1 1 43 GND
6 HDMI_R_D1-

2
D1- R161
D1_shield 5
4 HDMI_R_D1+ 3 4 +3VS 2 1 PCH_HDMI_HPD IHDMI@ ASM1442 QFN_48P_7X7
D1+ HDMI_R_D2- 3 4
D2- 3
2 W CM-2012-900T_0805 @ 10K_0402_5%
D2_shield
2

1 HDMI_R_D2+ HDMI_R_D1+ R183 2 1 UMA_DVI_TXD1+ @

D2+ 0_0402_5% IHDMI@ R189
A A
TYCO_1939864-1_19P 100K_0402_5%

HDMI_R_D2+ R187 2 1 UMA_DVI_TXD2+

1

0_0402_5% IHDMI@
L11
2 2 1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
3 3 4 4 Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

W CM-2012-900T_0805 @
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI/HCMI-CEC
HDMI_R_D2- R188 2 1 UMA_DVI_TXD2- AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0_0402_5% IHDMI@ 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 15 of 45
5 4 3 2 1
 5 4 3 2 1

C287
CMOS Setting, near DDR Door 15P_0402_50V8J
JCMOS 2 1
+RTCVCC 1 2PCH_RTCRST# 1 2
R282 20K_0402_1% Y3

10M_0402_5%
1
1 2 3 NC OSC 4

R283
C288 1U_0402_6.3V4Z
iME Setting. J2
2 NC OSC 1 U11A
1 2PCH_SRTCRST# 1 2 32.768KHZ_12.5PF_Q13MC14610002

2
R284 20K_0402_1% PCH_RTCX1 B13 D33
RTCX1 FWH0 / LAD0 LPC_AD0 <31,32>
1 2 2 1 PCH_RTCX2 D13 B33
RTCX2 FWH1 / LAD1 LPC_AD1 <31,32>
C289 1U_0402_6.3V4Z C290 15P_0402_50V8J C32
FWH2 / LAD2 LPC_AD2 <31,32>
D
FWH3 / LAD3 A32 LPC_AD3 <31,32> D
PCH_RTCRST# C14 RTCRST#
FWH4 / LFRAME# C34 LPC_FRAME# <31,32>
+RTCVCC PCH_SRTCRST# D17 SRTCRST#
A34

RTC

LPC
SM_INTRUDER# LDRQ0#
Integrated SUS 1.05V VRM Enable 1
R285
2
1M_0402_5%
A16 INTRUDER# LDRQ1# / GPIO23 F34 FELICA_PW R <26>

High - Enable Internal VRs 1 2 PCH_INTVRMEN A14 AB9 SERIRQ

INTVRMEN SERIRQ SERIRQ <31,32>
PCH_INTVRMEN (must be always pulled high) R275 330K_0402_5%
1 2 +3VS
R286 10K_0402_5%
AZ_BITCLK A30 HDA_BCLK
SATA0RXN AK7
AZ_SYNC D29 AK6
HDA_SYNC HDA_SYNC SATA0RXP
AK11
PCH_SPKR SATA0TXN
This signal has a weak internal pull down. <19,30> PCH_SPKR P1 SPKR SATA0TXP AK9
H=>On Die PLL is supplied by 1.5V
AZ_RST#
*L=>On Die PLL is supplied by 1.8V C30 HDA_RST#
SATA1RXN AH6 SATA_PRX_C_DTX_N1 <25>
SATA1RXP AH5 SATA_PRX_C_DTX_P1 <25>
HDA_SDO <30> AZ_SDIN0_HD G30 HDA_SDIN0 SATA1TXN AH9 SATA_PTX_DRX_N1 <25> 1ST HDD
SATA1TXP AH8 SATA_PTX_DRX_P1 <25>
This signal has a weak internal pull down. <26> AZ_SDIN1_MD F30 HDA_SDIN1
This signal can't PU SATA2RXN AF11
E32 AF9

IHDA
HDA_SDIN2 SATA2RXP
SATA2TXN AF7
F32 HDA_SDIN3 SATA2TXP AF6
Flash Descriptor Security Overide Desktop Only
SATA3RXN AH3
C
Low = Enabled @ R118 1K_0402_5% AZ_SDOUT B29 AH1 C
HDA_SDO SATA3RXP
HDA_DOCK_EN# High = Disabled * 1 2 SATA3TXN AF3
SATA3TXP AF1
<31> PW RME_CTRL# H32

SATA
HDA_DOCK_EN# / GPIO33
SATA4RXN AD9 SATA_PRX_C_DTX_N4 <25>
CR_CPPE# J30 AD8
<29> CR_CPPE# HDA_DOCK_RST# / GPIO13 SATA4RXP SATA_PRX_C_DTX_P4 <25>
<26> AZ_BITCLK_MD R287 1 MDC@ 2 33_0402_5% AD6 SATA ODD
SATA4TXN SATA_PTX_DRX_N4 <25>
<30> AZ_BITCLK_HD R288 1 2 33_0402_5% AZ_BITCLK AD5
SATA4TXP SATA_PTX_DRX_P4 <25>

<26> AZ_SYNC_MD R289 1 MDC@ 2 33_0402_5% PCH_JTAG_TCK M3 AD3

JTAG_TCK SATA5RXN SATA_PRX_C_DTX_N5 <25>
<30> AZ_SYNC_HD R290 1 2 33_0402_5% AZ_SYNC AD1
SATA5RXP SATA_PRX_C_DTX_P5 <25>
PCH_JTAG_TMS K3 AB3 eSATA
JTAG_TMS SATA5TXN SATA_PTX_DRX_N5 <25>
<26> AZ_RST_MD# R291 1 MDC@ 2 33_0402_5% AB1
SATA5TXP SATA_PTX_DRX_P5 <25>
<30> AZ_RST_HD# R292 1 2 33_0402_5% AZ_RST# PCH_JTAG_TDI K1 JTAG_TDI

JTAG
<26> AZ_SDOUT_MD R293 1 MDC@ 2 33_0402_5% PCH_JTAG_TDO J2 AF16
R294 1 JTAG_TDO SATAICOMPO
<30> AZ_SDOUT_HD 2 33_0402_5% AZ_SDOUT
PCH_JTAG_RST# J4 AF15 SATAICOMP 1 2
TRST# SATAICOMPI +1.05VS
R295 37.4_0402_1%

+3VS
PCH_SPI_CLK BA2 SPI_CLK
PCH_SPI_CS0# AV3 SPI_CS0# CR_W AKE# R302 2 1 10K_0402_5%
ITPM Enabled Internal: Pull down 20k AY3 T3 SATA_LED#
+3VS SPI_CS1# SATALED# SATA_LED# <33>

High = Enabled
SPI_MOSI 2 @ 1PCH_SPI_MOSI AY1 Y9 CR_W AKE# SATA_LED# R301 2 1 10K_0402_5%
B Low = Disabled (Default) SPI_MOSI SATA0GP / GPIO21 CR_W AKE# <29> B
R273 1K_0402_5%

SPI
PCH_SPI_MISO AV1 V1 PCH_GPIO19
SPI_MISO SATA1GP / GPIO19
PCH_GPIO19 R306 1 2 10K_0402_5%
IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@

+3VALW +3VALW +3VALW +3VALW

Socket: SP07000F500 & SP07000H900

1

@ @ @
R386 R363 @ R643
200_0402_5% 200_0402_5% R536 20K_0402_5% +3VS
200_0402_5%
4MB
2

PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_RST#

1
1

@ @ @ U13 +RTCBATT
R355 R535 @ R364 C293 8 4
VCC VSS

1
100_0402_5% 100_0402_5% R537 10K_0402_5% 0.1U_0402_16V4Z for EMI request
100_0402_5% 2
3 W PCH_SPI_CLK D13
2

7 BAS40-04_SOT23-3
HOLD

1
+RTCVCC
PCH_SPI_CS0# 1 R385

2
S @ 10_0402_5%
+CHGRTC
PCH_SPI_CLK 6 1
C C291

2
1 2 PCH_JTAG_TCK PCH_SPI_MOSI 5 2 PCH_SPI_MISO 1 Change netname to +CHGRTC
R156 51_0402_5% D Q @ C16 0.1U_0402_16V4Z
A
06/01 change R125 from 4.7K to 51 ohm MX25L3205DM2I-12G SO8 10P_0402_50V8J 2 for RTC issue at pre-MP A

PCH JTAG Enable PCH JTAG Disable (Default) 2

PCH Pin RefDes ES1 ES2 ES1 ES2
PCH_JTAG_TDO R358 No Install 200ohm No Install No Install
R535 No Install 100ohm No Install No Install
PCH_JTAG_TMS R355 200ohm 200ohm No Install No Install Security Classification Compal Secret Data Compal Electronics, Inc.
R354 100ohm 100ohm No Install No Install 2009/10/05 2010/01/23 Title
PCH_JTAG_TDI R536 200ohm 200ohm 20Kohm No Install Issued Date Deciphered Date
R537 100ohm 100ohm 10Kohm No Install
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH-SPI/SATA/LPC/RTC/HDA
PCH_JTAG_TCK R156 51ohm 51ohm 51ohm 51ohm Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PCH_JTAG_RST# R643 20Kohm 20Kohm No Install No Install B 2.0
R353 10Kohm 10Kohm No Install No Install
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 16 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS
+3VALW 2 R229 1 2.2K_0402_5%
2 R230 1 2.2K_0402_5% R231 4.7K_0402_5%

5
Q3B R232 4.7K_0402_5%

PCH_SMBDATA 3 4 PM_SMBDATA <11,12,13,27>

2
Q3A 2N7002DW -T/R7_SOT363-6

PCH_SMBCLK 6 1 PM_SMBCLK <11,12,13,27>

2N7002DW -T/R7_SOT363-6

D U11B D

PCIE_PRX_C_LANTX_N1 BG30 B9 EC_LID_OUT# EC_LID_OUT# <31>

<28> PCIE_PRX_C_LANTX_N1 PERN1 SMBALERT# / GPIO11
For LAN PCIE_PRX_C_LANTX_P1 BJ30
<28> PCIE_PRX_C_LANTX_P1 PERP1
<28> PCIE_PTX_C_LANRX_N1 C371 2 1 0.1U_0402_16V7K PCIE_PTX_LANRX_N1 BF29 H14 PCH_SMBCLK
C340 2 PETN1 SMBCLK
<28> PCIE_PTX_C_LANRX_P1 1 0.1U_0402_16V7K PCIE_PTX_LANRX_P1 BH29 PETP1
C8 PCH_SMBDATA
SMBDATA
<27> PCIE_PRX_W LANTX_N2 AW30 PERN2
<27> PCIE_PRX_W LANTX_P2 BA30 PERP2 +3VS
For WLAN <27> PCIE_PTX_C_W LANRX_N2 C274 2 1 0.1U_0402_16V7K PCIE_PTX_W LANRX_N2 BC30 J14 PCH_GPIO60 +3VALW 2 R233 1 2.2K_0402_5%
C275 2 PETN2 SML0ALERT# / GPIO60
<27> PCIE_PTX_C_W LANRX_P2 1 0.1U_0402_16V7K PCIE_PTX_W LANRX_P2 BD30
PETP2 2 R234 1 2.2K_0402_5%

5
C6 PCH_SMLCLK0 Q4B
PCIE_PRX_NEW TX_N3 SML0CLK
AU30

SMBus
<27> PCIE_PRX_NEW TX_N3 PERN3
For NewCard NEW @ PCIE_PRX_NEW TX_P3 AT30 G8 PCH_SMLDATA0 PCH_SMLDATA1 3 4
<27> PCIE_PRX_NEW TX_P3 PERP3 SML0DATA EC_SMB_DA2 <31,32,33>
<27> PCIE_PTX_C_NEW RX_N3 C269 2 1 0.1U_0402_16V7K PCIE_PTX_NEW RX_N3 AU32 PETN3

2
<27> PCIE_PTX_C_NEW RX_P3 C270 2 1 0.1U_0402_16V7K PCIE_PTX_NEW RX_P3 AV32 Q4A 2N7002DW -T/R7_SOT363-6
PETP3 PCH_GPIO74
SML1ALERT# / GPIO74 M14
<27> PCIE_PRX_JETTX_N4 NEW @ BA32 PCH_SMLCLK1 6 1
PERN4 EC_SMB_CK2 <31,32,33>
<27> PCIE_PRX_JETTX_P4 BB32 E10 PCH_SMLCLK1
C312 1 PERP4 SML1CLK / GPIO58
For JET <27> PCIE_PTX_C_JETRX_N4 2 0.1U_0402_16V7K PCIE_PTX_JETRX_N4 BD32 PETN4
2N7002DW -T/R7_SOT363-6
C301 1 2 0.1U_0402_16V7K PCIE_PTX_JETRX_P4 BE32 G12 PCH_SMLDATA1
<27> PCIE_PTX_C_JETRX_P4 PETP4 SML1DATA / GPIO75

PCI-E*
<29> PCIE_PRX_C_CRTX_N5 BF33 PERN5
<29> PCIE_PRX_C_CRTX_P5 BH33 PERP5 CL_CLK1 T13

Controller
For Card Reader C302 1 2 0.1U_0402_16V7K PCIE_PTX_CRRX_N5 BG32
<29> PCIE_PTX_C_CRRX_N5 PETN5
C868 1 2 0.1U_0402_16V7K PCIE_PTX_CRRX_P5 BJ32 T11
<29> PCIE_PTX_C_CRRX_P5 PETP5 CL_DATA1 +3VALW

Link
BA34 PERN6 CL_RST1# T9
C AW34 C
PERP6 PCH_SMLCLK0 2.2K_0402_5% R237
BC34 PETN6 2 1
BD34 PCH_SMLDATA0 2.2K_0402_5% 2 1 R238
PETP6 CLKREQ_PEG# PCH_GPIO60 10K_0402_5% R239
PEG_A_CLKRQ# / GPIO47 H1 1 2 +3VALW 2 1
AT34 R260 10K_0402_5% PCH_GPIO74 10K_0402_5% 2 1 R240
PERN7 EC_LID_OUT# 10K_0402_5% R241
AU34 PERP7 2 1
AU36 PETN7 CLKOUT_PEG_A_N AD43
AV36 PETP7 CLKOUT_PEG_A_P AD45
NC BG34 AN4 CLK_PEG# <5>
PERN8 CLKOUT_DMI_N

PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_PEG <5>
BG36 PETN8
BJ36 PETP8
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
<28> CLK_LAN# AK48 CLKOUT_PCIE0N
LAN <28> CLK_LAN AK47 CLKOUT_PCIE0P

From CLK BUFFER

CLKIN_DMI_N AW24 PCH_CLK_DMI# <13>
CLKREQ_LAN# P9 BA24 PCH_CLK_DMI <13>
<28> CLKREQ_LAN# PCIECLKRQ0# / GPIO73 CLKIN_DMI_P

+3VS AM43 AP3

<27> CLK_W LAN# CLKOUT_PCIE1N CLKIN_BCLK_N CLK_BCLK# <13>
CLKREQ_NEW #
WLAN <27> CLK_W LAN AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_BCLK <13> FROM CLK GEN FOR: 133/100/96/14.318 MHZ
1 2
10K_0402_5% R244 CLKREQ_W LAN# U4
<27> CLKREQ_W LAN# PCIECLKRQ1# / GPIO18
CLKIN_DOT_96N F18 CLK_DOT# <13>
1 2 CLKREQ_W LAN# E18 CLK_DOT <13>
10K_0402_5% R248 CLKIN_DOT_96P
<27> CLK_NEW # AM47 CLKOUT_PCIE2N
B
NewCard <27> CLK_NEW AM48 CLKOUT_PCIE2P B
CLKIN_SATA_N / CKSSCD_N AH13 CLK_SATA# <13>
CLKREQ_NEW # N4 AH12 CLK_SATA <13> R247 1M_0402_5%
+3VALW <27> CLKREQ_NEW # PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P
2 1

1 2 CLKREQ_LAN# AH42 P41 CLK_14M_PCH <13> Y2

<27> CLK_JET# CLKOUT_PCIE3N REFCLK14IN
10K_0402_5% R246 JET AH41 PCH_X1 1 2 PCH_X2
<27> CLK_JET CLKOUT_PCIE3P
1 2 CLKREQ_JET# <27> CLKREQ_JET# CLKREQ_JET# A8 J42 1 25MHZ_20PF_7A25000012 1
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCILOOP <20>
10K_0402_5% R245 C277 C278

1 2 CLKREQ_CR# AM51 AH51 PCH_X1 27P_0402_50V8J 27P_0402_50V8J

<29> CLK_CR# CLKOUT_PCIE4N XTAL25_IN 2 2
10K_0402_5% R249 Card Reader AM53 AH53 PCH_X2
<29> CLK_CR CLKOUT_PCIE4P XTAL25_OUT
1 2 PCH_GPIO44 CLKREQ_CR# M9 AF38 XCLK_RCOMP 1 2 +1.05VS
10K_0402_5% R250 PCIECLKRQ4# / GPIO26 XCLK_RCOMP R252 90.9_0402_1%

1 2 PCH_GPIO56 AJ50 T45 Note: Stuff 0 ohm if

10K_0402_5% R251 CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64 C277 @
AJ52 CLKOUT_PCIE5P 0_0402_5% 25MHz crystal un-stuff
PCH_GPIO44 H6 P43
Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65

AK53 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66 T42 for EMI request

AK51 CLKOUT_PEG_B_P @
PCH_GPIO56 P13 N50 CLK_PCILOOP 1 @ 2 1 2
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67 R125 10_0402_5%
C265 22P_0402_50V8J
A
IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ @ A
CLK_14M_PCH 1 @ 2 2 1
R70 100_0402_5%
C206 100P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CLK/PCIE/SMBUS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 17 of 45
5 4 3 2 1
 5 4 3 2 1

@
PM_PW ROK 1 2

C481 330P_0402_50V7K
@
D 1 2 D

C482 330P_0402_50V7K U11C

@ BA18
FDI_RXN0 FDI_CTX_PRX_N0 <6>
1 2 <6> DMI_CTX_PRX_N0 BC24 DMI0RXN FDI_RXN1 BH17 FDI_CTX_PRX_N1 <6>
<6> DMI_CTX_PRX_N1 BJ22 DMI1RXN FDI_RXN2 BD16 FDI_CTX_PRX_N2 <6>
C483 330P_0402_50V7K AW20 BJ16
<6> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN3 FDI_CTX_PRX_N3 <6>
<6> DMI_CTX_PRX_N3 BJ20 DMI3RXN FDI_RXN4 BA16 FDI_CTX_PRX_N4 <6>
FDI_RXN5 BE14 FDI_CTX_PRX_N5 <6>
For ESD request at PVT <6> DMI_CTX_PRX_P0 BD24 DMI0RXP FDI_RXN6 BA14 FDI_CTX_PRX_N6 <6>
<6> DMI_CTX_PRX_P1 BG22 DMI1RXP FDI_RXN7 BC12 FDI_CTX_PRX_N7 <6>
<6> DMI_CTX_PRX_P2 BA20 DMI2RXP
<6> DMI_CTX_PRX_P3 BG20 DMI3RXP FDI_RXP0 BB18 FDI_CTX_PRX_P0 <6>
FDI_RXP1 BF17 FDI_CTX_PRX_P1 <6>
<6> DMI_PTX_CRX_N0 BE22 DMI0TXN FDI_RXP2 BC16 FDI_CTX_PRX_P2 <6>
<6> DMI_PTX_CRX_N1 BF21 DMI1TXN FDI_RXP3 BG16 FDI_CTX_PRX_P3 <6>
+3VALW BD20 AW16
<6> DMI_PTX_CRX_N2 DMI2TXN FDI_RXP4 FDI_CTX_PRX_P4 <6>
<6> DMI_PTX_CRX_N3 BE18 DMI3TXN FDI_RXP5 BD14 FDI_CTX_PRX_P5 <6>
FDI_RXP6 BB14 FDI_CTX_PRX_P6 <6>
1 2 PCH_SUSPW RDN BD22 BD12
<6> DMI_PTX_CRX_P0 DMI0TXP FDI_RXP7 FDI_CTX_PRX_P7 <6>
R316 10K_0402_5% BH21
<6> DMI_PTX_CRX_P1 DMI1TXP
1 2 PCH_LOW _BAT# BC20
<6> DMI_PTX_CRX_P2 DMI2TXP
R318 10K_0402_5% BD18 BJ14
<6> DMI_PTX_CRX_P3 DMI3TXP FDI_INT FDI_INT <6>
1 2 IBEX_RI#

DMI
FDI
R320 10K_0402_5% BF13
FDI_FSYNC0 FDI_FSYNC0 <6>
+1.05VS 1 2 DMI_COMP BH25
R311 49.9_0402_1% DMI_ZCOMP
FDI_FSYNC1 BH13 FDI_FSYNC1 <6>
2 1 PM_PW ROK BF25
R329 10K_0402_5% DMI_IRCOMP
BJ12
C 2 1 PW ROK Close to PCH FDI_LSYNC0 FDI_LSYNC0 <6> C
R322 10K_0402_5% BG14
FDI_LSYNC1 FDI_LSYNC1 <6>
2 1 LAN_RST#
R323 10K_0402_5%

2 @ 1
0_0402_5% R256

+3VS XDP_DBRESET# T6 J12 EC_SW I# EC_SW I# 2 1

<5> XDP_DBRESET# SYS_RESET# WAKE# EC_SW I# <27,28> +3VALW
0.1U_0402_16V4Z R313 10K_0402_5%
1 2
C272 VGATE M6 Y1 PM_CLKRUN# 2 1 +3VS
<31,42> VGATE SYS_PWROK CLKRUN# / GPIO32
5

U12 R319 8.2K_0402_5%

1 IN1
P

<31> PM_PW ROK

System Power Management

4 PW ROK B17
VGATE O PWROK
2 IN2
G

SN74AHC1G08DCKR_SC70-5 1 2 K5 P8 SUS_STAT# PADT38

PADT38
3

R321 0_0402_5% MEPWROK SUS_STAT# / GPIO61

LAN_RST# A10 F3 SUS_CLK PADT39

PADT39
LAN_RST# SUSCLK / GPIO62
For ESD request at PVT
<5> DRAMPW ROK D9 DRAMPWROK SLP_S5# / GPIO63 E4 PM_SLP_S5# <31>
@
PM_SLP_S4# 2 1
PCH_RSMRST# C16 H7
RSMRST# SLP_S4# PM_SLP_S4# <31>
C490 0.1U_0402_16V7K
B @ B
PCH_SUSPW RDN M1 P12 2 1
<31> PCH_SUSPW RDN SUS_PWR_DN_ACK / GPIO30 SLP_S3# PM_SLP_S3# <31>
C491 0.1U_0402_16V7K
P5 K8 @
<31> PBTN_OUT# PWRBTN# SLP_M#
2 1

+3VALW 1 2 PCH_ACIN P7 N2 C492 0.1U_0402_16V7K

R324 330K_0402_5% ACPRESENT / GPIO31 TP23
D26
1 2 PCH_LOW _BAT# A6 BJ10 @
<31,33,35> ACIN BATLOW# / GPIO72 PMSYNCH PMSYNCH <5>
PM_SLP_S5# 2 1
CH751H-40PT_SOD323-2
IBEX_RI# F14 F6 C493 0.1U_0402_16V7K
RI# SLP_LAN# / GPIO29 @
2 1
IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@
+3VALW C494 0.1U_0402_16V7K
@
1 2 2 1
R690 1K_0402_5%
0_0402_5% @1 2 R325 C495 0.1U_0402_16V7K

Q26 1 PCH_RSMRST#
C

<31> EC_RSMRST# 3
E

2 1
MMBT3906_SOT23-3 R326
10K_0402_5%
B
2

+3VALW 2 1
A
R327 A
1

4.7K_0402_5%
D15A D15B
BAV99DW -7_SOT363 BAV99DW -7_SOT363

Security Classification Compal Secret Data Compal Electronics, Inc.

6

1 2
RSMRST# circuit R328
2.2K_0402_5%
Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH-DMI/FDI/PWM
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 18 of 45
5 4 3 2 1
 5 4 3 2 1

U11D
EC_ENBKL T48 BJ46
<31> EC_ENBKL L_BKLTEN SDVO_TVCLKINN
1 2 EC_ENBKL T47 BG46
<13> UMA_ENVDD L_VDD_EN SDVO_TVCLKINP
R124 100K_0402_5%
<13> PCH_PW M Y48 L_BKLTCTL SDVO_STALLN BJ48
SDVO_STALLP BG48
<13> LCD_EDID_CLK AB48 L_DDC_CLK
<13> LCD_EDID_DATA Y45 L_DDC_DATA SDVO_INTN BF45
SDVO_INTP BH45
1 2 LCTL_CLK AB46
+3VS L_CTRL_CLK
+3VS 1 R1433 2 10K_0402_5% LCTL_DATA V48 L_CTRL_DATA
R54 10K_0402_5%
1 2 LVDS_IBG AP39 T51
LCD_EDID_CLK R55 2.37K_0402_1% LVD_IBG SDVO_CTRLCLK
D 2 1 AP41 LVD_VBG SDVO_CTRLDATA T53 D
R59 2.2K_0402_5% T15 PAD
AT43 LVD_VREFH
2 1 LCD_EDID_DATA AT42 BG44
R60 2.2K_0402_5% LVD_VREFL DDPB_AUXN
DDPB_AUXP BJ44
DDPB_HPD AU38 2 1

LVDS
<13> LCD_TXCLK- AV53 R68 100K_0402_5%
LVDSA_CLK# +3VS
<13> LCD_TXCLK+ AV51 LVDSA_CLK DDPB_0N BD42
DDPB_0P BC42
<13> LCD_TXOUT0- BB47 LVDSA_DATA#0 DDPB_1N BJ42
BA52 BG42

Digital Display Interface

<13> LCD_TXOUT1- LVDSA_DATA#1 DDPB_1P

1
<13> LCD_TXOUT2- AY48 LVDSA_DATA#2 DDPB_2N BB40
AV47 BA40 R120 R121
LVDSA_DATA#3 DDPB_2P 2.2K_0402_5% 2.2K_0402_5%
DDPB_3N AW38
BB48 BA38 IHDMI@ IHDMI@
<13> LCD_TXOUT0+ LVDSA_DATA0 DDPB_3P
<13> LCD_TXOUT1+ BA50

2
LVDSA_DATA1
<13> LCD_TXOUT2+ AY49 LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49 UMA_HDMI_CLK <15>
DDPC_CTRLDATA AB49 UMA_HDMI_DATA <15>
AP48 LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
DDPC_AUXP BD44
AY53 LVDSB_DATA#0 DDPC_HPD AV40 PCH_HDMI_HPD <15,21>
AT49 LVDSB_DATA#1
+3VS AU52 BE40
LVDSB_DATA#2 DDPC_0N UMA_HDMI_TX2- <15>
AT53 LVDSB_DATA#3 DDPC_0P BD40 UMA_HDMI_TX2+ <15>
DDPC_1N BF41 UMA_HDMI_TX1- <15>
2 1 UMA_CRT_CLK AY51 BH41
LVDSB_DATA0 DDPC_1P UMA_HDMI_TX1+ <15>
C R63 2.2K_0402_5% AT48 BD38 C
LVDSB_DATA1 DDPC_2N UMA_HDMI_TX0- <15>
AU50 LVDSB_DATA2 DDPC_2P BC38 UMA_HDMI_TX0+ <15>
2 1 UMA_CRT_DATA AT51 BB36
LVDSB_DATA3 DDPC_3N UMA_HDMI_TXC- <15>
R61 2.2K_0402_5% BA36
DDPC_3P UMA_HDMI_TXC+ <15>

<14> UMA_CRT_B AA52 CRT_BLUE DDPD_CTRLCLK U50

1 2 UMA_CRT_B AB53 U52
<14> UMA_CRT_G CRT_GREEN DDPD_CTRLDATA
R56 150_0402_1% AD53
<14> UMA_CRT_R CRT_RED
1 2 UMA_CRT_G
R57 150_0402_1% BC46
UMA_CRT_R DDPD_AUXN
1 2 <14> UMA_CRT_CLK V51 CRT_DDC_CLK DDPD_AUXP BD46
R58 150_0402_1% <14> UMA_CRT_DATA V53 AT38 2 1
CRT_DDC_DATA DDPD_HPD R77 100K_0402_5%
DDPD_0N BJ40
<14> UMA_CRT_HSYNC Y53 CRT_HSYNC DDPD_0P BG40
<14> UMA_CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38

CRT
DDPD_2N BF37
2 R266 1CRT_IREF AD48 DAC_IREF DDPD_2P BH37
AB51 CRT_IRTN DDPD_3N BE36
1K_0402_1% BD36
DDPD_3P
IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@

+3VS
+1.8VS_PCH_NAND
B B

2 @ 1 NV_ALE NV_ALE <20>

1 @ 2 PCH_SPKR R267 1K_0402_5%
PCH_SPKR <16,30>
R269 1K_0402_5%
2 @ 1 NV_CLE NV_CLE <20>
R268 1K_0402_5%

1K_0402_5% 2 @ 1 R270 PCI_GNT#0

PCI_GNT#0 <20>
1K_0402_5% 2 @ 1 R271 PCI_GNT#1
PCI_GNT#1 <20>

2 @ 1 PCI_GNT#3
PCI_GNT#3 <20>
R272 1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH-CRT/LVDS/HDMI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 19 of 45
5 4 3 2 1
 5 4 3 2 1

1 2
R253 @ 0_0402_5%
+3VS

1 2
C477 0.1U_0402_16V4Z

5
U8
U11E 1 PLT_RST#

P
IN1
H40 AD0 NV_CE#0 AY9 <5> BUF_PLT_RST# 4 O
N34 AD1 NV_CE#1 BD1 IN2 2

G
1
D C44 AD2 NV_CE#2 AP15 D

2
A38 BD8 SN74AHC1G08DCKR_SC70-5

3
AD3 NV_CE#3 R129 R51
C36 AD4
J34 AV9 100K_0402_5% 100K_0402_5%
AD5 NV_DQS0 @
A40 BG8

2
AD6 NV_DQS1
D45

1
AD7
E36 AD8 NV_DQ0 / NV_IO0 AP7
H48 AD9 NV_DQ1 / NV_IO1 AP6
E40 AD10 NV_DQ2 / NV_IO2 AT6
C40 AD11 NV_DQ3 / NV_IO3 AT9
M48 AD12 NV_DQ4 / NV_IO4 BB1
M45 AD13 NV_DQ5 / NV_IO5 AV6
F53 AD14 NV_DQ6 / NV_IO6 BB3
M40 AD15 NV_DQ7 / NV_IO7 BA4

NVRAM
M43 AD16 NV_DQ8 / NV_IO8 BE4
J36 AD17 NV_DQ9 / NV_IO9 BB6
K48 AD18 NV_DQ10 / NV_IO10 BD6
F40 AD19 NV_DQ11 / NV_IO11 BB7
+3VS C42 BC8
RP1 AD20 NV_DQ12 / NV_IO12
K46 AD21 NV_DQ13 / NV_IO13 BJ8
1 8 PCI_REQ#1 M51 BJ6
AD22 NV_DQ14 / NV_IO14
2 7 J52 AD23 NV_DQ15 / NV_IO15 BG6
3 6 PCI_PIRQD# K51
PCI_IRDY# AD24
4 5 L34 AD25 NV_ALE BD3 NV_ALE <19>
F42 AD26 NV_CLE AY6 NV_CLE <19>
8.2K_0804_8P4R_5% J40 AD27
G46 AD28
RP2 F44 AU2 NV_RCOMP 1 @ 2
PCI_PIRQH# AD29 NV_RCOMP R276 32.4_0402_1%
1 8 M47 AD30

PCI
C 2 7 PCI_TRDY# H36 AV7 C
PCI_FRAME# AD31 NV_RB#
3 6
4 5 PCI_PIRQA# J50 AY8
C/BE0# NV_WR#0_RE#
G42 C/BE1# NV_WR#1_RE# AY5
8.2K_0804_8P4R_5% H47 C/BE2#
G34 C/BE3# NV_WE#_CK0 AV11
RP3 BF5
PCI_STOP# PCI_PIRQA# NV_WE#_CK1
1 8 G38 PIRQA#
2 7 PCI_PIRQE# PCI_PIRQB# H51
PCI_PIRQC# PCI_PIRQC# PIRQB#
3 6 B37 PIRQC# USBP0N H18 USB20_N0 <25>
4 5 PCI_PIRQG# PCI_PIRQD# A44 J18 USB-RIGHT1
PIRQD# USBP0P USB20_P0 <25>
USBP1N A18 USB20_N1 <25>
8.2K_0804_8P4R_5% PCI_REQ#0 F51 C18 USB-RIGHT2
REQ0# USBP1P USB20_P1 <25>
PCI_REQ#1 A46 N20
REQ1# / GPIO50 USBP2N USB20_N2 <25>
ODD_EN# B45 P20 USB-Left1
<34> ODD_EN# REQ2# / GPIO52 USBP2P USB20_P2 <25>
PCI_REQ#3 M53 J20
+3VS REQ3# / GPIO54 USBP3N USB20_N3 <25>
RP4 USBP3P L20 USB20_P3 <25> eSATA-USB
<19> PCI_GNT#0 F48 GNT0# USBP4N F20 USB20_N4 <27>
1 8 PCI_REQ#3 K45 G20 NewCard
<19> PCI_GNT#1 GNT1# / GPIO51 USBP4P USB20_P4 <27>
2 7 PCI_PIRQF# GNT2#: Not F36 A20
GNT2# / GPIO53 USBP5N USB20_N5 <26>
3 6 PCI_PIRQB# H53 C20 BT
pull low, <19> PCI_GNT#3 GNT3# / GPIO55 USBP5P USB20_P5 <26>
4 5 PCI_REQ#0 M22 Swap USB port4 and port8 at PVT
PCI_PIRQE# USBP6N
internal pull B41 PIRQE# / GPIO2 USBP6P N22
8.2K_0804_8P4R_5% PCI_PIRQF# K53 B21 HM55 USB port6/7 NC
up 20K PCI_PIRQG# PIRQF# / GPIO3 USBP7N
A36 PIRQG# / GPIO4 USBP7P D21
PCI_PIRQH# A48 H22
+3VS PIRQH# / GPIO5 USBP8N USB20_N8 <26>
USBP8P J22 USB20_P8 <26> FPM

USB
RP5 K6 E22
T37 PAD PCIRST# USBP9N USB20_N9 <26>
1 8 PCI_DEVSEL# F22 Felica
B USBP9P USB20_P9 <26> B
2 7 PCI_PERR# PCI_SERR# E44 A22
SERR# USBP10N USB20_N10 <27>
3 6 PCI_SERR# PCI_PERR# E50 C22 TV#2
PERR# USBP10P USB20_P10 <27>
4 5 PCI_PLOCK# G24
USBP11N USB20_N11 <13>
8.2K_0804_8P4R_5% PCI_IRDY# USBP11P H24 USB20_P11 <13> Int. Camera
A42 IRDY# USBP12N L24 USB20_N12 <27>
PCI_DEVSEL#
H44 PAR USBP12P M24 USB20_P12 <27> 3G/TV#1
F46 DEVSEL# USBP13N A24 USB20_N13 <27>
PCI_FRAME# C46 C24 WiMax(WLAN)
FRAME# USBP13P USB20_P13 <27>
PCI_PLOCK# D49 PLOCK#
USBRBIAS# B25
PCI_STOP# D41 +3VALW
PCI_TRDY# STOP# USBBIAS
C48 TRDY# USBRBIAS D25 2
R278
1
22.6_0402_1%
Within 500 mils RP6
M7 SLP_CHG_M4 4 5
PME# USB_OC#0 USB_OC#4
OC0# / GPIO59 N16 USB_OC#0 <25,31> (USB-Right) 3 6
PLT_RST# D5 J16 USB_OC#1 USB_OC#1 <25,31> (USB-Left & eSATA) USB_OC#0 2 7
<27,28,29,31,32> PLT_RST# PLTRST# OC1# / GPIO40
F16 USB_OC#2 SLP_CHG_M3 1 8
OC2# / GPIO41 USB_OC#3
N52 CLKOUT_PCI0 OC3# / GPIO42 L16
P53 E14 USB_OC#4 10K_0804_8P4R_5%
CLKOUT_PCI1 OC4# / GPIO43
2 1 CLK_SIO P46 CLKOUT_PCI2 OC5# / GPIO9 G16 SLP_CHG_M3
SLP_CHG_M3 <25>
<32> CLK_PCI_DDR 22_0402_5% R280
2 1 CLK_EC P51 CLKOUT_PCI3 OC6# / GPIO10 F12 SLP_CHG_M4
SLP_CHG_M4 <25> RP8
<31> CLK_PCI_EC 22_0402_5% R281
<17> CLK_PCILOOP 2 1 CLK_PCH P48 CLKOUT_PCI4 OC7# / GPIO14 T15 EXP_CPPE#
EXP_CPPE# <27>
22_0402_5% R279 USB_OC#2 4 5
USB_OC#1 3 6
IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ USB_OC#3 2 7
EXP_CPPE# 1 8

A
10K_0804_8P4R_5% A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH USB/PCI/NAND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 20 of 45
5 4 3 2 1
 5 4 3 2 1

U11F

<15,19> PCH_HDMI_HPD PCH_HDMI_HPD Y3 AH45

BMBUSY# / GPIO0 CLKOUT_PCIE6N
CLKOUT_PCIE6P AH46
D GPIO8 PCH_GPIO1 C38 D
TACH1 / GPIO1
Not pull down PCH_GPIO6 D37 TACH2 / GPIO6
Internal: Pull up 20k CLKOUT_PCIE7N AF48

MISC
EC_SCI# J32 AF47
During Reset: High <31> EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
Initial: High <31> EC_SMI# EC_SMI# F10 GPIO8
GPIO15 PCH_GPIO12 K9 U2 GATEA20
LAN_PHY_PWR_CTRL / GPIO12 A20GATE GATEA20 <31>
a Strong pull up may be needed
PCH_GPIO15 T7
for GPIO Functionality GPIO15
Internal: Pull down 20k PCH_GPIO16 AA2 AM3
SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# <5>
During Reset: Low RF_OFF#
<27> RF_OFF# F38 TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P AM1 CLK_CPU_BCLK <5>
Initial: Low
BT_DET# Y7 BG10
<26> BT_DET# SCLOCK / GPIO22 PECI PECI <5>

GPIO
H10 T1 KB_RST#
GPIO24 RCIN# KB_RST# <31>
On-Die PLL VR @ PCH_GPIO27
2 1 AB12 GPIO27 PROCPWRGD BE10 H_PW RGOOD <5>

CPU
High = Enabled (Default) R274 1K_0402_5%
PCH_GPIO27 PCH_GPIO28 V13 BD10 THRMTRIP_PCH# 1 2
Low = Disabled GPIO28 THRMTRIP# H_THERMTRIP# <5>
R212 56_0402_1%
<26,27> BT_PW R# M11 STP_PCI# / GPIO34
+3VS V6
<26> BT_RST# SATACLKREQ# / GPIO35
1 2 +VTT
PROJECT_ID0 AB7 BA22 R210 56_0402_1%
C SATA2GP / GPIO36 TP1 C
1 2 PCH_GPIO1 PROJECT_ID1 AB13 SATA3GP / GPIO37 TP2 AW22
10K_0402_5% R214
1 2 PCH_GPIO6 PCH_GPIO38 V3 SLOAD / GPIO38 TP3 BB22
10K_0402_5% R218
1 2 EC_SCI# CIR_EN# P3 AY45
10K_0402_5% R224 SDATAOUT0 / GPIO39 TP4
1 2 PCH_GPIO16 LVDS_SEL H3 PCIECLKRQ6# / GPIO45 TP5 AY46
10K_0402_5% R221
1 2 RF_OFF# <5> RST_GATE
RST_GATE F1 PCIECLKRQ7# / GPIO46 TP6 AV43
10K_0402_5% R220
1 2 BT_DET# <27> ISDBT_DET ISDBT_DET AB6 AV45
8.2K_0402_5% R215 SDATAOUT1 / GPIO48 TP7
1 2 PCH_GPIO38 <31> THM_ALT#
THM_ALT# AA4 SATA5GP / GPIO49 TP8 AF13
10K_0402_5% R217
1 2 CIR_EN# PCH_GPIO57 F8 GPIO57 TP9 M18
100K_0402_5% R254
@ 1 2 PROJECT_ID0 N18
10K_0402_5% R255 TP10
1 2 PROJECT_ID1 A4 VSS_NCTF_1 TP11 AJ24
10K_0402_5% R216 A49

NCTF
VSS_NCTF_2

RSVD
1 2 ISDBT_DET A5 VSS_NCTF_3 TP12 AK41
@ 10K_0402_5% R257 A50 VSS_NCTF_4
1 2 THM_ALT# A52 VSS_NCTF_5 TP13 AK42
10K_0402_5% R259 A53 VSS_NCTF_6
B2 VSS_NCTF_7 TP14 M32
B4 VSS_NCTF_8
B52 VSS_NCTF_9 TP15 N32 PROJECT_ID1 PROJECT_ID0 2010 Project ID setting
B53 VSS_NCTF_10
B B
BE1 VSS_NCTF_11 TP16 M30
BE53 VSS_NCTF_12 0 0 NBQAA (Streamline-M/-S 11.6/13.3")
BF1 VSS_NCTF_13 TP17 N30
BF53 VSS_NCTF_14
+3VALW BH1 VSS_NCTF_15 TP18 H12 0 1 NBQAA (Bordeuax 14")
BH2 VSS_NCTF_16
BH52 VSS_NCTF_17 TP19 AA23
1 2 EC_SMI# BH53 1 0 NWQAA (Marseille 16")
R225 10K_0402_5% VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
1 2 PCH_GPIO57 BJ2 VSS_NCTF_20
R226 10K_0402_5% BJ4 AB38 1 1 NALAA (Hamburg 17.3")
VSS_NCTF_21 NC_2
1 2 PCH_GPIO15 BJ49 VSS_NCTF_22
R227 1K_0402_5% BJ5 AB42
VSS_NCTF_23 NC_3
1 2 PCH_GPIO28 BJ50 VSS_NCTF_24
R242 10K_0402_5% LVDS_SEL=H BJ52 AB41
VSS_NCTF_25 NC_4
1 2 LVDS_SEL BJ53
R222 10K_0402_5% for Single Channel LVDS D1
VSS_NCTF_26
T39
VSS_NCTF_27 NC_5
1 2 RST_GATE D2 VSS_NCTF_28 Not pull low
R223 10K_0402_5% D53 VSS_NCTF_29 internal pull up
1 2 PCH_GPIO12 E1 VSS_NCTF_30 INIT3_3V# P6
10K_0402_5% R219 E53 VSS_NCTF_31
TP24 C10 Internal: Pull up 20k
IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@
During Reset: High
Initial: High
1 2 PROJECT_ID0
R416 10K_0402_5%
1 @ 2 PROJECT_ID1
A
R415 10K_0402_5% A
1 @ 2 BT_RST#
R228 10K_0402_5%
1 2 ISDBT_DET
R261 47K_0402_5%
1 CIR@ 2 CIR_EN#
R461 10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH CPU/GPIO
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 21 of 45
5 4 3 2 1
 5 4 3 2 1

Add R52 for CRT wave issue at pre-MP

+1.05VS +3VS
U11G POWER +3VS_VCCADAC
R52 L12
AB24 VCCCORE[1] VCCADAC[1] AE50 1 2 2 1
1 1 AB26 69mA 2 1 0_0603_5% 2.2_0603_1%
C295 C294 VCCCORE[2]
AB28 VCCCORE[3] VCCADAC[2] AE52
10U_0805_10V4Z 1U_0402_6.3V4Z AD26 C296 C297 C298 Change L12 to 2.2 ohm
VCCCORE[4]

CRT
D AD28 AF53 0.01U_0402_25V7K 0.1U_0402_16V4Z 10U_0805_10V4Z D
2 2
AF26
VCCCORE[5] VSSA_DAC[1] 1 2 for CRT issue at pre-MP
VCCCORE[6]

VCC CORE
AF28 VCCCORE[7] VSSA_DAC[2] AF51
AF30 VCCCORE[8] close to AE50
AF31 VCCCORE[9]
AH26 VCCCORE[10]
AH28 VCCCORE[11]
AH30 VCCCORE[12]
AH31 VCCCORE[13] > 1mA VCCALVDS AH38 +3VS
AJ30 VCCCORE[14]
AJ31 VCCCORE[15] VSSA_LVDS AH39

+1.05VS 1432mA
VCCTX_LVDS[1] AP43 +1.8VS
59mA VCCTX_LVDS[2] AP45
AT46

LVDS
VCCTX_LVDS[3] C300 C299
AK24 VCCIO[24] VCCTX_LVDS[4] AT45
0.01U_0402_25V7K 0.01U_0402_25V7K
+3VS
BJ24 VCCAPLLEXP 40mA
VCC3_3[2] AB34

AN20 VCCIO[25] 375mA VCC3_3[3] AB35

AN22 2

HVCMOS
VCCIO[26] 0.1U_0402_16V4Z
AN23 VCCIO[27] VCC3_3[4] AD35
AN24 C303
VCCIO[28]
AN26 VCCIO[29] 1
AN28 VCCIO[30] close to AB34
BJ26 VCCIO[31]
C BJ28 C
VCCIO[32]
AT26 VCCIO[33]
AT28 VCCIO[34]
+1.05VS AU26 VCCIO[35] +PCH_VRM
AU28 VCCIO[36]
1 2 AV26 VCCIO[37]
C304 10U_0805_10V4Z AV28 196mA AT24
VCCIO[38] VCCVRM[2]
1 2 AW26 VCCIO[39]
C305 1U_0402_6.3V4Z AW28 3062mA
VCCIO[40] +VTT

DMI
1 2 BA26 VCCIO[41] VCCDMI[1] AT16
C306 1U_0402_6.3V4Z +PCH_VRM +1.8VS
BA28 VCCIO[42] 61mA +PCH_VCCDMI
1 2 BB26 VCCIO[43] VCCDMI[2] AU16 1 2
C307 1U_0402_6.3V4Z BB28 1 R335 0_0603_5%
VCCIO[44] C309
1 2 BC26 VCCIO[45] 2 1

PCI E*
C308 1U_0402_6.3V4Z BC28 1U_0402_6.3V4Z R336 0_0402_5%
VCCIO[46]
BD26 VCCIO[47] 2
BD28 VCCIO[48] close to AT16
BE26 VCCIO[49] VCCPNAND[1] AM16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 AK19 +1.8VS_PCH_NAND +1.8VS
VCCIO[52] VCCPNAND[4]
BH27 VCCIO[53] VCCPNAND[5] AK15
156mA VCCPNAND[6] AK13 1
R338
2
0_0603_5%
AN30 VCCIO[54] VCCPNAND[7] AM12 2

NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
+3VS AM15 C311
VCCPNAND[9] 0.1U_0402_16V4Z
1
2 1 AN35 VCC3_3[1] 375mA close to Ak13
C310 0.1U_0402_16V4Z
B B

+PCH_VRM AT22 VCCVRM[1] +3VS

BJ18 VCCFDIPLL 37mA VCCME3_3[1] AM8
VCCME3_3[2] AM9
FDI

+1.05VS AM23 VCCIO[1] 85mA VCCME3_3[3] AP11 2

VCCME3_3[4] AP9
C313 0.1U_0402_16V4Z
1
close to AM8
IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH POWER-1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Tuesday, March 23, 2010 Sheet 22 of 45
5 4 3 2 1
 5 4 3 2 1

U11J POWER +1.05VS

AP51 VCCACLK[1] VCCIO[5] V24

52mA VCCIO[6] V26 1
C316
AP53 VCCACLK[2] 3062mA VCCIO[7] Y24
VCCIO[8] Y26
1U_0402_6.3V4Z
AF23 V28 2
VCCLAN[1] VCCSUS3_3[1]
VCCSUS3_3[2] U28
VccLAN may be grounded if Intel LAN is disabled AF24 VCCLAN[2] 320mA VCCSUS3_3[3] U26
VCCSUS3_3[4] U24
D VCCSUS3_3[5] P28 D
2 1 +TP_PCH_VCCDSW Y20 P26 +3VALW
C320 0.1U_0402_16V4Z DCPSUSBYP VCCSUS3_3[6]
VCCSUS3_3[7] N28
Near AD38 VCCSUS3_3[8] N26
+1.05VS AD38 VCCME[1] VCCSUS3_3[9] M28
1 1 1 VCCSUS3_3[10] M26 2 2
AD39 L28 C321 C325

USB
C391 C322 C318 VCCME[2] VCCSUS3_3[11]
VCCSUS3_3[12] L26
If two VccME rails can be 22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V4Z AD41 J28 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 VCCME[3] VCCSUS3_3[13] 1 1
J26
combined, only total 2 x 22 ȝF and AF43
VCCSUS3_3[14]
H28
VCCME[4] VCCSUS3_3[15]
2 x 1 ȝF caps are necessary 163mA VCCSUS3_3[16] H26
AF41 VCCME[5] VCCSUS3_3[17] G28
1849mA VCCSUS3_3[18] G26
AF42 VCCME[6] VCCSUS3_3[19] F28
Near V39 VCCSUS3_3[20] F26
V39 E28 +3VALW +5VALW
VCCME[7] VCCSUS3_3[21]
1 1 1 E26

Clock and Miscellaneous

VCCSUS3_3[22]
V41 C28

CH751H-40PT_SOD323-2
C447 C323 C324 VCCME[8] VCCSUS3_3[23]
VCCSUS3_3[24] C26

1
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V4Z V42 B27
2 2 2 VCCME[9] VCCSUS3_3[25] D16 R344
VCCSUS3_3[26] A28
Y39 VCCME[10] VCCSUS3_3[27] A26
100_0402_1%
Y41 U23

2
VCCME[11] VCCSUS3_3[28] +3VS +5VS
Y42 VCCME[12] VCCIO[56] V23 +1.05VS

1
F24 +PCH_VCC5REFSUS 2 1
V5REF_SUS C326 1U_0402_6.3V4Z D17 R346
+VCCRTCEXT
> 1mA
C 1 2 V9 DCPRTC CH751H-40PT_SOD323-2 C
C327 0.1U_0402_16V4Z 100_0402_1%

2
+1.05VS L17 1 2 196mA > 1mA K49 +PCH_VCC5REF +PCH_VCC5REF
10UH_LB2012T100MR_20% V5REF
1 +PCH_VRM AU24

PCI/GPIO/LPC
VCCVRM[3]
1 1
1

C328 + C329 +3VS C330

220U_6.3V_M_R15 1U_0402_6.3V4Z R347 +1.05VS_PCHDPLL_A
68mA VCC3_3[8] J38
BB51 VCCADPLLA[1]
0_0603_5% BB53 L38 1U_0402_6.3V4Z
2 2 @ VCCADPLLA[2] VCC3_3[9] 2
2
69mA M36 C333
2

L18 1 +1.05VS_PCHDPLL_B VCC3_3[10] 0.1U_0402_16V4Z

2
10UH_LB2012T100MR_20%
BD51 VCCADPLLB[1] 375mA
1 BD53 VCCADPLLB[2] VCC3_3[11] N36
1
1
C331 + C332 1U_0402_6.3V4Z AH23 P36
+1.05VS VCCIO[21] VCC3_3[12]
220U_6.3V_M_R15 1U_0402_6.3V4Z 1 1 1 AJ35 VCCIO[22]
AH35 VCCIO[23] VCC3_3[13] U35
2 2 C334 C335 C336 +3VS
1U_0402_6.3V4Z AF34 3062mA
2 2 2 VCCIO[2]
VCC3_3[14] AD13 2 1
1U_0402_6.3V4Z AH34 C337 0.1U_0402_16V4Z
VCCIO[3]
Short AF34, AH34 and AF32 power
AF32
for HDMI Deep Color VCCIO[4]
AK3
+VCCSST VCCSATAPLL[1]
1
C338
2
0.1U_0402_16V4Z
V12 DCPSST 31mA VCCSATAPLL[2] AK1

+1.05VS
1 2 +V1.1A_INT_VCCSUS Y22 DCPSUS
C341 0.1U_0402_16V4Z AH22
B VCCIO[9] B

+3VALW 163mA
For HDA power rail to +1.5V P18 VCCSUS3_3[29] 196mA VCCVRM[4] AT20 +PCH_VRM

1 2 U19

SATA
C343 0.1U_0402_16V4Z VCCSUS3_3[30]

PCI/GPIO/LPC
VCCIO[10] AH19 +1.05VS
U20 VCCSUS3_3[31] 1
U54 AD20 C342
APL5508-25DC-TRL_SOT89-3 VCCIO[11] 1U_0402_6.3V4Z
U22 VCCSUS3_3[32]
+3VALW VCCIO[12] AF22
2 3 +3VS 2
IN OUT +1.5VALW
375mA VCCIO[13] AD19
GND
1
C344
2
0.1U_0402_16V4Z
V15 VCC3_3[5] 3062mA VCCIO[14] AF20
VCCIO[15] AF19
1

@ V16 AH20
C125 1 C126 VCC3_3[6] VCCIO[16]
1U_0603_10V6K 4.7U_0805_6.3V6K +VTT Y16 AB19
2

@ @ VCC3_3[7] VCCIO[17]
VCCIO[18] AB20
1 2 VCCIO[19] AB22
C345 4.7U_0603_6.3V6K +1.05VS
> 1mA VCCIO[20] AD22
1 2 AT18 V_CPU_IO[1]
C346 0.1U_0402_16V4Z AA34 +PCH_VCCME1 R351 1 2 0_0402_5%
CPU

VCCME[13]
1 2 VCCME[14] Y34 +PCH_VCCME2 R352 1 2 0_0402_5%
C347 0.1U_0402_16V4Z AU18 V_CPU_IO[2] 1849mA VCCME[15] Y35 +PCH_VCCME3 R353 1 2 0_0402_5%
VCCME[16] AA35 +PCH_VCCME4 R354 1 2 0_0402_5%
+RTCVCC
RTC

1 2 A12 2mA 6mA L30 +VCC_HDA R356 1 2 0_0402_5% +3VALW

VCCRTC VCCSUSHDA
HDA

C351 0.1U_0402_16V4Z VCCSUSHDA can be

A 1 A
IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@
either 1.5V or 3.3V
1 2 C350 R357 1 2 0_0402_5% +1.5VALW
C348 1U_0402_6.3V4Z @
1U_0402_6.3V4Z
2
1 2 For HDA power rail to +3.3V(default) /+1.5V
C349 0.1U_0402_16V4Z
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH POWER-2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Tuesday, March 23, 2010 Sheet 23 of 45
5 4 3 2 1
 5 4 3 2 1

U11I
AY7 VSS[159] VSS[259] H49
B11 H5 U11H
VSS[160] VSS[260]
B15 VSS[161] VSS[261] J24 AB16 VSS[0]
B19 VSS[162] VSS[262] K11
B23 VSS[163] VSS[263] K43 AA19 VSS[1] VSS[80] AK30
B31 VSS[164] VSS[264] K47 AA20 VSS[2] VSS[81] AK31
B35 VSS[165] VSS[265] K7 AA22 VSS[3] VSS[82] AK32
B39 VSS[166] VSS[266] L14 AM19 VSS[4] VSS[83] AK34
B43 VSS[167] VSS[267] L18 AA24 VSS[5] VSS[84] AK35
B47 VSS[168] VSS[268] L2 AA26 VSS[6] VSS[85] AK38
D B7 VSS[169] VSS[269] L22 AA28 VSS[7] VSS[86] AK43 D
BG12 VSS[170] VSS[270] L32 AA30 VSS[8] VSS[87] AK46
BB12 VSS[171] VSS[271] L36 AA31 VSS[9] VSS[88] AK49
BB16 VSS[172] VSS[272] L40 AA32 VSS[10] VSS[89] AK5
BB20 VSS[173] VSS[273] L52 AB11 VSS[11] VSS[90] AK8
BB24 VSS[174] VSS[274] M12 AB15 VSS[12] VSS[91] AL2
BB30 VSS[175] VSS[275] M16 AB23 VSS[13] VSS[92] AL52
BB34 VSS[176] VSS[276] M20 AB30 VSS[14] VSS[93] AM11
BB38 VSS[177] VSS[277] N38 AB31 VSS[15] VSS[94] BB44
BB42 VSS[178] VSS[278] M34 AB32 VSS[16] VSS[95] AD24
BB49 VSS[179] VSS[279] M38 AB39 VSS[17] VSS[96] AM20
BB5 VSS[180] VSS[280] M42 AB43 VSS[18] VSS[97] AM22
BC10 VSS[181] VSS[281] M46 AB47 VSS[19] VSS[98] AM24
BC14 VSS[182] VSS[282] M49 AB5 VSS[20] VSS[99] AM26
BC18 VSS[183] VSS[283] M5 AB8 VSS[21] VSS[100] AM28
BC2 VSS[184] VSS[284] M8 AC2 VSS[22] VSS[101] BA42
BC22 VSS[185] VSS[285] N24 AC52 VSS[23] VSS[102] AM30
BC32 VSS[186] VSS[286] P11 AD11 VSS[24] VSS[103] AM31
BC36 VSS[187] VSS[287] AD15 AD12 VSS[25] VSS[104] AM32
BC40 VSS[188] VSS[288] P22 AD16 VSS[26] VSS[105] AM34
BC44 VSS[189] VSS[289] P30 AD23 VSS[27] VSS[106] AM35
BC52 VSS[190] VSS[290] P32 AD30 VSS[28] VSS[107] AM38
BH9 VSS[191] VSS[291] P34 AD31 VSS[29] VSS[108] AM39
BD48 VSS[192] VSS[292] P42 AD32 VSS[30] VSS[109] AM42
BD49 VSS[193] VSS[293] P45 AD34 VSS[31] VSS[110] AU20
BD5 VSS[194] VSS[294] P47 AU22 VSS[32] VSS[111] AM46
BE12 VSS[195] VSS[295] R2 AD42 VSS[33] VSS[112] AV22
BE16 VSS[196] VSS[296] R52 AD46 VSS[34] VSS[113] AM49
BE20 VSS[197] VSS[297] T12 AD49 VSS[35] VSS[114] AM7
C BE24 T41 AD7 AA50 C
VSS[198] VSS[298] VSS[36] VSS[115]
BE30 VSS[199] VSS[299] T46 AE2 VSS[37] VSS[116] BB10
BE34 VSS[200] VSS[300] T49 AE4 VSS[38] VSS[117] AN32
BE38 VSS[201] VSS[301] T5 AF12 VSS[39] VSS[118] AN50
BE42 VSS[202] VSS[302] T8 Y13 VSS[40] VSS[119] AN52
BE46 VSS[203] VSS[303] U30 AH49 VSS[41] VSS[120] AP12
BE48 VSS[204] VSS[304] U31 AU4 VSS[42] VSS[121] AP42
BE50 VSS[205] VSS[305] U32 AF35 VSS[43] VSS[122] AP46
BE6 VSS[206] VSS[306] U34 AP13 VSS[44] VSS[123] AP49
BE8 VSS[207] VSS[307] P38 AN34 VSS[45] VSS[124] AP5
BF3 VSS[208] VSS[308] V11 AF45 VSS[46] VSS[125] AP8
BF49 VSS[209] VSS[309] P16 AF46 VSS[47] VSS[126] AR2
BF51 VSS[210] VSS[310] V19 AF49 VSS[48] VSS[127] AR52
BG18 VSS[211] VSS[311] V20 AF5 VSS[49] VSS[128] AT11
BG24 VSS[212] VSS[312] V22 AF8 VSS[50] VSS[129] BA12
BG4 VSS[213] VSS[313] V30 AG2 VSS[51] VSS[130] AH48
BG50 VSS[214] VSS[314] V31 AG52 VSS[52] VSS[131] AT32
BH11 VSS[215] VSS[315] V32 AH11 VSS[53] VSS[132] AT36
BH15 VSS[216] VSS[316] V34 AH15 VSS[54] VSS[133] AT41
BH19 VSS[217] VSS[317] V35 AH16 VSS[55] VSS[134] AT47
BH23 VSS[218] VSS[318] V38 AH24 VSS[56] VSS[135] AT7
BH31 VSS[219] VSS[319] V43 AH32 VSS[57] VSS[136] AV12
BH35 VSS[220] VSS[320] V45 AV18 VSS[58] VSS[137] AV16
BH39 VSS[221] VSS[321] V46 AH43 VSS[59] VSS[138] AV20
BH43 VSS[222] VSS[322] V47 AH47 VSS[60] VSS[139] AV24
BH47 VSS[223] VSS[323] V49 AH7 VSS[61] VSS[140] AV30
BH7 VSS[224] VSS[324] V5 AJ19 VSS[62] VSS[141] AV34
C12 VSS[225] VSS[325] V7 AJ2 VSS[63] VSS[142] AV38
C50 VSS[226] VSS[326] V8 AJ20 VSS[64] VSS[143] AV42
B B
D51 VSS[227] VSS[327] W2 AJ22 VSS[65] VSS[144] AV46
E12 VSS[228] VSS[328] W52 AJ23 VSS[66] VSS[145] AV49
E16 VSS[229] VSS[329] Y11 AJ26 VSS[67] VSS[146] AV5
E20 VSS[230] VSS[330] Y12 AJ28 VSS[68] VSS[147] AV8
E24 VSS[231] VSS[331] Y15 AJ32 VSS[69] VSS[148] AW14
E30 VSS[232] VSS[332] Y19 AJ34 VSS[70] VSS[149] AW18
E34 VSS[233] VSS[333] Y23 AT5 VSS[71] VSS[150] AW2
E38 VSS[234] VSS[334] Y28 AJ4 VSS[72] VSS[151] BF9
E42 VSS[235] VSS[335] Y30 AK12 VSS[73] VSS[152] AW32
E46 VSS[236] VSS[336] Y31 AM41 VSS[74] VSS[153] AW36
E48 VSS[237] VSS[337] Y32 AN19 VSS[75] VSS[154] AW40
E6 VSS[238] VSS[338] Y38 AK26 VSS[76] VSS[155] AW52
E8 VSS[239] VSS[339] Y43 AK22 VSS[77] VSS[156] AY11
F49 VSS[240] VSS[340] Y46 AK23 VSS[78] VSS[157] AY43
F5 VSS[241] VSS[341] P49 AK28 VSS[79] VSS[158] AY47
G10 VSS[242] VSS[342] Y5
G14 Y6 IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@
VSS[243] VSS[343]
G18 VSS[244] VSS[344] Y8
G2 VSS[245] VSS[345] P24
G22 VSS[246] VSS[346] T43
G32 VSS[247] VSS[347] AD51
G36 VSS[248] VSS[348] AT8
G40 VSS[249] VSS[349] AD47
G44 VSS[250] VSS[350] Y47
G52 VSS[251] VSS[351] AT12
AF39 VSS[252] VSS[352] AM6
H16 VSS[253] VSS[353] AT13
H20 VSS[254] VSS[354] AM5
A H30 VSS[255] VSS[355] AK45 A
H34 VSS[256] VSS[356] AK39
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

Security Classification Compal Secret Data Compal Electronics, Inc.

IBEXPEAK-M QV20 A0_FCBGA1071 HM55R1@ 2009/10/05 2010/01/23 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH-GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Tuesday, March 23, 2010 Sheet 24 of 45
5 4 3 2 1
 5 4 3 2 1

SATA HDD Conn. SATA ODD Conn JODD

+5VS Place closely JHDD SATA CONN. 1

GND SATA_PTX_C_DRX_P4 C378 1
1.2A A+ 2 2 0.01U_0402_25V7K SATA_PTX_DRX_P4 <16>
3 SATA_PTX_C_DRX_N4 C377 1 2 0.01U_0402_25V7K
A- SATA_PTX_DRX_N4 <16>
1 1 1 1 GND 4
C356 C357 C358 C359 5 SATA_PRX_DTX_N4 C376 1 2 0.01U_0402_25V7K
B- SATA_PRX_C_DTX_N4 <16>
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 6 SATA_PRX_DTX_P4 C375 1 2 0.01U_0402_25V7K
B+ SATA_PRX_C_DTX_P4 <16>
GND 7
2 2 2 2

DP 8
+5V 9 +5VS_ODD +5VS_ODD
D SSD HDD need 400mA for 3V(PHISON) +5V 10 Place components closely ODD CONN. D
+3VS 11 1.1A
MD
+3VS rail reserve for SSD 15 GND GND 12
14 GND GND 13 1 1 1 1 1
1 1 1 1 C352 C353 C354
C363 C364 C365 C366 @ C355 C360
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z @SANTA_206401-1_RV 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
@ 2 2 2 2 2
2 2 2 2

JHDD
Reserve for EMI request W=60mils
1
GND
A+
A-
2
3
4
SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1
C369 1
C367 1
2 0.01U_0402_25V7K
2 0.01U_0402_25V7K
SATA_PTX_DRX_P1 <16>
SATA_PTX_DRX_N1 <16>
USB Board@ Right Side R73
1
@
0_0402_5%
2
+USB_VCCA
22
21
JPIO
22
@

GND SATA_PRX_DTX_N1 C368 1 21

B- 5 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N1 <16> 20 20
6 SATA_PRX_DTX_P1 C370 1 2 0.01U_0402_25V7K L53 19
B+ SATA_PRX_C_DTX_P1 <16> 19
7 <20> USB20_P0 1 2 USB20_P0_R Add +5VALW and +5VL at DVT 18
GND 1 2 18
17 17
+5VL 1 2 +5V_IO 16
USB20_N0_R R149 0_0402_5% USB20_N1_R 16
V33 8 +3VS <20> USB20_N0 4 4 3 3 15 15
9 W=60mils +5VALW 1 2 USB20_P1_R 14
V33 WCM-2012-900T_0805 R148 0_0402_5% 14
10 13
V33
GND 11 +5VALW 1.4A +USB_VCCA
For EMI request
1 2 @ 12
13
12
12 U14 @ R87 0_0402_5% USB20_N0_R 11
GND @ R1434 0_0402_5% USB20_P0_R 11
GND 13 1 GND VOUT 8 2 1 10 10
14 2 7 C361 1000P_0402_50V7K 1 2 9
V5 +5VS VIN VOUT 9
V5 15 3 VIN VOUT 6 8 8
16 USB_EN# 4 5 USB_OC#0 <20,31> L54 7
V5 EN FLG <30> HP_R 7
17 1 <20> USB20_N1 1 2 USB20_N1_R 6
C GND 1 2 <30> HP_L 6 C
18 RT9715BGS_SO8 5
Reserved C362 5
GND 19 <30> MIC1_L 4 4
20 4.7U_0805_10V4Z <20> USB20_P1 4 3 USB20_P1_R 3
V12 2 @ 4 3 <30> MIC1_R 3
24 GND V12 21 <30> NBA_PLUG 2 2
23 22 WCM-2012-900T_0805 1
GND V12 <30> BACK_SENSE 1
1 2
@ R88 0_0402_5% ACES_85201-2005N
@ SANTA_191201-1

this is temp. footprint

eSATA/USB Combo +5VALW 1.4A +USB_VCCB +USB_VCCB

U15 W=60mils

U52
+3VALW 1
2
3
GND VOUT
VIN VOUT
8
7
6 220U_6.3V_M_R15
W=60mils
1000P_0402_50V7K
USB Board@ Left Side
C384 0.1U_0402_16V4Z VIN VOUT
<31> USB_CHG_EN# 4 EN FLG 5 USB_OC#1 <20,31>
USB20_P3_S 1 10 1 2 1 1 1
1D+ VCC RT9715BGS_SO8 Q8
1
USB20_N3_S 2 9 SLP_CHG# C383 + 1 3

S
1D- S SLP_CHG# <31> +USB_VCCC +USB_VCCB
4.7U_0805_10V4Z C379 C380 C381
USB20_P3 3 8 USB20_P3_R @ 2 2 1 2 AO3413_SOT23
<20> USB20_P3 2D+ D+ 2 2 +5VALW
R568 100K_0402_5%

G
2
USB20_N3 4 7 USB20_N3_R 0.1U_0402_16V4Z
<20> USB20_N3 2D- D-
5 6 USB_CHG_EN# D18 @ <31> USB_EN# USB_EN#
GND OE#
2
B For ESD request at PVT Place U52 close to PCH 1
3
eSATA/USB Conn +USB_VCCC
B

USB_CHG_EN#
@ TS3USB221RSER_QFN10_2x1P5 within 1200 mils PJDLC05C_SOT23-3
JESATA
USB C426 220U_6.3V_M_R15
2 1 1 VBUS
USB20_N3_RL

+
2 D- 1 2
C455 0.1U_0402_16V7K USB20_P3_RL 3
@ D+
4 GND
2 1 C428 1 2 1000P_0402_50V7K

SATA_PTX_C_DRX_P5
5 GND W=60mils
C456 0.1U_0402_16V7K C385 1 2 0.01U_0402_25V7K 6
<16> SATA_PTX_DRX_P5 A+
@ C386 1 2 0.01U_0402_25V7K SATA_PTX_C_DRX_N5 7 ESATA @ R195 0_0402_5% C389 1 2 0.1U_0402_16V4Z
<16> SATA_PTX_DRX_N5 A-
2 1 8 GND SHIELD 12 2 1
C387 1 2 0.01U_0402_25V7K SATA_PRX_DTX_N5 9 13
<16> SATA_PRX_C_DTX_N5 B- SHIELD WCM-2012-900T_0805
C474 0.1U_0402_16V7K C388 1 2 0.01U_0402_25V7K SATA_PRX_DTX_P5 10 14 JUSB @
+USB_VCCB <16> SATA_PRX_C_DTX_P5 B+ SHIELD
11 GND SHIELD 15 <20> USB20_N2 3 3 4 4 1 VCC GND 5
USB20_N2_R 2 6
FOX_3Q318111 USB20_P2_R D- GND
3 D+ GND 7
U53 @ <20> USB20_P2 2 1 4 8
2 1 GND GND
1

<20> SLP_CHG_M3 1 1OE#

4 R949 R952 @ R1432 0_0402_5% L15 ALLTOP C107L8-10405-L
2OE# 75K_0402_1% 43K_0402_1%
<20> SLP_CHG_M4 10 3OE# 2 1
13 4OE# 2 1
L16 @ R194 0_0402_5%
2

USB20_P3_S 2 3 USB20_P3_S_O USB20_P3_R 2 1 USB20_P3_RL

USB20_N3_S 1A 1B USB20_N3_S_O USB20_P3_S_O 2 1
5 2A 2B 6
9 8 R131 1 2 USB20_N3_S_O
3A 3B 100_0402_1% USB20_N3_R USB20_N3_RL D23 @
12 4A 4B 11 3 3 4 4
1

USB20_P2_R 2
+USB_VCCB 14 7 R951 R950 WCM-2012-900T_0805 1
VCC GND 51K_0402_1% 51K_0402_1% USB20_N2_R
2 3
SN74CBT3125PWRG4_TSSOP14 2 1
A C382 @ R1431 0_0402_5% PJDLC05C_SOT23-3 A
2

0.1U_0402_16V4Z
1

SLP_CHG FUNCTION SLP_CHG_M3 SLP_CHG_M4

Security Classification Compal Secret Data Compal Electronics, Inc.
LOW D=1D Mode 3 HIGH LOW Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SATA-HDD/ODD/USB
Mode 4 Size Document Number Rev
HIGH D=2D LOW HIGH AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 25 of 45
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS MDC 1.5 Conn.

BlueTooth Interface

2
2 R49
R361 C396 +3VALW 1 2 +MDC_VCC
100K_0402_5% 0.1U_0402_16V7K MDC@ 0_0603_5% 1 1 1 1
BT@

3
1 S
R48 C392 C393 C394 C395
+1.5VALW 1 2

1
G
<21,27> BT_PW R# 1 2 2 @ 0_0603_5% 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z 4.7U_0805_10V4Z
R362 47K_0402_5% 1 2 MDC@ 2 MDC@ 2 MDC@ 2 MDC@
BT@ C390 D Q28 BT@

1
D 0.01U_0402_25V7K AO3413_SOT23 D
BT@ For HDA power rail to +3.3V(default) /+1.5V
2
+BT_VCC
JMDC
Bluetooth Connector
1 GND1 RES0 2 +MDC_VCC
(MAX=200mA) Reverse JBT Pin Definition at DVT <16> AZ_SDOUT_MD 3 IAC_SDATA_OUT RES1 4
+BT_VCC 5 GND2 3.3V 6 +3VALW
1 JBT @ 7 8
<16> AZ_SYNC_MD IAC_SYNC GND3
8 AZ_SDIN1_MD_R 9 10
BT@ C398 C399 BT@ GND IAC_SDATA_IN GND4
7 GND <16> AZ_RST_MD# 11 IAC_RESET# IAC_BITCLK 12 AZ_BITCLK_MD <16>
4.7U_0805_10V4Z 0.1U_0402_16V4Z

2
2
6 6
5 R368

GND
GND
GND
GND
GND
GND
USB20_P5 5 10_0402_5%
<20> USB20_P5 4 4
USB20_N5 3
<20> USB20_N5 3
<21> BT_RST# 1 BT@ 2 BT_RESET# 2 <16> AZ_SDIN1_MD 2 1 AZ_SDIN1_MD_R ACES_88018-124G

13
14
15
16
17
18

1
R366 2 R369 33_0402_5% MDC@ @
<21> BT_DET# 1 1 1
0_0402_5% C400
C397 ACES_87213-0600G_6P Connector for MDC Rev1.5 10P_0402_50V8J
0.1U_0402_16V4Z
BT@ 2

For EMI

Felica
C
B-CAS Circuit +5VALW +5VS C
1

1 TV@ Inrush current = 0A

TV@RB2
TV@RB2 CB1
0.1U_0402_16V7K
100K_0402_5%
3

RB5 2 S
QB1 TV@
2

+3VS
G
2 1 2 AO3413_SOT23
3

47K_0402_5% D +3VS JFEL @

1
1

2N7002KDW _SOT363-6 TV@ +5VS_BCAS +5VS_L_BCAS 1

+FLICA_VCC 1
QB2B TV@ LB1 TV@ 1 USB20_N9 2
<20> USB20_N9 2
BCPW ON 5 CB2 1 2 USB20_P9 3
<27> BCPW ON <20> USB20_P9 3

2
TV@ 2
0.01U_0402_25V7K +5VS_L_BCAS 1 1 FBMA-L11-201209-221LMA30T_0805 2 FELICA@ FELICA@ C758 FLICA_GND 4 4
1

CB4 FELICA@ C414 0.1U_0402_16V4Z 5

4

5
1

TV@ CB5 TV@ R419 FELICA@ C479 0.1U_0402_16V4Z 2

1 6 6
TV@ RB7 0.1U_0402_16V4Z 1U_0402_6.3V4Z 100K_0402_5% 0.1U_0402_16V7K 7 G1

1
10K_0402_5% TV@ RB8 CB3 TV@ 2 2 1 S
8

1
2.2K_0402_5% 4.7U_0603_6.3V6K FELICA@1
G
Q20 R132 G2
2 2
2

2 R403 47K_0402_5% 2 AO3413_SOT23 0_0603_5% ACES_87151-06051

2

C403 D FELICA@ FELICA@

1
1
D 0.01U_0402_25V7K

2
2 FELICA@
+5VS_L_BCAS <16> FELICA_PW R 1
G
+FLICA_VCC
Q34 S 2N7002_SOT23-3

3
FELICA@
TV@
5

UB1
B B
1
P

IN1 B_R_BCRST 1 TV@ B_BCRST

O 4 2 B_BCRST <27>
BCRSTM 2 RB9 100_0402_5%
<27> BCRSTM IN2
G

SN74AHC1G08DCKR_SC70-5
3

TV@
5

UB2
1
Finger printer
P

IN1 B_R_XBCCLK1 TV@ B_XBCCLK

O 4 2 B_XBCCLK <27>
XBCLKM 2 RB11 100_0402_5%
<27> XBCLKM IN2
G

SN74AHC1G08DCKR_SC70-5
3

JFP
+3VS 1 R134 2 +3VS_FP 1 1
0_0603_5% 1 2
<20> USB20_N8 2
FP@ C480 3 5
<20> USB20_P8 3 GND
0.1U_0402_16V4Z FP_GND4 6
+5VS_L_BCAS FP@ 4 GND

1
2 ACES_85201-04051
1 2 R133 @
RB12 TV@ 0_0603_5%
3

RB1 TV@ E 10K_0402_5% D82 FP@ FP@

+5VS_L_BCAS 1 2 2 1 2 QB4 TV@ BCIO 4 2
BCIO <27>

2
RB13 TV@ B 2SB1197K_SOT23-3 VIN IO1
10K_0402_5% 10K_0402_5% C 3 1
1

A IO2 GND A
6

1 2
RB14 TV@ CM1293A-02SR SOT143-4
QB2A 1.5K_0402_5% For ESD
CPLGP1 2 2N7002KDW _SOT363-6
<27> CPLGP1
TV@
Security Classification Compal Secret Data Compal Electronics, Inc.
1

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BT/FP/Felica/B-CAS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 26 of 45
5 4 3 2 1
 Slot#1 Half PCIe Mini Card-WLAN/WiMax
WLAN&BT Combo module circuits +3VS
120 MIL For SED
BT BT 2 1
on module on module
+3VALW
@ PJ27 2 1 JUMP_43X79 +3V_WLAN
Slot 2 Half & Full PCIe Mini Card- 3G/ JET/ TV Tuner 0.1U_0402_16V4Z
1 1 1

1
+1.5VS +3VS CM4 CM5 CM6 C255
Enable Disable +3VS 2 1
@ PJ26 2 1 JUMP_43X79 3G@ 3G@ 3G@ 47P_0402_50V8J
500mA 3G@
Short PJ27 for WiFi(WLAN)/WiMax combo module

2
J3G @ 2 2 2
BT_CRTL HI LO PCIE--JET B-CAS 2.75 A
0.01U_0402_25V7K 4.7U_0805_10V4Z
Short PJ26 for WiFi(WLAN) module only. 1
3
1 2 2
4
<26> XBCLKM 3 4
BT_PWR# LO HI BCCDET 5 6
5 6
<17> CLKREQ_JET# 7 7 8 8 +UIM_PWR
+1.5VS +3V_WLAN UIM_DATA
For SED For SED 9 9 10 10
**If +3V_WLAN is +3VS, please <17> CLK_JET# 11 12 UIM_CLK
0.1U_0402_16V4Z 0.1U_0402_16V4Z 11 12 UIM_RESET RM3 0_0402_5%
<17> CLK_JET 13 14
remove D21. 1 1 1 1 1 1 15
13 14
16 COMMON 1 3G@ 2 UIM_VPP
15 16

1
17 18 ISDBT_DET COMMON
<26> BCRSTM 17 18 ISDBT_DET <21>
CM7 CM8 CM9 C254 CM1 CM2 CM3 C253 19 20 RF_OFF# 1 TV@ 2 BCIO
<26> BCPWON 19 20 RF_OFF# <21> BCIO <26>
D24 47P_0402_50V8J 47P_0402_50V8J 21 22 PLT_RST# USB--TV#2 RM7 0_0402_5%

2
SUSP# BT_CTRL 2 2 2 2 2 2 21 22 USB20_P10_TV 1 R1435 2 TV@ 0_0402_5%
1 2 <17> PCIE_PRX_JETTX_N4 23 23 24 24 USB20_P10 <20>
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z 25 26 USB20_N10_TV 1 2 TV@ 0_0402_5%
<17> PCIE_PRX_JETTX_P4 25 26 USB20_N10 <20>
CH751H-40PT_SOD323-2 27 28 R135
27 28
1

D R72 1 3G@ PM_SMBCLK

29 30 2 0_0402_5%
<21,26> BT_PWR# 2 <17> PCIE_PTX_C_JETRX_N4 31
29
31
30
32 32 R85 1 2 0_0402_5% PM_SMBDATA Close to J3G
G 33 34 3G@
<17> PCIE_PTX_C_JETRX_P4 33 34
Q36 S 2N7002_SOT23-3 35 36 USB20_N12 <20> +5VS_BCAS 20 mA 1 TV@ 2 +VCC_SIM
3

35 36 RM4 0_0603_5%
37 37 38 38 USB20_P12 <20> USB--3G/TV#1
+3VS 39 39 40 40 +UIM_PWR 1 3G@ 2
41 42 LED_WIMAX# RM1 0_0603_5%
+1.5VS +3V_WLAN 41 42 CPLGP1
43 43 44 44 CPLGP1 <26>
JWLAN 1 A 2 A 45 46
45 46 TMPTU1_SXP <31>
1 2 47 48 UIM_RESET 1 3G@ 2 SIM_RESET
1 2 <31> TMPTU2_SXP 47 48
3 4 49 50 B-CAS RM5 0_0402_5%
BT_CTRL 3 4 49 50 B_BCRST
5 5 6 6 51 51 52 52 <26> B_BCRST 1 TV@ 2
7 8 RM8 0_0402_5%
<17> CLKREQ_WLAN# 7 8
9 9 10 10 53 GND1 GND2 54
<17> CLK_WLAN# 11 11 12 12
13 14 UIM_CLK 1 3G@ 2 SIM_CLK
<17> CLK_WLAN 13 14 +UIM_PWR
15 16 FOX_AS0B226-S40N-7F RM9 0_0402_5%
15 16 B_XBCCLK
17 17 18 18 <26> B_XBCCLK 1 TV@ 2
19 20 RM10 0_0402_5%
19 20 WL_OFF# <31>
21 22 PLT_RST#
21 22 PLT_RST# <20,28,29,31,32>

1
23 24 RM2
<17> PCIE_PRX_WLANTX_N2 23 24
25 26 4.7K_0402_5% UIM_DATA 1 3G@ 2 SIM_DATA
<17> PCIE_PRX_WLANTX_P2 25 26
27 28 J3GSIM @ @ RM11 0_0402_5%
27 28 +VCC_SIM BCIO
29 29 30 30 PM_SMBCLK <11,12,13,17> 1 VCC GND 4 1 TV@ 2
31 32 SIM_RESET 2 5 UIM_VPP RM12 0_0402_5%
<17> PCIE_PTX_C_WLANRX_N2 PM_SMBDATA <11,12,13,17>

2
31 32 RST VPP

1
33 34 1 SIM_CLK 3 6 SIM_DATA
<17> PCIE_PTX_C_WLANRX_P2 33 34 CLK I/O
35 36 USB20_N13 <20> DM1 1
35 36 CM13 CM14
WLAN/ WiFi 37 37 38 38 USB20_P13 <20> WiMax 0.1U_0402_16V4Z
RLZ20A_LL34 7 NC NC 8
22P_0402_50V8J
+3V_WLAN 39 39 40 40 3G@ 1 1
41 42 LED_WIMAX# 3G@ 2 MOLEX_47273-0001~D @
LED_WIMAX# <33>

2
41 42 CM15 CM16 2
43 43 44 44
45 46 1 2 +3VS 10P_0402_50V8J 10P_0402_50V8J
45 46 RM6 100K_0402_5% 3G@ 2 2 3G@
47 47 48 48
1 2 49 50 WIMAX@ Add BCCDET pull down
<31> E51_TXD 49 50
<31> E51_RXD 1R16 0_0402_5%
2 51 51 52 52
R17 0_0402_5%
53 54 BCCDET 1 2
GND1 GND2 R307 470_0402_5%
Debug card using
TV@
@ FOX_AS0B226-S40N-7F

+3VALW_CARD +3VS_CARD +1.5VS_CARD

+3VALW
Imax = 0.275A Imax = 1.35A Imax = 0.75A
1 1 1 1 1 1
1 NEW@ 2 CP_USB# CN1 CN2 CN3 CN4 CN5 CN6
RN4 100K_0402_5% 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
NEW@ NEW@ NEW@ NEW@ NEW@ NEW@ JEXP @
2 2 2 2 2 2 1
USB20_N4_R GND
2 USB_D-
USB20_P4_R 3
CP_USB# USB_D+
4 CPUSB#
5 RSV
6 RSV
PM_SMBCLK 7
UN1 NEW@ PM_SMBDATA SMB_CLK
60mils 8 SMB_DATA
+1.5VS 12 1.5Vin 1.5Vout 11 +1.5VS_CARD +1.5VS_CARD 9 +1.5V
+3VS +3VS 14 13 10
1.5Vin 1.5Vout +1.5V
<18,28> EC_SWI# 11 WAKE#
+3VS 40mils +3VALW_CARD 12 +3.3VAUX
1

RN6 1 2 3 PERST# 13
+3VS 3.3Vin 3.3Vout +3VS_CARD PERST#
10K_0402_5% CN7 4 5 +3VS_CARD 14
3.3Vin 3.3Vout +3.3V
1

@ 0.1U_0402_16V4Z 40mils 15
RN7 UN2 @ CLKREQ# +3.3V
+3VALW 17 AUX_IN AUX_OUT 15 +3VALW_CARD 16 CLKREQ#
5

10K_0402_5% @ 2 EXP_CPPE# 17
<20> EXP_CPPE#
2

@ CLKREQ# PLT_RST# CPPE#

2 6 19 Reserve for EMI request 18
G Vcc

B SYSRST# OC# <17> CLK_NEW# REFCLK-

4 CLKREQ_NEW# 19
2

Y CLKREQ_NEW# <17> <17> CLK_NEW REFCLK+

1 20 8 PERST# R95 0_0402_5% NEW@ 20
A <31,40> SYSON SHDN# PERST# GND
1 2 <17> PCIE_PRX_NEWTX_N3 21 PERn0
NC7SZ32P5X_NL_SC70-5 1 16 22
<31,34,37,41> SUSP# <17> PCIE_PRX_NEWTX_P3
3

STBY# NC L56 @ PERp0

another at page36 23 GND
1

D EXP_CPPE# 10 CPPE# GND 7 <17> PCIE_PTX_C_NEWRX_N3 24 PETn0

RCLKEN 2 Q158 <20> USB20_P4 1 2 USB20_P4_R <17> PCIE_PTX_C_NEWRX_P3 25
G @ CP_USB# 1 2 PETp0
9 CPUSB# Thermal_Pad 21 26 GND
S
3

2N7002E-T1-GE3_SOT23-3 RCLKEN 18 <20> USB20_N4 4 3 USB20_N4_R

CLKREQ# RCLKEN 4 3
1 NEW@ 2 CLKREQ_NEW# 27 GND GND 29
RN8 0_0402_5% TPS2231MRGPR-2 QFN WCM-2012-900T_0805 28 30
GND GND
R94 0_0402_5% NEW@ SANTA_130801-5_NR
1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

2009/10/05 2010/01/23 Title
Issued Date Deciphered Date PCIe-WLAN/JET/3G/TV#1/TV#2/NewCard
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 27 of 45
 A B C D E

UL1

<17> PCIE_PRX_C_LANTX_P1 CL1 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_P1 22 HSOP LED3/EEDO 31 LL1,CL13 will be changed to
37 LAN_SK_LINK# +LAN_VDD10
LED1/EESK 2.2uH&4.7uF after EVT test
<17> PCIE_PRX_C_LANTX_N1 CL2 1 2 0.1U_0402_16V7K PCIE_PRX_LANTX_N1 23 HSON LED0 40 LAN_ACTIVITY#
LL1
PCIE_PTX_C_LANRX_P1 17 30 RL2 2 1 10K_0402_5% +LAN_REGOUT 1 2
<17> PCIE_PTX_C_LANRX_P1 HSIP EECS/SCL +3V_LAN
PCIE_PTX_C_LANRX_N1 18 32 RL1 2 1 10K_0402_5% 2.2UH +-5% NLC252018T-2R2J-N Close to Pin 27,39,12,47,48
<17> PCIE_PTX_C_LANRX_N1 HSIN EEDI/SDA
1 2
Layout Note: LL1 must be
RL19 0_0402_5% 16 1 LAN_MDI0+ within 200mil to Pin36, CL13 CL9 1 2
<17> CLKREQ_LAN# CLKREQB MDIP0
YL1 2 LAN_MDI0- CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL10
LAN_X1 LAN_X2 PLT_RST# MDIN0 LAN_MDI1+ 200mil to LL1 2 1
1 2 <20,27,29,31,32> PLT_RST# 25 PERSTB MDIP1 4 1 2
5 LAN_MDI1- +LAN_REGOUT: Width =60mil 0.1U_0402_16V4Z CL4
25MHZ_20PF_7A25000012 CLK_LAN MDIN1 LAN_MDI2+
1 <17> CLK_LAN 19 REFCLK_P NC/MDIP2 7 1 2 1
1 1 CLK_LAN# 20 8 LAN_MDI2- 0.1U_0402_16V4Z CL5
<17> CLK_LAN# REFCLK_N NC/MDIN2
10 LAN_MDI3+ 1 2
CL26 CL27 NC/MDIP3 LAN_MDI3- 0.1U_0402_16V4Z CL6
NC/MDIN3 11
27P_0402_50V8J 27P_0402_50V8J LAN_X1 43 1 2
2 2 CKXTAL1 0.1U_0402_16V4Z CL7 8111E@
LAN_X2 44 13 +LAN_VDD10 CL7 close to pin12
CKXTAL2 DVDD10 +LAN_VDD10 +LAN_EVDD10
DVDD10 29
DVDD10 41
EC_SW I# 28 2 1
+3V_LAN <18,27> EC_SW I# LANWAKEB 0_0603_5% LL2 1 2
@ ISOLATEB 26 27 +3V_LAN
EC_SW I# ISOLATEB DVDD33 CL18 CL17
1 2 DVDD33 39
RL3 100K_0402_5% 1U_0402_6.3V4Z 0.1U_0402_16V4Z Close to Pin 3,6,9,13,29,41,45
RL21 2 1
14 NC/SMBCLK AVDD33 12 +3V_LAN
8111E@ 2 1 10K_0402_5% 15 42 +3V_AVDDXTAL +LAN_VDD10
+3VS RL22 1 NC/SMBDATA AVDD33
+3V_LAN 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 Close to Pin 21
AVDD33 48 1 2
0.1U_0402_16V4Z CL19
1

ENSW REG 33 1 2
RL6 ENSWREG 0.1U_0402_16V4Z CL20
EVDD10 21 +LAN_EVDD10
1K_0402_1% +LAN_VDDREG 34 1 2
VDDREG 0.1U_0402_16V4Z CL21
35 VDDREG AVDD10 3 +LAN_VDD10
6 1 2
2

ISOLATEB AVDD10 +3V_LAN +LAN_VDDREG 0.1U_0402_16V4Z CL22

RTL8105E RTL8111E AVDD10 9
1 2 46 RSET AVDD10 45 1 2
Pin14 NC NC RL5 2.49K_0402_1% 2 1 0.1U_0402_16V4Z CL23 8111E@
24 36 +LAN_REGOUT 0_0603_5% LL3 1 2 1 2
RL7 GND REGOUT 0.1U_0402_16V4Z CL24 8111E@
Pin15 NC 10K ohm PD 49 PGND
15K_0402_5% CL28 CL29 1 2
Pin38 1K ohm Pull-high 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL25 8111E@
RTL8111E-GR-VB_QFN48_6X6 2 1
2 8111E@ CL23,CL24,CL25 close to pin6,9,41, respectively 2

+3VALW TO +3V_LAN
+3VALW +3V_LAN
+3VALW
2

Vgs=-4.5V,Id=3A,Rds<97mohm
RL25 RL4
100K_0402_5%
CL12
2 +3V_AVDDXTAL RL8
0_0402_5%
+3V_LAN 0_0402_5% LAN Conn.
1

0.1U_0402_16V7K QL1
1

S
PJ28 RL9 ENSW REG JLAN
1

1 G +LAN_VDD10
1 2 2 JUMP_43X39 @ 0_0402_5% LAN_ACTIVITY# 2 RL10 1 LAN_ACTIVITY#_R 12
<31> W OL_EN# Yellow LED-
RL16 47K_0402_5% @ Reserved For 1.05V Crystal 150_0402_5%
2

1
D
1 RL23 2 1 11
1

CL14 AO3413_SOT23 +3V_LAN RL17 150_0402_5% Yellow LED+

0_0402_5%
2

0.01U_0402_25V7K +3V_LAN CL11 RJ45_MIDI3- 8

@ PR4-
0.1U_0402_16V4Z
2 2 RJ45_MIDI3+ 7 PR4+
CL11 close to pin42
1 1 RJ45_MIDI1- 6 PR2-
CL15 CL8 1U_0402_6.3V4Z RJ45_MIDI2- 5
4.7U_0805_10V4Z PR3-
@ 2 2 RJ45_MIDI2+ 4 PR3+
Add UL3 at PVT
RJ45_MIDI1+ 3 PR2+
3 UL3 8105E@ RJ45_MIDI0- 2 3
PR1-
SHLD2 14
LAN_MDI0+ 1 16 RJ45_MIDI0+ RJ45_MIDI0+ 1
LAN_MDI0- TD+ TX+ RJ45_MIDI0- PR1+
For P/N and footprint 2 TD- TX- 15 SHLD1 13
3 14 LAN_SK_LINK# 2 RL14 1 LAN_SK_LINK#_R 10
Please place them to ISPD page CT CT 150_0402_5% Green LED-
4 NC NC 13
UL1 5 12 2 1 9
NC NC +3V_LAN Green LED+
6 CT CT 11
LAN_MDI1+ 7 10 RJ45_MIDI1+ RL18 150_0402_5% SUYIN_100073FR012G101ZL
LAN_MDI1- RD+ RX+ RJ45_MIDI1- @
8 RD- RX- 9

8105E 10/100M X'FORM_ NS681680

8105E@ RJ45_GND 1 2 1000P_1808_3KV7K LANGND
CL36 1 1
UL4 UL4 8111E@ CL37 CL38
CL39 1000P_0402_50V7K
1 TCT1 MCT1 24 2 1 1 8111E@ 2 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
LAN_MDI3- RJ45_MIDI3- 8111E@ RL11 75_0402_1% 2 2
2 TD1+ MX1+ 23
LAN_MDI3+ 3 22 RJ45_MIDI3+
TD1- MX1- CL40 1000P_0402_50V7K
10/100M transformer 4 21 2 1 1 8111E@ 2
@ LAN_MDI2- TCT2 MCT2 RJ45_MIDI2- 8111E@ RL12 75_0402_1%
5 TD2+ MX2+ 20
LAN_MDI2+ 6 19 RJ45_MIDI2+
TD2- MX2- CL41 1000P_0402_50V7K
7 TCT3 MCT3 18 2 1 1 2
LAN_MDI1- 8 17 RJ45_MIDI1- RL13 75_0402_1%
LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+
9 TD3- MX3- 16
CL42 1000P_0402_50V7K
10 TCT4 MCT4 15 2 1 1 2
LAN_MDI0- 11 14 RJ45_MIDI0- RL15 75_0402_1%
LAN_MDI0+ TD4+ MX4+ RJ45_MIDI0+
4 12 TD4- MX4- 13 4

1 RJ45_GND
SUPERW ORLD_SW G150401
CL34
Place CL34 colse 0.1U_0402_25V4K
to LAN chip 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTL8105E/8111E 10/100/1000 LAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NWQAA LA6061P M/B 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 24, 2010 Sheet 28 of 45
A B C D E
 A B C D

+1.8VS_OUT CC3 close to pin 5

+3VALW
CC2 close to CC3 D3E mode
CC1 is near CC3

1
20mil
RC6

1000P_0402_50V7K
10U_0805_10V4Z

0.1U_0402_16V4Z
0.22U_0402_6.3V4K
1 1 1 1
10K_0402_5%
CC1 CC2 CC3 CC4
CC4 close to pin 10

2
2 2 2 2 RC31 0_0402_5%
<16> CR_CPPE# 1 2 CPPE#

1 JMB389C / JMB385C RC14 0_0402_5%

SD_CD#
1

<16> CR_W AKE# 1 2

+3VS
UC2 JMB389@
+TVA33 place near pin 19,20 and 44 +TVA33
CLK_CR# 3 5 JMB389@ 1 2
<17> CLK_CR# CLK_CR APCLKN APVDD RC19 0_0402_5% CC5 0.1U_0402_16V4Z
<17> CLK_CR 4 APCLKP APV18 10 2
36 1 2 1 2 JMB389@
PCIE_PTX_C_CRRX_N5 NC/TAV33 CC6 0.1U_0402_16V4Z CC12
<17> PCIE_PTX_C_CRRX_N5 9 APRXN
PCIE_PTX_C_CRRX_P5 8 19 40mil 1 2 0.1U_0402_16V4Z
<17> PCIE_PTX_C_CRRX_P5 APRXP DV33 CC7 0.1U_0402_16V4Z 1
DV33 20
<17> PCIE_PRX_C_CRTX_N5 CC8 1 2 0.1U_0402_16V7K PCIE_PRX_CRTX_N5 11 44
CC9 0.1U_0402_16V7K PCIE_PRX_CRTX_P5 APTXN DV33 +1.8VS_OUT
<17> PCIE_PRX_C_CRTX_P5 1 2 12 APTXP DV18 18 CC12 close to pin 36
DV18 37 20mil Power On Strapping setting
2 1 APREXT 7
RC3 APREXT XD_SD_MS_D0
12mil MDIO0 48 2 1 Description
12K_0402_1% 47 XD_SD_MS_D1 CC11 10U_0805_10V4Z Pin name
RC3 JMB389@ +SEL43 MDIO1 XD_SD_MS_D2
43 SDDV/MDIO4 MDIO2 46 High low
9.1K_0402_1% 39 45 XD_SD_MS_D3 CC11 close to pin18
JMB385@ TXIN/NC MDIO3 SEL41 1 2
MDIO6/4 41 For intenal LDO's usage
42 SDCLK_MSCLK_XDCE# MDIO7 on-boardϪ add-in card
MDIO5 SEL24
24
JMB389 G/MDIO6
MDIO7 40 XD_CLE CC10
JMB389@ 29 XD_SD_D4 0.22U_0402_6.3V4K CR_LED CR_LED
RC5 MDIO8 XD_SD_D5
<20,27,28,31,32> PLT_RST# 1 2 100_0402_5% 1 XRSTN MDIO9 28 CC10 close to pin37 MDIO14 high active low activeϪ
1 2 27 XD_SD_D6
CC13 XTEST MDIO10 XD_SD_D7
MDIO11 26
0.1U_0402_16V4Z 25 XD_RE#
RC5 JMB389@ CPPE# MDIO12 XD_RB# +3VS
13 CPPE_N MDIO13 23
0_0402_5% 2 XD_CD# XD_ALE
14 CR1_CD2N MDIO14 22
JMB385@
30 XD_CLE 1 2
+3VS MS_CD# NC/SPI_SCK SEL33 RC28 10K_0402_5%
2
15 CR1_CD1N NC/SPI_CSN 33 MDIO7 2

SD_CD# 16 34
JMB385@ CR1_CD0N NC/SPI_SO
NC/SPI_SI 35
1 2 SD_CD# 40 mils
RC27 4.7K_0402_5% +VCC_OUT 17 XD_ALE 1 2
JMB385@2 MS_CD# CR1_PCTLN RC26 @ 10K_0402_5%
1 APGND 6 MDIO14
RC29 4.7K_0402_5% 31
XD_CD# CR_LED NC/GND
1 2 21 CR1_LEDN NC/GND 32 1 2
RC32 4.7K_0402_5% 38 RC25 200K_0402_5%
JMB385@ NC/GND

GND 49
RC11
22_0402_5% JMB389-QGAZ0C_QFN48_7X7
JMB389@
place 6 GND vias on T-pad
RC12
22_0402_5% UC2
JMB389@ JMB385-QGAZ0C JMB385@ JMB385@
+VCC_OUT JMB385@ RC15 CC19 RC18 0_0402_5%
RC13 SD_CLK 1 2 1 2 SEL33 1 2
22_0402_5% JMB385@
2 1 XDW P#_SDW P# JMB389@ 100_0402_5% 100P_0402_50V8J
RC7 10K_0402_5% JMB385@ JMB385@
1 2 XD_RB# JMB385@ RC16 CC20 RC1 0_0402_5%
RC9 1K_0402_5% SDCLK_MSCLK_XDCE# RC11 1 2 FBMA-10-100505-121T_0402 SD_CLK MS_CLK 1 2 1 2 SEL24 1 2
2 1 SDCMD_MSBS_XDW E# JMB385@ JMB385@
RC30 10K_0402_5% RC12 1 2 FBMA-10-100505-121T_0402 MS_CLK 100_0402_5% 100P_0402_50V8J
JMB385@ JMB385@ JMB385@ JMB385@
RC13 1 2 FBMA-10-100505-121T_0402 XD_CE# RC24 CC21 RC21 0_0402_5%
XD_CE# 1 2 1 2 1 2 XDW P#_SDW P#
JMB389@
3 Reserved for EMI,close to UC1.42 100_0402_5% 100P_0402_50V8J 3

RC22 0_0402_5%
SEL41 1 2
SD_CD# XD_CD# Reserved for EMI,close to JREAD JMB385@
5 in 1 Card Reader RC23 0_0402_5%
JREAD @ 1 2 SDCMD_MSBS_XDW E#
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1
+VCC_OUT JMB389@
@ CC22 CC23 @ 14 +VCC_OUT
MS-VCC MS_CLK RC20 0_0402_5%
40 mils 33 XD-VCC MS-SCLK 15
2 2 XD_CD# MS_CD# +SEL43
34 XD-CD-SW MS-INS 17 1 2
1 1 XD_RB# 1 21 SDCMD_MSBS_XDW E# JMB385@
CC18 XD_RE# XD-R/B MS-BS XD_SD_MS_D0
2 XD-RE MS-DATA0 19
CC17 XD_CE# 3 20 XD_SD_MS_D1 JMB389@
10U_0805_10V4Z 0.1U_0402_16V4Z XD_CLE XD-CE MS-DATA1 XD_SD_MS_D2 CC16 2.2U_0603_6.3V6K
4 XD-CLE MS-DATA2 18
2 2 XD_ALE XD_SD_MS_D3
5 XD-ALE MS-DATA3 16 1 2
SDCMD_MSBS_XDW E# 6
XDW P#_SDW P# XD-WE
7 XD-WP SD-VCC 23 +VCC_OUT
24 SD_CLK CC16 close to pin43
XD_SD_MS_D0 SD-CLK SDCMD_MSBS_XDW E#
8 XD-D0 SD-CMD 12 For internal LDO in SD3.0
XD_SD_MS_D1 9 25 XD_SD_MS_D0
XD_SD_MS_D2 XD-D1 SD-DAT0 XD_SD_MS_D1
26 XD-D2 SD-DAT1 29
XD_SD_MS_D3 27 10 XD_SD_MS_D2
XD_SD_D4 XD-D3 SD-DAT2 XD_SD_MS_D3
28 XD-D4 SD-DAT3 11
XD_SD_D5 30 35 XDW P#_SDW P#
XD_SD_D6 XD-D5 SD-WP-SW SD_CD#
31 XD-D6 SD-CD-SW 36
CR_LEDCON# CR_LEDCON# <33> XD_SD_D7 32 XD-D7

4in1-GND 13
4in1-GND 22
4in1-GND 37
RC8 38
4in1-GND
4
2 1 0_0402_5% 4
1

QC1 D TAITW _R015-211-LM-A_NR

2 CR_LED
2N7002_SOT23-3 G
2

@ S Confirm sinking 16mA

3

RC10
4.7K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
@ 2009/10/05 2010/04/07 Title
Issued Date Deciphered Date
Card Reader JMB385C/389C
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 29 of 45
A B C D
 5 4 3 2 1

RA2
Speaker Connector 10/20 Change LA6~LA9 to 0 ohm resister
+PVDD1 600 mA 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z +5VALW placement near Audio Codec
1 1 0_0603_1% 1 1
CA57 CA44 RA13
place close to chip CA56 CA43 SPKL+ 2 1 SPK_L1

2
0_0603_1% 1
JA1 2 2 2 2

2
+3VS 1 2 0.1U_0402_16V4Z +DVDD_IO JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z CA19 DA7 @
RA19 FBMH1608HM601-T @ 10U_0805_10V4Z 2 2
2

1
1 1 @ place close to chip CA24 1
CA2 CA1 1 1U_0402_6.3V4Z 3

1
+1.5VS 1 @ 2 @
RA20 FBMH1608HM601-T 10U_0805_10V4Z +3VS_DVDD RA11 CA20 1 PESD5V0U2BT_SOT23-3
2 2 +PVDD2 0.1U_0402_16V4Z RA14 @ 10U_0805_10V4Z JSPK
D 2 1 +5VALW D
0_0603_1% SPKL- 2 SPK_L2 SPK_L1
1 1 1 1 2 1 1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z CA60 @ CA59 CA58 0_0603_1% SPK_L2 2
35 mA CA61 @ @ @ RA15 SPK_R1 2
+3VS 1 2 3 3
RA1 FBMH1608HM601-T +AVDD SPKR+ 2 1 SPK_R1 SPK_R2 4
1 1 2 2 2 2 4
0_0603_1% 1
CA8 CA7 10U_0805_10V4Z 10U_0805_10V4Z PESD5V0U2BT_SOT23-3ACES_85204-0400N
10U_0805_10V4Z RA3 CA25 2 @
2 2 68 mA 10U_0805_10V4Z 0.1U_0402_16V4Z 2 @ 10U_0805_10V4Z
1 +5VALW 2 1
0_0603_1% 2 CA27 3
RA36 RA35 1 1U_0402_6.3V4Z
MIC1_LINE1_R_L @ DA6 @

39

46

25

38
1 1 1 1

9
UA1 CA3 CA4 CA5 CA6 CA26 1
0_0402_5% 0_0402_5% RA30 Change CA9 and CA10 RA16 @ 10U_0805_10V4Z

DVDD_IO
DVDD

PVDD1

PVDD2

AVDD1

AVDD2
SPKR- 2 SPK_R2
Ext. Mic/LINE IN 0_0402_5%
@ to 1U at pre-MP 2 2 2 2
2
0_0603_1%
1
place close to chip
10U_0805_10V4Z 0.1U_0402_16V4Z
CA9 1U_0402_6.3V4Z
23 40 SPKL+
RA39 RA38 24
LINE1_L SPK_OUT_L+
41 SPKL- Beep sound
MIC1_LINE1_R_R CA10 LINE1_R SPK_OUT_L- EC Beep RA7
14 45 SPKR+ 1 2
LINE2_L SPK_OUT_R+ <31> EC_BEEP#
0_0402_5% 0_0402_5% 1U_0402_6.3V4Z 15 44 SPKR- 47K_0402_5%
RA37 4.7U_0805_10V4Z CA21 LINE2_R SPK_OUT_R-
0_0402_5% MIC1_LINE1_R_L 2 1 21 MIC1_L HP_OUT_L 32 RA4 75_0402_1%
HP_L <25>
@ 22 33
MIC1_LINE1_R_R 2 1
MIC1_R HP_OUT_R RA5 75_0402_1%
HP_R <25>
PCI Beep RA8
CA13
10/9 Add RA30,RA35~RA39 16 1 2 1 2 MONO_IN
4.7U_0805_10V4Z CA22 MIC2_L <16,19> PCH_SPKR
for AMP gain Test 17 MIC2_R 47K_0402_5%
10 AZ_SYNC_HD 0.1U_0402_16V4Z
SYNC AZ_SYNC_HD <16>
INT_MIC_DATA 2 6 AZ_BITCLK_HD
C <13> INT_MIC_DATA GPIO0/DMIC_DATA BCLK AZ_BITCLK_HD <16> C
INT_MIC_CLK_R 3 GPIO1/DMIC_CLK

1
5 AZ_SDOUT_HD AZ_SDOUT_HD <16> 1
SDATA_OUT
EC_MUTE# 4 8 AZ_SDIN0_HD_R 2 1 RA12 CA18
<31> EC_MUTE# PD# SDATA_IN AZ_SDIN0_HD <16>
RA6 33_0402_5% 10K_0402_5% 0.1U_0402_16V4Z
2

2
AZ_RST_HD# 11 47 Change to AGND for
<16> AZ_RST_HD# RESET# EAPD
high frequency noise issue
1

SPDIFO 48
1 2 MONO_IN 12
RA40 CA11 CA12 100P_0402_50V8J PCBEEP
MONO_OUT 20
100K_0402_5% 0.01U_0402_25V7K
@ @ SENSE_A 13 Ext.MIC/LINE IN JACK
2

SENSE A
For EMI MIC2_VREFO 29
18 SENSE B
MIC1_VREFO_R 30 +MIC1_VREFO_R CA23 10U_0805_10V4Z RA33 2 1 +MIC1_VREFO_R
1 2 36 28 1 2 1K_0402_5% RA31 2.2K_0402_5%
+5VALW CA15 CBP LDO_CAP MIC1_LINE1_R_R 2 1 MIC1_R <25>
2.2U_0603_6.3V4Z 35 27 AC_VREF
CBN VREF
RA43 +MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1% MIC1_LINE1_R_L 2 1
MIC1_VREFO_L JDREF MIC1_L <25>
100K_0402_5% 1 1 1K_0402_5%
@ 43 34 CPVEE 1 2 RA32 2 1 +MIC1_VREFO_L
EC_MUTE# PVSS2 CPVEE CA14 2.2U_0603_6.3V4Z CA17 CA16 RA29 2.2K_0402_5%
42 PVSS1
49 26 10U_0805_10V4Z
DVSS2 AVSS1
1

2 2 @
7 DVSS1 AVSS2 37
RA45 0.1U_0402_16V4Z
4.7K_0402_5% Add RA45 and un-mount RA43 at PVT ALC269Q-VB2-GR_QFN48_7X7
for audio noise issue place close to chip
DGND AGND
2

B MIC_SENSE B
for EMI request

6
for EMI request
EC control EC_MUTE# behavior: High-state / low-state @ QA1A
AZ_BITCLK_HD 1 @ 2 1 2 RA28 100K_0402_5%
For EMI CA47 1 2 0.1U_0603_50V7K RA42 10_0402_5% 2N7002DW -T/R7_SOT363-6 2
CA62 10P_0402_50V8J
RA41 CA48 1 2 0.1U_0603_50V7K

1
INT_MIC_CLK_R
<13> INT_MIC_CLK
FBMA-10-100505-301T CA49 1 2 0.1U_0603_50V7K Add RA43 for S/M battery mode at PVT
CAM@
1 CA50 1 2 0.1U_0603_50V7K
CA28 +3VL RA44 100K_0402_5%
27P_0402_50V8J 1 2
@ RA18 FBMH1608HM601-T for RF request
2 RA34 100K_0402_5%
+3VALW
@

<31> SM_SENSE#

3
place close to chip QA1B
Sense Pin Impedance Codec Signals Function
MIC_SENSE 2 1 SENSE_A 5 BACK_SENSE <25>
39.2K PORT-I (PIN 32, 33) Headphone out RA10 20K_0402_1% 2N7002DW -T/R7_SOT363-6

4
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A
<25> NBA_PLUG
10K PORT-C (PIN 23, 24) RA21 39.2K_0402_1%
A A

5.1K (PIN 48)

39.2K PORT-E (PIN 14, 15)

SENSE B 20K PORT-F (PIN 16, 17)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 200910/9 Deciphered Date 2010/01/23 Title

10K PORT-H (PIN 20) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDA CODEC ALC269
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 30 of 45
5 4 3 2 1
 5 4 3 2 1

+3VL
+3VL
0.1U_0402_16V4Z 0.1U_0402_16V4Z BATT_TEMPA 1 2
1 1 1 1 2 2 C442 C445 100P_0402_50V8J
C436 1 2 ACIN_D 1 2
C437 C438 C439 C440 C441 C446 100P_0402_50V8J
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z
2 2 2 2 1 1

111
125
0.1U_0402_16V4Z 1000P_0402_50V7K

22
33
96

67
9
for EMI request U19

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
CLK_PCI_EC
TV tuner +3VS
D D

1
R377 GATEA20 1 21 KB_LED temperature
<21> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F KB_LED <32>
@ 10_0402_5% KB_RST# 2 23 EC_BEEP# R754 10K_0402_5%
<21> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP# <30>
SERIRQ 3 26 SM_SENSE# TMPTU1_SXP 1 2
<16,32> SERIRQ SERIRQ# FANPWM1/GPIO12 SM_SENSE# <30>
LPC_FRAME# 4 27 ACOFF
2

<16,32> LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF <37>

1 LPC_AD3 5 R757 10K_0402_5%
<16,32> LPC_AD3 LAD3
LPC_AD2 7 PWM Output TMPTU2_SXP 1 2
<16,32> LPC_AD2 LAD2
C443 LPC_AD1 8 63 BATT_TEMPA
<16,32> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA <36>
@ 22P_0402_50V8J LPC_AD0 TMPTU1_SXP
2 <16,32> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
TMPTU1_SXP <27> +3VL
ADP_I/AD2/GPIO3A 65 ADP_I <37>
CLK_PCI_EC 12 AD Input 66 ADP_V
<20> CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V <37>
PLT_RST# 13 75 TMPTU2_SXP
<20,27,28,29,32> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 TMPTU2_SXP <27>
ECRST# 37 76 HDPACT CEC_INT# 2 1
+3VL R378 EC_SCI# ECRST# SELIO2#/AD5/GPIO43 HDPACT <32> R53 100K_0402_5%
<21> EC_SCI# 20 SCI#/GPIO0E
47K_0402_5% W L_BT_LED# 38
<33> W L_BT_LED# CLKRUN#/GPIO1D
2 1 ECRST# 68 VTTP_EN CAP_INT# 1 @ 2
DAC_BRIG/DA0/GPIO3C VTTP_EN <39>
70 EN_DFAN1 R1436 4.7K_0402_5%
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <6>
2 1 DA Output 71 IREF
IREF/DA2/GPIO3E IREF <37>
C444 0.1U_0402_16V4Z KSI0 55 72 CHGVADJ
KSI0/GPIO30 DA3/GPIO3F CHGVADJ <37>
KSI1 56
KSI2 KSI1/GPIO31 +5VS
57 KSI2/GPIO32
KSI3 58 83 EC_MUTE#
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# <30>
KSI4 59 84 USB_EN#
+3VL KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <25>
KSI5 60 85 USB_CHG_EN# TP_CLK 1 2
KSI5/GPIO35 PSCLK2/GPIO4C USB_CHG_EN# <25>
KSI6 61 PS2 Interface 86 HDPINT R379 4.7K_0402_5%
KSI6/GPIO36 PSDAT2/GPIO4D HDPINT <32>
1 2 KSO1 KSI7 62 87 TP_CLK TP_DATA 1 2
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <33>
R380 47K_0402_5% KSO0 39 88 TP_DATA R381 4.7K_0402_5%
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <33>
1 2 KSO2 KSO1 40
R382 47K_0402_5% KSO2 KSO1/GPIO21
41 KSO2/GPIO22
KSO3 42 97 VGATE +3VALW
KSO3/GPIO23 SDICS#/GPXOA00 VGATE <18,42>
to avoid EC entry ENE test mode KSO4 43 98 W OL_EN#
C KSO4/GPIO24 SDICLK/GPXOA01 W OL_EN# <28> C
KSO5 PW RME_CTRL# LID_SW #
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW #
PW RME_CTRL# <16> 2
47K_0402_5%
1
R383
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW # <32>
KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27 SYSON
47 KSO8/GPIO28 1 2
KSO9 48 119 EC_SI_SPI_SO R5 4.7K_0402_5%
KSI[0..7] KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO <32>
KSO10 49 120 EC_SO_SPI_SI
<32,33> KSI[0..7] KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <32>
KSO11 50 SPI Flash ROM 126 SPI_CLK
KSO[0..17] KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK <32>
KSO12 51 128 SPI_CS#
<32,33> KSO[0..17] KSO12/GPIO2C SPICS# SPI_CS# <32>
KSO13 52 R341 330K_0402_5%
KSO14 KSO13/GPIO2D
53 KSO14/GPIO2E +3VALW 1 2
KSO15 54 73 CIR_IN
RP7 KSO16 KSO15/GPIO2F CIR_RX/GPIO40 CAP_INT# D21
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 CAP_INT# <33>
+3VL 1 8 EC_SMB_CK1 KSO17 82 89 FSTCHG ACIN_D 2 1
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <37> ACIN <18,33,35>
2 7 EC_SMB_DA1 90 BATT_FULL_LED#
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# <33>
+3VS 3 6 EC_SMB_CK2 91 CAPS_LED# CH751H-40PT_SOD323-2
CAPS_LED#/GPIO53 CAPS_LED# <32> +3VALW
4 5 EC_SMB_DA2 EC_SMB_CK1 77 GPIO BATT_LOW_LED#/GPIO54 92 BATT_CHG_LOW _LED#
<15,36> EC_SMB_CK1 SCL1/GPIO44 BATT_CHG_LOW _LED# <33>
EC_SMB_DA1 78 93 PW R_ON_LED#
<15,36> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PW R_ON_LED# <33>
2.2K_0804_8P4R_5% EC_SMB_CK2 79 SM Bus 95 SYSON
<17,32,33> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <27,40>
EC_SMB_DA2 80 121 VR_ON SLP_CHG# 2 1
<17,32,33> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <42>
127 ACIN_D R1428 10K_0402_5%
AC_IN/GPIO59

PM_SLP_S3# 6 100 EC_RSMRST# SUSP# R423 2 1 10K_0402_5%

<18> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# <18>
SLP_S5# 14 101 EC_LID_OUT#
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# <17>
For EMI EC_SMI# 15 102 EC_ON VR_ON R462 2 1 10K_0402_5%
<21> EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON <33>
THM_ALT# 16 103 TP_LED
<21> THM_ALT# LID_SW#/GPIO0A EC_SWI#/GPXO06 TP_LED <33>
ESB_CK 17 104 PM_PW ROK
<33> ESB_CK SUSP#/GPIO0B ICH_PWROK/GPXO06 PM_PW ROK <18>
@ ESB_DAT 18 GPO 105 BKOFF# Add R462 at PVT
<33> ESB_DAT PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# <13>
1 2 PLT_RST# PCH_SUSPW RDN 19 GPIO 106 W L_OFF#
<18> PCH_SUSPW RDN EC_PME#/GPIO0D WL_OFF#/GPXO09 W L_OFF# <27>
C819 180P_0402_50V8J 25 107 CAP_RST#
EC_THERM#/GPIO11 GPXO10 CAP_RST# <33>
FAN_SPEED1 28 108 LOGO_LED
B
1
@
2 SUSP#
<6> FAN_SPEED1
<32> HDPLOCK
<27> E51_TXD
HDPLOCK
E51_TXD
29
30
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
GPXO11 LOGO_LED <33>
CIR +5VL B

C820 180P_0402_50V8J E51_RXD 31 110 CEC_INT#

<27> E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXID1 CEC_INT# <15>

2
ON/OFFBTN# 32 112 EC_ENBKL
<33> ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2 EC_ENBKL <19>
PW R_SUSP_LED# 34 114 USB_OC#1 R748
<33> PW R_SUSP_LED# PWR_LED#/GPIO19 GPXID3 USB_OC#1 <20,25>
NUM_LED# 36 GPI 115 SLP_CHG# 10K_0402_5%
<32> NUM_LED# NUMLED#/GPIO1A GPXID4 SLP_CHG# <25>
116 SUSP#
GPXID5 SUSP# <27,34,37,41>
117 PBTN_OUT#
PBTN_OUT# <18>

1
GPXID6 USB_OC#0 U45
Close to EC GPXID7 118 USB_OC#0 <20,25>
CRY1 122 CIR_IN 1
CRY2 XCLK1 +EC_V18R Vout
123 XCLK0 V18R 124
+5VL 1 CIR@ 2 +5VL_CIR 2 VCC
AGND

+3VALW R750 100_0805_5%

GND
GND
GND
GND
GND

C818 C448 3
4.7U_0805_10V4Z C783 GND
2 1
KB926QFE0_LQFP128_14X14 4.7U_0805_10V4Z 4
11
24
35
94
113

69

GND
5

U44 0.1U_0402_16V4Z CIR@

1 IRM-V536/TR1_3P
P

<18> PM_SLP_S5# IN1 +3VALW

4 SLP_S5# CIR@
O R389
<18> PM_SLP_S4# 2 IN2
G

CRY1 1 2CRY2
SN74AHC1G08DCKR_SC70-5 @
3

@ 10M_0402_5% CIR_IN 1 2
R435
100K_0402_5% C180 330P_0402_50V7K
@ @
D86 @ 1 1 LOGO_LED H L 1 2
1

PM_SLP_S4# 2 LOGO_LED
1

1 C449 C450 C185 330P_0402_50V7K

2

PM_SLP_S5# Y4 @
18P_0402_50V8J

3
18P_0402_50V8J
OSC

OSC

2 2 R436 EC ver. KB926D3 KB926E0 1 2

A PJDLC05C_SOT23-3 100K_0402_5% A
C217 330P_0402_50V7K
NC

NC

For ESD request at PVT

2

R337 100K_0402_5%
1 2 VTTP_EN

R342 100K_0402_5% 32.768KHZ_12.5PF_Q13MC14610002 Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 E51_TXD 2009/10/05 2010/01/23 Title
Issued Date Deciphered Date
ENE-KB926 RevD2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 31 of 45
5 4 3 2 1
 Lid SW LPC Debug Port Please place the PAD under DDR DIMM.

SPI Flash (256KB) +3VALW

+3VS H7

6 5
U21
+3VL APX9132ATI-TRL_SOT23-3
<16,31> SERIRQ 1 2 7 4 PLT_RST# <20,27,28,29,31>
2 3 R392 0_0402_5%

GND
20mils VDD VOUT LID_SW # <31>
1
C451 U22 8 3
<16,31> LPC_AD3 LPC_AD2 <16,31>
8 4 1 1

1
0.1U_0402_16V4Z VCC VSS
2 C453 C452
3 W <16,31> LPC_AD1 9 2 LPC_AD0 <16,31>
0.1U_0402_16V4Z 10P_0402_50V8J
2 2
7 HOLD
<16,31> LPC_FRAME# 10 1 CLK_PCI_DDR <20>
<31> SPI_CS# 1 S

2
SPI_CLK 6
<31> SPI_CLK C DEBUG_PAD @ R393
5 2 22_0402_5%
<31> EC_SO_SPI_SI D Q EC_SI_SPI_SO <31>
MX25L2005CMI-12G SOP 8P

1
2
C457
SPI_CLK 1 R394 @2 1 2 22P_0402_50V8J
10_0402_5% C454 @ 10P_0402_50V8J 1

reserve for EMI, close to U22

reserve for EMI

Keyboard LED UG1 GSENSOR@

+5VS
Q38
AO3413_SOT23-3
KBL@ JBLG
G-Sensor +3VS_HDP 2
12
Vdd1
Vdd2
Voutx
Vouty
3
5
VOUTX CG1
VOUTY CG2
VOUTZ CG3
1
1
2 GSENSOR@
2 GSENSOR@
0.033U_0402_16V7K
0.033U_0402_16V7K
Voutz 7 1 2 GSENSOR@ 0.033U_0402_16V7K
S

3 1 +5VS_LED 1 1 +5VS_LED
1 2 RG2 @ SELF_TEST 4 10
2 ST NC1
1

3 3 +3VS 2 1 +3VS_HDP 6 PD NC2 11

R587 C836
G

4 8 14 Reserve for 2nd Source

2

10K_0402_5% 0.1U_0402_16V4Z 4 0_0603_5% FS NC3

GND 5 NC4 15
KBL@ 2 KBL@
GND 6 NC5 16
2

@ ACES_85201-0405N +5VS +3VS_HDP 9 1 +3VS_HDP

+3VS_HDP Rev GND1
GSENSOR@ DG1 CH751H-40PT_SOD323-2 13 CG9 0.1U_0402_16V4Z UG4 @
GND2
1

D @
1 2 2 1VOUTX2 6
2 Q52 2 2 TSH35TR_LGA16 CG10 0.1U_0402_16V4Z XOUT VDD
<31> KB_LED
G 2N7002_SOT23-3 please close to JKB1 CG12 UG3 GSENSOR@ @ 2 1VOUTY3
S KBL@ 1U_0402_6.3V4Z CG13 CG11 0.1U_0402_16V4ZYOUT 1
3

KSO16 GSENSOR@ 1U_0402_6.3V4Z @ NC

1 2 1 VIN VOUT 5 2 1VOUTZ4 ZOUT NC 8
C401 100P_0402_50V8J 1 1 GSENSOR@
NC 11
KSO17 1 2 2 UG1 & UG4 must place on TOP side 9 12
C402 100P_0402_50V8J GND CG14 0G-DET NC
NC 14
KSO2 1 2 3 4 2 1 +3VS_HDP 7
C404 100P_0402_50V8J SHDN# BP SLEEP#
10 G-SELECT
KSO1 1 2 @ SELF_TEST 13 5
C405 100P_0402_50V8J G9191-330T1U_SOT23-5 0.22U_0402_10V4Z ST VSS

KEYBOARD CONN. KSO0 1

C406
2
100P_0402_50V8J Change UG3 to SA000022I00 at PVT
MMA7360LR2_LGA14

KSO4 1 2
KSI[0..7] C407 100P_0402_50V8J
KSI[0..7] <31,33>
KSO3 1 2
KSO[0..17] C408 100P_0402_50V8J UG5
KSO[0..17] <31,33>
KSO5 1 2
JKB C409 100P_0402_50V8J 1 11 HDPACT <31>
<17,31,33> EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01
JKB34 1 2 +3VS KSO14 1 2
34

2
KSO16 R372 300_0402_5% C410 100P_0402_50V8J
33 KSO6 SELF_TEST RG9
32 1 2 2 P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 12
KSO17 C411 100P_0402_50V8J 47K_0402_5%
31 KSO7 GSENSOR@
30 1 2
C412 100P_0402_50V8J +3VS_HDP RG3 2 1 3 13

1
29 KSO2 KSO13 GSENSOR@ 4.7K_0402_5% RESET# P1_4/TXD0
28 1 2
KSO1 C413 100P_0402_50V8J
27 KSO0 KSO8 RG4 2
26 1 2 1GXOUT 4 XOUT/P4_7 P1_3/KI3#/AN11/TZOUT 14 HDPLOCK <31>
KSO4 C415 100P_0402_50V8J GSENSOR@ 4.7K_0402_5%
25 KSO3 KSO9 RG10 47K_0402_5%
24 1 2
KSO5 C416 100P_0402_50V8J 5 15 VOUTZ 2 1
23 KSO14 KSO10 VSS/AVSS P1_2/KI2#/AN10/CMP0_2 GSENSOR@
22 1 2
KSO6 C417 100P_0402_50V8J
21 KSO7 KSO11 RG5 2
20 1 2 1GXIN 6 XIN/P4_6 P4_2/VREF 16 +3VS_HDP
KSO13 C418 100P_0402_50V8J GSENSOR@ 4.7K_0402_5%
19 KSO8 KSO12
18 1 2 1
KSO9 C419 100P_0402_50V8J 7 17 VOUTX CG6
17 KSO10 KSO15 VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_16V4Z
16 1 2
KSO11 C420 100P_0402_50V8J GSENSOR@
15 KSO12 KSI7 RG6 2
14 1 2 2 1 4.7K_0402_5% 8 MODE P1_0/KI0#/AN8/CMP0_0 18 VOUTY
KSO15 C421 100P_0402_50V8J GSENSOR@
13 KSI7 KSI2
12 1 2
KSI2 C422 100P_0402_50V8J HDPINT RG7 2 1 1K_0402_5% 9 19
11 KSI3 KSI3 <31> HDPINT GSENSOR@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
10 1 2
KSI4 C423 100P_0402_50V8J
9 KSI0 KSI4
8 1 2 1 1 10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA2 <17,31,33>
KSI5 C424 100P_0402_50V8J CG8
7 KSI6 KSI0 CG7 GSENSOR@
6 1 2
KSI1 C425 100P_0402_50V8J 0.1U_0402_16V4Z 0.1U_0402_16V4Z R5F211B4D34SP GSENSOR@
5 JKB4 KSI5 GSENSOR@ 2 2
4 2 1 +3VS 1 2
CAPS_LED# R376 300_0402_5% C427 100P_0402_50V8J
3 CAPS_LED# <31>
KSI6 1 2
2 NUM_LED# C429 100P_0402_50V8J
1 NUM_LED# <31>
KSI1 1 2
ACES_88170-3400 C431 100P_0402_50V8J
@ CAPS_LED# 1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
C433 100P_0402_50V8J 2009/10/05 2010/01/23 Title
NUM_LED#
Issued Date Deciphered Date
1
C435
2
100P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SPI ROM/TP/KB/Debug
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 32 of 45
 5 4 3 2 1

+3VL
Power Button Caps Sensor/Light Sensor Conn. Touchpad & Light Pipe Connector

2
debug phase using R395 JCS @ SW1
+5VALW 1
100K_0402_5% 1 SW_L
51_ON# <35> +3VL 2 1 3
FBMA-11-100505-301T_0402 +3VS 2
3

1
ON/OFFBTN# L13 1 ESB_DAZ 3
Remove SW2 ON/OFFBTN# <31> <31> ESB_DAT 2 4
4
2 4

6
TOP side L14 1 2 ESB_CKZ 5 Remove D19 at DVT
at pre-MP <31> ESB_CK 5
1 Q7A FBMA-11-100505-301T_0402 6 SMT1-05_4P
<31> CAP_INT#

6
5
C458 2N7002DW-T/R7_SOT363-6 CAP_RST# 7 6
<31> CAP_RST# 7
0.1U_0402_25V6 2 8 JTPL
<31> EC_ON <17,31,32> EC_SMB_CK2 8
@ 9 1
<17,31,32> EC_SMB_DA2 9 +5VS 1

2
2
10 <31> TP_CLK 2

1
SW3 @ R396 10 2
11 <31> TP_DATA 3
D GND SW_L 3 D
1 3 10K_0402_5% 12 4
GND SW_R 4
5
ACES_85201-1005N 5
BTM side 2 4 For EMI request 6

1
TP_LED# 6
7
SMT1-05_4P KSI6 7
Remove J3 at PVT <31,32> KSI6 8 SW4
6
5

KSO0 8
For EMI <31,32> KSO0 9
9
10 SW_R 1 3
10

3
JPOWER 11
PWR_ON_LED# @ R428 C869 @ GND
1 1
12 2 4
ESB_DAZ Q7B GND
2 2 ON/OFFBTN#
1
R22
2
390_0402_5%
+5VALW 1 2 1 2
ACES_85201-1005N SMT1-05_4P
3 3
5

6
5
D83 100_0402_5% 100P_0402_50V8J <31> TP_LED @
4 4 ON/OFFBTN# 2N7002DW-T/R7_SOT363-6
G1 5
2

4
@ R427 C870 @
G2 6
1
PWR_ON_LED# 3 ESB_CKZ 1 2 1 2
ACES_85201-0405N
@ PJSOT05C_SOT23-3 100_0402_5% 100P_0402_50V8J

Screw Hole
H5 H6 H8 H9 H10 H11 H12 H13 H14
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
@ @ @ @ @ @ @ @ @

DC-IN LED

1
ACIN <18,31,35> WiMAX LED R506
WIMAX_LED_GND# 1 2 LED_WIMAX# <27>
2

0_0402_5%

2
Q35A @ H1 H26
C C
DC_IN 6 1 R819 H_2P7x3P2N H_2P7N
+5VS 2 1 6 1 @ @
2N7002DW-T/R7_SOT363-6 10K_0402_5%

1
5
WIMAX@ Q156A
2N7002KDW_SOT363-6
WIMAX_LED_GND# 3 4 WIMAX@

Q156B
2N7002KDW_SOT363-6
WIMAX@

MINI CARD -- 3G

CPU H15 H16 H17

HDD LED SATA_LED# <16>
Logo LED H_3P3 H_3P3 H_3P3
2

H20 H21 H22 H23 @ @ @

H_4P2 H_4P2x4P7 H_4P2x4P7 H_4P7
LOGO_LED <31>

1
+5VS 2 R404 1 6 1 @ @ @ @

5
10K_0402_5% D22

1
5

Q9A HT-SV116BP_WHITE
2N7002DW-T/R7_SOT363-6 +5VS 1 2 2 1 LOGO_LED# 3 4
HDD_LED# 3 4 R774 120_0402_5%
2N7002KDW_SOT363-6
Q9B 2N7002DW-T/R7_SOT363-6 Q6B MDC MINI CARD -- WLAN
1 @ 2
R1430 0_0402_5% 1 2 2 1 H24 H25 H18 H19
R776 120_0402_5% H_3P3 H_3P3 H_3P3 H_3P3
HT-SV116BP_WHITE @ @ @ @
D20

1
B B

PCB Fedical Mark PAD

FD1 FD2 FD3 FD4

@ @ @ @

1
LED/B Connector

JLED @
ISPD
+5VALW 1
1
+5VS 2
WIMAX_LED_GND# 2
3
WL_BT_LED# 3
<31> WL_BT_LED# 4
DC_IN 4
5
PWR_ON_LED# 5 PJP1 45@ ZZZ U11 HM55R3@
<31> PWR_ON_LED# 6
PWR_SUSP_LED# 6
<31> PWR_SUSP_LED# 7
HDD_LED# 7
8
CR_LEDCON# 8
<29> CR_LEDCON# 9
BATT_FULL_LED# 9
<31> BATT_FULL_LED# 10
BATT_CHG_LOW_LED# 10
<31> BATT_CHG_LOW_LED# 11 13
11 GND PJP1 PCB LA-6061P PCH
12 14
12 GND
A A
ACES_85201-1205N

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR BTN/Can. Sensor/TP/LEDs
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 33 of 45
5 4 3 2 1
 A B C D E

+3VALW TO +3VS +5VALW TO +5VS +1.5V to +1.5VS

+3VALW +3VS Vgs=-0V,Id=9A,Rds=18.5mohm +5VALW +5VS
4.7U_0805_10V4Z +1.5V +1.5VS
4.7U_0805_10V4Z
1 1 1 1 Vgs=10V,Id=14.5A,Rds=6mohm
Q29 C459 C460 4.7U_0805_10V4Z Q30 C461 C462 1 1
+5VS Q31 C463 C464

470_0805_5%

470_0805_5%
8 D S 1 8 D S 1

470_0805_5%
7 D S 2 7 D S 2 8 D S 1

2
2 2 R406 +3VS 2 2 R407
6 D S 3 6 D S 3 7 D S 2
2 2 R408
1 5 D G 4 5 D G 4 6 D S 3 1
1U_0402_6.3V4Z 1U_0402_6.3V4Z 5 4

0.1U_0402_16V4Z

0.1U_0402_16V4Z
SI4800BDY_SO8 D G
1 R409 2 +VSB 1 2 SI4800BDY_SO8 1 R410 2 +VSB 1U_0402_6.3V4Z

3 1

3 1
1 1 47K_0402_5% C292 C821 1 1 47K_0402_5% FDS6676AS_SO8 1 R411 2

0.01U_0402_25V7K
4.7U_0805_10V4Z

0.022U_0402_25V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z
+VSB

3 1
1

6
C466 1 1 1 220K_0402_5%

4.7U_0805_10V4Z

6
C465 R412 Q10A C315 C467 C468 R413 Q11A FDS6676AS

0.1U_0402_25V6
2 1

C470
330K_0402_5% Q10B 200K_0402_5% Q11B C469 R414 Q12A
2 2 SUSP @ 2 2 @ SUSP 5 820K_0402_5% Q12B
2 5 2
2N7002DW -T/R7_SOT363-6 2 2N7002DW -T/R7_SOT363-6 2 2 SUSP 5
2
2

2
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6
1

2
2N7002DW -T/R7_SOT363-6

4
For EMI request
For EMI request

For S3 CPU Power Saving

+5VS TO +5VS_ODD +3VALW
+5VS

+5VS

2
+5VS_ODD PS@
2 R425 2
2

2 100K_0402_5%

2
R398 C471 Vgs=-4.5V,Id=3A,Rds<97mohm
10K_0402_5% 0.1U_0402_16V7K R426
0.75VR_EN# <41>

1
470_0805_5%
2

1
1

3
S
R128 Q45 PJ33 Q48B
2

1
G
1 2 2 JUMP_43X79 2N7002DW -T/R7_SOT363-6 PS@
<20> ODD_EN#
@ PS@
+5VS_ODD
1

47K_0402_5% 2
D
<5,39> VTTPW ROK 1 2 0.75VR_EN 5
1

1
AO3413_SOT23 Q160 D R169 100K_0402_5%
1

C276 ODD_EN# 2

4
6
0.01U_0402_25V7K G Q48A
1 2N7002_SOT23-3 S 2N7002DW -T/R7_SOT363-6
1

3
1 PS@
C680 SUSP 2
C679 1U_0402_6.3V4Z
4.7U_0805_10V4Z 2

1
@ 2

Reserve for EMI test

3 3

For S3 CPU Power Saving

+5VALW +0.75VS
+3VS +5VS +5VALW R421
47_0805_5%

2
PS@
R422 R421
2 2 2 100K_0402_5% 470_0805_5%
C473 C475 C478 NOPS@
0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K

1
SUSP
1 1 1 <9,41> SUSP

3
Q5B
Q5A 2N7002DW -T/R7_SOT363-6
2N7002DW -T/R7_SOT363-6
2 5 SUSP
<27,31,37,41> SUSP#
another at page42

4
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC-DC INTERFACE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 34 of 45
A B C D E
 A B C D

VS
VIN PR1
PL1 VIN 1M_0402_1%
PF1 SMB3025500YA_2P
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2
1 2

1
1
PJP1 N1 PR3
10A_125V_451010MRL PR2 5.6K_0402_5% PR4

680P_0402_50V7K
1000P_0402_50V7K

1000P_0402_50V7K
+ 1
84.5K_0402_1% 10K_0402_1%

680P_0402_50V7K

100P_0402_50V8J

100P_0402_50V8J
1

1
1 1

PC5
2 1 2 ACIN <18,31,33>

2
+

1
PC1

PC2

PC3

PC4

PC6
PR5

8
3 22K_0402_1% PU1A

2
-
@ 1 2 3

P
2
@ + PACIN
- 4 O 1 PACIN <37>
2 -

G
1
@ SINGA_2DW -0005-B03

1
PR6 LM393DG_SO8

4
PC7 20K_0402_1% PC8 PD1 PR7
0.068U_0402_10V6K .1U_0402_16V7K GLZ4.3B_LL34-2 10K_0402_1%

2
2

2
2 1 +CHGRTC
PR8
VIN 10K_0402_1%
3.3V Vin Detector

2
PD2
High 18.384 17.901 17.430
RLS4148_LL34-2 Low 17.728 17.257 16.976

1
BATT+ 2 1

1
PD3 PR9 PR10
RLS4148_LL34-2 PQ1 68_1206_5% 68_1206_5%
TP0610K-T1-E3_SOT23-3
PR11

2
200_0603_5%
2
CHGRTCP 1 2 N1 3 1 VS 1 2 2

PR12
1

1K_1206_5%
1

1
PC10 PD4
PR13 PC9 0.1U_0603_25V7K 2 1 N3 1 2
100K_0402_1% 0.22U_0603_25V7K VIN B+
2

2
RLS4148_LL34-2 PR14
2

1K_1206_5%
<33> 51_ON# 1 2
PR15 1 2
22K_0402_1%
RTC Battery PR16
1K_1206_5%

1
1

PR19 PR20
PR17
200_0603_5%
- PBJ1 + PR21
560_0603_5%
PR22
560_0603_5%
VL
100K_0402_1%
1 2
2.2M_0402_5%
2 1
PR18
499K_0402_1%
PU2 G920AT24U_SOT89-3 2 1 1 2 1 2
3.3V +RTCBATT

2
2

+CHGRTC 3 2 N2
OUT IN PD5

8
@ MAXEL_ML1220T10 RB715F_SOT323-3 PU1B
1

GND
2 5

P
<38> EN0 +
PC11 PC12 1 7
10U_0805_10V4Z 1 O
<37> ACON 3 6 2 1
2

+CHGRTC

G
-

1
1U_0805_25V6K
SP093MX0000 LM393DG_SO8 PR23 PR24

1
10K_0402_1% 499K_0402_1% PC14

1
PR26 1000P_0402_50V7K
PC13 @ PR25 191K_0402_1%

2
3 3

1000P_0402_50V7K 66.5K_0402_1%

2
1

2
PC15
1000P_0402_50V7K

2
PR27

1
PJ1 PJ4 PJ3 D 47K_0402_1%
+3VALW P 2 1 +3VALW +1.5VP 2 1 +1.5V +1.8VSP 2 1 +1.8VS PQ2 2 2 1 PACIN
2 1 2 1 2 1 SSM3K7002FU_SC70-3 G
@ JUMP_43X118 @ JUMP_43X118 @ JUMP_43X79 S

3
(5A,200mils ,Via NO.= 10) (2A,80mils ,Via NO.= 4)
(9A,360mils ,Via NO.= 18)

1
OCP(min)=7.7A
OCP(min)=9.8A PJ6
PJ5
+5VALW P 2 1 +5VALW PJ8 VL 2 1 +5VL
2 1 +GFX_COREP +GFX_CORE 2 1
2 2 1 1 2 +5VALW P
@ JUMP_43X118 @ JUMP_43X39
(5A,200mils ,Via NO.= 10) @ JUMP_43X118 (100mA,40mils ,Via NO.= 2)
PQ3
OCP(min)=7.9A PJ10 Precharge detector DTC115EUA_SC70-3

3
PJ7 2 2 1 1 PJ9 15.97V/14.84V FOR
+VSBP 2 2 1 1 +VSB @ JUMP_43X118 +3VLP 2 2 1 1 +3VL ADAPTOR
@ JUMP_43X39 (22A,880mils ,Via NO.=44) @ JUMP_43X39
(100mA,40mils ,Via NO.= 2)
(120mA,40mils ,Via NO.= 1) OCP(min)=26A
PJ17
4
PJ11 +0.75VSP 2 1 +0.75VS
4

2 1
2 2 1 1
@ JUMP_43X79
@ JUMP_43X118 (1.5A,60mils ,Via NO.= 4)
PJ13
+VTTP 2 2 1 1 +VTT
@ JUMP_43X118
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
(20A,800mils ,Via NO.=40)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN / DETECTOR
OCP(min)=27.49A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 35 of 45
A B C D
 A B C D

1 1
VMB
PF2 PL2
PH1 under CPU botten side :
PJP2 15A_65V_451015MRL SMB3025500YA_2P
1 BATT_S1 1 2 1 2
CPU thermal protection at 95degree C
1 BATT+
2 2
3 BATT_P3 1 2 1 2
Recovery at 56 degree C
3 +3VLP
4 BATT_P4 PR28 PR29
4

1
BATT_P5 1K_0402_1% 47K_0402_1%
5 5 PH2 near main Battery CONN :

1
10 6 EC_SMDA PC16 PC17
GND 6 EC_SMCA @ PC18 1000P_0402_50V7K 0.01U_0402_25V7K
11 7 BAT. thermal protection at 95 degree C

2
GND 7

1
12 8 0.1U_0402_25V6K

2
GND 8 PR30
13 GND 9 9
1K_0402_1%
Recovery at 48 degree C
@ SUYIN_200045MR009G171ZR

2
VL

PD7
1

PJSOT24C_SOT23-3

1
PD6 2

1
PJSOT24C_SOT23-3 1 PR31
3 PC19 19.6K_0402_1%
PR32 0.1U_0603_25V7K

2
6.49K_0402_1% PR33
2

2
2 1 19.6K_0402_1%
+3VLP

2
PR34

1
1

8.66K_0402_1%
PR35 PU4
2
1K_0402_1% 1 8 2

1
VCC TMSNS1

1
2 7
2

GND RHYST1
2

PR36 PR37 3 6 PH1

BATT_TEMPA <31> OT1 TMSNS2
100_0402_1% 100_0402_1% 100K_0402_1%_NCP15W F104F03RC

1
4 5

2
<38> VS_ON OT2 RHYST2 PR40
1

G718TM1U_SOT23-8 7.87K_0402_1%
EC_SMB_DA1 <15,31>

2
EC_SMB_CK1 <15,31>

1
PH2
100K_0402_1%_NCP15W F104F03RC

2
PQ4
TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
3 3
100K_0402_1%

0.1U_0603_25V7K
0.22U_0603_25V7K
1

1
PR41

PC20

PC21

@ @
2

2
2

VL PR42
22K_0402_1%
1 2
2

PR43
100K_0402_1%

PR44
1

0_0402_5% D
1 2 2 PQ5
<38> POK
G SSM3K7002FU_SC70-3
.1U_0402_16V7K

.1U_0402_16V7K

S
3
1

1
PC76

@ PC22
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 36 of 45
A B C D
 A B C D

B+

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
PQ6
AO4435_SO8

1
PC73

PC74

PC75
1 8
2 7
B+ PL19 3 6

2
PQ7 P2 PQ8 P3 PR45 HCB4532KF-800T90_1812 CHG_B+ 5
AO4435_SO8 AO4407A_SO8 0.02_2512_1%
VIN 8 1 1 8 1 4 2 1

4
7 2 2 7
CSIN @ PQ9

0.1U_0402_25V6K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
6 3 3 6 2 3
5 5 AO4435_SO8
1 8
CSIP 2 7

4
1
1 1

3 6

1
PQ11 TP0610K-T1-E3_SOT23-3 5

3
PQ10 PR46 PR47 10_0603_5%

5600P_0402_25V7K
2
DTA144EUA_SC70-3 200K_0402_1% DCIN

0.1U_0603_25V7K
3 1 1 2

4
P3

PC28
2
1

PC23

PC24

PC25

PC26
2 PR49

1
PC27
PR50 PQ12 47K_0402_1%

1
PR48 100K_0402_1% DTC115EUA_SC70-3 1 2

2
47K_0402_1% @ VIN

2
PR51 PD8
2

2
100K_0402_1% 2 FSTCHG PR52 PD9
1

2
1

PD10 2 1 2 1 10K_0402_1% 1 2 ACOFF

1SS355_SOD323-2 3
1 2 6251VDD SUSP# <27,31,34,41> 1SS355_SOD323-2

1
RB715F_SOT323-3 PR54

2.2U_0603_6.3V6K
PC29
2 PR53 200K_0402_1%

3
1

1
PQ13 10K_0402_1% 1 2 VIN
DTC115EUA_SC70-3 2 1 PU5 PC31
<31> FSTCHG 0.1U_0603_25V7K

2
DCIN

100K_0402_1%
1 2 1 24 2 1 PQ15 PD11
3

VDD DCIN
1

1
DTC115EUA_SC70-3 2 1 2

PR56
PC30
PR55 .1U_0402_16V7K 2 23 1SS355_SOD323-2
ACSET ACPRN
1

D 150K_0402_1% PR57
2 PQ14 20_0603_5%
2

1
G SSM3K7002FU_SC70-3 6251_EN CSON D
3 EN CSON 22 1 2

1
S @ PC34 PC32 PC33 2 PACIN
3

5
6
7
8
680P_0402_50V7K 0.047U_0603_16V7K 0.1U_0603_25V7K G
CSON

AO4466_SO8
1 2 4 21 1 2 PQ16
SSM3K7002FU_SC70-3

3
CELLS CSOP PR58 SSM3K7002FU_SC70-3
PC35 6800P_0402_25V7K 20_0603_5%

PQ17
2 2
1 2 5 ICOMP CSIN 20 2 1
1

2
D PR59 4
PQ18

2 PC36 PR60 6.81K_0402_1% PC37 20_0603_5%

G 1 2 1 2 6 19 0.1U_0603_25V7K1 2

1
VCOMP CSIP PL3 PR63
S
3

0.01U_0402_25V7K 1 2 PR62 47K_0402_1% PR61 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1% BATT+

3
2
1
PR64 1 2 7 18 LX_CHG 2.2_0603_1% 1 2 CHG 1 4
ICM PHASE

1
22K_0402_5% @ PC38 100P_0402_50V8J

4.7_1206_5%
5
6
7
8

PR65
PACIN 1 2 1 2 2 3
<35> PACIN
PC39 6251VREF DH_CHG

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
8 VREF UGATE 17
PR66 .1U_0402_16V7K PR67 PC40
154K_0402_1%<31> ADP_I
<35> ACON

AO4466_SO8
0_0603_5% 0.1U_0603_25V7K

1
PC41

PC42

PC107
2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1
<31> IREF CHLIM BOOT
1

1
PR68 4

1
75K_0402_1% PD12

680P_0603_50V8J
0.01U_0402_25V7K

2
PQ19

PC43
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1

2
1

1
PC44

ACOFF 2 PQ20 PR69 1 26251VDD

<31> ACOFF

3
2
1
DTC115EUA_SC70-3 120K_0402_1% PR70 11 14 DL_CHG
VADJ LGATE

2
20K_0402_1% PR71
2

4.7_0603_5%
2

12 13 PC45
3

1
GND PGND 4.7U_0805_6.3V6K

ISL6251AHAZ-T_QSOP24

PR72
15.4K_0402_1%
1 2
<31> CHGVADJ
1

3
PR73 3

31.6K_0402_1%
VIN
2

CP mode

1
Iada=0~3.42A(65W) CP= 92%*Iada; CP=3.147A
PR74
Vaclim=1.08V(65W) PR68=75k PR45=0.02 309K_0402_1%

PR75

2
10K_0402_1%
1 2
CC=0.25A~3A CHGVADJ=(Vcell-4)/0.10627 ADP_V <31>

1
IREF=1.016*Icharge Vcell CHGVADJ

1
PR76
47K_0402_1% PC46
IREF=0.254V~3.048V 4V 0V .1U_0402_16V7K

2
VCHLIM need over 95mV 4.2V 1.882V 2

4.35V 3.2935V

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 37 of 45
A B C D
 5 4 3 2 1

2VREF_51125

1U_0603_10V6K
D D

1
PC47

2
PR77 PR78
13K_0402_1% 30K_0402_1%
1 2 1 2

PR79 PR80
B++
20K_0402_1% 19.1K_0402_1%
PL20 1 2 1 2 B++
HCB4532KF-800T90_1812

ENTRIP2

ENTRIP1
B+ 2 1 +3VLP
PR81 PR82
150K_0402_1% 150K_0402_1%
1 2 1 2
10U_1206_25V6M

10U_1206_25V6M
1

1
PC48

PC49
4.7U_0805_10V6K
2

1
PU6

5
6
7
8
PC50

TONSEL
ENTRIP2

FB2

FB1

ENTRIP1
REF
8
7
6
5

1
C C
25 PQ22
PQ21 P PAD AO4466_SO8

2
AO4466_SO8
7 VO2 VO1 24 POK <36> 4
4
8 23 PC52
PR83 VREG3 PGOOD PR84 .1U_0402_16V7K
1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2

3
2
1
2.2_0603_1% BOOT2 BOOT1 2.2_0603_1%
1
2
3

PL4 PC51 UG_3V 10 21 UG_5V PL5

4.7U_LF919AS-4R7M-P3_5.2A_20% .1U_0402_16V7K UGATE2 UGATE1 4.7U_LF919AS-4R7M-P3_5.2A_20% +5VALWP
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1
1

8
7
6
5

5
6
7
8

1
LG_3V LG_5V
4.7_1206_5%

4.7_1206_5%
12 LGATE2 LGATE1 19
PR85

PR86
Ipeak=5A

SKIPSEL
PQ23 PQ24

VREG5
Imax=3.5A AO4712_SO8 AO4712_SO8
220U_6.3V_M

220U_6.3V_M
1 1

GND

VIN

NC
RT8205EGQW _W QFN24_4X4

EN
F=305kHZ
2

2
+ <35> EN0 +
PC53

PC54
4 4
PR87
Total capacitor

13

14

15

16

17

18
1

1
499K_0402_1%
680P_0603_50V8J

680P_0603_50V8J
2 2
220u
PC55

PC56
B+ 1 2
2

1
2
3

3
2
1

2
ESR=15m ohm

1
100K_0402_5%
1
1U_0402_6.3V6K

PR88
1 2
VL
PC57

PC58
@ PR89

4.7U_0805_10V6K
2
B 0_0402_5% B

Ipeak=5A

2
ENTRIP1 ENTRIP2 B++ Imax=3.5A
F=245kHZ

1
Total capacitor

0.1U_0603_25V7K
2
220u

PC59
1

D D
2VREF_51125
PQ25 2 2 PQ26 ESR=15m ohm
SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
S S
3

VL 2 1
1

PR90
100K_0402_1% PQ27
<36> VS_ON DTC115EUA_SC70-3

VS 1 2 2

PR91
42.2K_0402_1%

0.01U_0402_16V7K
1

100K_0402_1%
1
PR92

PC60

A A

@
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALWP/5VALWP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 38 of 45
5 4 3 2 1
 A B C D

1 PL6 1

B+ HCB4532KF-800T90_1812

2 1+VTTP_B+
4.7U_0805_25V6-K +5VS

4.7U_0805_25V6-K

4.7U_0805_25V6-K
VTTPW ROK <5,34>
1

1
PR93
VTTPW ROK_CPU <5>
PC61

PC62

PC63 3.4K_0402_1% PR94 2.2_0603_1%

2

1 2 1 2 1 2

BST_+VTTP
PR181 0_0402_5% PC64

DH_+VTTP
LX_+VTTP
1 2 1 2 0.1U_0603_25V7K
+5VALW
PR141 2.43K_0402_1% PR95 4.53K_0402_1%
Ipeak=20A

DH_+VTTP

5
PR96
Imax=14A
0_0402_5% PR97 PQ28

16

15
F=231.5kHZ

1
PU7 4.7_0603_5%
1 2 TPCA8030-H_SOP-ADV8-5
Total capacitor 1170u

UG
GND

PGOOD

PHASE

BOOT
+VTTP_VCC

2
4 ESR=3.33m ohm
3 VIN PVCC 14 1 2 PC65
+VTTP_VCC 2.2U_0603_6.3V6K
Arrandale 1.05V

3
2
1
4 13 DL_+VTTP PL7
VCC LG 1.0UH_PCMC104T-1R0MN_20A_20%
1

PC66 1 2
2

2.2U_0603_6.3V6K
+VTTP 2

APW 7138NITRL_SSOP16
12
2

PGND

4.7_1206_5%

390U_2.5V_M
1

1
TPCA8028-H_SOP-ADVANCE8-5
+

PQ29

PR99

PC67
1 2 5 11 SE_+VTTP 1 2
<31> VTTP_EN EN ISEN PR98
PR100 2

FSET
6.49K_0402_1%
0_0402_5%

2
VO
NC

FB
4

680P_0603_50V8J
.1U_0402_16V7K

1
6

10
1

PC69
3
2
1

2
PC68

+VTTP
FB_+VTTP
2

@ Material Note:
33.2K_0402_1%

0.01U_0402_16V7K
1

1
330uF/ 6mohm, number are 3,
1
@ PR101

57.6K_0402_1%

power x1, HW x2
PR102

@ PC70
2
1

2
2200P_0603_50V7K

@ PC71
33P_0402_50V8J
2

1
@ PC72
2

3 3

1 2 1 2+VTTP
PR103 PR104
3.32K_0402_1% 0_0402_5%
1

PR106 1 2
4.42K_0402_1% PR108 VTT_SENSE <8> PJ20
10_0402_5% +VTTP +1.05VS
2 1 Arrandale -- mount,
2

2 1
1
PR110
2
VSS_SENSE_VTT <8>
@ JUMP_43X79 Clarksfield --non mount @
(7.0A,280mils ,Via NO.=14)
10_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+VTTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NWQAA LA6061P M/B 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 24, 2010 Sheet 39 of 45
A B C D
 5 4 3 2 1

PL21
HCB2012KF-121T50_0805

1.5V_B+ 2 1 B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC91

PC92
D D

5
6
7
8

2
PQ34
AO4466_SO8

PR127
255K_0402_1% 4
1 2
PR128
0_0402_5%
1 2 BST_1.5V 1 2
<27,31> SYSON

3
2
1
PR129

1
2.2_0603_1% PC94 PL10

15

14
1
@PC93
@ PC93 PU10 0.1U_0603_25V7K 1.8UH_SIL104R-1R8PF_9.5A_30%
.1U_0402_16V7K 1 2 1 2

EN/DEM

NC

BOOT
+1.5VP

2
DH_1.5V

4.7_1206_5%
2 TON UGATE 13

1
PR131 LX_1.5V
Ipeak=9A

PR130
3 12

220U_6.3V_M
VOUT PHASE 1

5
6
7
8
100_0603_1%
+
Imax=6.3A

PC95
+5VALW 1 2 4 11 1 2 +5VALW PQ35
VDD CS PR132 AO4712_SO8 F=313kHZ

2
5 10 18K_0402_1%
FB VDDP 2 Total capacitor
1

1
6 9 DL_1.5V 4 610u

680P_0603_50V8J
PGOOD LGATE

PGND

PC97
PC96

GND
4.7U_0603_6.3V6K ESR=5m ohm
2

2
1
C C
RT8209BGQW _W QFN14_3P5X3P5 PC98

3
2
1
4.7U_0805_10V6K

2
PR133
10K_0402_1%
1 2
10K_0402_1%
1
PR134

B B

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23
+1.5VP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NWQAA LA6061P M/B 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 24, 2010 Sheet 40 of 45
5 4 3 2 1
 A B C D

+1.5V

1
PJ23

1
@ JUMP_43X79
1 1

2 2
PU11
1 6
VIN VCNTL +5VALW

4.7U_0805_6.3V6K
2 GND NC 5

1
3 VREF NC 7

1
PC100

1K_0402_1%
PR135
@ PR136 4 8 PC99

2
0_0402_5% VOUT NC 1U_0603_10V6K

2
1 2 9
<9,34> SUSP

2
TP
G2992F1U_SO8

PR137

0.1U_0402_10V7K
+0.75VSP

1
0_0402_5% D

1K_0402_1%
SSM3K7002FU_SC70-3
PQ36

PR138

PC102
1 2 2
<34> 0.75VR_EN# G

1
S

3
1
PC103

2
@ PC101 10U_0805_6.3V6M

2
.1U_0402_16V7K

2
2 2

PL22
HCB2012KF-121T50_0805 PL9

4
PU9 2.2UH_FMJ-0630T-2R2 HF_8A_20%
2 1 10 2 LX_SY8033B 1 2

PG
+5VALW PVIN LX +1.8VSP
1

1
9 PVIN LX 3
PC85 PR126
22U_0805_6.3V6M 8 4.7_1206_5%

22U_0805_6.3V6M

22U_0805_6.3V6M
2

3
SVIN 3

1
6 FB_SY8033B PC86

1 2
FB

1
PC88

PC89
1 2 EN_SY8033B 5 PR124 68P_0402_50V8J
<27,31,34,37> SUSP# EN

NC

NC
TP PC90 51.1K_0402_1%

2
PR122 680P_0603_50V8J

2
1

0_0402_5%
11

2
1

@ PR125 @ PC83 SY8033BDBC_DFN10_3X3

499K_0402_1% .1U_0402_16V7K
2
2

1
PR123
25.5K_0402_1%

2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
0.75VSP/+1.8VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 41 of 45
A B C D
 8 7 6 5 4 3 2 1

CPU_VID0 2 1 PR142 1K_0402_1% CPU_VID0 2 1 @ PR143 1K_0402_1% +CPU_B+

PL11
CPU_VID1 2 1 PR144 1K_0402_1% CPU_VID1 2 1 @ PR145 1K_0402_1% HCB4532KF-800T90_1812
1 2 B+
CPU_VID2 2 1 PR146 1K_0402_1% CPU_VID2 2 1 @ PR147 1K_0402_1%

PR150 0_0402_5% CPU_VID3 2 1@ PR148 1K_0402_1% CPU_VID3 2 1 PR149 1K_0402_1%

10U_1206_25V6M

10U_1206_25V6M
2200P_0402_50V7K
470P_0603_50V8J

0.1U_0603_25V7K
H 1 2 1 1 1 H

68U_25V_M_R0.36

68U_25V_M_R0.36

68U_25V_M_R0.36
<8> CPU_VID0
PR153 0_0402_5% CPU_VID4 2 1@ PR151 1K_0402_1% CPU_VID4 2 1 PR152 1K_0402_1%

1
+ + +

PC112

PC116

PC113

PC114

PC111

PC185

@ PC115
<8> CPU_VID1 1 2
PR156 0_0402_5% CPU_VID5 1 PR154 1K_0402_1% CPU_VID5 1 @ PR155 1K_0402_1%

PC110
2 2
<8> CPU_VID2 1 2

2
5
PR159 0_0402_5% CPU_VID6 2 1@ PR157 1K_0402_1% CPU_VID6 2 1 PR158 1K_0402_1% 2 2 2
1 2 PQ37
<8> CPU_VID3
PR162 0_0402_5% H_DPRSLPVR 2 1 PR160 1K_0402_1% H_DPRSLPVR 2 1 @ PR161 1K_0402_1%
1 2 TPCA8030-H_SOP-ADV8-5
<8> CPU_VID4
PR164 0_0402_5% H_PSI# 2 1 PR163 1K_0402_1%
<8> CPU_VID5 1 2 4
PR165 0_0402_5%
1 2 +VTT
<8> CPU_VID6
PC117

3
2
1
PR166 2.2_0603_1% 0.22U_0603_25V7K
PR167 0_0402_5% BOOT2 1 2 BOOT2_2 1 2
1 2 PL12
<31> VR_ON
UGATE2 0.36UH_PCMC104T-R36MN1R17_30A_20%
G PR168 0_0402_5% G
1 2 PHASE2 4 1 +CPU_CORE
<8> H_DPRSLPVR
3 2 V2N
<13> CLK_ENABLE#

5
@ PQ38

PR169
4.7_1206_5%

10K_0402_5%
1

1
TPCA8028-H_SOP-ADVANCE8-5
PQ39

3.65K_0805_1%
+3VS PR172 TPCA8028-H_SOP-ADVANCE8-5 PR171
1.91K_0402_1% 1_0402_5%

PR170

PR173
1 2 CLK_ENABLE# @ PR175
LGATE2 4 4 0_0402_5%

2
2

1 2 V1N
PR174
1.91K_0402_1%
PR177 VSUM+

3
2
1

3
2
1

1
0_0402_5%

680P_0603_50V8J
<18,31> VGATE
1

VSUM-

PC118
1 2

2
@ PR178 1K_0402_1%
F
1 2 ISEN2 F
+VTT
PR179 0_0402_5%
<8> H_PSI# 1 2
PR180
1 2 ISL62883HRZ-T_QFN40_5X5~D
147K_0402_1%
PC119 +5VALW
1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

PU13 1 2
CLK_EN#
DPRSLPVR

VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR_ON

2
30 PR183
BOOT2
29 0_0402_5%
UGATE2
1 28
PGOOD PHASE2
2 27

1
PSI# VSSP2
3 26
RBIAS LGATE2
4 25
VR_TT# VCCP
E 5 24 E
NTC PWM3
6 23
VW LGATE1
7 22
COMP VSSP1
8 21
FB PHASE1
9
ISEN3
UGATE1

1 2 10 PR186 0_0402_5%
BOOT1
ISUM+

ISEN2
ISEN1

ISUM-
VSEN

IMON

1 2
249K_0402_1%

8.06K_0402_1%

1U_0603_10V6K
VDD
1000P_0402_50V7K

RTN

VIN

PC126 41
AGND
1

22P_0402_50V8J
PC127

PC128
PR189

PR188

11
12
13
14
15
16
17
18
19
20

PR194
2

562_0402_1% PC130
@ 1 2 1 2
2

390P_0402_50V7K
PR196 PR195 0_0402_5%
2.43K_0402_1% 1 2
1 2 1 2 <8> IMVP_IMON Arrandale -- 2 phase 1H1L
PC131 PR198 0_0402_5%
D 10P_0402_50V8J 1 2 +CPU_B+ D
0.22U_0603_25V7K

1 2 1 2
PR201 1_0402_5%
PC132 PR199 1 2 +5VALW +CPU_B+
150P_0402_50V8J 412K_0402_1% ISEN2 1 2
1

1
PC133

PC134

PC135
1U_0603_10V6K

0.22U_0603_25V7K

PR202 0_0402_5%
PC137 0.22U_0402_6.3V6K

PC138 0.22U_0402_6.3V6K

ISEN1 1 2 PR204
2

BOOT1

8.87K_0402_1%

470P_0603_50V8J
5
Layout Note: PR203 0_0402_5%

10U_1206_25V6M

10U_1206_25V6M
2

PQ43
1

1
PH3 place near VSSSENSE

PC139
TPCA8030-H_SOP-ADV8-5

PC140

PC141
Phase1 L-MOS
2

2
VSUM+ UGATE1 4

+CPU_CORE 1 2
PC143
1

C @ PR205 10_0402_5% PR207 2.2_0603_1% 0.22U_0603_25V7K C

3
2
1
0.047U_0402_16V7K

1
VSUM-

1 2 BOOT1_1 1 2
2.61K_0402_1%
0.22U_0603_10V7K

PL14
PR208

PR206 0.36UH_PCMC104T-R36MN1R17_30A_20%
1

82.5_0402_1%
PC144

PC145

<8> VCCSENSE 1 2
2

PHASE1 4 1 +CPU_CORE
2

PR209 0_0402_5%
2

2
1

3 2 V1N
1

5
TPCA8028-H_SOP-ADVANCE8-5
PC146

TPCA8028-H_SOP-ADVANCE8-5
PQ44

@ PQ45
330P_0402_50V7K

4.7_1206_5%
2

1
10K_0402_1%_ERTJ0EG103FA

PC147

PR210

10K_0402_5%
3.65K_0805_1%
2

1
0.01U_0402_25V7K PR213
1_0402_5%
LGATE1

PR212
4 4
330P_0402_50V7K

@ PR216

PR211
11K_0402_1%

2
1

PH4

PC148 0_0402_5%
PC149

PR215

2
1000P_0402_50V7K 1 2 1 2 V2N
PR217 0_0402_5%
2

3
2
1

3
2
1

1
1 2 PR214 VSUM-

680P_0603_50V8J
2

B <8> VSSSENSE B
1.2K_0402_1%

PC150
2
@ PR219 10_0402_5%
1 2 1 2 1 2 VSUM- VSUM+
@ PC186 @ PR220 ISEN1
Layout Note:
1200P_0402_50V7K 100_0402_1%
Place near Phase1 Choke
.1U_0402_16V7K
1

PC151
2

A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 42 of 45
8 7 6 5 4 3 2 1
 A B C D E F G H

1 1

<9>

<9>

<9>

<9>

<9>

<9>

<9>
GFXVR_VID_0

GFXVR_VID_1

GFXVR_VID_2

GFXVR_VID_3

GFXVR_VID_4

GFXVR_VID_5

GFXVR_VID_6
<9>
GFXVR_EN
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
+5VS

+GFX_B+ PL15
HCB4532KF-800T90_1812

2
+1.05VS

PR221

PR222

PR223

PR224

PR225

PR226

PR227

PR231
2 1 B+
1

PR228
@ PR229 10_0603_1%
300K_0402_5%

10U_1206_25V6M

10U_1206_25V6M
1

1
PC152

PC153
GFX_EN
2

2
<9> GFXVR_IMON GFX_IMON

5
GFX_VCC
+3VS PC154
1

1U_0805_25V6K

32

31

30

29

28

27

26

25

2
0.056U_0402_16V7K
1

PR232
PQ46
PC155

6.98K_0402_1%

VID0

VID1

VID2

VID3

VID4

VID5

VID6
EN
1
2

24 PR234 PC157 4 NTMFS4921NT1G_SO8FL-5

2

PR233 VCC 2.2_0603_1% 0.22U_0603_25V7K

1
10K_0402_1% PWRGD
23 GFX_BOOST 1 2GFX_BOOST-1
1 2
1

GFX_IMON BST
2
2

PC156 IMON GFX_DRVH PL16

22

3
2
1
1000P_0402_50V7K DRVH 0.36UH_PCMC104T-R36MN1R105_30A_20%
2 3 2
2

VSS_AXG_SENSE CLKEN# GFX_SW

21 1 2
4
SW +GFX_COREP
FBRTN ADP3211AMNR2G_QFN32_5X5 20 +5VS

1
PVCC

TPCA8028-H_SOP-ADVANCE8-5
GFX_FB

PQ47
1 2 5
FB PU15 GFX_DRVL
PC158 PC160 1 GFX_COMP 6 DRVL
19 2 1
PR235
1 Ipeak=22A
COMP
220P_0402_50V7K 47P_0402_50V8J
PGND
18 PC159 4.7_1206_5% + PC161 Imax=15.4A
GFX_VCC 7 2.2U_0603_10V6K 390U_2.5V_M
2

12
1 2 1 2GFX_COMP-1
1 2
GPU
AGND
17 4 F=350kHZ
GFX_ILIM 8 PC163 2
Total capacitor

CSCOMP
PR236 PC162 PR237 ILIM 680P_0603_50V8J
33

CSREF

2
AGND

RAMP

LLINE

CSFB
1K_0402_1% 470P_0402_50V8J 20K_0402_1% 720u

IREF

RPM

RT

3
2
1
ESR=3.75m ohm

10

11

12

13

14

15

16
2

PR238
10.7K_0402_1%
GFX_IREF

GFX_RAMP

GFX_CSCOMP

GFX_CSFB

GFX_CSCOMP
GFX_RT
2 GFX_RPM
PH5
GFX_CSCOMP 1

220K_0402_5%_ERTJ0EV224J~D

1 2
80.6K_0402_1%

237K_0402_1%

340K_0402_1%
2

2
PR239

Avoid high dV/dt

PR240

PR241

Place RTH1 close to inductor

PR242
71.5K_0402_1% on the same layer
1

2 1
422K_0402_1%
1

1
2

PR245

1
PR243 PR244

1
0_0402_5% 0_0402_5% PC165
560P_0402_50V7K PR246
2

PC164 165K_0402_1%
1

2
1000P_0402_50V7K

2
PR248 2 1
1K_0402_1%
3 3
+GFX_B+ 2 1 GFX_RAMP-1 PR247
40.2K_0603_1%
<9>

<9>

Connect to input caps

VSS_AXG_SENSE

VCC_AXG_SENSE

PC166 PC167
1000P_0402_50V7K 1000P_0402_50V7K
2

Shortest the
Switchable -- mount
net trace Non Swithchable--non mount @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/02 Deciphered Date 2010/10/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+GFX_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: Wednesday, March 24, 2010 Sheet 43 of 45
A B C D E F G H
OP!EBUF!!!!!!!!!!!!!!!!!!!QBHF!!!!!!!!!!!!!!!!!!!!!!!!!!!NPEJGJDBUJPO!MJTU!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!QVSQPTF
................................................................................................................................
EVT P39-PWR_+VTTP Change PR141 2.26k to 2.43k Modify VTTPWROK voltage (2009/11/25)
EVT P39-PWR_+VTTP Remove PC71 33P, PC72 2200P, PR101 33.2k APW7138 not use this function (2009/11/25)
EVT P38-PWR_3VALWP/5VALWP Change PR92 49.9k to 42.2k Modify VS divider voltage to drive MOS (2009/11/25)
EVT P42-PWR_CPU_CORE Change PL12,PL14 SH000005680 to SH00000IK00 Use 5% DCR choke (2009/11/25)
EVT P43-PWR_GM VGA_CORE Change PH5 SL20000058L to SL200000500 Use Compal PN (2009/11/25)
DVT P48-PWR_BATTERY CONN / OTP Add PD6, PD7 ESD diode For ESD solution(2009/12/28)
DVT P43-PWR_GM VGA_CORE Change PL16 SH00000HK00 to SH00000IK00 Use same PN choke (2009/12/28)
DVT P42-PWR_CPU_CORE Change PC114, PC111, PC185 from SF000000F80 to Cost down (2009/12/28)
SF000000W00
DVT P43-PWR_GM VGA_CORE Change PC161 to SGA00002680 For DVT budding(thermal issue), it will change to original type for PVT (2009/12/28)
DVT P50-PWR_3VALWP/5VALWP Change PR83,PR84 0 to 2.2 Add boost resistor(For EMI solution)(2009/12/28)
Add PR85,PR86 4.7 and PC55,PC56 680P Add snubber(For EMI solution)(2009/12/28)
DVT P42-PWR_CPU_CORE Change PR166,PR207 0 to 2.2
Add PR169,PR210 4.7 and PC118,PC150 680P
DVT P55-PWR_GM VGA_CORE Change PR234 0 to 2.2 Add boost resistor(For EMI solution)(2009/12/28)
Add PR235 4.7 and PC163 680P Add snubber(For EMI solution)(2009/12/28)
DVT P48-PWR_BATTERY CONN / OTP Change PR33 10k,PR31 21k to 19.6k, PR34 9.53k to Adjust OTP setting point(2009/12/28)
8.66k, PR40 47k to 7.87k

DVT P39-PWR_+VTTP Change PR98 4.99k to 6.49k Adjust VTT_DIS OCP to 27.49A (2009/12/31)
DVT P49-PWR_CHARGER Add PC73,PC74,PC75 10U Reserve for EMI solution(2009/12/28)
DVT P42-PWR_CPU_CORE Change PR204 8.25k to 8.87k Adjust resistor for Imon (2009/12/31)
DVT P55-PWR_GM VGA_CORE Change PR247 34.8k to 40.2k Adjust GFX load line (2009/12/31)
DVT P41-PWR_0.75VSP/1.8VSP Change PC90 SE025681K80 to SE024681J80 Use same PN (2009/12/31)
PVT P41-PWR_0.75VSP/1.8VSP Remove PR136, Add PR137 0 Ohm For S3 power saving function (2010/02/03)
PVT P43-PWR_GM VGA_CORE Change PC161 to SF000002O00 Change to original type for PVT (2010/02/03)
PVT P49-PWR_CHARGER Change PC24,PC25,PC26 4.7U to 10U For EMI solution(ISN test) (2010/02/03)
PVT P49-PWR_CHARGER Add PC107 10U For EMI solution(ISN test) (2010/02/03)
PVT P49-PWR_CHARGER Add PC73,PC74,PC75 10U For EMI solution(ISN test) (2010/02/03)
PVT P49-PWR_CHARGER Add PC76 0.1U For ESD solution (2010/02/03)
PVT P38-PWR_3VALWP/5VALWP Change PQ27 from SSMK7002 to DTC115EUA Use low Vth Transistor (2010/02/03)
PVT P43-PWR_GM VGA_CORE Change PQ46 TPCA8030 to NTMFS4921NHT1G For EMI solution (2010/02/03)
Pre MP P52-PWR_1.05VSP/1.8VSP Change PR123 316k to 25.5k,PR124 402k to 51.1k Adjust 1.8V voltage divided resistor (2010/03/07)
Pre MP P52-PWR_1.05VSP/1.8VSP Change PU9 from MP2121 to SY8033 MP2121 ESD fail (2010/03/07)
Pre MP P52-PWR_1.05VSP/1.8VSP Delete PR125 0 Ohm Change for SY8033 solution(2010/03/07)
Change PC85 from 0.1U to 22U
Delete PC87 10UF, PC84 0.1U
Pre MP P52-PWR_1.05VSP/1.8VSP Change PC86 10U to 68P Improve 1.8V transient under shoot(2010/03/07)
Pre MP P49-PWR_CHARGER Change PC24,PC25,PC26 10U to 4.7U 10U 0805 size price too high(2010/03/07)
Pre MP P47-PWR_DCIN/DECTOR Change PC12 from SE033105Z80 to SE000001380 Change PN(2010/03/07)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NWQAA LA6061P M/B 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, March 23, 2010 Sheet 44 of 45
 5 4 3 2 1

PIR (Product Improve Record)

NWQAA LA-6061P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 0.2
GERBER-OUT DATE: 2009/12/30
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------
1 12/7 25 Add +5VALW for JPIO pin5 For BACK_SENSE detect
D
2 12/7 13 Remove JLVDS pin10 and pin12 for +LCDVDD_R 3D Panel max. current is 1.5A D

3 12/8 33 Combine JTOUCH and JLP to JTPL and remove C648 For ME cost down
4 12/17 33 Remove D19 Move D19 to LS-6061P
5 12/18 26 Reverse JBT pin definition Due to pin reverse
6 12/18 30 Add RA43 For codec EC_MUTE# issue
7 12/21 29 Change JREAD to Push-push type (R015-211-LM-A) For PRD update
8 12/21 13 Move LED_PWM and BKOFF#_R to JLVDS pin10 and pin12 For avoiding +LCD_INV short issue
9 12/22 32 Change H7 footprint to "DEBUG_PAD-MB-S" For debug use
10 12/23 27 Add D24 and Q36 for BT_CTRL For WLAN & BT combo module
11 12/23 21 Add R461 For CIR_EN#
12 12/24 25 Change JPIO footprint and reverse its pin definition For ME request
13 12/24 15 Add R145 For U9 ESD damage issue
14 12/24 29 Add F3 For Card reader issue
15 12/29 25 Add R148 and R149 For Sleep & play music
16 12/29 13 Add C871 and C872 For RF request
---------------------------------------------------------------------------------------------------------------------
NWQAA LA-6061P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2 TO 0.3
C GERBER-OUT DATE: 2010/02/08 C

NO DATE PAGE MODIFICATION LIST PURPOSE

---------------------------------------------------------------------------------------------------------------------
1 1/15 30 Add RA43 For sleep & music on battery mode
2 1/21 31 Add R462 Avoid VR_ON floating
3 1/25 32 Change UG3 to SA000022I00 For LDO issue
4 1/25 33 Change SW2 to @ For ME interfere issue
5 2/1 15 Add R130 For AOC monitor issue
6 2/1 31 Change U19 to SA00001J5A0 For KB926 E0 version
7 2/1 29 Remove F3 For UC1 ES2 sample
8 2/1 16 Add D19 and R150 For RTC charge issue
9 2/2 31 Add CAP_RST# to EC For ESD issue
10 2/3 29 Change RC7 to 33 ohm For EMI request
---------------------------------------------------------------------------------------------------------------------
NWQAA LA-6061P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.3 TO 1.0
GERBER-OUT DATE: 2010/03/15
NO DATE PAGE MODIFICATION LIST PURPOSE
B
--------------------------------------------------------------------------------------------------------------------- B
1 3/6 29 Add QC2 and RC16 For O2 B0 workaround
2 3/7 16 Change D13.2 power to +CHGRTC For RTC issue
3 3/12 33 Change H15~H19 to H_3P3 For ME request
4 3/15 33 Remove SW2 For ESD request
5 3/15 30 Change CA9 and CA10 to 1U For cut-off frequency
6 3/16 30 Change MONO_IN to AGND For high frequency noise issue
---------------------------------------------------------------------------------------------------------------------
NWQAA LA-6061P SCHEMATIC CHANGE LIST
REVISION CHANGE: 1.0 TO 2.0
GERBER-OUT DATE: 2010/03/19
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------
1 3/17 29 Change cardreader to JMB385/389 For customer request
2 3/18 31 Remove D86 For ESD request
3 3/18 22 Add R52 For CRT wave issue
4 3/19 22 Change L12 to 2.2 ohm For CRT wave issue
5 3/22 15 Add D54 For HDMI CEC issue
A 6 3/24 13 Change C213 to 1U For NALAA ESATA performance low issue A

---------------------------------------------------------------------------------------------------------------------

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/10/05 Deciphered Date 2010/01/23 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NWQAA LA6061P M/B
Date: W ednesday, March 24, 2010 Sheet 45 of 45
5 4 3 2 1