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PWM Datasheet

The document describes a hardware pulse width modulation (PWM) signal generator that can be implemented on an FPGA. It contains registers and counters to store the PWM period and duty cycle values. The PWM generator provides complementary PWM outputs and a programmable dead zone to prevent simultaneous output activation. An 8051 microcontroller interface allows programming the PWM period, duty cycle, and dead zone registers. A C program example shows how to control the PWM duty cycle using push buttons connected to an 8051.

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baruaeee
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
144 views

PWM Datasheet

The document describes a hardware pulse width modulation (PWM) signal generator that can be implemented on an FPGA. It contains registers and counters to store the PWM period and duty cycle values. The PWM generator provides complementary PWM outputs and a programmable dead zone to prevent simultaneous output activation. An 8051 microcontroller interface allows programming the PWM period, duty cycle, and dead zone registers. A C program example shows how to control the PWM duty cycle using push buttons connected to an 8051.

Uploaded by

baruaeee
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Hardware PWM Generator

_____________General Description _______________________Features

A Pulse Width Modulation (PWM) • Built-in 8051 interface hardware


signal generator works by varying the • 10-bit user selectable period
duty cycle of a square wave while • Complementary outputs provided
keeping the period fixed. The hardware for use in H-Bridge applications
PWM generator was designed for
implementation on a Xilinx XC4005XL • 4-bits programmable dead zone
FPGA. It contains circuitry that allows counter
easy interface to an 8051
microcontroller.
____________Contact Information
The hardware PWM generator provides
a 10-bit user selectable period and a Dr. Daryl Beetner
programmable dead zone to prevent the University of Missouri-Rolla
PWM signal and its complement to be Department of Electrical and Computer
active at the same time, an important Engineering
feature in H-bridge/motor applications. 1870 Miner Circle
Rolla, MO-65409-1060

___________________Applications http://www.ece.umr.edu/courses/cpe214

Motor speed control


Switching power supply
Communications
Dimmers
Heat control

______________Pin Configuration

Figure 1. Pin configuration

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Hardware PWM Generator
_____________________________________________________Functional Diagram

Figure 2. Functional diagram

PIN Name Description


P0(7:0) Multiplexed Address/Data bus
P2(7:0) High Byte address bus
ALE Address Latch Enable – address is latched on falling edge
Clk System clock
RD/ Active low read enable
WR/ Active low write enable
RESET/ Active low reset
PwmH PWM output
PwmL Complementary PWM output
P0_out(7:0) 8-bit output used for testing the model
P0_out_E Enable for tri-state buffer

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Hardware PWM Generator
______________Detailed Description prevent abrupt changes in PWM output.
Changes to the period and duty cycle
Model Function thus take effect upon the next reload of
the period counter.
Registers
The hardware PWM generator consists Slow Clock Generator
of several registers and counters as The clock to the counters is provided
shown in Figure 2. Two 2-bit registers from a slow clock generator, such that a
and two 8-bit registers are used to store low frequency PWM signal can be
the 10 bit period and duty cycle. A 4-bit generated. Using the main 12MHz
register is used to store the system clock to generate a low
programmable dead-zone value. These frequency signal would make the PWM
registers are written to through an 8051 too large to synthesize easily.
interface, in which Port 0 is an 8-bit
multiplexed address-low/data bus and Output Generator
Port 2 is the upper 8 bits of the address The output generator is responsible for
bus. generating pwmH and its
complementary (pwmL) signal. The
Decoder pwmH signal is set high as the period
The decoder is used to map registers and duty counters begin to count down
within the 8051’s external address space. from their maximum values. Once the
The registers locations are shown below. duty cycle counter reaches zero, the
pwmH signal is set low, and the dead
Address Register zone counter begins to count down.
0xFFFB Low 8 bits of period Once the dead zone counter reaches
0xFFFC High 2 bits of period (least zero, the pwmL signal is set to high.
significant bits used) When the period counter reaches the
0xFFFD Low 8 bits of duty cycle value stored in the dead zone register,
0xFFFE High 2 bits of duty cycle the pwmL signal is set to low. When the
(least significant bits used) period counter reaches zero, the pwmH
0xFFFF 4-bit programmable dead signal is set high again. This way the
zone (only least significant 4 pwmH and pwmL signals are never
bits used) active at the same time.

Counters 8051 Interface


The period, duty cycle and dead zone The hardware PWM generator output
counters are countdown counters, which can be easily controlled with an 8051.
are loaded with the values from their P0, P2, ALE, RD/, and WR/ are simply
respective registers. These counters are connected to the associated signals on
used for timing inside the model. They the 8051. Figure 3 shows the appropriate
count down to zero, then stop and wait connections within the XC4005
until the period counter reaches zero, at schematic.
which point all counters are reloaded
with the current values in their
respective registers. This helps to

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Hardware PWM Generator

Figure 3. XC4005 schematic with hardware PWM generator

_______________________________________________________________________4
Hardware PWM Generator
___________________________________________________________8051 Interface

Below is a sample C program for the 8051 to control the duty cycle of the hardware
PWM generator using push-buttons. The pushbuttons are connected to ground and to
pins P1^0, P1^1, and P1^2.

#include <reg51.h>
#include <absacc.h>
#define BASE 0xfff8 // base address
#define TL XBYTE[BASE+3] // low 8 bits of period (0xFFFB)
#define TH XBYTE[BASE+4] // high 2 bits of period (0xFFFC)
#define DCL XBYTE[BASE+5] // low 8 bits of duty cycle (0xFFFD)
#define DCH XBYTE[BASE+6] // high 2 bits of duty cycle (0xFFFE)
#define DZ XBYTE[BASE+7] // 4 bits of dead zone (0xFFFF)

#define uchar unsigned char


#define uint unsigned int
#define CLKPERIC 12 // 12 for regular 8051, 6 for 89C51Rx2's
#define FCLK 12 // clock frequency in MHz

// In hardware (XC4005 schematic) PWM signal is connected to port 1 pin 5 as shown in


// Figure 3

sbit INC=P1^0; // input pin, if zero increase the duty cycle


sbit DEC=P1^1; // input pin, if zero decrease the duty cycle
sbit STOP=P1^2; // input pin, if zero stop generating PWM signal,
// by making duty cycle zero

// this function is used to get rid of push buttons bouncing


/* delay for t msec. Use timer 0 */
void msec(uint t){
#define T1000 (-1000+22)*FCLK/CLKPERIC
TMOD=(TMOD&0xF0) | 0x01; /* 16bit timer mode */
while (t>0) { /*delay 1 msec */
TH0= (T1000) >> 8; /* upper half of -1000 (0xfc) */
TL0= (T1000) & 0xff; /* lower half of -1000 (0x18) */
TR0= 1; /* start timer 0 */
while (~TF0); /* wait for TF0=1 */
TR0= 0; /* stop timer and clear overflow bit */
TF0= 0;
t=t-1;
}
}

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Hardware PWM Generator

void main(void){

TL= 255; // fix the frequency of the PWM signal to 256 * slow clock
// period
TH= 0; // high 2 bits of period register
DZ= 1; // dead zone=1
DCH=0; // high 2 bits of duty cycle
DCL=100; // initial value of duty cycle
STOP=1; // inputs pulled high initially
INC=1;
DEC=1;

while(1) {
if (~STOP){
DCL=0; // stop generating PWM signal
msec(700); // delay to take care of push-button bouncing
}
else {
if (~INC) {
DCL=DCL+5; // increment duty cycle
msec(700); // delay to take care of push-button bouncing
}
else {
if (~DEC) {
DCL=DCL-5; // decrement duty cycle
msec(700); // delay to take care of push-button bouncing
}
}
}
} // end of while
} // end of main

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