Defect Detection in Si-Wafer
Defect Detection in Si-Wafer
Defect Detection in Si-Wafer
Abstract
Defects in silicon wafers have been of great scientific and technological
interest since before the earliest days of the silicon transistor. Recently
much attention has been focused on crystal originated pits on the polished
surface of the wafer. These defects have been shown to contribute to gate
dielectric breakdown. The present work relates to surface and/or subsurface
defect inspection systems for semiconductor industries and particularly to an
inspection system for defects such as swirl defects and groups of particles in
unpolished silicon wafers before the wafer reclamation and/or the wafer
fabrication process using a digital shearography technique. The method
described here relates specifically to semiconductor wafers, but may be
generalized to any other samples. In the present work, surface or subsurface
defects are detected and evaluated by stressing the silicon wafer while
looking for defect-induced anomalies in a fringe pattern, generated by the
interference of two speckle patterns, in the CCD camera and digital image
processing.
1. Introduction been utilized for the surface defect characterization [1]. How-
ever, in the semiconductor industry, the main challenge lies in
Silicon wafers are widely used in the semiconductor and the characterization of subsurface as well as surface defects.
microelectronics industries. With this material, there is There has been very little research work in the characterization
an immense need to obtain a defect-free highly polished of subsurface defects in Si wafers.
surface for improved yield and performance of the micro- Optical interferometric techniques have been used for non-
components. The current practice in the semiconductor destructive testing (NDT) of objects. Two of these techniques
industry is to inspect the wafers for any surface defects only are electronic speckle pattern interferometry (ESPI) and
at the end of the final polishing stage. At this stage, the speckle shearing interferometry, also known as shearography.
subsurface defects are visible (as they have been exposed by These techniques have been used to detect hidden defects
polishing) as minute spots forming spiral rings or ‘swirls’. in aircraft parts, turbine blades, space vehicles, automobiles
These subsurface defects, which cannot be detected before and many other products [2]. Shearography is a laser
the reclamation process or wafer fabrication process, cause optical method, which is suited for either NDT or for
a high wafer rejection rate at the end of the finishing stage. strain analysis. In contrast to holography, which measures
Unfortunately, there is no instrument currently available to surface displacements, shearography measures derivatives
inspect the ‘prime’/‘test’ wafers at the subsurface level before of surface displacements. Since strains are functions of
wafer fabrication/reclamation. displacement derivatives, shearography allows strains to be
Several techniques such as x-ray, atomic force mi- determined without numerical differentiating displacement
croscopy, scanning tunnelling microscopy, scanning electron data. Defects in objects normally create strain concentrations;
microscopy, and acoustic scanning electron microscopy have it is easier to correlate defects with strain anomalies
using shearography than displacement anomalies applying be a defective wafer. This is because, each time the wafer is
holography. Furthermore, rigid body motions do not produce reclaimed, about 15 µm thickness of wafer will be processed
strain, thus shearography is insensitive to such motions and and inspected for particles.
does not need to adopt any particular device for vibration The study of defects in silicon crystals has been an integral
isolation [2]. part of silicon research activity from the earliest days of the
The bare, ground, lapped or etched wafer surfaces are used silicon transistor. In the mid-1970s, Rozgonyi [5] noted the
to inspect the subsurface defects by digital shearography [3]. importance of suitable diagnostics in detecting and identifying
The qualitative inspection of subsurface defects and the the various types of defects in the crystal. Over the last
principles and method of inspection are described in this paper. two decades, many new diagnostic tools have been developed
The quantitative analysis and serial automatic measurement of and effectively employed. This led the industry to a greatly
small areas are being carried out using a macro focus lens at improved understanding of defects in silicon and resulted in
different locations on the wafer to detect distributed subsurface a significant reduction in yield losses while the number of
wafer particles of micron size. processing steps increased more than eightfold [6].
Typically, a semiconductor wafer may have a very large
2. Inspection in semiconductor wafer manufacturing number of defects, of varying patterns, such as swirl, cluster
or random particles, voids, scratches, cracks or damage,
The Semiconductor Industry Association’s (SIA) International which may have resulted from a great number of causes,
Technology Roadmap for Semiconductors [4] identifies lack such as crystal pulling during crystal growth or improper
of progress in the inspection and characterization of defects control of process parameters during the lapping, etching
and particles on wafers to be a potential barrier to device and polishing processes. Among all of these, the most
miniaturization. The roadmap specifies that by 2005, 30 nm interesting were the ‘swirl’ defects, which were attributed to
particles must be detectable on bare silicon and nonmetallic vacancy clustering such as voids or vacancy-type dislocation
films, 39 nm particles on metallic films and 100 nm particles loops, until their discovery by electron microscope. Swirl
on wafer backsides, for which no solutions currently exist. defects are classified into two types: ‘A’ (larger) and ‘B’
Semiconductor wafer manufacturers already use lasers to (smaller). In 1975, ‘A’ defects were identified as interstitial-
detect particles on expensive silicon wafers, which contain type dislocation loops by electron microscopy, although ‘B’
hundreds of chips. But the manufacturing operation must be defects could not be detected [7]. The practitioners in
shut down while workers try to determine what the particles the production lines prefer abbreviations like ‘COP’ (crystal
are made of and where they came from, especially when large originated particles or pits) or ‘LPD’ (light point defects). The
quantities are found. The source of the particles must be COPs have attracted much interest because they may decrease
eliminated before production can resume. As the features in reliability and manufacturing yield of semiconductor devices.
circuits are getting smaller every 18 months or so, the size of a Recently, COPs have been recognized as surface defects
killer defect is getting smaller and smaller. Because circuits in or micro-pits generated during the crystal ingot growing
new computer chips are only slightly wider than the particles, process and detected by particle counters after surface cleaning
the contaminants are large enough to short-circuit the tiny processes [8].
‘wires’ in the chips. With the need to detect smaller defects, In order to increase the yield in the manufacturing process,
the costs of inspecting wafers are skyrocketing. In order for the said defects are to be detected at an early stage of the
new advances to be implemented in production environments, process as well as controlled during the production process.
improvements in sensitivity must be achieved. In the mid 1980s, surface (visual) defects (scratches, voids,
The processing cost of silicon wafers and the control of particles, masking errors, etc) were considered to have the
defects (at sub-micron size and, especially, those present at greatest impact on semiconductor yield. This led to the
subsurface level) on these wafers are most critical to the wafer development of automatic surface defect detection equipment
fabrication/reclamation industries. It has been reported that and fabrication procedures designed to identify, control and
millions of dollars were lost each year owing to the failure eliminate sources of surface defects. Commercial wafer defect
of detecting these defects in silicon wafers prior to the wafer inspection systems, such as KLA’s Tencor instrument, are
fabrication/reclamation processes. The wafers produced by currently available to surface inspect the defects at the end
the wafer fabrication process are called as ‘prime’ wafers. of the manufacturing process in semiconductor industries.
Wafers which fail to meet certain standards, will be rejected Unfortunately the same level of success has not been achieved
at different stages of the fabrication process. These rejected for subsurface (non-visual) defects. Optical or e-beam
wafers are known as ‘test’ wafers. ‘Test’ wafers are useful techniques that have been used successfully to identify and
for monitoring the operation of the device manufacturing steps remove sources of surface defects cannot be applied to
during trial runs before the start of actual device manufacturing subsurface defects. Some of these defects are generally
using the ‘prime’ wafers. ‘Test’ wafers can be used 5–6 associated with open contacts or vias, gate dielectric defects or
times for trail runs and, prior to each trial, they have to be parametric variation, and residues or voids within the device
processed or reclaimed (stripping and lapping through to fine structures. Without tools to identify, measure and analyse these
polishing). Wafer reclamation is a re-processing technology defects, attempts to eliminate them are limited to trial and
used on rejected wafers during the wafer fabrication. error efforts. As a result, subsurface defects comprise 65%
In wafer reclamation industries, a general rule is that a of all the reasons for yield loss [9]. So it is very important to
wafer with a subsurface defect at a depth of 15 µm and a detect and analyse the subsurface defects in the wafer before
defect size of more than 10 µm in diameter is considered to making them into devices. An attempt has been made here for
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Defect detection in unpolished Si wafers by digital shearography
37
G Udupa et al
Ps (x s, ys, z s) Mirror M1
He-Ne Laser
P (x, y, z)
Pc (x 0, y0, z 0) Spatial filter SF1
P (x+u, y+v, z+w)
X
Before
Loading Deformation Y Collimator
PC
after loading Z
φ = 4π/λ[∂w/∂y]δy.
Wafer Mirror M4
38
Defect detection in unpolished Si wafers by digital shearography
Zoom Lens
Mirror 4
CCD
Mirror 3 Camera
Mirror 2
TOP VIEW
ϕ 200 mm
SF2
He- Ne Laser
B-swirl
Wafer mount
Unpolished
Wafer
IR Lamp A-swirl
Figure 4. The experimental set-up of the wafer defect detection pits (see inset figure) whereas the A-swirls are designated as
system. hillocks.
To characterize the defects on the wafer during the
of COPs on the processed wafer surface. First the polished reclamation processes, an optical profiler is used to measure
wafers were inspected using a wafer inspection system, in the surface defects generated either during the wafer processing
this case a KLA Tencor instrument. The processed wafers or during crystal growth or both. Figure 7 shows the results
were subsequently measured using a Wyko optical profiler of 2D and 3D surface topography measurements of a single
to study the defects quantitatively. Figure 5 shows a ‘swirl’ defect on the lapped Si wafer by an optical profiler. The
defect revealed after final polishing as seen by the KLA Tencor three-dimensional representation of the surface topography
instrument. These are micro-defects, located in a spiral pattern provides a clear indication of size, depth and shape of the
in wafers cut perpendicular to the crystal growth direction. The defect. The defects are almost circular (or rectangular) in
wafer defect map obtained by this instrument does not show shape at the surface and tapered down like a cup up to a
whether the defects are of class ‘A’ or ‘B’. The instrument depth of about 205 nm as shown in figure 7. The diameter
shows these defects in the form of black dots on the wafer map. of the defects varies from 5 to 10 µm. The depth and shape
To classify these defects requires a high magnification scanning of the defect change as the process changes from lapping
electron microscope, which shows clearly the defects as in to fine polishing. Figure 8 shows the results of 2D and
figure 6 [11]. The A-swirl defect (the black–white contrasts) 3D surface topography measurement of a single defect on
are larger size defects much smaller in number whereas the the fine polished Si wafer. The defects are irregular (or
B-swirl defects (white dots) are a lot of small defects. Close elliptical) in shape at the surface and taper down like cones
evaluation shows that the B-swirls are designated as shallow or pyramids to a depth of about 5 nm. The size (diameter)
39
G Udupa et al
Table 1. Surface topography parameters of processed Si wafers (measurement area: 225.7 µm × 296.7 µm).
Sl. Parameters/ Ra Rq Rz Rt Defect Defect
no processes (nm) (nm) (nm) (nm) diameter (µm) depth (nm)
1 Lapping 1.92 6.31 221.1 296.5 10–15 200
2 Etching 1.44 1.99 44.61 67.09 5–10 50
3 Stock polishing 1.10 1.32 8.10 11.84 2–8 10
4 Fine polishing 0.85 1.08 7.94 8.58 0.05–5 5
um nm um X Profile
14.6 54.41
-0.00
30.00 -0.02
12.0
10.00 -0.04
10.0 -0.06
-10.00
-0.08
8.0 -30.00 -0.10 Rq 56.93 nm
-50.00 -0.12 Ra 36.63 nm
6.0 -0.14 Rt 205.32 nm
-70.00
4.0 -90.00
-0.16 Rp 7.43 nm
-0.18 Rv -197.89 nm
2.0 -0.20 um
-127.86 0 10 20 30 40 50
0.0
um
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.2
um Y Profile
nm
-0.00
54.4
-0.02
-0.04
-0.06
-0.08
-0.10 Rq 63.90 nm
14.6 Ra 45.88 nm
-0.12
-0.14 Rt 204.32 nm
-127.9 -0.16 Rp 8.31 nm
0.0 -0.18 Rv -196.01 nm
0.0 um
18.2 -0.20
um 0 5 10 15 20 25 30 35 40
Figure 7. The 2D and 3D surface topography map of a single defect on the lapped Si wafer by a Wyko optical profiler indicating average
roughness (Ra ), RMS deviation (Rq ), peak to valley height (Rt ), maximum peak height (Rp ) and maximum valley depth (Rv ) of the surface
profile.
nm X Profile
0.94 nm
0.00
0
-1.00 -1
Rq 1.29 nm
-2.00 -2 Ra 1.03 nm
Rt 4.56 nm
-3 Rp 0.67 nm
-3.00
Rv -3.89 nm
-4 um
-3.86
0 2 4 6 8 10
nm
0.94
Y Profile
nm 0.00 nm
0.50
0.9
0.00
-1.00 -0.50
-1.00
-1.50
-2.00
-3.9 -2.00 Rq 1.24 nm
10.1 0 Ra 0.99 nm
-2.50
-3.00 -3.00 Rt 4.25 nm
0.0 9.0
Rp 0.36 nm
-3.50
um -3.86 Rv -3.89 nm um
-4.00
0 1 2 3 4 5 6 7 8 9
Figure 8. The 2D and 3D surface topography map of a single defect on the polished Si wafer by a Wyko optical profiler indicating average
roughness (Ra ), RMS deviation (Rq ), peak to valley height (Rt ), maximum peak height (Rp ) and maximum valley depth (Rv ) of the surface
profile.
of the defects typically varies from 5 µm to 50 nm at the designated as average roughness (Ra ), RMS deviation (Rq ),
surface. Table 1 shows the surface topography parameters ten-point height (Rz ) and peak to valley height (Rt ) of the
of the processed Si wafers along with defect size during the surface under measurement. As the value of surface roughness
wafer processing stages. The optical profiler gives four surface parameters decreases, there is a considerable decrease in size
roughness parameters, indicative of the surface roughness and and depth of defects in the Si wafer from the lapping to fine
40
Defect detection in unpolished Si wafers by digital shearography
mm
1.8
ϕ15 1.6
1.4
1.2
1.0
0.8
ϕ20
ϕ2 0.6
ϕ5
0.4
0.2
ϕ10
0.0 mm
0.0 0.5 1.0 1.5 2.0 2.4
(a) (b)
ϕ15
ϕ20
ϕ2
ϕ5
ϕ10
(c) (d)
Figure 9. Demonstration of the measurement range (a) two bonded wafers with simulated subsurface defects, (b) contour map of a 2 mm
defect by a Wyko optical profiler, (c) fringe pattern showing four subsurface defects and (d) fringe pattern showing a 2 mm subsurface
defect.
polishing process. However, these defects affect the final and a program written using the Auto-Pro scripting facilities
performance and decrease reliability and manufacturing yield available in the software to perform the above methods of
of semiconductor devices. Some of these defects or voids subtraction. The real-time subtraction was carried out using
may be originally embedded (during crystal growth) in the the fixed reference frame method or the permanently refreshed
silicon wafer and will be revealed at the surface after the reference frame method [12]. A lateral shear of 10 mm was
polishing process (as seen in figure 5) and result in rejection used throughout the experiment.
of wafers at the end of the final process. The difficult task is The suitability of the measurement range for this
to detect these subsurface defects in unpolished Si wafers and application can be demonstrated using two bonded wafers as
sort them into defective and non-defective wafers. This helps shown in figure 9(a). The two unpolished wafers of 200 mm
not only in reducing scrap but also saving both the processing diameter were bonded at specific spots with various sizes using
and manpower costs associated with producing swirl free non- a steel filled epoxy adhesive. The simulated defects substituted
defective wafers for IC packaging. between the two wafers vary in size from approximately 2
to 20 mm diameter. Figure 9(b) shows the contour map
5.2. Study of subsurface defects in an unpolished Si wafer of a defect with about 2 mm diameter seen using the low
magnification objective lens (2.5×) available in the optical
Defects/flaws in silicon wafers induce strain concentrations on profiler. The diameter of the defects may change a little after
the wafers. Shearography reveals these defects by translating the bonding. The fringe pattern in figure 9(c) successfully
the defect-induced strain concentrations to anomalies in the reveals the location of the four simulated subsurface defects of
fringe patterns. An unpolished wafer of 200 mm diameter size 5, 10, 15 and 20 mm as seen by the bull’s-eye anomaly in
and thickness about 700 µm was clamped along the edges in the fringe pattern. In comparison with figure 9(a), the bull’s-
a wafer mount, leaving 190 mm diameter exposure area for eye corresponds to the positions of the four simulated defects.
laser illumination on one side of the wafer. Thermal loading However the smallest simulated defect, of size 2 mm, was not
was applied using an infrared lamp was placed at its centre on detected when viewing the whole wafer surface. An attempt
other side of the wafer as shown in figure 4. The temperature has been made to detect this defect by reducing the field of
gradient induces thermal stresses in the wafer. Either the view with the zoom lens. Figure 9(d) shows the detection of
double exposure or the real-time method can be used to perform the smallest defect, which shows the position correctly at the
the subtraction. The Image-Pro Plus software along with centre of the wafer. Similar experiments were also conducted
image processing card was installed in a Pentium 4 computer in detecting debonds between two bonded wafers. The present
41
G Udupa et al
Defects
Cluster Swirl
Defects
Area
1000
(a) 100
100
Count
mm2
50
10
1
0.2 0.5 1 2 5 10 20 50 100 500 2000
0.160 9900
Diameter (µm)
Figure 11. The surface defects map after polishing the wafer of
figure 10(a), revealed by a KLA Tencor instrument with a graph
showing defect particle count and the corresponding defect size.
42
Defect detection in unpolished Si wafers by digital shearography
43