DS1643

DS1643
Nonvolatile Timekeeping RAM

FEATURES PIN ASSIGNMENT

• Form, fit, and function compatible with the MK48T08
Timekeeping RAM NC 1 28 VCC

• Integrated NV SRAM, real time clock, crystal, power–

A12 2 27 WE

A7 3 26 CE2
fail control circuit and lithium energy source
A6 4 25 A8
• Standard JEDEC bytewide 8K x 8 static RAM pinout
A5 5 24 A9
• Clockregisters are accessed identical to the static A4 6 23 A11
RAM. These registers are resident in the eight top A3 7 22 OE
RAM locations.
A2 8 21 A10
• Totally nonvolatile with over 10 years of operation in A1 9 20 CE
the absence of power
A0 10 19 DQ7

• Access times of 120 ns and 150 ns DQ0 11 18 DQ6

• Quartz accuracy ±1 minute a month @ 25°C, factory

DQ1 12 17 DQ5

DQ2 13 16 DQ4
calibrated
GND 14 15 DQ3
• BCD coded year, month, date, day, hours, minutes,
and seconds with leap year compensation valid up to 28–PIN ENCAPSULATED PACKAGE
(700 MIL EXTENDED)
2100

• Power–failwrite protection allows for ±10% VCC

power supply tolerance

ORDERING INFORMATION
DS1643–XXX 28–pin DIP module

–120 120 ns access

–150 150 ns access

DESCRIPTION
The DS1643 is an 8K x 8 nonvolatile static RAM with a The RTC clock registers are double buffered to avoid
full function real time clock which are both accessible in access of incorrect data that can occur during clock up-
a bytewide format. The nonvolatile time keeping RAM is date cycles. The double buffered system also prevents
pin and function equivalent to any JEDEC standard time loss as the timekeeping countdown continues un-
8K x 8 SRAM. The device can also be easily substituted abated by access to time register data. The DS1643
in ROM, EPROM and EEPROM sockets providing read/ also contains its own power–fail circuitry which dese-
write nonvolatility and the addition of the real time clock lects the device when the VCC supply is in an out of toler-
function. The real time clock information resides in the ance condition. This feature prevents loss of data from
eight uppermost RAM locations. The RTC registers unpredictable system operation brought on by low VCC
contain year, month, date, day, hours, minutes, and se- as errant access and update cycles are avoided.
conds data in 24 hour BCD format. Corrections for the
day of the month and leap year are made automatically.

Copyright 1995 by Dallas Semiconductor Corporation. 041697 1/11

All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
 DS1643

PIN DESCRIPTION DS1643 clock registers should be halted before clock

A0–A12 – Address Input data is read to prevent reading of data in transition.
CE – Chip Enable However, halting the internal clock register updating
OE – Output Enable process does not affect clock accuracy. Updating is
WE – Write Enable halted when a one is written into the read bit, the seventh
NC – No Connection most significant bit in the control register. As long as a
VCC – +5 Volts one remains in that position, updating is halted. After a
GND – Ground halt is issued, the registers reflect the count, that is day,
DQ0-DQ7 – Data Input/Output date, and time that was current at the moment the halt
command was issued. However, the internal clock reg-
isters of the double buffered system continue to update
CLOCK OPERATIONS–READING THE so that the clock accuracy is not affected by the access
CLOCK of data. All of the DS1643 registers are updated simul-
While the double buffered register structure reduces the taneously after the clock status is reset. Updating is
chance of reading incorrect data, internal updates to the within a second after the read bit is written to zero.

DS1643 BLOCK DIAGRAM Figure 1

CLOCK
OSCILLATOR AND REGISTERS
32.768 KHz CLOCK COUNTDOWN
CHAIN

CE

WE
8K X 8 NV SRAM
OE

POWER MONITOR, POWER GOOD A0–A12

+ SWITCHING, AND
VBAT WRITE PROTECTION
DQ0–DQ7

VCC

041697 2/11
 DS1643

DS1643 TRUTH TABLE Table 1

VCC CE CE2 OE WE MODE DQ POWER
VIH X X X DESELECT HIGH Z STANDBY
X VIL X X DESELECT HIGH Z STANDBY
5 VOLTS ± 10% VIL VIH X VIL WRITE DATA IN ACTIVE
VIL VIH VIL VIH READ DATA OUT ACTIVE
VIL VIH VIH VIH READ HIGH Z ACTIVE
<4.5 VOLTS X X X X DESELECT HIGH Z CMOS STANDBY
>VBAT
<VBAT X X X X DESELECT HIGH Z DATA RETENTION
MODE

SETTING THE CLOCK running, the LSB of the seconds register will toggle at
The 8–bit of the control register is the write bit. Setting 512 Hz. When the seconds register is being read, the
the write bit to a one, like the read bit, halts updates to DQ0 line will toggle at the 512 Hz frequency as long as
the DS1643 registers. The user can then load them with conditions for access remain valid (i.e., CE low, OE low,
the correct day, date and time data in 24 hour BCD for- CE2 high, and address for seconds register remain valid
mat. Resetting the write bit to a zero then transfers and stable).
those values to the actual clock counters and allows
normal operation to resume.
CLOCK ACCURACY
The DS1643 is guaranteed to keep time accuracy to
STOPPING AND STARTING THE CLOCK within ±1 minute per month at 25°C. The clock is cali-
OSCILLATOR brated at the factory by Dallas Semiconductor using
The clock oscillator may be stopped at any time. To in- special calibration nonvolatile tuning elements. The
crease the shelf life, the oscillator can be turned off to DS1643 does not require additional calibration and tem-
minimize current drain from the battery. The OSC bit is perature deviations will have a negligible effect in most
the MSB for the seconds registers. Setting it to a 1 stops applications. For this reason, methods of field clock cal-
the oscillator. ibration are not available and not necessary. Attempts
to calibrate the clock that may be used with similar de-
vice types (MK48T08 family) will not have any effect
FREQUENCY TEST BIT even though the DS1643 appears to accept calibration
Bit 6 of the day byte is the frequency test bit. When the data.
frequency test bit is set to logic “1” and the oscillator is

041697 3/11
 DS1643

DS1643 REGISTER MAP – BANK1 Table 2

DATA
ADDRESS FUNCTION
B7 B6 B5 B4 B3 B2 B1 B0
1FFF – – – – – – – – YEAR 00–99
1FFE X X X – – – – – MONTH 01–12
1FFD X X – – – – – – DATE 01–31
1FFC X FT X X X – – – DAY 01–07
1FFB X X – – – – – – HOUR 00–23
1FFA X – – – – – – – MINUTES 00–59
1FF9 OSC – – – – – – – SECONDS 00–59
1FF8 W R X X X X X X CONTROL A
OSC = STOP BIT R = READ BIT FT = FREQUENCY TEST
W = WRITE BIT X = UNUSED

NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.

RETRIEVING DATA FROM RAM OR CLOCK WRITING DATA TO RAM OR CLOCK

The DS1643 is in the read mode whenever WE (write The DS1643 is in the write mode whenever WE and CE
enable) is high and CE (chip enable) is low. The device are in their active state. The start of a write is referenced
architecture allows ripple-through access to any of the to the latter occurring transition of WE or CE. The ad-
address locations in the NV SRAM. Valid data will be dresses must be held valid throughout the cycle. CE or
available at the DQ pins within tAA after the last address WE must return inactive for a minimum of tWR prior to
input is stable, providing that the CE and OE access the initiation of another read or write cycle. Data in must
times and states are satisfied. If CE or OE access times be valid tDS prior to the end of write and remain valid for
are not met, valid data will be available at the latter of tDH afterward. In a typical application, the OE signal will
chip enable access (tCEA) or at output enable access be high during a write cycle. However, OE can be active
time (tOEA). The state of the data input/output pins (DQ) provided that care is taken with the data bus to avoid bus
is controlled by CE and OE. If the outputs are activated contention. If OE is low prior to WE transitioning low the
before tAA, the data lines are driven to an intermediate data bus can become active with read data defined by
state until tAA. If the address inputs are changed while the address inputs. A low transition on WE will then dis-
CE and OE remain valid, output data will remain valid for able the outputs tWEZ after WE goes active.
output data hold time (tOH) but will then go indeterminate
until the next address access.

041697 4/11
 DS1643

DATA RETENTION MODE clock and RAM data retention when the VCC supply is
When VCC is within nominal limits (VCC > 4.5 volts) the not present. The capability of this internal power supply
DS1643 can be accessed as described above by read is sufficient to power the DS1643 continuously for the
or write cycles. However, when VCC is below the pow- life of the equipment in which it is installed. For specifi-
er–fail point VPF (point at which write protection occurs) cation purposes, the life expectancy is 10 years at 25°C
the internal clock registers and RAM is blocked from ac- with the internal clock oscillator running in the absence
cess. This is accomplished internally by inhibiting ac- of VCC power. The DS1643 is shipped from Dallas
cess via the CE and CE2 signals. When VCC falls below Semiconductor with the clock oscillator turned off, so
the level of the internal battery supply, power input is the expected life should be considered to start from the
switched from the VCC pin to the internal battery and time the clock oscillator is first turned on. Actual life ex-
clock activity, RAM, and clock data are maintained from pectancy of the DS1643 will be much longer than 10
the battery until VCC is returned to nominal level. years since no internal lithium battery energy is con-
sumed when VCC is present. In fact, in most applica-
tions, the life expectancy of the DS1643 will be approxi-
INTERNAL BATTERY LONGEVITY mately equal to the shelf life (expected useful life of the
The DS1643 has a self contained lithium power source lithium battery with no load attached) of the lithium bat-
that is designed to provide energy for clock activity, and tery which may prove to be as long as 20 years.

041697 5/11
DS1643

ABSOLUTE MAXIMUM RATINGS*

Voltage on Any Pin Relative to Ground –0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature –20°C to +70°C
Soldering Temperature 260°C for 10 seconds (See Note 7)

* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Supply Voltage VCC 4.5 5.0 5.5 V 1
Logic 1 Voltage All Inputs VIH 2.2 VCC+0.3 V
Logic 0 Voltage All Inputs VIL –0.3 0.8 V

DC ELECTRICAL CHARACTERISTICS (0°C ≤ tA ≤ 70°C; VCC = 5.0V ± 10%)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Average VCC Power Supply ICC1 65 mA 2, 3
Current
TTL Standby Current (CE = VIH, ICC2 3 6 mA 2, 3
CE2 = VIL)
CMOS Standby Current ICC3 2 4.0 mA 2, 3
(CE=VCC–0.2V, CE2=GND+0.2V)
Input Leakage Current (any input) IIL –1 +1 µA

Output Leakage Current IOL –1 +1 µA

Output Logic 1 Voltage VOH 2.4 V

(IOUT = –1.0 mA)
Output Logic 0 Voltage VOL 0.4 V
(IOUT = +2.1 mA)
Write Protection Voltage VTP 4.0 4.25 4.5 V

041697 6/11
 DS1643

AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5.0V ± 10%)

DS1643–120 DS1643–150
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time tRC 120 150 ns
Address Access Time tAA 120 150 ns
CE and CE2 Access Time tCEA 120 150 ns
CE and CE2 Data Off Time tCEZ 40 50 ns
Output Enable Access Time tOEA 100 120 ns
Output Enable Data Off Time tOEZ 35 45 ns
Output Enable to DQ Low–Z tOEL 5 5 ns
CE and CE2 to DQ Low–Z tCEL 5 5 ns
Output Hold from Address tOH 5 5 ns
Write Cycle Time tWC 120 150 ns
Address Setup Time tAS 0 0 ns
CE and CE2 Pulse Width tCEW 100 120 ns
Address Hold from End of Write tAH1 5 5 ns 5
tAH2 30 30 ns 6
Write Pulse Width tWEW 120 150 ns
WE Data Off Time tWEZ 40 50 ns
WE or CE Inactive Time tWR 10 10 ns
Data Setup Time tDS 85 110 ns
Data Hold Time High tDH1 0 0 ns 5
tDH2 15 15 ns 6

AC TEST CONDITIONS
Input Levels: 0V to 3V
Transition Times: 5 ns

CAPACITANCE (tA = 25°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Capacitance on all pins CI 7 pF
(except DQ)
Capacitance on DQ pins CDQ 10 pF

041697 7/11
DS1643

AC ELECTRICAL CHARACTERISTICS (POWER–UP/DOWN TIMING) (0°C to 70°C)

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE2, CE or WE at VIH before tPD 0 µs
Power Down
VPF (Max) to VPF (Min) tF 300 µs
VCC Fall Time
VPF (Min) to VSO tFB 10 µs
VCC Fall Time
VSO to VPF (Min) tRB 1 µs
VCC Rise Time
VPF (Min) to VPF (Max) tR 0 µs
VCC Rise Time
Power–Up tREC 15 25 35 ms
Expected Data Retention Time tDR 10 years 4
(Oscillator On)

DS1643 READ CYCLE TIMING

READ READ WRITE
tRC tRC tWC

A0–A12

tAA tAH
tAS
tCEA

CE

tCEL

tOEA
OE

tWR

tWEW
WE tOEL

tOH tOEZ

DQ0–DQ7
VALID OUT VALID OUT VALID IN

041697 8/11
 DS1643

DS1643 WRITE CYCLE TIMING

WRITE WRITE READ
tWC tWC tRC

A0–A12

tAS tAH2
tAA
tWR

tAH1
tCEW
CE

tOEA

OE

tWR

tWEW
WE
tDH1
tDH2 tDS tWEZ
tCEZ
tDS

DQ0– VALID VALID IN VALID IN VALID OUT

DQ7 OUT

POWER–DOWN/POWER–UP TIMING
VCC

VPF (MAX)

VPF (MIN) VPF

tF tR

VSO VSO
tFB tRB

tPD tREC

CE

IBATT
DATA RETENTION
tDR

041697 9/11
DS1643

NOTES:
1. All voltages are referenced to ground.

2. Typical values are at 25°C and nominal supplies.

3. Outputs are open.

4. Data retention time is at 25°C and is calculated from the date code on the device package. The date code XXYY
is the year followed by the week of the year in which the device was manufactured. For example, 9225, would
mean the 25th week of 1992.

5. tAH1, tDH1 are measured from WE going high.

6. tAH2, tDH2 are measured from CE going high.

7. Real–Time Clock Modules can be successfully processed through conventional wave–soldering techniques as
long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post solder
cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.

OUTPUT LOAD
+5 VOLTS

1.8KΩ

D.U.T.

1KΩ

100 pF

041697 10/11
 DS1643

DS1643 28–PIN PACKAGE

PKG 28–PIN

DIM MIN MAX

A IN. 1.470 1.490

MM 37.34 37.85

B IN. 0.675 0.740

MM 17.75 18.80
1
A C IN. 0.335 0.355
MM 8.51 9.02

D IN. 0.075 0.105

MM 1.91 2.67

E IN. 0.015 0.030

MM 0.38 0.76
C F IN. 0.140 0.180
MM 3.56 4.57

F G IN. 0.090 0.110

MM 2.29 2.79

D K G H IN. 0.590 0.630

MM 14.99 16.00

J IN. 0.010 0.018

MM 0.25 0.45

K IN. 0.015 0.025

MM 0.43 0.58

J
E

H
B

041697 11/11