E C E N 5 2 6 3 D i g i t a l V L S I D e s i g n

I/O Pads
Some way must be provided to get signals to and from the chip. The usual method is to
solder very thin wires directly to the chip. In order to make good electrical contact
between the chip circuitry and the bonding wires, a metal bonding pad must be designed
into the chip circuitry. The bonding pads are usually about 0.1mm on a side and spaced
about 0.1mm between pads. These sizes and spacing are about the same for all processes
regardless of line width since it is extremely difficult to make physical solder joints on
pads that are any smaller. A cutaway of a typical wire bonded package is shown.
bonding wires

chip

package leads

bonding wire

pad

An alternate method of bonding to the pads is to use solder bumps. First a droplet of sol-
der is put on each pad. Then the chip is flipped over and bonded directly to the circuit
board or chip carrier without the use of bonding wires.
solder bump

chip (side view)

(flip)

multi-chip
carrier

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Fig. 1.61 p. 54 Chip layout with Pad Frame and Power/Ground pads on right side. Note
the large power/ground metal lines for the pad drivers.

Pad frames can be designed for any size chip and any desired number of pads. A pad
frame has been laid out in our 0.6 µm pad library which looks like the following.

5000λ
1500µm

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O
I/O I/O

I/O 3000λ I/O

I/O 900µm I/O

I/O I/O

I/O GND

VDD I/O

I/O I/O

I/O I/O

I/O I/O

I/O I/O
I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

All the pads are bidirectional Input/Output pads except for the VDD and GND pads in the
2
middle of the right and left side rows. The internal circuitry must fit into the 3000λ area
inside the frame. This pad frame has 2 power/ground pads and 38 signal pads for a total of
40 pads. All power and ground lines in your design must be connected to the VDD and
GND pads.

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Output Pads

Pad Driver
(very large)
From To out-
inside side
chip world

Pad Capacitance
(very large)

Drivers: L > Lmin to provide high breakdown voltage, W/L ~ 100 or more to get large
drive current.

Folded layout for drivers makes it possible to have very wide transistors without excessive
gate poly delays.

drain

gate
source

Note that the gates of these transistors present a large gate load to anything trying to drive
them. An intermediate sized inverter buffer is usually provided as part of the pad driver
circuitry to drive the pad drivers while presenting a smaller gate load to the internal cir-

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cuitry. Because of the large currents flowing in the pad drivers, they are much more sus-
ceptible to latch up than smaller transistors. Guard rings are used around these transistors.

Fig. 12.17 p. 782

Input Pads

Input Buffer
From out- To inside
side chip
world

Pad Capacitance
(very large)

The input buffer usually has very low Vinv to accommodate TTL logic levels (0.8V, 2.0V).

Note that the input pad and buffer present a capacitive load to the outside world. This is
good for preventing any DC load current, but it is bad because large voltages may build up
on the input pad from static electricity until the chip circuitry is damaged. Voltages up to
1000V can be put on the input pin merely by touching an unprotected input with your fin-
ger. Also, the peak electrostatic discharge (ESD) current can be as much as an amp.

~1K
+
1000V
-
ESD Equivalent Circuit for Finger

Input pads must be provided with special circuitry to protect the internal circuitry from
these large voltages and currents.

Input protection Fig. 12.19 p. 783

The diodes keep the input voltage in the range

∠ 0.7V < V in < V dd + 0.7V .

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Unfortunately, the diodes also increase the capacitive load of the input by a factor of about
2. The parasitic p-n junction diode in the diffusion layers can be used to form the diodes.
Input
Vdd Vdd Vdd

<=>
n+ p+ n+

n-well Input

Input
GND GND
Input
<=>
p+ n+ p+
p-substrate
GND

Tri-state/Bidirectional Pad

Logic for bi-directionality is built into the pad driver. Fig. 12.21 p. 783

The tri-state driver has a clever implementation. Fig. 12.22 p. 783

Typical pad layout (for a 1.6mm process). Fig. 12.23 p. 785

Pad schematic. Fig. 12.24 p. 786

Modern processes operate at low internal voltages compared to the voltage of off-chip sig-
nals. Voltage level converters are often built into the pad driver circuitry.
Fig. 12.25 p. 786

I/O Pads September 19, 2005 page 5 of 5