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Assignment # 1

This document provides instructions for an assignment on VLSI design. It asks students to design a 4-bit priority encoder circuit using different CMOS techniques: (1) compound logic, (2) only NAND gates, (3) only NOR gates, (4) only transmission gates, and (5) tri-state inverters. Students are instructed to draw the truth table, minimize it with K-maps, and implement the priority encoder circuit for each technique. They also must analyze the pros and cons of each implementation. The assignment is due on February 28th, 2019.

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Ahmad Ali
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Download as PDF, TXT or read online on Scribd
19 views

Assignment # 1

This document provides instructions for an assignment on VLSI design. It asks students to design a 4-bit priority encoder circuit using different CMOS techniques: (1) compound logic, (2) only NAND gates, (3) only NOR gates, (4) only transmission gates, and (5) tri-state inverters. Students are instructed to draw the truth table, minimize it with K-maps, and implement the priority encoder circuit for each technique. They also must analyze the pros and cons of each implementation. The assignment is due on February 28th, 2019.

Uploaded by

Ahmad Ali
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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COMSATS University Islamabad, Lahore Campus

Department of Electrical & Computer Engineering


Assignment # 1
Course Title: VLSI Design Course Code: EEE434 Credit Hours: 4(3,1)
Bachelor of Engineering Honors
Electrical (Electronics) Engineering,
Course Instructor: Dr. Muhammad Naeem Awais Programme Name:
Bachelor of Engineering Honors
Computer Engineering

Semester: 6th, 7th, 8th Batch: FA15,FA16, SP15 Date: 25 February 2019

Last Date: 28 February 2019 Maximum Marks: 2.5 + 0.5 = 3

Question # 1: A 4-bit Priority Encoder has D0, D1, D2 and D3 as inputs and x and y as outputs
where D1 has the lowest priority and D2 has the highest priority. D0 has the 2nd highest priority
and D3 has the 2nd lowest priority. Design a set of CMOS circuits for this circuit with the
following techniques:

a) Using a compound CMOS logic implementation


b) Using an implementation comprised only of CMOS NAND gates
c) Using an implementation comprised only of CMOS NOR gates
d) Using only Transmission gates
e) Using Tri-state inverters with its supporting circuit for select lines

Hint: Start designing this combinational circuit by draw the truth table, minimize it through K-
map and then implement priority encoder circuit.

Question # 2: Analyze all the above implementations in Question # 1 from a) to e) and list down
the pros & cons of each implementation.

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