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    Section-A: Time: 2 Hours. Date of Examination

    Uploaded by

    Anuj Kumar
    This document appears to be an exam for a 4th semester operating systems course. It includes sections on deadlock conditions, paging, memory management algorithms, and the banker's algorithm for deadlock avoidance. Some key questions ask students to calculate a need matrix in deadlock avoidance, explain memory reference times with and without cache, and differentiate logical from physical addresses in paging. The exam covers essential topics in operating systems like concurrency, memory management, virtual memory, and deadlock prevention.

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    Section-A: Time: 2 Hours. Date of Examination

    Uploaded by

    Anuj Kumar
    41 views2 pages
    This document appears to be an exam for a 4th semester operating systems course. It includes sections on deadlock conditions, paging, memory management algorithms, and the banker's algorithm for deadlock avoidance. Some key questions ask students to calculate a need matrix in deadlock avoidance, explain memory reference times with and without cache, and differentiate logical from physical addresses in paging. The exam covers essential topics in operating systems like concurrency, memory management, virtual memory, and deadlock prevention.

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    OS ST2.pdf

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    This document appears to be an exam for a 4th semester operating systems course. It includes sections on deadlock conditions, paging, memory management algorithms, and the banker's algorithm for deadlock avoidance. Some key questions ask students to calculate a need matrix in deadlock avoidance, explain memory reference times with and without cache, and differentiate logical from physical addresses in paging. The exam covers essential topics in operating systems like concurrency, memory management, virtual memory, and deadlock prevention.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    41 views2 pages

    Section-A: Time: 2 Hours. Date of Examination

    Uploaded by

    Anuj Kumar
    This document appears to be an exam for a 4th semester operating systems course. It includes sections on deadlock conditions, paging, memory management algorithms, and the banker's algorithm for deadlock avoidance. Some key questions ask students to calculate a need matrix in deadlock avoidance, explain memory reference times with and without cache, and differentiate logical from physical addresses in paging. The exam covers essential topics in operating systems like concurrency, memory management, virtual memory, and deadlock prevention.

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    © All Rights Reserved
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    of 2

    (Following Paper Code and Roll No.

    to be filled in your Answer Book)


    PAPER CODE:- NCS-401 101 Roll No.

    B. Tech.
    ST-II Examination: EVEN SEMESTER 2015-16
    SEMESTER: 4th BRANCH: COMPUTER SCIENCE & ENGINEERING SECTION: A, B, & C
    Subject Name: Operating System
    Time: 2 Hours. Date of Examination: 28th March 2016 Total Marks: 50
    Note: Do as Directed. Missing data if any may be suitably assumed and mentioned. Symbols have
    their usual meaning.

    SECTION-A
    Attempt all parts. All parts carry equal marks. [2x5=10]

    (a) List the various conditions for deadlock occurrences.


    (b) How to calculate the content of need matrix?
    (c) Why page size is always in power of 2?
    (d) Explain compaction with suitable example.
    (e) Draw the paging hardware diagram.

    SECTION-B

    Note: Attempt any four questions from this section. [5x4=20]

    1. Explain the difference between internal and external fragmentation with suitable example.
    2. Explain the necessary condition for deadlock.
    3. Given memory partitions of 100K, 500K, 200K, 300K, and 600K (in order), how would each of the
    First-fit, Best-fit, and Worst-fit algorithms place processes of 212K, 417K, 112K, and 426K (in
    order)? Which algorithm makes the most efficient use of memory?
    4. Consider a paging system with the page table stored in memory. If a memory reference takes 400 ns,
    how long does a paged memory reference take? If we add associative registers, and 80 percent of all
    page-table references are found in the associative registers, what is the effective memory reference
    time? (Assume that finding a page-table entry in the associative registers(TLB) takes zero time, if
    the entry is there.)
    5. What is thread? Explain different types of thread models.
    6. Explain the following:-
    (a) page number (b) page offset (c) pages (d) frames (e) fragmentation
    SECTION-C
    Note: Attempt any two questions from this section. [10x2=20]

    1. Consider the following snapshot of a system:

    Allocation Max Available

    ABCD ABCD ABCD

    P0 0012 0012 1520

    P1 1000 1750

    P2 1354 2356

    P3 0632 0652

    P4 0014 0656

    Answer the following questions using the banker’s algorithm:

    a. What is the content of the matrix Need?

    b. Is the system in a safe state?

    c. If a request from process P1 arrives for (0, 4, 2, 0), can the request be granted immediately?

    2. Differentiate between logical address and physical address. Consider a logical address space of eight pages of

    2048 words each, mapped onto a physical memory of 64 frames.

    a. How many bits are there in the logical address?

    b. How many bits are there in the physical address?

    3. Write down the banker’s algorithm and resource request algorithm for calculating the safe sequence.
    4. Explain the Following:-
    (a) Recovery from deadlock.
    (b) Paging with TLB.

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