Interrupt Processing

The occurrence of an interrupt triggers a number of events, both in the processor hardware and
in software.
When an I/O device completes an I/O operation, the following sequences of hardware events
occurs:
1. The device issues an interrupt signal to the processor.
2. The processor finishes execution of the current instruction before responding to the interrupt.
3. The processor tests for the interrupt; if there is one interrupt pending, then the processor
sends an acknowledgement signal to the device which issued the interrupt. After getting
acknowledgement, the device removes its interrupt signals.
4. The processor now needs to prepare to transfer control to the interrupt routine. It needs to
save the information needed to resume the current program at the point of interrupt. The
minimum information required to save is the processor status word (PSW) and the location of
the next instruction to be executed which is nothing but the contents of program counter. These
can be pushed into the system control stack.
5. The processor now loads the program counter with the entry location of the interrupt handling
program that willrespond to the interrupt.

Interrupt Processing:

 An interrupt occurs when the processor is executing the instruction of location N.

 l At that point, the value of program counter is N+1 .

 l Processor services the interrupt after completion of current instruction execution.

  l First, it moves the content of general registers to system stack.
 l Then it moves the program counter value to the system stack.

 l Top of the system stack is maintained by stack pointer.

 l The value of stack pointer is modified to point to the top of the stack.

 l If M elements are moved to the system stack, the value of stack pointer is changed from

T to T-M. l Next, the program counter is loaded with the starting address of the interrupt
service routine.
 l Processor starts executing the interrupt service routine.

Return from Interrupt:

 l Interrupt service routine starts at location X and the return instruction is in location X +
L.
 l After fetching the return instruction, the value of program counter becomes X + L + 1.

 l While returning to user's program, processor must restore the earlier values.

 l From control stack, it restores the value of program counter and the general registers.

 l Accordingly it sets the value of the top of the stack and accordingly stack pointer is

updated.
 l Now the processor starts execution of the user's program (interrupted program) from

memory location N + 1.

Once the program counter has been loaded, the processor proceeds to the next instruction
cycle, which begins with an interrupt fetch. The control will transfer to interrupt handler routine
for the current interrupt.
The following operations are performed at this point.
6. At the point, the program counter and PSW relating to the interrupted program have been
saved on the system stack. In addition to that some more information must be saved related to
the current processor state which includes the control of the processor registers, because these
registers may be used by the interrupt handler. Typically, the interrupt handler will begin by
saving the contents of all registers on stack.
7. The interrupt handles next processes the interrupt. This includes an examination of status
information relating to the I/O operation or, other event that caused an interrupt.
8. When interrupt processing is complete, the saved register values are retrieved from the stack
and restored to the registers.
9. The final act is to restore the PSW and program counter values from the stack. As a result,
the next instruction to be executed will be from the previously interrupted program.

Design Issues for Interrupt

Two design issues arise in implementing interrupt I/O.
 l There will almost invariably be multiple I/O modules, how does the processor determine
which device issued the interrupt?
 l If multiple interrupts have occurred how the processor does decide which one to

process?

Device Identification
Four general categories of techniques are in common use:
m Multiple interrupt lines

m Software poll

m Daisy chain (hardware poll, vectored)

m Bus arbitration ( vectored)

Multiple Interrupts Lines:

The most straight forward approach is to provide multiple interrupt lines between the processor
and the I/O modules.
It is impractical to dedicate more than a few bus lines or processor pins to interrupt lines.
Thus, though multiple interrupt lines are used, it is most likely that each line will have multiple
I/O modules attached to it. Thus one of the other three techniques must be used on each line.
Software Poll :
When the processor detects an interrupt, it branches to an interrupt service routine whose job is
to poll each I/O module to determine which module caused the interrupt. The poll could be
implemented with the help of a separate command line (e.g. TEST I/O). In this case, the
processor raises TEST I/O and place the address of a particular I/O module on the address
lines. The I/O module responds positively if it set the interrupt.
Alternatively, each I/O module could contain an addressable status register. The processor then
reads the status register of each I/O module to identify the interrupting module.
Once the correct module is identified, the processor branches to a device service routine
specific to that device.
The main disadvantage of software poll is that it is time consuming. Processor has to check the
status of each I/O module and in the worst case it is equal to the number of I/O modules.
Daisy Chain :
In this method for interrupts all I/O modules share a common interrupt request lines. However
the interrupt acknowledge line is connected in a daisy chain fashion. When the processor
senses an interrupt, it sends out an interrupt acknowledgement.
The interrupt acknowledge signal propagates through a series of I/O module until it gets to a
requesting module.
The requesting module typically responds by placing a word on the data lines. This word is
referred to as a vector and is either the address of the I/O module or some other unique
identification. In either case, the processor uses the vector as a pointer to the appropriate
device service routine. This avoids the need to execute a general interrupt service routine first.
This technique is referred to as a vectored interrupt.

Fig : Daisy chain arrangement

Bus Arbitration :
In bus arbitration method, an I/O module must first gain control of the bus before it can raise the
interrupt request line. Thus, only one module can raise the interrupt line at a time. When the
processor detects the interrupt, it responds on the interrupt acknowledge line. The requesting
module then places it vector on the data line.
Handling multiple interrupts
There are several techniques to identify the requesting I/O module. These techniques also
provide a way of assigning priorities when more than one device is requesting interrupt service.
With multiple lines, the processor just picks the interrupt line with highest priority. During the
processor design phase itself priorities may be assigned to each interrupt lines.
With software polling, the order in which modules are polled determines their priority.
In case of daisy chain configuration, the priority of a module is determined by the position of
the module in the daisy chain. The module nearer to the processor in the chain has got higher
priority, because this is the first module to receive the acknowledge signal that is generated by
the processor.
In case of bus arbitration method, more than one module may need control of the bus. Since
only one module at a time can successfully transmit over the bus, some method of arbitration is
needed. The various methods can be classified into two group – centralized and distributed.
In a centralized scheme, a single hardware device, referred to as a bus controller or arbiter is
responsible for allocating time on the bus. The device may be a separate module or part of the
processor.
In distributed scheme, there is no central controller. Rather, each module contains access
control logic and the modules act together to share the bus.
It is also possible to combine different device identification techniques to identify the devices
and to set the priorities of the devices. As for example multiple interrupt lines and daisy chain
technologies can be combined together to give access for more devices.
In one interrupt line, more than one device can be connected in daisy chain fashion. The High
priorities devices should be connected to the interrupt lines that has got higher priority.
A possible arrangement is shown in the Figure
Interrupt Nesting
The arrival of an interrupt request from an external device causes the processor to suspend the
execution of one program and starts the execution of another. The execution of this another
program is nothing but the interrupt service routine for that specified device.
Interrupt may arrive at any time. So during the execution of an interrupt service routine, another
interrupt may arrive. This kind of interrupts are known as nesting of interrupt.
Whether interrupt nesting is allowed or not? This is a design issue. Generally nesting of interrupt
is allowed, but with some restrictions. The common notion is that a high priority device may
interrupt a low priority device, but not the viceversa. To accomodate such type of restrictions, all
computer provide the programmer with the ability to enable and disable such interruptions at
various time during program execution. The processor provides some instructions to enable the
interrupt and disable the interrupt. If interrupt is disabled, the CPU will not respond to any
interrupt signal. On the other hand, when multiple lines are used for interrupt and priorities are
assigned to these lines, then the interrupt received in a low priority line will not be served if an
interrupt routine is in execution for a high priority device.
After completion of the interrupt service routine of high priority devices, processor will respond
to the interrupt request of low priority devices

DISK DRIVE

The data on the disk are organized in a concentric set of rings, called track. Each track has the
same width as the head. Adjacent tracks are separated by gaps. This prevents error due to
misalignment of the head or interference of magnetic fields.
For simplifying the control circuitry, the same number of bits are stored on each track. Thus
the density, in bits per linear inch, increases in moving from the outermost track to the
innermost track. Data are transferred to and from the disk in blocks. Usually, the block is smaller
than the capacity of the track. Accordingly, data are stored in block-size regions known as
sector.
To avoid, imposition unreasonable precision requirements on the system, adjacent tracks
(sectors) are separated by intratrack (intersector) gaps.
Some means are needed to locate sector positions within a track. Clearly there must be some
starting points on the track and a way of identifying the start and end of each sector. These
requirements are handled by means of a control data recorded on the disk. Thus, the disk is
formatted with some extra data used only by the disk drive and not accessible to the user.
Since data density in the outermost track is less and data density is more in inner tracks so
there are wastage of space on outer tracks.
To increase the capacity, the concept of zone is used instead of sectors. Each track is divided
in zone of equal length and fix amount of data is stored in each zone. So the number of zones
are less in innermost track and number of zones are more in the outermost track. Therefore,
more number of bits are stored in outermost track. The disk capacity is increasing due to the
use of zone, but the complexity of control circuitry is also more.

Physical characteristics of disk

The head may be either fixed or movable with respect to the radial direction of the platter.
In a fixed-head disk, there is one read-write head per track. All of the heads are mounted on a
rigid arm that extends across all tracks.
In a movable-head disk, there is only one read-write head. Again the head is mounted on an
arm.Because the head must be able to be positioned above any track, the arm can be extended
or retracted for this purpose. The disk itself is mounted in a disk drive, which consists of the
arm, the shaft that rotates the disk, and the electronics circuitry needed for input and output the
binary data and to control the mechanism.
A non removable disk is permanently mounted on the disk drive. A removable disk can be
removed and replaced with another disk.
For most disks, the magnetizable coating is applied to both sides of the platters, which is then
referred to as double sided. If the magnetizable coating is applied to one side only, then it is
termed as single sided disk.
Some disk drives accommodate multiple platters stacked vertically above one another. Multiple
arms are provided for read write head. The platters come as a unit known as a disk pack.
The physical organization of disk is shown in the figure:

Organization and accessing of data on a disk

The organization of data on a disk is shown in the figure below.

On all surfaces of a stack of disks form a logical cylinder. Data bits are stored serially on each
track. Data on disks are addressed by specifying the surface number, the track number, and the
sector number.
In most disk systems, read and write operations always start at sector boundaries. If the number
of words to be written is smaller than that required to fill a sector, the disk controller repeats the
last bit of data for the remaining of the sector.
During read and write operation, it is required to specify the starting address of the sector from
where the operation will start, that is the read/write head must positioned to the correct track,
sector and surface. Therefore the address of the disk contains track no., sector no., and
surface no. If more than one drive is present, then drive number must also be specified.
The format of the disk address word is shown in the figure. It contains the drive no, track no.,
surface no. and sector no.
The read/write head will first positioned to the correct track. In case of fixed head system, the
correct head is selected by taking the track no. from the address. In case of movable head
system, the head is moved so that it is positioned at the correct track. By the surface no, it
selects the correct surface.
To get the correct sector below the read/write head, the disk is rotated and bring the correct
sector with the help of sector number. Once the correct sector, track and surface is decided, the
read/write operation starts next.
Suppose that the disk system has 8 data recording surfaces with 4096 track per surface. Tracks
are divided into 256 sectors. Then the format of disk address word is:
Suppose each sector of a track contains 512 bytes of disk recorded serially, then the total
capacity of
the disk is:

For moving head system, there are two components involved in the time delay between
receiving an address and the beginning of the actual data transfer.
Seek Time:
Seek time is the time required to move the read/write head to the proper track. This depends on
the initial position of the head relative to the track specified in the address.
Rotational Delay:
Rotational delay, also called the latency time is the amount of time that elapses after the head
is positioned over the correct track until the starting position of the addressed sector comes
under the Read/write head.
Disk Operation
Communication between a disk and the main memory is done through DMA. The following
information must be exchanged between the processor and the disk controller in order to
specify a transfer.
Main memory address :
The address of the first main memory location of the block of words involved in the transfer.
Disk address :
The location of the sector containing the beginning of the the desired block of words.
Word count :
The number of words in the block to be transferred.
The disk address format is:

The word count may correspond to fewer or more bytes than that are contained in a sector.
When the data block is longer than a track:
The disk address register is incremented as successive sectors are read or written. When one
track is completed then the surface count is incremented by 1.
Thus, long data blocks are laid out on cylinder surfaces as opposed to being laid out on
successive tracks of a single disk surface.
This is efficient for moving head systems, because successive sector areas of data storage on
the disk can be accessed by electrically switching from one Read/Write head to the next rather
than by mechanically moving the arm from track to track.The track-to-track movement is
required only at cylinder-to-cylinder boundaries.