AND8346/D

A519HRT HART) Modem

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APPLICATION NOTE
Introduction Physical Layer Specification2. The A5191HRT is intended
This application note describes a demonstration circuit to replace the 20C15 for all existing and future HART
that permits a user to implement a HART slave or master applications with no circuit topology changes. Only the
interface between a microprocessor and a process loop using values of four external resistors in the receive filter need to
the ON Semiconductor A5191HRT HART modem be adapted.
integrated circuit. The information in this Application Note
is correct to the best of our knowledge. Development of a Features
circuit suitable to the user’s particular system and • Same modem design as 20C15 from LSI Logic
application environment is the responsibility of the user. (formerly NCR and Symbios)
The HART (Highway Addressable Remote Transmitter) • Transmits a trapezoidal signal
communication protocol provides digital communication • Internal oscillator cell
for microprocessor−based process control instruments.
• Internal receive filter
HART uses the Bell−202 forward channel signaling
frequencies and bit rate (1200 bits/second) as making it a • Carrier detect
subset of the Bell−202 standard. HART−speaking devices • Available in 28−pin PLCC, 32−pin QFN and
can use virtually any Bell−202 standard modem. However, 32−pin LQFP Packages
the ON Semiconductor A5191HRT single−chip modem has • These Devices are Pb−Free and are RoHS Compliant
been designed to meet the low power requirements of This application note shows how to interface the
2−wire process instruments. A5191HRT modem to the HART network, as well as other
The ON Semiconductor A5191HRT modem is designed general advice on using the modem and on designing HART
to allow the user to easily implement a HART compliant devices. A block diagram showing a typical application of
Physical Layer design conforming to the HART FSK the A5191HRT in a HART Slave is shown in Figure 1.

PC20101210.4

RxD
RxA
TxD
+
UART
A5191HRT
RTS
4 − 20 mA

+
TxA Loop
CD
Current
mP

4 − 20 mA
DAC OUT
DAC −

Figure 1. HART Slave Application Block Diagram

© Semiconductor Components Industries, LLC, 2013 1 Publication Order Number:

August, 2013 − Rev. 4 AND8346/D
 AND8346/D

OVERVIEW OF HART COMMUNICATIONS

Analog Signaling The HART Master or Controller (Primary Master) detects

HART devices are connected in a conventional current this current variation by measuring the DC voltage across
loop arrangement shown in Figure 2. The HART Slave or the current sense resistor. The loop current varies from 4 to
Process Transmitter or Field Instrument (terminology used 20 mA at frequencies usually under 10 Hz.
by HART specification) signals by varying the amount of
current flowing through itself.

Process Variable

HART Master Network

24 V

4 − 20 mA
ADC Loop Current

Current
Sense Receive
Resistor
Amplifier
Receive
Amplifier

Tx Current
Modem

Tx Enable HART Slave

Modem

PC20101207.1
Tx Voltage

Figure 2. Current Loop with HART Signal Sources. Analog Signaling is Marked in Black. Digital Signaling is
Marked in Blue.

Digital Signaling HART Waveform

The HART (digital) signal is superimposed on the HART signals using phase−continuous
4−20 mA (analog) signal as shown in Figure 2 (marked in frequency−shift−keying (FSK) at 1200 bit/s.
blue). The Master transmits HART signals by applying a Phase−continuous frequency−shift−keying requires the
voltage signal across the current sense resistor and it phase angle of the mark (1200 Hz) and the space (2200 Hz)
receives a voltage signal by detecting the HART current to remain continuous at the 1200 bit/s bit boundaries. A
signal across the sense resistor. Conversely, the Slave HART Slave or Field Instrument transmits a HART signal
transmits by modulating the loop current with HART signals by modulating a high−frequency carrier current of about
and receives HART signals by demodulating the loop 1 mA p−p onto its normal output current. This is illustrated
current. in Figure 3 for a 6 mA analog signal.

Loop Current Phase continuous at bit boundary

Mark = 1200 Hz Space = 2200 Hz

6 mA 1 mA

Data t BIT
833 ms

PC20101207.2 “0” “1” “0” “1” “0” “0”

Figure 3. Field Instrument Current versus Time

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 AND8346/D

HART Slave Device HART network can only have one Primary and one
HART Slaves transmit by modulating the process Secondary Master connected a time.
4−20 mA DC loop current with a 1 mA p−p AC current
signal as shown in Figure 3. Since the average value of the Multiplexing a HART Master
HART signal is zero, the DC value of the process loop To reduce the design complexity of a multiple loop HART
remains unchanged. Receive circuits in a HART Slave Master, the physical layer can be multiplexed to two or more
device amplify, filter, and demodulate the current signal. process loops. This is usually done with analog switches that
allow signals as high as 6 Vp−p to pass and exhibit an
HART Multi−dropped Slave Devices extremely low ‘on resistance’. The added impedance of the
Some current loops (called networks in HART switch directly affects the output impedance of the Master
documents) use only digital signaling. The field instrument device.
current is fixed at 4 mA or some other convenient value, and The multiplexer can switch only the HART signal or it can
only digital communication occurs. Up to 15 such field switch both the HART signal and the associated signal
instruments with unique addresses of 1 through 15 may be return. Switching the signal return insures the physical layer
connected in parallel. More address space is available for interface will be non−intrusive to the HART network if a
devices compliant with HART specification rev. 5 or higher failure were to occur. Typically, the analog switches connect
(up to 38 bits). A device that is not multi−dropped will to each process loop through a coupling capacitor (about
usually have its address set to 0. 2.2 mF).
The greatest disadvantage of multiplexing HART signals
HART Master Device
is the reduction in communication throughput to each Slave
HART Masters transmit by driving the loop with a low
device.
impedance voltage source as shown in Figure 2. Regardless
whether a master or field device is transmitting, a signal HART Cabling
voltage of about 500 mVp−p is developed across the Because of the relatively low HART frequencies, there is
conductors of the current loop (assuming a 500 W current little cable attenuation and delay distortion. This results in
sense resistor), and is seen by both devices. Receive circuits very few restrictions on constructing networks. The
in each device filter and demodulate the signal voltage. complete topology requirements and electrical requirements
for HART devices are given in the HART Physical Layer
HART Primary Master
Specification2.
In general, a HART Primary Master is the device that In most applications, HART communications can be
provides the communications between the control system performed up to a distance of 1500 meter using existing field
(DCS) and the remote process instruments with the intent to wiring for a 2−wire process instrument.
receive process information and perform maintenance
operations. A HART network that has a HART Master HART Data Link Layer
interface integrated into the DCS will usually be configured Normally, one HART device talks while others listen.
as a Primary Master. Talking means that the device applies the modulated carrier
to the network cable. A given device applies the carrier in
HART Secondary Master
one unbroken segment called a frame. Between frames the
In general, a second HART interface connected to a network is silent. Field instrument frames are usually
network that contains a Master will be a Secondary Master. responses to commands by a Master. Further information on
An example of a Secondary Master is a hand−held network protocol is found in the HART Data Link Layer
communicator that would be connected directly across a Specification1.
HART. Such a network may have a Primary Master. A

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 AND8346/D

A5191HRT FUNCTIONAL BLOCKS

VDD VDDA RxAFI RxAF

PC20101211.1

RESET
Demodulator RxA
RxD Logic
FSK_IN

Rx Comp Rx HP Filter
AREF

Carrier Detect
CD Counter
CDREF
Carrier Comp DEMODULATOR

RTS MODULATOR

Numeric
Sine
TxA
TxD Controlled
Shaper
FSK_OUT
Oscillator

Clock
Oscillator
BIAS
A5191HRT

XOUT XIN CBIAS VSS VSSA

Figure 4. A5191HRT Block Diagram

HART MODEM

Demodulator The bit rate is nominally 1200 bits/second. The output of

The demodulator accepts an FSK signal at its RxA input the modulator RxD is qualified with the carrier detect signal
and reproduces the original modulating signal at its RxD CD. Therefore only RxA signals large enough to be detected
output shown below: (100 mVp−p typical) by the carrier detect function will
The modem uses shift frequencies of nominally 1200 Hz produce demodulated output at RxD.
(logical one, mark) and 2200 Hz (logical zero, space).

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 AND8346/D
FSK_IN

RxD

LSB MSB IDLE (mark)

IDLE (mark)

Start D0 D1 D2 D3 D4 D5 D6 D7 Par Stop

PC20101207.4 “0” “1” “0” “1” “0” “0” “1” “0” “1” “0”
t
tBIT 8 data bits BIT

Figure 5. Demodulator Signal Timing

Modulator TxA output. RTSB must be a logic low for the modulator
The modulator accepts digital data in NRZ form at its TxD to be active.
input and generates the FSK modulated signal at its

RTS

IDLE (mark)

TxD
tBIT

Start Par Stop

t

“0” “1” “0” “1” “0” “0” “1” “0” “1” “0”
TxA

0.5 V

PC20101208.3

Figure 6. Modulator Signal Timing

Transmit Waveshaping For VAREF = 1.235 V

The A5191HRT generates a HART compliant trapezoidal VTxA = 1.235 x 0.417 = 0.515 V p−p
FSK modulated signal at its TxA output. Shown in Figure 6 The DC bias voltage of TxA is VTxA = 0.5 V.
are actual transmit signals from a A5191HRT. This means that when:
The amplitude of TxA is proportional to the analog RTSB = “1” VTxA = 0.5 V
reference voltage as follows: RTSB = “0” VTxA has a voltage swing from 0.16 V
V TxA,p*p + V AREF 0.417 to 0.77 V.

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 AND8346/D

VTxA VTxA
“1” = Mark; fm =1.2 kHz “0” = Space; fs =2.2 kHz

0.5 V 0.5 V 0.5 V 0.5 V

SRm = 1860 V/s t (ms) SRs = 3300 V/s t (ms)

0 1 2 0 1 2
PC20101209.4

Figure 7. TxA Waveforms

Carrier Detect FSK_IN
Low HART input signal levels increases the risk for the
1 2 3 4
generation of bit errors. If the received signal is below this
100 mV p−p level the demodulator is disabled. 50 mV

NOTE: HART Physical Layer Specification specifies a 0

signal level > 120 mVp−p as a valid carrier; signal level
< 80 mVp−p as noise.
This level detection is done in the Carrier Detector. The CD
output of the demodulator is qualified with the carrier detect tCD 2.2 ms
signal (CD), therefore, only RxA signals large enough to be
detected (100 mVp−p typically) by the carrier detect circuit
produce received serial data at RxD.
PC20101211.2

Figure 9. Carrier Detect Timing

Once CD goes inactive, it takes four consecutive pulses
out of the comparator to assert CD again. Four consecutive
pulses equals tCD = 3.33 ms when the received signal is
1200 Hz and tCD = 1.82 ms when the received signal is 2200
Hz.

Clock Oscillator
The A5191HRT requires a 460.8 kHz clock. This
frequency is generated in the internal clock oscillator block,
designed to use either a quartz crystal, ceramic resonator, or
Figure 8. Demodulator Carrier and Signal an external clock.
Comparator

The carrier detect comparator shown in Figure 8

generates logic Low output if the RxAFI voltage is below
CDREF. The comparator output is fed into a carrier detect
block. The carrier detect block drives the carrier detect
output pin CD high if nRTS is high and four consecutive
pulses out of the comparator have arrived. CD stays high as
long as nRTS is high and the next comparator pulse is
received in less than 2.2 ms.

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 AND8346/D

input to the oscillator cell. Table 5 lists commonly available

clock frequencies for crystals suited to this purpose. The
Clock interface between the microprocessor clock and the
Oscillator A5191HRT could be as simple as a direct connection or a
single integrated circuit.

XIN PC20101208.5
XOUT

R1
Xtal
Clock
Oscillator
C1 C2

PC20101118.6
XOUT XIN
Figure 10. Oscillator Connection for Ceramic
Resonator or Quartz Crystal 460.8 kHz
When using a crystal or resonator the accuracy should be
at least 1%. The oscillator requires two external capacitors Figure 11. External Clock
and one external resistor, which values varies depending on
the used type. The specifications are listed in Table 4. Care NOTE: Output XOUT is driven by an external source
should be taken to keep the circuit board traces between the
A5191HRT and the external oscillator components as short
as possible. Table 2. COMMONLY AVAILABLE FREQUENCY
MULTIPLES
Ceramic Resonator Sources Frequency Multiple
Ceramic resonators are less expensive than quartz
1.8432 MHz x4
crystals, but are not as accurate. Unfortunately, ceramic
resonators at the needed frequency require special ordering 3.6864 MHz x8
in very large quantities. Ceramic resonators that oscillate at 7.3728 MHz x16
460.8 kHz are available from: 14.7456 MHz x32
http://www.ecsxtal.com/store/dc-4-ecs-resonators.aspx
www.raltron.com/products/resonators/default.asp 29.4912 MHz x64

Quartz crystals are available from:

Clock Skew
www.aelcrystals.co.uk
If one uses the same time base for both the modem and the
www.statek.com/prod_thruholecrystals.php
UART, a 1% accurate time base may not be good enough.
The problem is a combination of receive data jitter and clock
Table 1. CERAMIC RESONATOR AND QUARTZ skew between transmitting and receiving HART devices. If
CRYSTAL VALUES the transmit time base is at 99% of nominal and the receive
Description Ceramic Quartz Unit time base in another device is at 101% of nominal, the
Type ECS Crystal Statek CX−1V
receive data (at the receiving UART) will be skewed by
ZTB Series Series roughly 21% of one bit time at the end of each 11−bit byte.
This is shown in Figure 12. The skew time is measured from
Frequency 460.8 460.8 kHz
the initial falling edge of the start bit to the center of the 11th
C1 220 47 pF bit cell. This 21% skew by itself isn’t bad. However, there
C2 220 22 pF is another error source for bit boundary jitter. The Phase
R1 0 10 kW
Lock Loop demodulator in the A5191HRT produces jitter in
the receive data that can be as large as 12% of a bit time.
Maximum ESR N.A. 12 kW
Therefore, a bit boundary can be shifted by as much as 24%
of a bit time relative to its ideal location based on the start−bit
External Clock transition. (The start−bit transition and a later transition can
It may be desirable to use an external clock of 460.8 kHz be shifted in opposite directions for a total of 24%.)
rather than the internal oscillator cell because of the cost and The clock skew and jitter added together is 45%, which is
availability of quartz crystals or ceramic resonators. In the amount that a bit boundary could be shifted from its
addition, the A5191HRT consumes less current when an expected position. UARTs that sample at mid−bit will not be
external clock is used as shown in Figure 11. An external affected. However, there are UARTs that take multiple
clock associated with the microprocessor (running at a samples during each bit to try to improve on error
frequency that is a multiple of 460.8 kHz) can be used as an

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 AND8346/D

performance. These UARTs may not be satisfactory, Even if your own time base is perfect, you still must plan
depending on how close the samples are to each other, and on a possible 35% shift in a bit boundary, since you don’t
how samples are interpreted. A UART that takes a majority have control over time bases in other HART devices.
vote of 3 samples is acceptable.

tBIT
Transmitter tBIT
tBIT@ 99% nominal CLK
2

Start D0 D1 D2 D3 D4 D5 D6 D7 Par Stop

t

Receiver 45% t BIT = 1200-1

tBIT@ 101 % nominal CLK
21% tBIT = 1200-1

t
PC20101209.1
UART mid bit sample moment ±12% jitter

Figure 12. Clock Skew

RECEIVE ANALOG CIRCUITRY

Receive High−pass Filter The interfering analog signal should be reduced to at least
To remove the interfering analog signal, a high−pass filter ten times smaller than the smallest HART signal, or under
is required in the HART signal receive path. The filter about 7.5 mV. Therefore, the high−pass filter should have an
requirements are found as follows. From section 7.1 of the attenuation of 63 dB at 25 Hz. The HART signal band covers
HART Physical Layer Specification2, the interfering signal approximately 950 Hz to 2500 Hz, which means that the
can be as high as 16 V p−p at 25 Hz. high−pass filter should begin rolling off somewhere below
NOTE: This is directly related to limits on analog 950 Hz and be 63 dB down at 25 Hz. This is illustrated in
signaling. The difference in specifications for analog Figure 13.
interference as output versus analog interference as input is
the result of the loads being different.

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 AND8346/D

Figure 13. Receive Filter Bounds

The A5191HRT has an internal active filter to attenuate Table 3. RECEIVE FILTER VALUES FOR A5191HRT
the frequencies outside the HART band. In addition to the AND 20C15
internal active filter, an external passive filter is necessary to
Symbol A5191HRT 20C15 Tolerance Unit
complete the filtering requirements. The external capacitors
and resistor were too large in size to cost effectively integrate R1 215 402 1% kW
into the A5191HRT silicon. R2 215 453 1% kW
The external components required for the receive filter is R3 499 825 1% kW
shown in Figure 14. All the external capacitors are ±5% and
R4 787 787 1% kW
the resistors are ±1% components (except the 3 MW which
is ±5%). R5 422 732 1% kW
The external components on the receiver create a third R6 215 215 1% kW
order high pass filter with a pole at 624 Hz and a first order
R7 3 3 5% MW
low pass filter with a pole at 2500 Hz. Internally, the
A5191HRT has a high pass pole at 35 Hz and a low pass pole C1 470 470 5% pF
at 90 kHz, each of which can vary by as much as ±30 %. The C2 1 1 5% nF
input impedance to the entire filter is greater than 150 kW at C3 1 1 5% nF
frequencies less than 50 kHz.
C4 220 220 5% pF
A5191HRT is a pin to pin replacement for 20C15. Only
the values of four resistors in the receiver need to be The values shown for all external components in
changed. (See Table 5 values marked in italic).The different Figures 14 and Table 6 and all other circuits in this
resistor values change the shape of the lower pass band for application note are those used in the circuitry which was
the receive filter. It creates a more robust and noise immune used to pass the HART physical layer conformance test for
receiver and as a results provides more margin in passing the the A5191HRT.
out−of−band noise interference tests.

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 AND8346/D

C4 R6 R5

RxAFI RxAF PC20101124.1

HART IN

300 pF

R3 C3 C2 C1
RxA

15 MW
R4 R2 R1
Rx Comp 214 kW

40 pF
R7
44 kW

Carrier Comp Rx HP Filter AREF

1.235 VDC

CDREF
AREF − 80 mV

DEMODULATOR

Figure 14. Receive Filter

Voltage References The bias current controls the operating parameters of the
The A5191HRT requires two voltage references, AREF internal operational amplifiers and comparators and should
and CDREF. AREF sets the DC operating point of the be set to 2.5 mA.
internal operational amplifiers and is the reference for the The value of the bias current resistor is determined by the
Rx comparator. reference voltage AREF and the following formula:
If A5191HRT operates at VDD = 3.3 V the AREF
ON Semiconductor LM285D−1.2 1.235 V reference is R BIAS +
2.5 mA
recommended. In the case VDD = 5 V, AREF is typically
2.5 VDC. LM285D−2.5 is recommended. The recommended bias current resistor is 499 kW when
The level at which CD (Carrier Detect) becomes active is AREF is equal to 1.235 V or 100 kW when AREF is 2.5 V.
determined by the DC voltage difference (CDREF − AREF). Supply Current Budget and Transmitter Lift−Off
Selecting a voltage difference of 80 mV will set the carrier Voltage
detect to a nominal 100 mVp−p. Current consumption of internal circuits is important in
Analog Bias Resistor
any 2−wire field instrument. It becomes critically important
The A5191HRT requires a bias current resistor RBIAS to in a microprocessor− based field instrument featuring both
be connected between CBIAS and VSS. analog and digital signaling. The available current is derived
here and some techniques are examined for reducing current
consumption.
The nominal HART signal transmitted by a field
BIAS instrument is 0.5 mA peak. When this is superimposed upon
2.5 mA

AREF
a 4 mA analog signal, the terminal current must vary
between 3.5 mA and 4.5 mA. During the peak of the HART
OPA waveform, the instrument has 4.5 mA available, but during
the valley it has only 3.5 mA. Energy storage techniques can
be used to allow the internal circuits to draw a steady 4 mA
at all times. However, to be effective at HART frequencies,
the storage capacitor should be quite large. A large capacitor
PC20101118.4 CBIAS (or any form of energy storage device) complicates the
RBIAS
circuit design if intrinsic safety is required.
Therefore, the circuit is normally designed to run
everything on 3.5 mA. Another 200 to 400 mA is often
subtracted from this to allow some margin and to satisfy
Figure 15. Bias Circuit
other conditions. Assuming a guard value of 200 mA, the

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 AND8346/D

internal circuits of the 2−wire field instrument have to live temperature. One way of reducing the A5191HRT current
on a diet of 3.3 mA during transmit. While receiving 3.8 mA consumption is to operate it at reduced voltage. Since the
is available. A5191HRT is a CMOS part, current consumption is roughly
proportional to supply voltage. Operation at VDD = 3.3 V is
Loop Current (mA) common.
In applying the A5191HRT be careful not to let inputs
float. The nRTS pin of the A5191HRT will often be driven
4
1 mA by an I/O pin of a microprocessor. During power−up or after
HART signal
reset an I/O pin may be tri−stated, allowing it to float. This
3.5
3.3
can cause the A5191HRT to draw excess current. In some
200 mA guardband
3.3 mA
cases the current may be large enough to prevent the field
Supply Current Budget instrument from starting up properly. There should be a
1 MW pull−up resistor on RTSB.
t
The transmitter lift−off voltage is the minimum terminal
PC20101212.1
voltage at which it is guaranteed to operate. When only
Figure 16. Supply Current Budget analog signaling is involved, lift−off voltage is an
unambiguous quantity. But when HART digital signaling is
A characteristic of the A5191HRT is that its current added, the available voltage can swing by as much as 0.75 V
consumption is approximately 350 to 450 mA. This leads to above and below the DC level. The minimum applied
the fortunate circumstance that the remaining (non−modem) voltage is the DC level minus 0.75 volt. You should either
circuits always have at least 2.85 mA available. Margins design the field instrument to accommodate the dips in
may be needed to cover current consumption over voltage, or else specify the lift−off voltage to include them.

INTERFACING TO THE HART NETWORK

Slave Device capacitively coupled into the summing junction, to preserve

The Slave interface to the network is typically a current DC accuracy of the 4 − 20 mA analog signal. Also shown in
regulator, as illustrated in simplified form in Figure 17. Its Figure 17 is the receive path, consisting of a capacitor from
output current is controlled by varying a much smaller the collector of the current regulator transistor to a
current into an op−amp summing junction. This junction is high−impedance amplifier. Both the receive amplifier and
a convenient point at which to sum the analog and digital the transmit current source should present a high impedance
signals, thereby achieving superposition of the digital signal (greater than 100 kW) to the network.
onto the analog. The digital transmit signal (TxA) is

Receive
Amplifier +
A5191HRT

RxA

TxA

Loop Loop
Amplifier Current

Vref

D/A
Converter
−
PC20101125.2

Figure 17. Simplified HART Slave Interface Circuit

Transmit Interface amplifier in the current loop regulator or at the regulator

The amplitude of TxA is nominally 500 mVp−p. The itself. It is recommended that the amplitude can be adjusted
HART Physical Layer requires the Slave to modulate the with voltage gain circuits. Using a small series capacitance
loop with a 1 mA p−p signal. The amplitude of modulation to attenuate the signal may cause distortion of the
of the loop current will have to be adjusted before the transmitted signal.

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 AND8346/D

Receive Interface network is driven by a low output impedance (600 W or less)

All HART receivers require non−disruptive coupling to voltage amplifier circuit that can be switched to a high
the network current loop. This connection can be made with impedance state using RTSB. The output of the voltage
capacitive or inductive coupling without corruption of the amplifier needs to be high impedance while the HART
process loop current. Typically a HART Slave uses a small Master receives, to insure a high input impedance for the
value (1 nF) capacitor to couple an adequate signal level to receiver. Typically a HART Master uses a 2.2 mF coupling
the receive filter. capacitor to insure the transmitter circuit meets the output
impedance requirements specified in the HART Physical
Master Device
Layer Specification.
The HART Master interfaces to the network as a voltage
source, as illustrated in simplified form in Figure 18. The

Receive
Amplifier +
RxA
A5191HRT

RTS Loop
Current

TxA
PC20101125.3

Loop
Amplifier
Vref

Figure 18. Simplified HART Master Interface Circuit

Transmit Interface could have as much as 1 kW of loop resistance. This results

The amplitude of TxA is nominally 500 mVp−p. The in (20 – 4)10−3 x 1.103 = 16 V p−p low frequency carrier with
500 mVp−p meets the requirements for a HART Master. HART superimposed. The transmit switch must be designed
However, the A5191HRT is unable to source enough current to prevent this 16 V p−p signal from sinking current through
to drive a HART network, therefore a low impedance the HART transmitter’s output stage. Any clipping of the
voltage driver build around the Loop Amplifier is required 16 Vp−p signal through the HART transmitter or the use of
between the A5191HRT and the network. transient suppressors will result in the clipping of the
superimposed HART signal. The last solution will block and
Transmit Switch
not clip the 16 Vp−p process signal and will not corrupt the
During a HART message transmission from the Master,
input impedance. The third solution can be implemented
the output impedance of the voltage source is quite low (0 −
easily as shown in Figure 18.
600 W). However during reception of a HART message, the
input impedance of the receive section must be quite high. Receiving the HART Signal
Therefore, the transmitter section must be disabled when not
active (nRTS = “High”). HART Signal Coupling
Several methods can be used to achieve a high output All HART receivers require non−disruptive coupling to
impedance of the transmitter while nRTS is inactive. One the network current loop. This connection can be made with
method is choosing an op−amp with an “active low” current capacitive or galvanic coupling without corruption of the
programming resistor that will basically “turn−off” the process loop current. A receiver in a Master may use a single
op−amp during receive operations. A second method can be 2.2 mF capacitor to couple the HART signal in which the
implemented with a correctly biased discrete FET in series Master is always connected across a current sense resistor
with the output stage. Lastly, a discrete solid−state relay with and share the same ground. Where ground isolation is
a characteristically low “on resistance” can be used. required, another coupling capacitor may be necessary in the
All three above techniques will provide an adequate signal return connection.
solution for the impedance requirements. However, only the To insure complete isolation from the network, galvanic
third solution will allow proper circuit operation per the isolation is the preferred method. Typically a transformer
“bit−error−rate” requirements and does not need to be and a series capacitor are used to couple the HART signal.
powered by a dual supply. With this type of isolation, the master can be connected
Under worse case conditions, a transmitter could across the field instrument or the current sense resistor
dynamically change from 4 − 20 mA and a HART Master regardless of the polarity or grounding configuration.

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 AND8346/D

Current Sense Resistor PC20101125.5

The current sense resistor is considered an integral part of

4.7 mF
a HART Master. In operation, a HART message response HART
+
from a Slave is superimposed on the 4−20 mA current loop. Modem
The Slave’s 1 mA p−p HART signal is dropped across the Current
Loop
Master’s sense resistor. For a typical sense resistor of 250 W, Sense
Resistor
Current

one can expect 250 mVp−p signal extracted from a HART

Slave device. A HART Master can have a sense resistor −
ranging from 230 W to 600 W. 4.7 mF

Figure 20. Dual Capacitive Coupling

Master Connection to a HART Network
A HART Master must be able to receive voltage signals
Capacitive coupling can work well when Masters have
that are developed across the sense impedance. In addition,
their power isolated from ground. When the system power
it must be able to apply a transmit signal across the current
configuration is unknown, the use of transformer coupling
sense impedance. In some cases the Master will signal
will insure the elimination of ground effects. An example of
across the field device as well. In all cases, the presence of
transformer coupling is shown below in Figure 21.
the HART Master must not disrupt the analog signaling of
the process loop. Therefore, the HART signals must be PC20101125.6
non−intrusively coupled from the current sense resistor to
the Master through one of the various coupling techniques 2.2 mF
HART
listed below. Modem
+

Coupling Techniques Current

Sense
Loop
Coupling to the network is most commonly done with Resistor
Current

capacitors and transformers. The simplest form of coupling

−
is a single capacitor as shown in Figure 19.
This coupling technique will only work if one side of the Figure 21. Transformer Coupling
Current Sense Resistor is connected to the analog ground.
Grounding Effects
PC20101125.4
With the use of capacitive coupling, AC and DC ground
loops can be created if one is not aware of the grounding
2.2 mF
HART techniques of both the Master and the process loop. If the
Modem
+ Master is powered from a battery or a galvanically isolated
Current power source, then single capacitive coupling will work in
Sense
Resistor
Loop
Current any HART network.
If a Master (that does not have an isolated power source)
with single capacitive coupling is connected to a sense
This coupling technique will only work if one side resistor or field device that is not at ground potential, a DC
of the Current Sense Resistor is connected to the
ground loop will occur as shown in below:
analog ground.
In this case the Field Device will have a direct short across
Figure 19. Single Capacitive Coupling it.

Using two capacitors will allow a connection across a

sense resistor or field device that does not have one of its
connections at analog ground as show below in Figure 20.
When two coupling capacitors are used, lager values are
required to meet the impedance requirements.

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 AND8346/D
PC20101209.1
Loop
illustrated in Figure 24. This means, for example, that a
2.2 mF
Current sinusoidal output at 25 Hz must have an amplitude into a
HART 500 W test load of less than 8 Vp−p. It also means that a
+
Modem 25 Hz square wave of 8 Vp−p would not be acceptable, since
Current its harmonics do not decrease at a −40 dB rate.
Sense
Resistor The required roll−off of the 4 – 20 mA analog signal can
HART be achieved by various means, including:
Field
Device • Analog filters.
• Digital filters (software).
• Inherent filtering in the instrument sensor.
In this case the Field Device will have a direct Often it is a combination of these. Any convenient method
short across it. may be used to insure that changes in instrument output
Figure 22. Single Capacitor Coupled DC Ground current fall within the specification. If the field instrument
Loop uses a D/A converter (DAC) to generate its analog output,
If the Master has a ground connection that is not at the the output steps of the DAC must be sufficiently small or else
ground potential as the analog ground from the process loop, the high−frequency content of the steps must be removed by
it is possible to create AC ground loops. A noisy 240 VAC filtering. When large changes in the DAC output occur due
ground signal could be coupled directly unto the process to calibration operations, caution must be used not to have
loop ground (single capacitive coupling) or coupled unto the these DAC changes active during a HART command or
process loop (dual capacitive coupling) ground through the response. Any large and fast current changes that fall outside
connection. The AC noise potentially could impede HART the HART specifications can cause unreliable
communications and corrupt the accuracy of the DCS communications with the HART Master or Slave.
measuring the analog current as shown in Figure 23. The analog signaling of typical field instruments is
usually band−limited to the range of 1 to 10 Hz, so that the
PC20101209.2 roll−off starts well below the 25 Hz point of Figure 24. This
Loop can lead to simpler low− pass filtering. For example, a
HART
Current
single−pole filter that begins rolling off at 1 Hz falls below
Modem
+ the curve of Figure 24.
The dashed line illustrated the use of a simple first order
Current
Sense filter with a pole at 1 Hz.
Resistor

Digital Analog
Ground Ground

The dashed line shows the ground loop when a

single coupling capacitor is used..
Figure 23. Capacitor Coupled AC Ground Loop

Limiting the Analog Signal Frequency Bandwidth

Digital signaling can potentially interfere with analog
signaling. A much worse problem is the analog signal
interfering with digital signaling. This is due to the relative
size of the two signals. For example, a change from 4 to
20 mA can produce a voltage change of as high as 16 V
across the field instrument terminals, depending on the
amount of resistance in the loop. At the same time, the
instrument may be trying to detect a HART (digital) signal
as low as 80 mVp−p.
Figure 24. Analog Signal Bandwidth Limitation
Separating the two is usually done with a combination of
low−pass filtering of the analog signal and high−pass
filtering of the HART signal. The HART Physical Layer
Specification1 (section 7.2) limits the analog signal to
16 mA p−p at frequencies below 25 Hz and constrains the
output above 25 Hz to fall within a −40 dB/decade slope, as

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 AND8346/D

Miscellaneous UARTs differ in when they indicate empty. Some indicate

empty at the time of the last shift clock − that is,
Start of Frame
simultaneously with the stop bit being shifted out. But if
Because the HART carrier must be started and stopped, carrier were to be turned off at that time, the modem would
the receiving UART and processor must become cease transmitting and the stop bit wouldn’t be sent.
synchronized to each HART frame. During the Therefore, it is important to determine which kind of UART
synchronization period at the beginning of the frame, it is you have. If it behaves as described, then you should wait at
normal for some transmitted bytes to be corrupted or lost. least one bit time after the empty indication until you turn off
Various HART requirements have been devised to insure carrier. Note that adding a 1 bit delay can’t do any harm, even
that synchronization will occur. They are: if it isn’t needed.
• The transmitting device must send at least five
preamble bytes (hex FF). Misuse of Carrier Detect
• The transmitting device must load the first preamble To maximize speed, a field instrument will often be
byte into the transmit UART within 5−bit times of designed to begin its response frame immediately after the
starting carrier. Master’s command frame. These frames are close enough
together that there is not enough time for carrier detect to
• The receiving device must recognize carrier within
drop out. This brings out an important point regarding
30−bit times.
carrier detect: It sole purpose is to indicate the presence of
Correct start−up is based on the fact that, during the stream
carrier, so that receivers know that they have sufficient
of preamble bytes, the start bits (applied to the UART) are
signal to work with. Carrier detect is not intended to reliably
the only 0 bits.
indicate the start or end of a particular frame. Start of frame
Everything else (stop, data, and parity bits), including idle
detection is a Data Link Layer function and must occur
time, is a 1. Although some extra 0 bits may be generated by
through examination of the frame content.
the start−up transient, after a short time only valid start bits
will remain and the device will be synchronized. More information
More information can be found under following
End of Frame
weblinks:
The UART can cause a possible problem at the end of
frame. Normally, it is necessary to wait until the last bit of Datasheets and Application notes of devices used above
the last character of the frame has been sent until carrier is http://www.onsemi.com
turned off. The UART usually tells you it is empty, which is HART Standards:
an indication that you should turn carrier off. However, http://www.hartcomm.org/

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 AND8346/D

APPENDIX

HART Slave only. For detailed information on the Hart Physical Layer
The schematic in Figure 25 is a possible implementation specification and requirements see the HART Physical
of the HART Slave physical layer. The Loop Current Layer Specification1.
Regulator Circuit build around the op amp is for information

3.3 V
C4 R6 R5

VDD VDDA RxAFI RxAF

IC1 R14
R3 C3 C2 C1
C6 RESET
21, 30 13 24 27 29 31 32 16 15 RxA
CAT808 2 14

R4 R2 R1

R7
VDDA
RxD
25 LM285
AREF R9
A5191HRT
CD 8
26 Z1
3.3 V
R11 C5
mC R13 9
R10
+
CDREF
RTS
22
C9 Opamp
TxD TxA R15 Q1
23 7
17 18 1 3 4 5 11 28 6, 20 12,19 10

PC20101210.1 XOUT XIN VSS VSSA CBIAS

*
X1 HART &
C10 4 - 20 mA OUT
R12 R19 R17
C7 C8

R18
R20 R16
4 ć 20 mA
DAC OUT
−
**

Figure 25. Possible Implementation for HART Slave Physical Layer

Table 4. COMPONENT LIST HART SLAVE IMPLEMENTATION

Symbol Value Tolerance Units
R1 215 1% kW
R2 215 1% kW
R3 499 1% kW
R4 787 1% kW
R5 422 1% kW
R6 215 1% kW
R7 3 5% MW
R8 470 5% pF
R9 10 1% kW
R10 200 1% kW
R11 14.7 1% kW
R12 499 1% kW
R13 1 5% MW
R14 100 5% kW
*Value depends on used operational amplifier
* *Value depends on VMSB of DAC

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 AND8346/D

Table 4. COMPONENT LIST HART SLAVE IMPLEMENTATION

Symbol Value Tolerance Units
R15 47 1% kW
R16 11.3 1% kW
R17 120 1% W
R18 120 1% kW
R19 3.6 5% kW
R20 6.2** 1% kW
C1 470 5% pF
C2 1 5% nF
C3 1 5% nF
C4 220 5% pF
C5 10 20% nF
C6 100 20% nF
C7 220 5% pF
C8 220 5% pF
C9 100 5% nF
C10 *
Z1 LM285 http://www.onsemi.com/pub/Collateral/LM285−D.PDF
Q1 BC547 http://www.onsemi.com/pub/Collateral/BC546−D.PDF
IC1 CAT808 http://www.onsemi.com/pub/Collateral/CAT808−D.PDF
X1 ZTBF−460.8−E http://www.ecsxtal.com/store/pdf/ztb_ztbfr.pdf
*Value depends on used operational amplifier
* *Value depends on VMSB of DAC
HART Master coupling circuit build around the op amp is for information
The schematic in Figure 26 is a possible implementation only. For detailed information on the Hart Physical Layer
of the HART Master physical layer. The HART signal specification and requirements see HCF_SPEC−54.

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 AND8346/D

3.3 V
C4 R6 R5

VDD VDDA RxAFI RxAF

IC1 R14
R3 C3 C2 C1
C6 RESET
21, 30 13 24 27 29 31 32 16 15 RxA
CAT808 2 14

R4 R2 R1

R7
VDDA
RxD
25 LM285
AREF R9
A5191HRT
CD 8
26
Z1
3.3 V
R11 C5
mC R13 9
R10
CDREF
RTS
22
Opamp
TxD TxA MC74VHC1GT66
23 7 C9
17 18 1 3 4 5 11 28 6, 20 12,19 10 Loop
PC20101210.1 XIN VSS VSSA CBIAS Current
XOUT IC2
X1
R15
R12 RTS
C7 C8

Figure 26. Possible Implementation for HART Master Physical Layer

Table 5. COMPONENT LIST HART MASTER IMPLEMENTATION

Symbol Value Tolerance Unit
R1 215 1% kW
R2 215 1% kW
R3 499 1% kW
R4 787 1% kW
R5 422 1% kW
R6 215 1% kW
R7 3 5% MW
R8 470 5% pF
R9 10 1% kW
R10 200 1% kW
R11 14.7 1% kW
R12 499 1% kW
R13 1 5% MW
R14 100 5% kW
R15 499* 1% W
C1 470 5% pF
C2 1 5% nF
C3 1 5% nF
C4 220 5% pF
C5 10 20 % nF
*Value depends on the required HART master Current Sense sensitivity

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 AND8346/D

Table 5. COMPONENT LIST HART MASTER IMPLEMENTATION

Symbol Value Tolerance Unit
C6 100 20 % nF
C7 220 5% pF
C8 220 5% pF
C9 2,2 20 % mF
Z1 LM285 http://www.onsemi.com/pub/Collateral/LM285−D.PDF
Q1 BC547 http://www.onsemi.com/pub/Collateral/BC546−D.PDF
IC1 CAT808 http://www.onsemi.com/pub/Collateral/CAT808−D.PDF
IC2 1GT66 http://www.onsemi.com/pub/Collateral/MC74VHC1GT66−D.PDF
X1 ZTBF−460.8−E http://www.ecsxtal.com/store/pdf/ztb_ztbfr.pdf
*Value depends on the required HART master Current Sense sensitivity
A5191HRT Current Consumption different operating conditions. Other possibilities to reduce
The current consumption of the 15191HRT can be current consumption include shutting down the master
drastically reduced by reducing operating voltage and using during dead time, and careful design of reference voltage
an external clock. Table 6 lists typical current usage under generation.

Table 6. CURRENT CONSUMPTION IN DIFFERENT CIRCUIT CIRCUMSTANCES

Operating Condition Operating Voltage Current Consumption
Idle, External oscillator 2.8 V 220 mA (Typ.)
Idle, External oscillator 3V 240 mA (Typ.)
Normal Operation 3V 350 mA (Typ.)
Absolute maximum current consumption 3V 450 mA (Max.)

REFERENCES

1. HART Communication Foundation Document Layer Specification, Revision 8.1; 9390 Research
Number HCF_SPEC−13, HART FSK Blvd., Suite I−350, Austin Texas, 78759.
Communication Protocol Specification, Revision 3. HART Communication Foundation Document
7.3; 9390 Research Blvd., Suite I−350, Austin Number HCF_TEST_2, HART FSK Physical
Texas, 78759. Layer Test Specification, Revision 2.1; 9390
2. HART Communication Foundation Document Research Blvd., Suite I−350, Austin Texas, 78759.
Number HCF_SPEC−54, HART FSK Physical

HART is a registered trademark of the HART Communication Foundation of Austin, Texas, USA. Any time that the term ‘HART’ is used in
this document or in any document referenced by this document, that term implies the registered trademark.

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