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October 20, 2017     2 comments

Gate Questions on Multiplexers (MUX) Search

1992
Question 1: GATE | GATE-EC-1992 Popular Tags Blog Archives

The logic realized by the circuit shown in figure is -

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(C) F = B ⊙ C
are given. GATE questions also given at
(D) F = B ⊗ C
the end of the chapter.
Answer: (B)
Explaination: GATE 2019 QUESTIONS-ANSWERS

2001 General Aptitude

Question 1: GATE | GATE-EC-2001
In the TTL circuit in the figure, S2 to S0 are select lines and X7 and X0 are input lines. S0 and Engineering Mathematics
X0 are LSBs. The output Y is -
Electronic Devices

Analog Circuits

Digital Electronics

Microprocessor(8085)

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(A) indeterminate
(B) A ⊗ B Electromagnetic Theory
(C) A ⊗ B
(D) C̅ .(A ⊗ B) + C.(A ⊗ B)
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Answer: (D)
Topicwise Previous Year GATE Questions on
Explaination:
Microprocessor 8085
2003 Microprocessor(8085) Topicwise Previous Year
GATE Questions(1987-2017) Gate Questions on
Question 1: GATE | GATE-EC-2003 (ISRO-EC-2017)
Fundamentals of Microprocessor Ga...
Without any additional circuitry, an 8:1 MUX can be used to obtain -

Gate Questions on Fundamentals of

(A) some but not all Boolean functions of 3 variables
Microprocessor
(B) all function of 3 variables but none of 4 variables
Gate Questions on Fundamentals of
(C) all functions of 3 variables and some but not all of 4 variables Microprocessor 1995 Question 1: GATE | GATE-
(D) all functions of 4 variables EC-1995 An ‘Assembler’ of a microp...

Answer: (C)
Gate Questions on Instruction Set of 8085
Explaination: Gate Questions on Instruction Set of 8085 1988
Question 1: GATE | GATE-EC-1988 In register index
2004 addressing mode...
Question 1: GATE | GATE-EC-2004

The minimum number of 2 to 1 multiplexers required to realize a 4 to 1 mutliplexer is -

(A) 1
(B) 2
(C) 3 Gate Questions on Memory and I/O
(D) 4 Interfacing of 8085
Gate Questions on Memory and I/O
Answer: (C) Interfacing of 8085 1988 Question 1:
GATE | GATE-EC-1988 A
Explaination: microprocessor with ...

Question 2: GATE | GATE-CS-2004 GATE Questions on Laplace

Consider a multiplexer with X and Y as data inputs and Z as control input. Z = 0 selects Transform
input X, and Z = 1 selects input Y. What are the connections required to realize the Gate Questions on Laplace
2-variable Boolean function f = T + R, without using any additional hardware ? Transform 1987 Question 1: GATE |
GATE-EC-1987 Laplace transform of
the functions t u(t) a...
(A) R to X, 1 to Y, T to Z
(B) T to X, R to Y, T to Z
(C) T to X, R to Y, 0 to Z Gate Questions on Architecture of 8085
(D) R to X, 0 to Y, T to Z Gate Questions on Architecture of 8085 1989
Question 1: GATE | GATE-EC-1989 In a
microprocessor system, the stack...
Answer: (A)

Explaination: Gate Questions on Multiplexers

(MUX)
2005 Gate Questions on Multiplexers
(MUX) 1992 Question 1: GATE |
Question 1: GATE | GATE-EC-2005
GATE-EC-1992 The logic realized by
The Boolean function f implemented in figure using two input multiplexers is - the circuit sho...

Gate Questions on Pins and Signals of 8085

Gate Questions on Pins and Signals of 8085 1993
Question 1: GATE | GATE-EC-1993 In a
microcomputer, wait states ...

Gate Questions on Flip-flop,

Counters and Shift-Registers
1988 Question 1: GATE | GATE-
(A) AB̅ C + ABC̅ EC-1988 The circuit given below is a
(B) ABC + AB̅ C̅ - (A) J-K Flip-Flop (B) Johnson's Co...
(C) A̅ BC + A̅ B̅C̅
(D) A̅ B̅C + A̅ BC̅ Gate Questions on Number System
Representation
Answer: (A) 1987 Question 1: GATE | GATE-EC-1987 The
Explaination: subtraction of a binary number Y from another
binary number X, done by ad...
2007
Question 1: GATE | GATE-EC-2007
BLOG ARCHIVE
In the following circuit, X is given by -
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Latches and Flip-Flops

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Gate Questions on Logic Families

(A) X = A B̅ C̅ + A̅ B C̅ + A̅ B̅ C + A B C Gate Questions on ADC and DAC Coverters

(B) X = A̅ B C + A B̅ C + A B C̅ + A̅ B̅ C̅
Boolean Algebra
(C) X = AB + BC + AC
(D) X = A̅ B̅ + B̅ C̅ + A̅ C̅ Gate Questions on Combinational Arithmetic
Circuit...
Answer: (A) Logic Gates
Explaination:
Gate Questions on Logic Gates
2008 Topicwise Previous Year GATE
Question 1: GATE | GATE-EC-2008 Questions(1987-2019)
For the circuit shown in the following figure I0-I3 are inputs to the 4:1 multiplexer R(MSB)
Gate Questions on Boolean Algebra
and S are control bits. The output Z can be represented by -
Gate Questions on Multiplexers (MUX)

Number System

Gate Questions on Floating Point

Representation

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Representation

Sequential Circuits

(A) P Q + P Q̅ S + Q̅ R̅ S̅ Gate Questions on Flip-flop, Counters and

(B) P Q̅ + P Q R̅ + P̅ Q̅ S̅ Shift-Re...
(C) P Q̅ R̅ + P̅ Q R + P Q R S + Q̅ R̅ S̅
(D) P Q R̅ + P Q R S̅ + P Q̅ R̅ S + Q̅ R̅ S̅
 ►  2013 (4)
Answer: (A)
Explaination:
FOLLOWERS
2009
Question 1: GATE | GATE-EC-2009 Followers (27) Next

What are the minimum number of 2 to 1 multiplexers required to generate a 2-input AND
gate and a 2-input Ex-OR gate?

(A) 1 and 2
(B) 1 and 3
(C) 1 and 1
(D) 2 and 2 Follow

Answer: (A) ABOUT ME

Explaination: SA MS

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2010
joy of the success in life...
Question 1: GATE | GATE-EC-2010
V I EW MY CO MPL E TE P RO F I LE

The Boolean function realized by the logic circuit shown is -

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(A) F=Σm(0,1,3,5,9,10,14)
(B) F=Σm(2,3,5,7,8,12,13)
(C) F=Σm(1,2,4,5,11,14,15)
(D) F=Σm(2,3,5,7,8,9,12)

Answer: (D)
Explaination:

2011
Question 1: GATE | GATE-EC-2011

The logic function implemented by the circuit below is (ground implies logic 0)-

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Theory Format

(A) F = AND(P,Q) The photonic nature of light

(B) F = OR (P,Q)
(C) F = XNOR (P,Q) Direct and Indirect Band Gap

(D) F = XOR (P,Q)

Energy of an Electron

Answer: (D) Bohr’s Atomic Model

Explaination:

2014 Theory Format

Question 1: GATE | GATE-EC-2014
The photonic nature of light

Consider the multiplexer-based logic circuit shown in the figure.

Direct and Indirect Band Gap

Energy of an Electron

Bohr’s Atomic Model

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Which one of the following Boolean functions is realized by the circuit?
Details
(A) F = W S1 S2
Details
(B) F = WS1 + WS2 + S1S2
(C) F = W + S1 + S2 BLOGGER TEMPLATES
(D) F = W ⊕ S1 ⊕ S2
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Answer: (D)
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Explaination:

Question 2: GATE | GATE-EC-2014 ABOUT ME

SA MS
In the circuit shown, W and Y are MSBs of the control inputs. The output F is given by -
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(A) F = W X + W X + Y Z
(B) F = W X + W X + Y Z
(C) F = W X Y + W X Y
(D) F = (W
(W + X ) Y Z

Answer: (C)

Explaination:

Question 3: GATE | GATE-EC-2014

If X and Y are inputs and the difference (D = X – Y) and the borrow (B) are the outputs,
which one of the following diagrams implements a half subtractor?

Answer: (A)

Explaination:

Question 4: GATE | GATE-EC-2014

An 8-to-1 multiplexer is used to implement a logical function Y, as shown in the figure. The
output Y is given by -

(A) Y = A B C + A C D
(B) Y = A B C + A B D
(C) Y = A B C + A C D
(D) Y = A B D + A B C
Answer: (C)

Explaination:

2015
Question 1: GATE | GATE-EC-2015

A 1-to-8 demultiplexer with data input Din, address inputs S0, S1, S2 (with S0 as the LSB)
and Y0 to Y7 as the eight demultiplexed outputs, is to be designed using two 2-to-4
decoders (with enable input E and address inputs A0 and A1) as shown in the figure. Din,
S0, S1 and S2 are to be connected to P, Q, R, and S, but not necessarily in this order. The
respective input connections to P, Q, R, and S terminals should be -

(A) S2, Din, S0, S1

(B) S1, Din, S0, S2
(C) Din, S0, S1, S2
(D) Din, S2, S0, S1

Answer: (D)

Explaination:

2016
Question 1: GATE | GATE-EC-2016

The functionality implemented by the circuit below is -

(A) 2 to 1 multiplexer
(B) 4 to 1 multiplexer
(C) 7 to 1 multiplexer
(D) 6 to 1 multiplexer

Answer: (B)

Explaination:

Question 2: GATE | GATE-EC-2016

A 4:1 multiplexer is to be used for generating the output carry of a full adder. A and B are
the bits to be added while Cin is the input carry and Cout is the output carry. A and B are to
be used as the select bits with A being the more significant select bit.
Which one of the following statements correctly describes the choice of signals to be
connected to the inputs I0, I1, I2, and I3 so that the output is Cout?

(A) I0 = 0, I1 = Cin, I2 = Cin and I3 = 1

(B) I0 = 1, I1 = Cin, I2 = Cin and I3 = 1
(C) I0 = Cin, I1 = 0, I2 = 1 and I3 = Cin
(D) I0 = 0, I1 = Cin, I2 = 1 and I3 = Cin

Answer: (A)

Explaination:

Question 3: GATE | GATE-EC-2016

For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are
2ns, 1.5ns and 1ns respectively. If all the inputs P, Q, R, S and T are applied at the same
time instant, the maximum propagation delay (in ns) of the circuit is __________.

Answer: 6 ns

Explaination:

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2 comments:

Unknown February 4, 2019 at 9:30 AM

Its very good .Please provide the explanation which helps us to check wheather our
analization is true are false
Reply

Replies

Sams February 10, 2019 at 3:53 AM

thank you for appreciating our work. We are working on it to provide the
explanation and theory, so that you can easily crack the examination.

Reply

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