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    Decade Counter

    Uploaded by

    Manohar thota
    This document contains VHDL code for a decade counter and its testbench. The decade counter code contains an entity with a clock, reset and 4-bit output port. It uses a process sensitive to the clock and reset to increment a 4-bit counter signal from 0 to 9 before resetting. The testbench instantiates the decade counter component and generates a clock signal while pulsing the reset. It maps the ports and monitors the output counter signal.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Decade Counter

    Uploaded by

    Manohar thota
    974 views3 pages
    This document contains VHDL code for a decade counter and its testbench. The decade counter code contains an entity with a clock, reset and 4-bit output port. It uses a process sensitive to the clock and reset to increment a 4-bit counter signal from 0 to 9 before resetting. The testbench instantiates the decade counter component and generates a clock signal while pulsing the reset. It maps the ports and monitors the output counter signal.

    Original Title

    DECADE COUNTER.docx

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    This document contains VHDL code for a decade counter and its testbench. The decade counter code contains an entity with a clock, reset and 4-bit output port. It uses a process sensitive to the clock and reset to increment a 4-bit counter signal from 0 to 9 before resetting. The testbench instantiates the decade counter component and generates a clock signal while pulsing the reset. It maps the ports and monitors the output counter signal.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    974 views3 pages

    Decade Counter

    Uploaded by

    Manohar thota
    This document contains VHDL code for a decade counter and its testbench. The decade counter code contains an entity with a clock, reset and 4-bit output port. It uses a process sensitive to the clock and reset to increment a 4-bit counter signal from 0 to 9 before resetting. The testbench instantiates the decade counter component and generates a clock signal while pulsing the reset. It maps the ports and monitors the output counter signal.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 3

    DECADE COUNTER VHDL CODE

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity DECADECOUNTER is

    Port ( clk: in std_logic; -- clock input

    reset: in std_logic; -- reset input

    counter: out std_logic_vector(3 downto 0) -- output 4-bit counter

    );

    end DECADECOUNTER ;

    architecture Behavioral of DECADECOUNTER is

    signal counter_up: std_logic_vector(3 downto 0);

    begin

    -- up counter

    process(clk,reset)

    begin

    if(rising_edge(clk)) then

    if(reset='1') then

    counter_up <= x"0";

    elsif counter_up<9 then

    counter_up <= counter_up + x"1";

    end if;

    end if;
    end process;

    counter <= counter_up;

    end Behavioral;

    DECADE COUNTER TESTBENCH CODING

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    -- FPGA projects using Verilog code VHDL code

    -- fpga4student.com: FPGA projects, Verilog projects, VHDL projects

    -- VHDL project: VHDL code for counters with testbench

    -- VHDL project: Testbench VHDL code for up counter

    entity tb_counters is

    end tb_counters;

    architecture Behavioral of tb_counters is

    component DECADECOUNTER

    Port ( clk: in std_logic; -- clock input

    reset: in std_logic; -- reset input

    counter: out std_logic_vector(3 downto 0) -- output 4-bit counter

    );

    end component;

    signal reset,clk: std_logic;


    signal counter:std_logic_vector(3 downto 0);

    begin

    dut: DECADECOUNTER port map (clk => clk, reset=>reset, counter => counter);

    -- Clock process definitions

    clock_process :process

    begin

    clk <= '0';

    wait for 10 ns;

    clk <= '1';

    wait for 10 ns;

    end process;

    -- Stimulus process

    stim_proc: process

    begin

    -- hold reset state for 100 ns.

    reset <= '1';

    wait for 20 ns;

    reset <= '0';

    wait;

    end process;

    end Behavioral;

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