Arithmetic Logic Unit (ALU) Miniproject
Arithmetic Logic Unit (ALU) Miniproject
Arithmetic Logic Unit (ALU) Miniproject
Objectives:
An Arithmetic and Logic Unit (ALU) is a combinational circuit that performs logic and
arithmetic micro-operations on a pair of n-bit operands (ex. A[3:0] and B[3:0]). The operations
performed by an ALU are controlled by a set of function-select inputs. In this lab you will
design a 4-bit ALU with 3 function-select inputs: Mode M, Select S1 and S0 inputs. The
mode input M selects between a Logic (M=0) and Arithmetic (M=1) operation. The functions
performed by the ALU are specified in Table I.
When doing arithmetic, you need to decide how to represent negative numbers. As is commonly
done in digital systems, negative numbers are represented in two’s complement. This has a
number of advantages over the sign and magnitude representation such as easy addition or
subtraction of mixed positive and negative numbers. Also, the number zero has a unique
representation in two’s complement. The two’s complement of a n-bit number N is defined as,
2n - N = (2n - 1 - N) + 1
The last representation gives us an easy way to find two’s complement: take the bit wise
complement of the number and add 1 to it. As an example, to represent the number -5, we take
two’s complement of 5 (=0101) as follows,
Numbers represented in two’s complement lie within the range -(2n-1) to +(2n-1 - 1). For a 4-bit
number this means that the number is in the range -8 to +7. There is a potential problem we still
need to be aware of when working with two's complement, i.e. over- and underflow as is
illustrated in the example below,
0 1 0 0 (=carry Ci)
+5 0 1 0 1
+4 + 0 1 0 0
+9 0 1 0 0 1 = -7!
also,
1 0 0 0 (=carry Ci)
-7 1 0 0 1
-2 + 1 1 1 0
-9 1 0 1 1 1 = +7!
Both calculations give the wrong results (-7 instead of +9 or +7 instead of -9) which is caused by
the fact that the result +9 or -9 is out of the allowable range for a 4-bit two’s complement number.
Whenever the result is larger than +7 or smaller than -8 there is an overflow or underflow and the
result of the addition or subtraction is wrong. Overflow and underflow can be easily detected
when the carry out of the most significant stage (i.e. C4 ) is different from the carry out of the
previous stage (i.e. C3).
You can assume that the inputs A and B are in two’s complement when they are presented to the
input of the ALU.
b. Design strategies
When designing the ALU we will follow the principle "Divide and Conquer" in order to use a
modular design that consists of smaller, more manageable blocks, some of which can be re-used.
Instead of designing the 4-bit ALU as one circuit we will first design a one-bit ALU, also called a
bit-slice. These bit-slices can then be put together to make a 4-bit ALU.
There are different ways to design a bit-slice of the ALU. One method consists of writing the
truth table for the one-bit ALU. This table has 6 inputs (M, S1, S0, C0, Ai and Bi) and two outputs
Fi and Ci+1. This can be done but may be tedious when it has to be done by hand.
An alternative way is to split the ALU into two modules, one Logic and one Arithmetic module.
Designing each module separately will be easier than designing a bit-slice as one unit. A possible
block diagram of the ALU is shown in Figure 2. It consists of three modules: 2:1 MUX, a Logic
unit and an Arithmetic unit.