Asynchronous

Sequential Circuits
 Synchronous Sequential Circuits
• The change of internal state occurs in response to the
synchronized clock pulses.
• The memory elements are flip‐flops.
Asynchronous Sequential Circuits
Asynchronous sequential circuits
- Internal states can change at any instant of time when there is a
change in the input variables
- No clock signal is required
- Have better performance but hard to design due to timing problems
n Input m Output
-The memory Variables Variables
elements are either xn Zm
unclocked FF’s or x1
Combinational Z1
time-delay elements. Circuit Design
-The design of these
circuits is more
y0 Y0
difficult than the delay
Secondary Variables Excitaion Variables
design of (present State) (next state)
delay
synchronous circuits
due to the timing yk
delay
Yk
problem.
 Why Asynchronous Circuits?
1- Accelerate the speed of the machine (no need to
wait for the next clock pulse).

2-Used when the input signals change independently

of the clock pulses.

3- Simplify the circuit in the small independent circuits.

4- Used to communicate two circuits each have its own

clock.
Asynchronous Circuits
• The delay elements provide short‐term memory for the sequential
circuits.

• Present state variables [y1..yk] are called secondary variables

n Input m Output
Variables Variables
• Next state variables
[Y1..Yk] are called excitation xn Zm
variables. x1
Combinational Z1
Circuit Design
• When an input variable
changes, it takes a certain
time to propagate through the y0 Y0
delay
combinational circuit to Secondary Variables Excitaion Variables
change Y, and then Y takes a (present State) (next state)
delay
certain time to propagate
through the delay element to yk Yk
delay
become a new state.
 Asynchronous Circuits
• The circuit reaches a steady‐state condition when yi = Yi for i=1,2,…, K.

• Stable System:
for a given value of input variables, the system is stable if the circuit
reaches a steady state condition.

• Fundamental‐mode operation:
this mode assumes that the one input signal changes at a time and
only when the circuit is in stable condition.

• The time between two input changes must be longer than the time it takes
the circuit to reach a stable state.
 Analysis Procedure
The analysis consists of obtaining a table or a diagram that
describes the sequence of internal states and outputs as a
function of changes in the input variables.

Transition Table

Flow Table

Stability Consideration
 Transition Table
Transition table is useful to analyze an asynchronous circuit from the circuit
diagram Procedure to obtain transition table:

1. Determine all feedback loops in the circuits

2. Mark the input (yi) and output (Yi) of each feedback loop

3. Derive the Boolean functions of all Y’s

4. Plot each Y function in a map and combine all maps into one table

5. Circle those values of Y in each square that are equal to the value of y in
the same row
Transition Table

Y1 = xy1 + x’y2
Y2 = xy’1 + x’y2
Transition Table
-If y=00 and x= 0 Y ==00
(Stable)
-If x changes from 0 to 1 while
y=00, the circuit changes Y to 01
which is temporary unstable
condition (Y != y)
-As soon as the signal propagates
to make Y = 01, the feedback
path causes a change in y to 01.
(transition form the first row to
the second row)
-If the input repeatedly alternates
between 0 and 1, the circuit will
repeat the sequence of states
 Transition Table
In an asynchronous sequential circuit, the internal state can
change immediately after a change in the input.

It is sometimes convenient to combine the internal state with

input
value together and call it the Total State of the circuit.
(Total state = Internal state + Inputs)

In the last example , the circuit has

• 4 stable total states: (y1y2x= 000, 011, 110, and 101)
• 4 unstable total states: (y1y2x= 001,010,111, and 100)
 Flow Table
• A flow table is similar to a transition table except that the
internal state are symbolized with letters rather than
binary numbers.
• It also includes the
output values of the
circuit for each stable
state.
 Flow Table
• In order to obtain the
circuit described by a
flow table, it is
necessary to convert the
flow table into a
transition table from
which we can derive the
logic diagram .

• This can be done

through the assignment
of a distinct binary value
to each state.
 Race condition
Two or more binary state
variables will change value
when one input variable
changes.
Cannot predict state
sequence if unequal delay
is encountered.
Non-critical race: The final
stable state does not
depend on the change
order of state variables
Critical race: The change
order of state variables will
result in different stable
states Should be avoided !!
 Race Solution
It can be solved by making a proper binary assignment to the
state variables.
The state variables must be assigned binary numbers in such
a way that only one state variable can change at any one
time when a state transition occurs in the flow table.
It will be discussed later.
 Stability Check
Asynchronous sequential circuits may oscillate between
unstable states due to the feedback
-Must check for stability to ensure proper operations
Can be easily checked from the transition table
-Any column has no stable states unstable
-Ex: when x1x2=11 in Fig. 9-9(b), Y and y are never the
same Y = x’1x2 + x2y’
 Latches in Asynchronous Circuits
-The traditional configuration of asynchronous circuits is using
one or more feedback loops
- No real delay elements.
-It is more convenient to employ the SR latch as a memory
element in asynchronous circuits
- Produce an orderly pattern in the logic diagram with the
memory elements clearly visible.
-SR latch is also an asynchronous circuit
- Will be analyzed first using the method for asynchronous
circuits.
SR Latch with NOR Gates

S=1, R=1 (SR = 1)

should not be used
⇒ SR = 0 is
normal mode

* should be carefully
checked first
SR Latch with NAND Gates

S=1, R=1 (SR = 1)

should not be used
⇒ SR = 0 is
normal mode

* should be carefully
checked first
 Analysis Procedure

Analysis Procedure for NOR latch based

asynchronous circuit
(i) Label each latch o/p with Yi and feed back path
with yi
(ii) Derive Boolean functions for Si and Ri
(iii) Check SR = 0 for each NOR latch
(iv) Evaluate Y = S + R’y for each latch
(v) Construct the transition table
(vi) Circle all stable states
Analysis Example
 Analysis Example
The procedure for analyzing an asynchronous sequential
circuit with SR latches can be summarized as follows:

1. Label each latch output with Yi and its external feedback

path with yi for i=1,2,…,k

2. Derive the Boolean functions for the Si and Ri inputs in each

latch.
S1  x1 y2 S2  x1 x2
\ \
R1  x x
1 2
R2  x2\ y1
 Analysis Example
3. Check whether SR =0 for each NOR latch or whether S’R’ =
0 for each NAND latch. (if either of these two conditions is
not satisfied, there is a possibility that the circuit may not
operate properly) \ \
S1 R1  x1 y2 x1 x2  0
\
S2 R2  x x x y  0
1 2 2 1
4. Evaluate Y = S + R’y for each NOR latch or Y = S’ + Ry for
each NAND latch.

Y1  S1  R1\ y1  x1 y2  ( x1  x2 ) y1  x1 y2  x1 y1  x2 y2

Y2  S2  R2\ y2  x1 x2  ( x2  y1\ ) y2  x1 x2  x2 y2  y1\ y2

 Analysis Example
5. Construct a map, with the y’s representing the rows and
the x inputs representing the columns.
6. Plot the value of Y=Y1Y2…Yk in the map.
7. Circle all stable states such that Y=y. the result is then
the transition table.
• The transition table shows that the circuit
is stable
• Race Conditions: there is a critical race
condition when the circuit is initially in total
state y1y2x1x2 = 1101 and x2 changes
from 1 to 0.
-The circuit should go to the total state
0000.
-If Y1 changes to 0 before Y2, the circuit Transition Table
goes to total state 0100 instead of 0000.
 Implementation Procedure
Procedure to implement an asynchronous sequential
circuits with SR latches:
1. Given a transition table that specifies the excitation function
Y = Y1Y2…Yk, derive a pair of maps for each Si and Ri
using the latch excitation table
2. Derive the Boolean functions for each Si and Ri (do not to
make Si and Ri equal to 1 in the same minterm square)
3. Draw the logic diagram using k latches together with the
gates required to generate the S and R (for NAND latch, use
the complemented values in step 2)
 Implementation Procedure
Latch Excitation Table
• During the implementation process, the transition table of
the circuit is available and we wish to find the values of S
and R .
• Excitation table: Lists the required inputs S and R for each
of the possible transition from y to Y.
 Implementation Example
• Given a transition table that specifies the excitation function
Y=Y1Y2…Yk, then the general procedure for implementing
a circuit with SR latches can be summarized as follows:
 Implementation Example
1. Derive a pair of maps for Si and Ri for each I = 1, 2,…,k.
(This is done by using the latch excitation table)
 Implementation Example
2. Draw the logic diagram, using k latches together with the
gates required to generate the S and R Boolean functions
obtained in step1 (for NAND latches, use the complemented
values)
 Debounce Circuit
Mechanical switches are often used to generate binary signals to a digital
circuit
-It may vibrate or bounce several times before going to a final rest
-Cause the signal to oscillate between 1 and 0

A debounce circuit can remove the series of pulses from a contact bounce
and produce a single smooth transition
-Position A(SR=01)  bouncing(SR=11)  Position B(SR=10)
Q = 1(set)  Q = 1(no change)  Q = 0 (reset)
 Design procedure
(i) Obtain a primitive table from specifications
(ii) Reduce flow table by merging rows in the primitive flow
table
(iii) Assign binary state variables to each row of reduced
table
(iv) Assign output values to dashes associated with unstable
states to obtain the output map
(v) Simplify Boolean functions for excitation and output
variables;
(vi) Draw the logic diagram
Design Example:

Problem Statement:
Design a gated latch circuit (memory element) with two
inputs, G(gate) and D(Data) and one output Q. The Q
output will follow the D input as long as G=1. when G
goes to 0, the information that was present at the D input
at the time of transition is retained at the Q output.
 Design Example:
1-Primitive Flow Table
• A primitive flow table is a flow table with only one stable total
state (internal state + input) in each row.
• In order to form the primitive flow table , we first form a table
with all possible total states.
 Design Example:
1-Primitive Flow Table
First, we fill in one square in each row
belonging to the stable state in that
row.
Next we note that both inputs are not
allowed to change at the same time,
we enter dash marks in each row that
differs in two or more variables from
the input variables associated with the
stable state.
Next it is necessary to find values for two
more squares in each row. The
comments listed in the previous table
may help in deriving the necessary
information.
All outputs associated with unstable
states are marked with a dash to
 Design Example:
2-Reduction of the Primitive
Flow Table
Two or more rows can be merged
into one row if there are non-
conflicting states and outputs in
every columns.
After merged into one row:
Don’t care entries are overwritten
Stable states and output values are
included
A common symbol is given to the
merged row
 Design Example:
3-Transition Table and Logic Diagram
• In order to obtain the circuit described by the reduced flow
table, it is necessary to assign a distinct binary value to each
state.
• This converts the flow table to a transition table.
• A binary state assignment must be made to ensure that the
circuit will be free of critical race. (This problem will be
covered later)
a=0, b=1 in this example
 Design Example:
Implementation with SR Latch

Listed according to the transition table and the excitation

table of SR latch
 Design Example:
4- Assigning Outputs to Unstable States
• While the stable states in a flow table have specific output
values associated with them, the unstable states have
unspecified output entries designated by a dash.
These unspecified output values must be chosen so that no
momentary false outputs occur when the circuit switches
between stable states.
_______________________________________
If the two stable states have the save output value, then an
unstable states that is a transient state between them must have
the same output.
If an output variable is to change as a result of a state change,
then this variable is assigned a don’t care condition.
 Design Example:
4- Assigning Outputs to
Unstable States
Ex:
• If a changes to b, the two stable states
have the same output value =0
the transient unstable state b in the first
row must have the same output value
=0
• If b changes to c, the two stable states
have different output values
the transient unstable state c in the
second row is assigned a don’t care
condition
 Reduction of States and Flow
Tables
Implication Table

Merging of the Flow Table

Compatible Pairs

Maximal Compatibles

Closed Covering Condition

 Implication Table
Equivalent States: Two states are equivalent if, for each
possible input, they give exactly the same output and go to
the same next states or to equivalent next states.

Equivalent states can be combined into one sate in the state

table.

The checking of each pair of states for possible equivalence in

a table with a large number of states can be done
systematically by means of an Implication Table.

Implication Table: It is a chart that consists of squares, one

for every possible pair of states.
 Implication Table (Example):
1. Place a cross in any square corresponding to a pair whose outputs are not
equal
2. Enter in the remaining squares the pairs of states that are implied by the pair of
states representing the squares. (Start form the top square in the left column
and going down and then proceeding with the next column to the right).
3. Make successive passes through the table to determine whether any additional
squares should be marked with a ‘x’.
4. Finally, all the squares that have no crosses are recorded with check marks.
 Implication Table (Example):
Its clear that (e,d) are equivalent. And
this leads (a,b) and (e,g) to be
equivalent too.
Finally we have [(a,b) , c , (e,d,g) , f
]4 states.
So the original flow table can be
reduced to:
 Merging of the Flow Table
The state table may be incompletely specified(Some next
states and outputs are don’t care).
Primitive flow tables are always incompletely specified
-Several synchronous circuits also have this property
Incompletely specified states are not “equivalent” Instead, we
are going to find “compatible” states
Two states are compatible if they have the same output and
compatible next states whenever specified Three procedural
steps:
-Determine all compatible pairs
- Find the maximal compatibles
-Find a minimal closed collection of compatible
Compatible Pairs
Implication tables are used to find compatible states.
-We can adjust the dashes to fit any desired condition.
-Must have no conflict in the output values to be merged.
 Maximal Compatibles
 A group of compatibles that contains all the possible combinations of
compatible states.
-Obtained from a merger diagram.
-A line in the diagram represents that two states are compatible.
 n-state compatible  n-sided fully connected polygon.
-All its diagonals connected.
• Not all maximal compatibles
are necessary.
 Closed Covering Condition
• The condition that must be satisfied for row merging is that
the set of chosen compatibles must:
1. Cover all states.
2. Be closed: ( the closure condition is satisfied if there are no implied
states or if the implied states are included within the set)
In the last example, the maximal compatibles are (a , b) (a ,
c , d), (b , e , f)
• if we remove (a , b), we get a set of two compatibles: (a , c ,
d) , (b , e , f)
-All the six states are included in this set.
-There are no impiled states for (a,c); (a,d);(c,d);(b,e);(b,f) and (e,f) [you
can check the implication table] . the closer condition is satisfied
The original primitive flow table can be merged into two rows, one
for each of the compatibles.
 Closed Covering Condition
(Example)
• From the given implication table, we have the
following compatible: pairs: ( a , b ) ( a , d ) ( b , c )(
c , d )( c , e ) ( d , e )
• From the merger diagram, we determine the
maximal compatibles: ( a , b ) ( a , d ) ( b , c ) ( c , d
,e)
• If we choose the two compatibles:( a , b ) ( c , d , e )

-All the 5 states are included in this set.

- The implied states for (a,b) are (b,c). But (b,c) are
not include in the chosen set This set is not closed.
-A set of compatibles that will satisfy the closed
covering condition is ( a , d ) ( b , c ) ( c , d , e )
 Race--Free State Assignment
Race
• Objective: choose a proper binary state assignment to
prevent critical races
• Only one variable can change at any given time when a
state transition occurs
• States between which transitions occur will be given
adjacent assignments
-Two binary values are said to be adjacent if they differ in
only one variable
• To ensure that a transition table has no critical races, every
possible state transition should be checked
-A tedious work when the flow table is large
-Only 3-row and 4-row examples are demonstrated
 3‐Row Flow‐Table Example
Three states require two binary variables
Outputs are omitted for simplicity
Adjacent info. are represented by a transition diagram
a and c are still not adjacent in such an assignment !!
-Impossible to make all states adjacent if only 3 states are
used
 3‐Row Flow‐Table Example
A race-free assignment can be obtained if we add anextra row
to the flow table
Only provide a race-free transition between the stable
states
The transition from a to c must now go through d
00  10  11 (no race condition)
 4‐Row Flow‐Table Example
• A flow table with 4 states requires
an assignment of two state
variables.
• If there were no transitions in the
diagonal direction (from a to c or
from b to d), it would be possible
to find adjacent assignment for the
remaining 4 transitions.

• In order to satisfy the adjacency

requirement, at least 3 binary
variables are needed.
 4‐Row Flow‐Table Example
• The following state assignment map is suitable for any 4‐row
flow table.
– a, b, c, and d are the original states.
– e, f, and g are extra states.
– States placed in adjacent squares in the map will have adjacent
assignments
 4‐Row Flow‐Table Example
• To produce cycles:
– The transition from a to d must be directed through the extra state e
– The transition from c to a must be directed through the extra state g
– The transition from d to c must be directed through the extra state f
 Multiple Row Method
 Multiple-row method is easier
May not as efficient as in above
shared-row method
 Each stable state is duplicated with
exactly the same output
Behaviors are still the same
 While choosing the next states,
choose the adjacent one
 Hazards
Hazards: are unwanted switching transients that may
appear at the output of a circuit because different paths
exhibit different propagation delay.

• Hazards occur in in combinational and asynchronous

circuits:
– In combination circuits, they may cause a temporarily false output
value.
– In asynchronous circuits, they may result in a transition to a wrong
stable state.
 Hazards
Static hazard: a momentary output change when no output
change should occur
If implemented in sum of products:
-no static 1-hazard  no static 0-hazard or dynamic hazard
Two examples for static 1-hazard:
 Hazards
• The dynamic hazard causes the output to change two, three
or four times when it should change from 1 to 0 or from 0 to
1.

• The occurrence of the hazard can be detected by inspecting

the map of a particular circuit.
 Hazards Free Circuit
• The change in x2 from 1 to 0 moves the
circuit from minterm 111 to minterm 101.
• The hazard exists because the change of
input results in a different product term
covering the two minterms.
• Whenever the circuit must move from one
product term to another, there is a
possibility of a momentary interval when
neither term is equal to 1, giving rise to
undesirable 0 output.
• The solution is to enclose the minterms
with another product term that overlaps
both groupings.
Hazard Free Circuit

The removal of hazards requires the addition of redundant

gates to the circuit.
 Remove Hazards with Latches
Implement the asynchronous circuit with SR latches can also
remove static hazards
A momentary 0 has no effects to the S and R inputs of a NOR latch
A momentary 1 has no effects to the S and R inputs of a NAND latch
 Example
• Consider a NAND SR‐latch with the following Boolean
functions for S and R
S = AB + CD
R = A’C
• Since this is a NAND latch we must use the complement
value for S and R
S = (AB + CD)’ =(AB)’(CD)’
R = (A’C)’
 Example
• The Boolean function for output is
Q = (Q’S)’ = [Q’ (AB)’(CD)’]’
• The output is generated with two levels of NAND gates:

• If output Q is equal to 1, then Q′ is equal to 0. If two of the

three inputs go momentarily to 1, the NAND gate associated
with output Q will remain at 1 because Q′ is maintained at 0.
 Essential Hazards
• Besides static and dynamic hazards, another type of
hazard in asynchronous circuits is called: Essential
Hazard
• Caused by unequal delays along two or more paths that
originate from the same input
• Cannot be corrected by adding redundant gates
• Can only be corrected by adjusting the amount of delay
in the affected path
- Each feedback path should be examined carefully !!
 Design Example
Recommended Design Procedure:

1. State the design specifications.

2. Derive a Primitive Flow Table.
3. Reduce the Flow Table by merging rows.
4. Make a race‐free binary state assignment.
5. Obtain the transition table and output map.
6. Obtain the logic diagram using SR latches.
 Design Example
1) Design Specifications:

It is necessary to design a negative‐edge‐triggered T

flip‐flop. The circuit has two inputs T (toggle) and C
(clock) and one output Q. The output state is
complemented if T=1 and the clock changes from 1 to 0
(negative‐edge‐triggering). Otherwise, under all input
condition, the output remains unchanged.
 Design Example
2) Primitive Flow Table
 Design Example
3) Merging of the Flow Table

Implication Table Merger Diagram

The maximal compatibles pairs are: (a , f) (b , g , h) (c , h)
(d , e , f)
 Design Example
In this particular example, the minimal collection of
compatibles is also the maximal compatibles set:
(a , f) (b , g , h) (c , h) (d , e , f)
 Design Example
4) State Assignment and Transition Table
No diagonal lines in the transition diagram:
No need to add extra states
 Design Example
5) Logic Diagram