AN1086

Switching Power Supply Design with the PIC16F785

The following is a list of the electrical specifications for
Author: Keith Curtis the design.
Microchip Technology Inc.

ELECTRICAL:
INTRODUCTION • 9-12 VDC input
Microcontrollers are rapidly gaining ground as required • 2.0-3.9 VDC output at 10A
components in the design of Switching Mode Power • <100 mV Ripple at the output
Supply designs (SMPS). Their flexibility and program- • Non-isolated buck-topology
mable nature gives manufacturers the ability to cus- • Current mode configuration
tomize designs quickly in response to customer
• Continuous inductor current operation
demands, and implement the wide variety of complex
and custom features required by today’s electronic sys- • Synchronous switching for increased efficiency
tems. However, even with all of the microcontroller’s • Ambient temperature sensor
strengths, adding a microcontroller to a SMPS design To keep the focus of the design, and simplify the firm-
still adds one or more devices to an already crowded ware design, the communications system for the
PCB. design will be limited to a simple parallel system. The
That is, it used to add additional devices; the new following is a description of the interface:
PIC16F785 actually reduces the number of devices in
a design by including not only the necessary interface COMMUNICATIONS:
peripherals for a SMPS design, but also two channels
of analog PWM, two voltage comparators, and two op • Active low SHUTDOWN input
amps. • Active high POWERGOOD output
Now, all the parts needed to implement the analog con- • Active high FAULT output
trol sections of up to two SMPS channels are included • Four preset voltage outputs, stored in on-chip
in the microcontroller. This means fewer parts to han- EEPROM and selected by two voltage select
dle, a simpler layout, and even a lower material cost. In jumpers.
addition, the microcontroller control over the SMPS
The deterministic functions that are implemented in the
analog blocks allows control up through a Level 3
design include the following:
design (on/off control, output control, and topology/con-
figuration control), something that is only rarely possi-
ble with a separate microcontroller/PWM controller DETERMINISTIC FEATURES:
solutions.
• Delayed start-up for sequencing with other power
In this application note, we will examine a typical buck supplies
topology intelligent SMPS design using the
• Soft start of the output voltage
PIC16F785. The design employs a Level 2 microcon-
troller integration, allowing the microcontroller to • Under voltage lockout
enable/disable and output voltage control. The micro- • Slew rate limiting on output changes
controller also has the ability to monitor the perfor- • Hysteretic over temp error
mance of the analog section of the SMPS design. • Shorted output Fault detection with limited restart
Using both, control and monitoring, the microcontroller • Over current alarm
implements a variety of deterministic functions.

© 2007 Microchip Technology Inc. DS01086A-page 1

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HARDWARE THEORY OF FIGURE 1: SMPS BLOCK DIAGRAM
OPERATION +12V

Current Current
Loop Transformer
SMPS SECTION T1

To better understand how the on-chip peripherals in the

microcontroller work in the traditional analog feedback
control of a SMPS design, an examination of the oper- PWM
Generator
ation of the SMPS power section is needed. Specifi- Output
cally, how the various peripherals are used, and what
control the microcontroller can exert over their Comparator
operation. +
Voltage Loop
-
A block diagram of the switching regulator is shown in
-
Figure 1. Note that there are two feedback paths, an +
inner current loop, and the outer voltage loop. Error Amp
Loop Filter VREF

CURRENT FEEDBACK LOOP

The inner current feedback path consists of a single
channel of the on-chip analog PWM generator, the
MOSFET driver U4, the two MOSFETs Q1 and Q2, the
inductor L1, and the current transformer (T1) (see
Figure 2).

FIGURE 2: CURRENT FEEDBACK LOOP

Required Current
(From Error Amp)
T1 +12V
Voltage
Comparator
-

+
D2
PWM BST Q1
DRVH

C8 L1
PHA IN SW Output
C1 C9
PIC16F785 DRVL Q2
U3

MOSFET U4
DRIVER

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 AN1086
The phase counter internal to the analog PWM module, the output capacitors C1 and C9. The ramping inductor
initiates the PWM pulse by setting the PHA flip-flop. current continues until the feedback from the current
This sets the PHA output, which sets the DRVH output transformer T1, reaches the desired level. When this
of the MOSFET driver U7, which turns on MOSFET Q1. happens, on-chip voltage comparator C2 resets the
While Q1 remains on, L1 is electrically connected PHA flip-flop, which terminates the PWM pulse, and
between +12V and the output. The voltage difference pulls the PHA output low. The DRVH output of U7 then
between the 12V input and the SMPS output causes goes low, and Q1 begins to turns off. See Figure 3 for
the current in L1 to ramp up, with the inductor current a diagram of the waveforms.
flowing from the +12V input, through the inductor L1, to

FIGURE 3: PULSE AND MOSFET TIMING

Charge Discharge

IL
Inductor
Current

PHA

DRVH

on
Q1
off

12V
SW

-.7V -.7V

DRVL

on
Q2
off
Time

© 2007 Microchip Technology Inc. DS01086A-page 3

AN1086
Even though the gate of Q1 has been pulled low and inductor passes the right amount of current into the
Q1 is turning off, the current flowing through L1 does capacitors, regardless of the load. If the inductor cur-
not stop. In fact, the current continues, driving the rent is too high, and the system is lightly loaded, the
MOSFET side of L1 low in an attempt to keep the cur- resulting output voltage could jump, or the output could
rent flowing. This eventually drives the MOSFET side have a large AC ripple. The task of regulating the
of L1 low enough to forward bias D1. amount of current in each charge/discharge cycle is the
The sense input SW of U7 monitors the voltage on the function of the voltage feedback loop.
MOSFET side of L1, waiting for the voltage at the
inductor to drop from +12V to below -0.7V ground.
When this occurs, the logic inside U7 turns on Q2 by
pulling its DRVL output high. This shorts out D1, caus-
ing the inductor current to flow from ground, through
Q1, through L1, and finally to the output.
So, in general, the current feedback path of this design
is very similar to the current feedback path of a discrete
switching power supply design. However, there are a
few notable differences:
1. The frequency of the PWM generated by the
PIC16F785 is programmable using the phase
counter and prescaler within the analog PWM
peripheral.
2. The phase delay between the PWM pulse out-
puts PHA and PHB programmable in the
PIC16F785.
3. The PWM module in the PIC16F785 can gener-
ate up to 2 channels with on-chip resources, and
3 channels using an external PWM generator
such as the MCP1630.
4. The analog PWM module in the PIC16F785 can
accept feedback from either single comparator,
or both, for either PWM channel. This means;
a) Each comparator can be dedicated to a
separate channel.
b) One comparator can drive both channels.
c) Both comparators can drive one, or both,
channels.
5. The PIC16F785 can shutdown the PWM
generator in software.
So, in addition to being a smaller solution, the
PIC16F785 is also significantly more flexible.

VOLTAGE FEEDBACK
The desired current flow in L1, from the previous sec-
tion, is set by the output of the error amplifier/loop filter
in the voltage feedback loop. The voltage feedback
loop consists of the all the elements in the current feed-
back loop, plus the output capacitors C1 and C9, the
error amplifier/loop filter (using the on-chip opa2 in the
PIC16F785), and a voltage reference generated by the
timer-based CCP PWM function in the microcontroller
(see Figure 4). The current flow in L1 is designed to be
continuous; it supplies all of the output current during
the cycle, with the output capacitors storing the extra
current from the high side of the charge cycle, for dis-
charge during the low side. The challenge in a continu-
ous current configuration is to make sure that the

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 AN1086
FIGURE 4: VOLTAGE FEEDBACK
C12

R4 C6 R19

R5
- OP2-
OP2
R6
+ OP2+ CCP
OPA2
C19

T1 +12V

D2
Voltage
Comparator
-
C2
+ C2IN+
BST
Phase
Counter Q1
PWM
DRVH

C8 L1
PHA IN SW Output

Q2 C1 C9
DRVL
U3 PIC16F785

U4

The feedback process starts with the error amplifier

and loop filter sampling the output voltage. The error
amplifier portion of the circuit (OPA2) compares the
output voltage to its reference voltage (C19), generat-
ing an error voltage. The error voltage is then passed to
the voltage comparator (C2) in the current loop, which
charges the inductor current up to the level of the error
amplifier output. This keeps the current level in the
inductor sufficient to maintain the charge in the output
capacitors, and supply the necessary output current
without overcharging the output capacitors and
creating an output over voltage condition.
There are two hidden challenges in a continuous cur-
rent design. One, the negative feedback of the voltage
loop, and the phase delay of the various components,
can create a condition in which the loop can go unsta-
ble and oscillate. Two, using a simple subtraction in the
error amplifier will result is a constant error between the
reference voltage and the feedback voltage.
It is the loop filter that acts to counteract the potential
instability. Two poles and a zero in the loop filter’s trans-
fer function introduce both gain and phase changes in
the feedback, such that the loop never has sufficient
gain to oscillate when the phase delay is a multiple of
360 degrees (see Figure 5).

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AN1086
FIGURE 5: FEEDBACK GAIN AND PHASE

Loop Filter

MOSFET + LC

Combined
Loop

Loop Filter

MOSFET + LC

Combined
Loop

180°

A secondary effect of the poles in the loop filter is their

integration of any constant errors. This results in an off- 1. The analog multiplexers on the inputs to the
set of the error amplifier output such that any constant comparators allow the software to switch
error is driven to zero. between two or more loop filters, giving the sys-
The location of the pole and zeros in the loop filter/error tem the ability to change its response
amplifier are determined by the resistors and capaci- characteristics.
tors in the feedback path of the op amp used as the 2. The analog multiplexers on the inputs to the
error amplifier/loop filter. comparators, and the systems ability to recon-
As you might expect, the choice of the poles and zeros figure which comparators are used for the PWM
in the loop filter is critical to maintaining the stability of feedback, allow the system to switch between a
the feedback loop. The poles and zero in the loop filter fully proportional feedback for continuous induc-
of this design have been chosen to provide a gain mar- tor current, and a hysteretic feedback for discon-
gin (amplitude) of greater than 30dB, and a phase mar- tinuous inductor current on the fly (see
gin of over 90 degrees. Figure 6).
So, the operation of the voltage feedback system is
nearly identical to any purely analog SMPS design. In
fact, the use of the CCP base PWM to generate a ref-
erence voltage for the error amplifier is commonly used
in intelligent SMPS designs. However, there are also
some important features that make the single chip
solution with the PIC16F785 significantly more flexible:

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 AN1086
FIGURE 6: CONTINUOUS/DISCONTINUOUS SWITCHING
PWM

PWM to
PHA
MOSFET Driver

C12
- From
T1 R4 C6 R19
C2
+ From
Voltage VOUT
R5
Comparator 1 -
OPA2
+ CCP
CVREF
0

MUX1
S1
-
C1 Continuous MUX = 1, S1 = Open
Voltage + Discontinuous MUX1 = 0, S1 = Closed
Comparator PIC16F785
3. The two phase capability of the analog feedback
PWM module allows the system to switch
between a single, two, or three phase PWM load
share system on the basis of load current, allow-
ing the use of multiple smaller power chains in
the place of one larger chain (see Figure 7 and
8).

© 2007 Microchip Technology Inc. DS01086A-page 7

AN1086
FIGURE 7: MULTIPHASE CONVERTER

+12V

T1
-
C2
+

DH L1
SW VOUT
PHA IN DL

DH L2
SYNC SW
PHB IN DL

MCP1630

OSC DH L3
CS SW
DL
VXT IN

-
OPA1
+

CCP

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 AN1086
FIGURE 8: MULTIPHASE TIMING DIAGRAMS

PHA

IL1

VOUT Time
Single Phase

PHA

IL1

PHB

IL2

VOUT Time
Two Phase

PHA

IL1

PHB

IL2

VXT

IL3

VOUT Time
Three Phase

© 2007 Microchip Technology Inc. DS01086A-page 9

AN1086
4. The PIC16F785 is also available as the the desired value. This means that the design will need
PIC16HV785 with an on-chip 5V shunt regulator some form of DAC to generate the digitally control
for powering the microcontroller and associated reference voltage.
circuitry. While DACs are available, their cost can be a problem
So, the power conversion section of the power supply in cost sensitive applications. Fortunately, there is an
design is comprised of the two feedback loops, the option; the CCP module within the microcontroller can
inner loop regulating inductor current, and the outer be configured to produce a timer-based PWM signal on
loop regulating the voltage. RC5/CCP1. This signal is then averaged out to a DC
level using a low pass RC filter composed of R6 and
MICROCONTROLLER SECTION C19. The resulting reference voltage is then related to
the supply voltage of the microcontroller (5 VDC) by the
In the beginning of this application note, it was stated duty cycle of the PWM. Also, given that the PWM has
that the purpose of the design was to provide a micro- a 10-bit resolution, this means that the reference volt-
controller control over the operation of the SMPS age can be controlled to within 0.1%, giving the
design, and a means to monitor its operation. So, what microcontroller a more than adequate level of control.
does the microcontroller control and what does it
Because the reference voltage PWM is based on the
monitor? (see Appendix A: “2.0V to 4.5V 10A
timers, internal to the microcontroller, its maximum fre-
Switcher Schematic”).
quency will be 1/1024th of the microcontroller’s
Let’s start with monitoring. Two obvious points to mon- instruction rate for 10 bits of resolution. As we will see
itor are the input and output voltage. The input voltage later, the instruction rate of the microcontroller is
will tell the microcontroller when the SMPS has suffi- 1 MIPS (million instructions per second). So, the refer-
cient voltage to operate properly, and the output volt- ence voltage PWM would have a frequency of 1 kHz.
age will tell the microcontroller when the SMPS is To average out the PWM signal to less than 1 LSb, it
supplying the appropriate voltage. will be necessary to place the corner frequency of the
So, the microcontroller will have to measure both volt- low pass filter at 1/1024th of the PWM frequency, or
ages. Unfortunately, ADC peripherals do not have large roughly 1 Hz. This would mean that the maximum rate
common mode input voltage ranges, so if the voltage to at which the power supply may ramp up its output will
be measured is greater than VDD, it will be necessary be roughly 1 second.
to scale the voltage down using a resistor divider. However, if the resolution of the reference voltage
This is in fact, the function of R17 and R18. They scale PWM is limited to 8 bits, resulting in control between
the input voltage down from 9-15 VDC, down to 1.17V- 0.5% and 1%, then the frequency of the PWM signal is
1.95V for conversion by the ADC. This will still provide 4 times higher. The corner frequency of the low pass
the ADC with a 38 mV resolution in measuring the input RC filter is correspondingly higher as well. So, dropping
voltage. The output of the SMPS is connected directly the resolution to 8 bits, moves the corner frequency to
to RC3/AN7 for conversion by the ADC. 16 Hz, giving the design the ability to change the output
in 62.5 ms. For the purposes of our discussion here,
Note: The scaling value was chosen assuming a this will be considered sufficient.
maximum supply voltage surge of 35V and
an ADC reference of 5V. Note: If a 10-bit resolution is required, or the
speed of the output must be increased, the
Because the output voltage is limited by the 50% duty use of a simple 2-pole op amp-based low
cycle (see the maximum duty cycle note), it is not nec- pass filter in series with the existing RC
essary to scale the output voltage measurement input low pass will speed up the system. A sin-
to the ADC. gle pole RC low pass reduced the ripple
U4 is a current mirror which generates an output volt- voltage in its output by 10:1 for every
age proportional to the output current. It is used to decade of frequency between the pulse
scale the output current for the ADC input on pin RA4. frequency and the filter corner frequency.
The only other system value that needs to be moni- Using a cascaded 3-pole filter reduces the
tored in the design is the ambient temperature of the ripple voltage at its output by 1000:1 for
system. This is accomplished by U1, a TC1047A ana- every decade of frequency. This means a
log linearized thermistor. Its output is monitored by the 3-pole filter would allow the use of a 10-bit
ADC through the analog input RA2/AN2. PWM, and still allow changes at a rate of
100 Hz or 10 ms.
Control of the SMPS design is via the reference voltage
used by the error amplifier in the voltage feedback loop.
By generating a voltage at the desired output voltage,
the voltage feedback loop will drive the SMPS output to

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 AN1086
Now that the microcontroller has access to the internal
signals of the power supply, and a means of control
Note: For systems that must switch faster than
over the output, the only remaining section to design is
10 ms, a DAC should be used. Several dif-
the software.
ferent varieties are available in various
resolutions and interfaces. To connect an
I2C™ DAC to the microcontroller, two SOFTWARE THEORY OF OPERATION
unused I/O pins can be used to create a
The basic software construct that will be used is a
software-based I2C peripheral.
simple infinite loop as shown in Figure 9.
The microcontroller also supplies the clock signal for
the PHA PWM, a 1 MHz clock which sets the frequency FIGURE 9: SOFTWARE FLOWCHART
and maximum duty cycle of the PWM pulses in the
SMPS. This clock signal is generated by the internal Reset
oscillator in the microcontroller, and routed internally to
the phase counter in the analog PWM module.
One final connection to the SMPS portion of the design
is required, the OD control pin on U4. When this input INIT
is pulled low, the outputs of the MOSFET driver are dis-
abled, and both MOSFETs are turned off. This has the
effect of isolating the output of the SMPS from +12V
and ground. For this design, the OD control will be used GET_INPUTS
to turn off the output, without creating a short circuit for
the charge in the output capacitors to ground through
the L1 and Q2.
DECISIONS
There are three other connections to the microcontrol-
ler that will be required for the design; an In-Circuit
Serial Programming™ port (ICSP™) through pins RA0,
RA1, and RA3. The control inputs SHUTDOWN, DO_OUTPUTS
VSEL0, and VSEL1 through the RA3, RB6 and RB7
pins. And, the Status output POWERGOOD, on RA5.
For the design presented here, the following conven-
tion will be applied to these interface connections; TIMER

• ICSP is only used for initial programming and the

pins are left open or have alternate uses under
normal operation. First in the flowchart is the INIT section, which contains
• The SHUTDOWN pin will disable the output of the all of the initial setting for the variables and peripherals
SMPS when pulled low. that will be used by the system. The next section,
• The POWERGOOD pin will indicate the correct located within the main loop, is the GET_INPUTS
output voltage is present when high, at all other block, which is charged with measuring the various sig-
times the output will be low indicating a fault con- nals monitored by the microcontroller, and gathering
dition or a command in the process of executing. the various communications and control inputs. The
• The VSEL0 and VSEL1 pins form a 2-bit binary third section, DECISIONS, makes decisions based on
number selecting the desired output voltage. the inputs to the system. The results from the DECI-
(VSEL0 is the LSb) SIONS block are then passed to the DO_OUTPUTS
section which makes the appropriate adjustments to
With the last of the connections to the microcontroller,
the controls, whether they are controls over the SMPS
the design of the hardware for the system is complete.
operation or communication outputs. The final section
It should be noted, that the additional circuitry for the
is the TIMER section which regulates the timing of the
microcontroller is limited to just the microcontroller itself
infinite loop. Here the rate at which inputs are gathered,
and a few interface connectors and resistors, while the
decisions are made, and controls are adjusted, is reg-
basic design of the SMPS section of the design is a tra-
ulated to provide predictable sampling and control rate
ditional analog current mode design. The only micro-
changes.
controller connections are the various points being
monitored by the microcontroller, the PWM signal pro-
vided by the microcontroller, and the reference voltage.

© 2007 Microchip Technology Inc. DS01086A-page 11

AN1086
The CCP module is configured for a single PWM output
by loading the CCP1CON register.
Note: For simplicity and ease of reading, the var-
ious sections of the software presented Note 1: Loading the CCP1CON register also sets
here are written in C. The routines can, of the 2 Least Significant bits of the PWM
course, be written in assembly, with poten- duty cycle. The 6 MSbs of the duty cycle
tially faster execution, however, this exer- are then set by loading the CCPR1L reg-
cise is left to the reader, as assembly ister. The final two PWM mode control
language versions of the routines would registers, PWM1CON and ECCPAS, are
not add clarity to the discussion. left with their default settings. This
disables both the automatic shutdown
INIT ROUTINE feature, and the H-bridge output dead-
band control.
The first section to explore is the INIT section. As men-
2: One possible addition to the system
tioned above, this section configures the various
would be a fast shutdown capability in the
peripherals for the system and presets any system
event of an output over voltage condition.
variables.
To implement this feature, one of the two
The first peripherals to be configured are the TRIS reg- voltage comparators would have to be
isters which control the direction of the Input/Output configured to monitor the output voltage.
pins for the microcontroller. The ports are also preset to When it exceeded its limit, the change in
their initial states. Next, all analog inputs are configured the comparator output would trigger the
by setting the ANSEL0 and ANSEL1 registers. This automatic shutdown and disable the
turns off the digital input to prevent shoot-through cur- reference voltage PWM.
rent in the input buffers when analog voltages are
The next peripheral to configure is the ADC. Loading
present.
the ADCON0 and ADCON1 registers sets five aspects
The next peripherals to configure are Timer2 and the of the ADC’s operation.
CCP module, which generate the reference voltage
1. Turns on the ADC.
PWM signal. While the CCP module controls the duty
cycle of the PWM output, and must be configured for 2. Sets the ADC clock frequency.
PWM mode, Timer2 is the time base of the PWM and 3. Selects the initial input channel (VIN).
must be running to for the CCP to generate and output 4. Selects VDD as the ADC reference voltage.
pulse. 5. Configures the ADC for a right justified output
Timer2 is enabled, and both the prescaler and (bit 0-7 in ADRESL, bits 8 and 9 in ADRESH).
postscaler are disabled by loading the T2CON register. Once configured, the ADC is now ready to perform its
The period of the PWM pulse is then set by loading a first conversion on the input voltage VIN. For conve-
hex 3F into the PR2 period register. This forces Timer2 nience, this first conversion is started in the INIT rou-
to roll over to 0 from 3F. When the resulting 6-bit timer tine. The value will be read and stored in the first call to
is combined with the internal 2-bit FOSC/4 counter, the the GET_INPUTS routine.
PWM output frequency will be 500 kHz/256 or 1950 Hz.
After the ADC, the op amps and comparators are
enabled and configured. For this design op amp 2 and
comparator 2 are used, with op amp 1 and comparator
1 disabled.
Note: The resources available on-chip are suffi-
cient to build two SMPS voltage and cur-
rent feedback loops, however, for this
design, only one SMPS design is imple-
mented.
Once the CCP is configured and generating a refer-
ence voltage, and the op amp and comparator used for
the loop filter and current feedback are enabled, the
analog PWM can be configured. This is done using the
PWMCON, PWMCLK, and PWMPH registers.

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 AN1086
For this design, a single output channel is enabled on 3. If the state variable is incremented each time the
PHA, using comparator C2 for feedback, with a phase statemachine is called, the routine will automat-
offset of 0, and a pulse frequency of 500 kHz. ically poll through all of the system inputs.
Note: The phase offset is relative to the SYNC 4. By manipulating the state variable, the order in
output from the peripheral. The SYNC out- which the inputs are sampled, can be altered
put/input is used to synchronize the pulse and some analog inputs can be skipped as well.
generation of multiple analog PWM mod- The resulting routine is displayed in Example 1.
ules, or to synchronize an external PWM Each time the routine is called within the infinite loop,
such as the MCP1630. The offset capabil- this statemachine will retrieve the result of the last con-
ity is used to offset the start of a given version, configure the ADC for the next channel, and
phase’s pulse relative to other pulses then start the conversion. The VSEL and SHUTDOWN
being generated by the on-chip PWM, or inputs are also polled each time the statemachine is
external PWM generators synchronized to called.
the internal PWM peripheral.
The final peripheral to configure is Timer0. It is used as EXAMPLE 1: DATA INDEXED STATE
the time base for the TIMER section of the software. MACHINE
For the purposes of this design, the basic timing tick void GetADC()
was chosen to be 1 ms. So, a prescaler value of 4:1, {
combined with the 8-bit Timer, and a 1 MIPS instruction char channelSelect[4] = {0x89, 0x9D,
rate will result in approximately a 1 ms roll over of 0x8D, 0xA5};
Timer0. ADCON0 = channelSelect[state1];
DelayUs(20);
The last activity in the INIT routine is the preset of any GODONE = 1;
variables used by the system. Because the routines while (GODONE == 1);
that use these variables have yet to be discussed, their monitor[state1] = ADRESL + (ADRESH*256);
preset values will be skipped over for now, and identi- state1++;
fied latter when the routine that uses the variables is if (state1 > 3) state1 = 0;
discussed. }

GET_INPUTS Recall that the INIT routine begins this process by start-
ing a conversion on the first input to be measured. That
The GET_INPUTS routine is charged with routinely means that the first time the statemachine is called,
sampling the various analog voltages in the system. To there will already be a value waiting for the
do this efficiently, a data indexed statemachine is used. statemachine to retrieve. This pre-conversion, and the
There are two standard forms of a statemachine, the clearing of the data array, presets all the variables to
execution indexed and the data indexed. In the more safe values so the DECISIONS routine will function
recognizable execution indexed form, a state variable properly. This prevents random data in the array from
is used to determine which, of several possible, blocks causing undesirable decisions and erroneous outputs.
of code is to be executed when the statemachine is Note: The INIT routine will also preset the state
called (see Figure 10). A data indexed statemachine, variable for the GET_INPUTS routine, so it
on the other hand, executes the same block of code will know where to place the data from the
each time it is called. It is the data acted upon by the first conversion.
statemachine that is indexed by the state variable (see
Figure 11).
This has several advantages for a routine such as the
GET_INPUTS routine:
1. The basic routine to control the ADC is the same
for all of the analog inputs; only the channel
select bits are changed. Using a data indexed
statemachine saves redundant coding for each
channel.
2. If the results from the ADC are stored in an
array, the state variable can be used to automat-
ically access the correct location for storing the
data, retrieving the next input configuration
value, and accessing alarm limits for the
individual analog inputs.

© 2007 Microchip Technology Inc. DS01086A-page 13

AN1086
FIGURE 10: EXECUTED INDEXED STATE ing an output. For the other states needed, we start by
MACHINE examining the deterministic function requirements for
Start the design.

DETERMINISTIC FUNCTIONS:
• Delayed start-up for sequencing
STATE = 1 Block 1
• Soft start
• Under voltage lockout
• Slew rate limiting on all VOUT changes
• Hysteretic over temp error
STATE = 2 Block 2 • Shorted output fault detection with limited restart
• Over current alarm
• Four programmable VOUT presets
The Delayed start-up indicates that there is a DELAY
state needed between the SHUTDN and ACTIVE
STATE = 3 Block 3 states.
Soft start function indicates that there will also be a
RAMP state in which the output will be ramp up from 0
to the final output voltage.
Under voltage lockout does not seem to indicate an
STATE = 4 Block 4 additional state, rather it is just a condition that would
force the transition from ACTIVE to SHUTDN, or
SHUTDN to DELAY.
Default Slew rate limiting on all VOUT changes indicates that
are additional states for ramping the output up and
down is required. However, if a single RAMP state is
Return created to ramp up or down, a separate state will not be
needed.

FIGURE 11: DATA INDEXED STATE The hysteretic over temp fault requires that the system
declare a error at one temperature, but then clear the
MACHINE
error at lower temperature. This will require an addi-
Start tional active state in which there is a error, but the
output is still active. Let’s call this the ERROR state.
Block A shorted output condition is an immediate fault, and a
Data[State] simple jump to the SHUTDN state, followed by a
restart, should be sufficient to handle the fault. How-
ever, if the fault persists, it may be necessary to have a
Return “Sticky” fault condition that requires intervention by the
communications function to clear. So, for this design, it
seems advisable to create a Fault state which can be
DECISIONS entered in response to a persistent fault and requires
The next section of the firmware design is the DECI- user intervention to move to the SHUTDN state.
SIONS section. In this section of the firmware, the data The over current alarm is similar to the over tempera-
gathered in the GET_INPUTS section is analyzed and ture alarm, however, it doesn’t require hysteresis, so it
the appropriate actions are taken. To perform this can be handled as simple comparison. If an over
function, an execution indexed statemachine is used. current condition exists, and if the power supply has
To design the required statemachine, it is first neces- completed the start-up delay and soft start, then turn on
sary to determine the various states in which the sys- the alarm LED. When and if the condition clears, then
tem can exist, and the reasons for changes in these turn off the LED. So, because the condition does not
states. Two obvious states are: SHUTDN, in which the require an additional historical information to operate, a
system is powered but is not producing an output, and separate state is not required.
ACTIVE, in which the system is powered and produc-

DS01086A-page 14 © 2007 Microchip Technology Inc.

 AN1086
The four programmable VOUT presets simply require One final step in the design of the DECISIONS state-
the system to recognize the new output voltage machine is to add a DEFAULT state to the SWITCH
request, and ramp up or down to the new voltage. So, statement of the statemachine. This state will catch any
like the under voltage lockout function, this is just a state variable value which does not correspond to a
condition forcing a move to the RAMP state. legitimate state. While this is unlikely to occur during
So, if we gather up the various states for the system, normal operation, it is possible that the state variable
we have: could become corrupted due to noise for EMI or RFI.
Therefore, including the catch-all state is a prudent
SHUTDN System is inactive safety measure.
DELAY System is delaying to start
RAMP Output is ramping up or down
ACTIVE Output is stable and active
ERROR Output is active with an error
FAULT Output is inactive pending release by
the user
The next step is to identify the reasons for changing
from one state to another. Again, from the deterministic
functions list, and our understanding of the designs
operation, we get the list of state transitions in Table 1.
TABLE 1: STATES
Current Next
Reason for Change
State State
SHUTDN DELAY SHUTDOWN = 1 and VIN > lockout
DELAY RAMP Delay complete
RAMP ACTIVE VOUT = Target
ACTIVE RAMP VOUT!= Target
(any) SHUTDN SHUTDOWN = 0 Or VIN < lockout
ACTIVE ERROR Temperature > highTempLimit
ACTIVE FAULT VOUT < ½ Target and Retry_count = 0
ACTIVE SHUTDN VOUT < ½ Target and Retry_count > 0
ERROR ACTIVE Temperature < lowTempLimit
ERROR FAULT VOUT < ½ Target and Retry_count = 0
ERROR SHUTDN VOUT < ½ Target and Retry_count > 0
Often, using a table for understanding the various
states and their transition conditions can be confusing.
Another method is to graphically plot out the state tran-
sitions as a series of circles and arrows. The circles
represent the various states, and the arrows represent
the state transitions. The reasons for the transitions are
then written along the arrows. Figure 12 shows an
example of such a plot based on the states and state
transitions of the DECISIONS state machine.
Now that the statemachine is sufficiently defined, we
can create the SWITCH statement and build in the
state change conditional statements. Example 2 shows
the resulting statemachine routine, plus the specific
actions to be taken in each state. We can also go back
to the INIT routine and add the necessary statement to
preset the state machine to the SHUTDN state at start-
up.

© 2007 Microchip Technology Inc. DS01086A-page 15

AN1086
FIGURE 12: STATE TRANSITION DIAGRAM

SHUTDN

En
ab
le
an
dL
ow
En

su
ly

abl

pp
pp

ea

ly
su
ow

nd
rL

Low
o
le

sup
ab
En

ply
FAULT DELAY
Shorted Output and Retry = 0

Shorted O

Delay Complete
Ena
ply
upply

ble
r Lowsup
utput and

and
Shorted Output and Retry > 0
Lows

Lo ws
Enable o
le or

Retry > 0

upply
Enable or Lowsupply
E nab

High Temp VOUT = Target RAMP

ERROR

Low Temp

ACTIVE
VOUT < > Target

High Temp DEFAULT

VOUT = Target

DS01086A-page 16 © 2007 Microchip Technology Inc.

 AN1086
EXAMPLE 2: MAIN EXECUTION INDEXED STATEMACHINE
void main()
{
Init();
while(1) {
GetADC();
switch (state2) {
case SHUTDN: POWERGOOD = 0;
retry = maxRetry;
FAULTLED = 1;
DutyCycleOut(0);
mDisableDrive
dutyCycle = 0;
waitCount = 100;
if ((ENABLE) && (monitor[3] > lowSupply))
state2 = DELAY;
break;

case DELAY: FAULT = 0;

waitCount--;
if (waitCount == 0)
state2 = RAMP;
break;

case RAMP: dutyCycle = dutyCycle + 1;

DutyCycleOut(dutyCycle);
mEnableDrive
if (dutyCycle >= GetVoltageSelect())
state2 = ACTIVE;
break;

case ACTIVE: POWERGOOD = 1;

if ((!ENABLE) || (monitor[3] < lowSupply))
state2 = IDLE;
if (monitor[2] > hiCurrent)
FAULTLED = 1;
else
FAULTLED = 0;
if (monitor[0] > hiTempLimit
state2 = ERROR;
if ((monitor[1] < (dutyCycle >> 1)) && (retry == 0))
state2 = FAULT
if ((monitor[1] < (dutyCycle >> 1)) && (retry-- > 0))
state2 = SHUTDN;
break;
case FAULT:
POWERGOOD = 0;
FAULTLED = 1;
if ((!ENABLE) & (monitor[3] < lowSupply))
state2 = SHUTDN;
break;
case ERROR:
POWERGOOD = 1;
FAULTLED = 1;
if (monitor[0] < lowTempLimit)
state2 = ACTIVE;
if ((!ENABLE) & (monitor[3] < lowSupply))
state2 = SHUTDN;
break;
default: state2 = SHUTDN;
break;
}
DelayMs(10);

© 2007 Microchip Technology Inc. DS01086A-page 17

AN1086
The actions taken in the DEFAULT state include verify- affecting the other bits. The remaining 6 MSbs can then
ing the output voltage, and checking for other potential be loaded into the CCPR1L register. Example 3 shows
errors in the system operation. If no errors are found, how this is accomplished in the DO_OUTPUTS routine.
and the system is generating the requested output volt-
age, the statemachine can return to the active state. EXAMPLE 3:
If not, then the power supply should go to the Fault void DutyCycleOut(unsigned int dc)
state and wait for instructions from the user. {
CCP1CON &= 0xCF;
There are a couple of interesting points to note about CCP1CON |= (dc & 0x03) * 16;
the DECISIONS routine: CCPR1L = dc / 4;
1. The state transition that checks for a low on the }
ENABLE input, or low input voltage is repeated
in all states but SHUTDN. To save space, this TIMER
statement could be moved before the SWITCH
statement, requiring only one instance of the The TIMER function is designed to synchronize the
test. execution of the infinite loop to a hardware counter
within the microcontroller. Doing this locks the start of
Note: The test would also override any other
the loop to a fixed time increment, and allows the loop
condition that could change STATE.
to manage the timing of it samples and control outputs.
2. The Fault state is “Sticky”, it requires the user to If the TIMER function was not present, the rate at which
pull the ENABLE input low to exit. This is the the output changed would be a function of what other
user intervention mentioned above. activities the microcontroller was performing at the
3. The test for a shorted output in the ACTIVE and time. This would make any ramping changes unpredict-
ERROR states directs the statemachine to able and nonlinear. So, locking the start time of the loop
either the SHUTDN state for restart, or the Fault to a fixed standard is the only way to maintain proper
state for hold based on the value in Retry_count. timing for the system.
This implements the limited number of retry on
The TIMER routine uses Timer0 as its time base.
faults.
Recall that in the INIT routine, Timer0 was configured
4. The Retry_count variable is only reloaded in the to roll over every 1 ms, so the system timing (tick) will
SHUTDN state when the ENABLE input is low. be in increments of 1 ms. The TIMER routine is just a
This allows a user shutdown to reset the function that holds up execution until the next time
counter, but prevents a restart from resetting the Timer0 rolls over. It then clears the interrupt flag indicat-
counter. ing the roll over and returns to the infinite loop so the
5. The DEFAULT state does check the status of the next pass can commence.
system and jumps to the appropriate state to
restart. Note: Because the system tick is 1 ms, the max-
imum start-up time for a 0 to maximum
6. Target[Vselect] is an array of preset output volt-
output voltage ramp is 256 ms or approxi-
ages, indexed by the two voltage select inputs.
mately ¼ of a second. If the ramp needs to
If a select pin changes, the value returned is the
be faster, then either the Timer0 configura-
new preset output.
tion should be changed to configure the
7. The order in which state transitions is tested is prescaler for a different prescaler ratio, or
important, the earlier tests have lower priority the ramp state in the DECISIONS state-
than the latter tests. So, the last condition tested machine should be modified to increment
has the ability to override the first condition the reference voltage duty cycle by a
tested. This simplifies the test statements by increment greater than 1.
removing some of the conditions that might
override a change.
The final result is a relatively simple system which
CONCLUSIONS
allows for the complex interaction of multiple conditions The design presented here shows an alternative sin-
and controls. gle-chip approach to adding intelligence to SMPS
designs. The basic design is really unchanged. There
DO_OUTPUTS are current and voltage feedback loops, a counter-
based PWM is used to generate the reference voltage
This section of the code consists of functions to set the to the voltage loop, and the microcontroller uses the
reference voltage duty cycle. reference voltage to modify the operation of the system
The function to set the reference voltage duty cycle has in response to conditions sensed through the ADC.
one complication, in that it has to set the two LSbs of
the duty cycle in the CCP1CON register, without

DS01086A-page 18 © 2007 Microchip Technology Inc.

 AN1086
While the design presented here is rudimentary, it does
show some of the advantages of having the analog
components in the SMPS feedback paths within the
microcontroller, and more importantly, under the
microcontroller’s control:
1. Giving the microcontroller access to the multi-
plexers on the comparator inputs gives the con-
trolling firmware the ability to reconfigure the
feedback pathways on the fly.
2. Control over the PWM generator allows the firm-
ware to reconfigure pulse frequency, phase, and
number of phases on the fly.
3. The on-chip peripheral reduces the parts count
for the design, reducing stocking and sourcing
problems.
4. The reprogramability of the microcontroller, and
its control over the various peripherals, allows
the firmware to configure the product through
firmware. Thus allowing production to customize
the system at the end of the line.
All in all, using a microcontroller to implement a SMPS
design allows for flexibility and greater capability. Using
a microcontroller with the necessary analog functions
on-chip, extends the flexibility and capability, while sim-
plifying the layout of the design.

MEMORY USAGE
The memory usage for the control program is as
follows:
Program memory 466 words out of 2K words
Data memory 30 bytes out of 128 bytes
EEPROM 8 bytes out of 256 bytes

Note: All code compiled with version 9.50 of

HI-TECH’s PICC.

Note: No compiler optimization was used.

© 2007 Microchip Technology Inc. DS01086A-page 19

AN1086
APPENDIX A: 2.0V TO 4.5V 10A SWITCHER SCHEMATIC

DS01086A-page 20 © 2007 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
ensure that your application meets with your specifications.
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
MICROCHIP MAKES NO REPRESENTATIONS OR
SmartShunt are registered trademarks of Microchip
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Technology Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are
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conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
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Endurance, UNI/O, WiperLock and ZENA are trademarks of
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All other trademarks mentioned herein are property of their
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© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

© 2007 Microchip Technology Inc. DS01086A-page 21

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