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In-Circuit Serial Programming™

(ICSP™) Guide

 2000 Microchip Technology Inc. May 2000 DS30277C

All rights reserved. Copyright  2000, Microchip Technology The Microchip name and logo, PIC, PICmicro, PRO MATE, PICSTART,
Incorporated, USA. Information contained in this publication regarding MPLAB, and The Embedded Control Solutions Company are registered
device applications and the like is intended through suggestion only and trademarks of Microchip Technology Inc. in the U.S.A. and other coun-
may be superseded by updates. No representation or warranty is given tries.
and no liability is assumed by Microchip Technology Incorporated with In-Circuit Serial Programming and ICSP are trademarks and SQTP is a
respect to the accuracy or use of such information, or infringement of service mark of Microchip Technology Inc.
patents arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except All other trademarks mentioned herein are property of their respective
with express written approval by Microchip. No licenses are conveyed, companies.
implicitly or otherwise, under any intellectual property rights.”

DS30277C - page ii  2000 Microchip Technology Inc.

Table of Contents
PAGE
SECTION 1 INTRODUCTION
In-Circuit Serial Programming™ (ICSP™) Guide ............................................................................................. 1-1
SECTION 2 TECHNICAL BRIEFS
How to Implement ICSP™ Using PIC12C5XX OTP MCUs ............................................................................. 2-1
How to Implement ICSP™ Using PIC16CXXX OTP MCUs ............................................................................. 2-9
How to Implement ICSP™ Using PIC17CXXX OTP MCUs ........................................................................... 2-15
How to Implement ICSP™ Using PIC16F8X FLASH MCUs .......................................................................... 2-21
SECTION 3 PROGRAMMING SPECIFICATIONS
In-Circuit Serial Programming for PIC12C5XX OTP MCUs ............................................................................. 3-1
In-Circuit Serial Programming for PIC12C67X and PIC12CE67X OTP MCUs .............................................. 3-15
In-Circuit Serial Programming for PIC14000 OTP MCUs ............................................................................... 3-27
In-Circuit Serial Programming for PIC16C55X OTP MCUs ............................................................................ 3-39
In-Circuit Serial Programming for PIC16C6XX/7XX/9XX OTP MCUs ............................................................ 3-51
In-Circuit Serial Programming for PIC17C7XX OTP MCUs ........................................................................... 3-71
In-Circuit Serial Programming for PIC18CXXX OTP MCUs ........................................................................... 3-97
In-Circuit Serial Programming for PIC16F62X FLASH MCUs ...................................................................... 3-135
In-Circuit Serial Programming for PIC16F8X FLASH MCUs ........................................................................ 3-149
In-Circuit Serial Programming for PIC16F8XX FLASH MCUs ..................................................................... 3-165
SECTION 4 APPLICATION NOTES
In-Circuit Serial Programming™ (ICSP™) of Calibration Parameters Using a PICmicro® Microcontroller ...... 4-1

 2000 Microchip Technology Inc. DS30277C-page iii

DS30277C-page iv © 2000 Microchip Technology Inc.
SECTION 1
INTRODUCTION

IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) GUIDE ................................................................... 1-1

 2000 Microchip Technology Inc. DS30277C-page 1-i

DS30277C-page 1-ii  2000 Microchip Technology Inc.
INTRODUCTION
In-Circuit Serial Programming™ (ICSP™) Guide
WHAT IS IN-CIRCUIT SERIAL WHAT CAN I DO WITH IN-CIRCUIT
PROGRAMMING (ICSP)? SERIAL PROGRAMMING?
In-System Programming (ISP) is a technique where a ICSP is truly an enabling technology that can be used
programmable device is programmed after the device in a variety of ways including:
is placed in a circuit board. • Reduce Cost of Field Upgrades
In-Circuit Serial Programming (ICSP) is an enhanced The cost of upgrading a system’s code can be
ISP technique implemented in Microchip’s PICmicro® dramatically reduced using ICSP. With very little
One-Time-Programmable (OTP) and FLASH RISC effort and planning, a PICmicro OTP- or FLASH-
microcontrollers (MCU). Use of only two I/O pins to based system can be designed to have code updates
serially input and output data makes ICSP easy to use in the field.
and less intrusive on the normal operation of the MCU.
For PICmicro FLASH devices, the entire code
Because they can accommodate rapid code changes memory can be rewritten with new code. In PICmicro
in a manufacturing line, PICmicro OTP and FLASH OTP devices, new code segments and parameter
MCUs offer tremendous flexibility, reduce development tables can be easily added in program memory areas
time and manufacturing cycles, and improve time to left blank for update purpose. Often, only a portion of
market. the code (such as a key algorithm) requires update.
In-Circuit Serial Programming enhances the flexibility • Reduce Time to Market
of the PICmicro even further.
In instances where one product is programmed with
This In-Circuit Serial Programming Guide is designed different customer codes, generic systems can be
to show you how you can use ICSP to get an edge over built and inventoried ahead of time. Based on actual
your competition. Microchip has helped its customers mix of customer orders, the PICmicro MCU can be
implement ICSP using PICmicro MCUs since 1992. programmed using ICSP, then tested and shipped.
Contact your local Microchip sales representative today The lead-time reduction and simplification of finished
for more information on implementing ICSP in your goods inventory are key benefits.
product.
• Calibrate Your System During Manufacturing
PICmicro MCUs MAKE IN-CIRCUIT Many systems require calibration in the final stages
SERIAL PROGRAMMING A CINCH of manufacturing and testing. Typically, calibration
parameters are stored in Serial EEPROM devices.
Unlike many other MCUs, most PICmicro MCUs offer a Using PICmicro MCUs, it is possible to save the addi-
simple serial programming interface using only two I/O tional system cost by programming the calibration
pins (plus power, ground and VPP). Following very sim- parameters directly into the program memory.
ple guidelines, these pins can be fully utilized as I/O
• Add Unique ID Code to Your System During
pins during normal operation and programming pins
Manufacturing
during ICSP.
Many products require a unique ID number or a
ICSP can be activated through a simple 5-pin connec-
serial number. An example application would be a
tor and a standard PICmicro programmer supporting
remote keyless entry device. Each transmitter has a
serial programming mode such as Microchip’s
unique “binary key” that makes it very easy to pro-
PRO MATE® II.
gram in the access code at the very end of the man-
No other MCU has a simpler and less intrusive Serial ufacturing process and prior to final test.
Programming Mode to facilitate your ICSP needs.
Serial number, revision code, date code, manufac-
turer ID and a variety of other useful information can
also be added to any product for traceability. Using
ICSP, you can eliminate the need for DIP switches or
jumpers.

In-Circuit Serial Programming and ICSP are trademarks of Microchip Technology Inc. SQTP is a service mark of Microchip Technology Inc.

 2000 Microchip Technology Inc. DS30277C-page 1-1

Introduction
In fact, this capability is so important to many of our • Program Dice When Using Chip-On-Board
customers that Microchip offers a factory program- (COB)
ming service called Serialized Quick Turn Program- If you are using COB, Microchip offers a comprehen-
ming (SQTPSM), where each PICmicro MCU device is sive die program. You can get dice that are
coded with up to 16 bytes of unique code. preprogrammed, or you may want to program the die
• Calibrate Your System in the Field once the circuit board is assembled. Programming
Calibration need not be done only in the factory. and testing in one single step in the manufacturing
During installation of a system, ICSP can be used to process is simpler and more cost effective.
further calibrate the system to actual operating
environment.
PROGRAMMING TIME
CONSIDERATIONS
In fact, recalibration can be easily done during
periodic servicing and maintenance. In OTP parts, Programming time can be significantly different
newer calibration data can be written to blank between OTP and FLASH MCUs. OTP (EPROM) bytes
memory locations reserved for such use. typically program with pulses in the order of several
• Customize and Configure Your System in the hundred microseconds. FLASH, on the other hand,
Field require several milliseconds or more per byte (or word)
to program.
Like calibration, customization need not done in the
factory only. In many situations, customizing a Figure 1 and Figure 2 below illustrate the programming
product at installation time is very useful. A good time differences between OTP and FLASH MCUs.
example is home or car security systems where ID Figure 1 shows programming time in an ideal program-
code, access code and other such information can mer or tester, where the only time spent is actually pro-
be burned in after the actual configuration is deter- gramming the device. This is only important to illustrate
mined. Additionally, you can save the cost of DIP the minimum time required to program such devices,
switches and jumpers, which are traditionally used. where the programmer or the tester is fully optimized.
Figure 2 is a more realistic programming time compar-
ison, where the “overhead” time for programmer or a
tester is built in. The programmer often requires 3 to 5
times the “theoretically” minimum programming time.

FIGURE 1: PROGRAMMING TIME FOR FLASH AND OTP MCUS

(THEORETICAL MINIMUM TIMES)

40
Typical
Typical
Programming Time (Seconds)

35 Flash
FLASH MCU
MCU

10 Microchip
Microchip
OTP
OTPMCU
MCU
5

0
0 1K 2K 4K 8K 16K

Memory Size (in bytes)

Note 1: The programming times shown here only include the total programming time for all memory. Typically, a
programmer will have quite a bit of overhead over this “theoretical minimum” programming time.
2: In the PIC16CXX MCU (used here for comparison) each word is 14 bits wide. For the sake of simplicity,
each word is viewed as “two bytes”.

DS30277C-page 1-2  2000 Microchip Technology Inc.

Introduction
FIGURE 2: PROGRAMMING TIME FOR FLASH AND OTP MCUS
(TYPICAL PROGRAMMING TIMES ON A PROGRAMMER)

280

260
240

Programming Time (Seconds)

220
200
Typical
Typical
180 Flash
FLASHMCU
MCU
160

140
120

100
80

60 Microchip
Microchip
40 OTP MCU
OTP MCU
20
0
0 1K 2K 4K 8K 16K

Memory Size (in bytes)

Note 1: The programming times shown are actual programming times on vendor supplied programmers.
2: Microchip OTP programming times are based on PRO MATE II programmer.

Ramifications Development Tools

The programming time differences between FLASH Microchip offers a comprehensive set of development
and OTP MCUs are not particular material for prototyp- tools for ICSP that allow system engineers to quickly
ing quantities. However, its impact can be significant in prototype, make code changes and get designs out the
large volume production. door faster than ever before.
PRO MATE II Production Programmer – a production
MICROCHIP PROVIDES A COMPLETE quality programmer designed to support the Serial
SOLUTION FOR ICSP Programming Mode in MCUs up to midvolume produc-
tion. PRO MATE II runs under DOS in a Command Line
Products Mode, Microsoft® Windows® 3.1, Windows® 95/98,
Microchip offers the broadest line of ICSP-capable and Windows NT®. PRO MATE II is also capable of
MCUs: Serialized Quick Turn ProgrammingSM (SQTPSM),
• PIC12C5XX OTP, 8-pin Family where each device can be programmed with up to 16
bytes of unique code.
• PIC12C67X OTP, 8-pin Family
• PIC12CE67X OTP, 8-pin Family Microchip offers an ICSP kit that can be used with the
Universal Microchip Device Programmer,
• PIC16C6XX OTP, Mid-Range Family
PRO MATE II. Together these two tools allow you to
• PIC17C7XX OTP High-End Family implement ICSP with minimal effort and use the ICSP
• PIC18CXXX OTP, High-End Family capability of Microchip’s PICmicro MCUs.
• PIC16F62X FLASH, Mid-Range Family Technical support
• PIC16F8X FLASH, Mid-Range Family
Microchip has been delivering ICSP capable MCUs
• PIC6F8XX FLASH, Mid-Range Family since 1992. Many of our customers are using ICSP
All together, Microchip currently offers over 40 MCUs capability in full production. Our field and factory appli-
capable of ICSP. cation engineers can help you implement ICSP in your
product.

 2000 Microchip Technology Inc. DS30277C-page 1-3

Introduction
NOTES:

DS30277C-page 1-4  2000 Microchip Technology Inc.

SECTION 2
TECHNICAL BRIEFS

HOW TO IMPLEMENT ICSP™ USING PIC12C5XX OTP MCUS ........................................................... 2-1

HOW TO IMPLEMENT ICSP™ USING PIC16CXXX OTP MCUS .......................................................... 2-9

HOW TO IMPLEMENT ICSP™ USING PIC17CXXX OTP MCUS ........................................................ 2-15

HOW TO IMPLEMENT ICSP™ USING PIC16F8X FLASH MCUS ....................................................... 2-21

 2000 Microchip Technology Inc. DS30277C-page 2-i

DS30277C-page 2-ii  2000 Microchip Technology Inc.
TB017
How to Implement ICSP™ Using PIC12C5XX OTP MCUs

Author: Thomas Schmidt

IN-CIRCUIT SERIAL PROGRAMMING
Microchip Technology Inc. To implement ICSP into an application, the user needs
to consider three main components of an ICSP system:
Application Circuit, Programmer and Programming
INTRODUCTION
Environment.
The technical brief describes how to implement in-cir- Application Circuit
cuit serial programming™ (ICSP) using the
PIC12C5XX OTP PICmicro® MCU. During the initial design phase of the application circuit,
certain considerations have to be taken into account.
ICSP is a simple way to manufacture your board with Figure 1 shows and typical circuit that addresses the
an unprogrammed PICmicro MCU and program the details to be considered during design. In order to
device just before shipping the product. Programming implement ICSP on your application board you have to
the PIC12C5XX MCU in-circuit has many advantages put the following issues into consideration:
for developing and manufacturing your product.
1. Isolation of the GP3/MCLR/VPP pin from the rest
• Reduces inventory of products with old of the circuit.
firmware. With ICSP, the user can manufacture 2. Isolation of pins GP1 and GP0 from the rest of
product without programming the PICmicro MCU. the circuit.
The PICmicro MCU will be programmed just 3. Capacitance on each of the VDD, GP3/MCLR/
before the product is shipped. VPP, GP1, and GP0 pins.
• ICSP in production. New software revisions or 4. Interface to the programmer.
additional software modules can be programmed 5. Minimum and maximum operating voltage for
during production into the PIC12C5XX MCU. VDD.
• ICSP in the field. Even after your product has
been sold, a service man can update your
program with new program modules.
• One hardware with different software. ICSP
allows the user to have one hardware, whereas
the PIC12C5XX MCU can be programmed with
different types of software.
• Last minute programming. Last minute pro-
gramming can also facilitate quick turnarounds on
custom orders for your products.

FIGURE 1: TYPICAL APPLICATION CIRCUIT

Application PCB VDD VDD
PIC12C5XX
GP3/MCLR/VPP
ICSP Connector

VDD
VSS
GP0
GP1

To application circuit
Isolation circuits

PICmicro, PRO MATE and PICSTART are registered trademarks of Microchip Technology Inc.
In-Circuit Serial Programming and ICSP are trademarks of Microchip Technology Inc.

 2000 Microchip Technology Inc. Preliminary DS91017B-page 2-1

TB017
Isolation of the GP3/MCLR/VPP Pin from the Total Capacitance on VDD, GP3/MCLR/VPP,
Rest of the Circuit GP1, and GP0
PIC12C5XX devices have two ways of configuring the The total capacitance on the programming pins affects
MCLR pin: the rise rates of these signals as they are driven out of
• MCLR can be connected either to an external RC the programmer. Typical circuits use several hundred
circuit or microfarads of capacitance on VDD, which helps to
• MCLR is tied internally to VDD dampen noise and improve electromagnetic interfer-
ence. However, this capacitance requires a fairly strong
When GP3/MCLR/VPP pin is connected to an external driver in the programmer to meet the rise rate timings
RC circuit, the pull-up resistor is tied to VDD, and a for VDD.
capacitor is tied to ground. This circuit can affect the
operation of ICSP depending on the size of the capac- Interface to the Programmer
itor. Most programmers are designed to simply program the
Another point of consideration with the GP3/MCLR/VPP PICmicro MCU itself and don’t have strong enough
pin, is that when the PICmicro MCU is programmed, drivers to power the application circuit.
this pin is driven up to 13V and also to ground. There- One solution is to use a driver board between the pro-
fore, the application circuit must be isolated from the grammer and the application circuit. The driver board
voltage coming from the programmer. needs a separate power supply that is capable of driv-
When MCLR is tied internally to VDD, the user has only ing the VPP, VDD, GP1, and GP0 pins with the correct
to consider that up to 13V are present during program- ramp rates and also should provide enough current to
ming of the GP3/MCLR/VPP pin. This might affect other power-up the application circuit.
components connected to that pin. The cable length between the programmer and the cir-
For more information about configuring the GP3/ cuit is also an important factor for ICSP. If the cable
MCLR/VPP internally to VDD, please refer to the between the programmer and the circuit is too long, sig-
PIC12C5XX data sheet (DS40139). nal reflections may occur. These reflections can
momentarily cause up to twice the voltage at the end of
Isolation of Pins GP1 and GP0 from the Rest the cable, that was sent from the programmer. This volt-
of the Circuit age can cause a latch-up. In this case, a termination
Pins GP1 and GP0 are used by the PICmicro MCU for resistor has to be used at the end of the signal line.
serial programming. GP1 is the clock line and GP0 is Minimum and Maximum Operating Voltage
the data line. for VDD
GP1 is driven by the programmer. GP0 is a bidirectional The PIC12C5XX programming specification states that
pin that is driven by the programmer when program- the device should be programmed at 5V. Special con-
ming and driven by the PICmicro MCU when verifying. siderations must be made if your application circuit
These pins must be isolated from the rest of the appli- operates at 3V only. These considerations may include
cation circuit so as not to affect the signals during pro- totally isolating the PICmicro MCU during program-
gramming. You must take into consideration the output ming. The other point of consideration is that the device
impedance of the programmer when isolating GP1 and must be verified at minimum and maximum operation
GP0 from the rest of the circuit. This isolation circuit voltage of the circuit in order to ensure proper program-
must account for GP1 being an input on the PICmicro ming margin.
MCU and for GP0 being bidirectional pin.
For example, a battery driven system may operate from
For example, PRO MATE® II has an output impedance three 1.5V cells giving an operating voltage range of
of 1 kΩ. If the design permits, these pins should not be 2.7V to 4.5V. The programmer must program the device
used by the application. This is not the case with most at 5V and must verify the program memory contents at
designs. As a designer, you must consider what type of both 2.7V and 4.5V to ensure that proper programming
circuitry is connected to GP1 and GP0 and then make margins have been achieved.
a decision on how to isolate these pins.

DS91017B-page 2-2 Preliminary  2000 Microchip Technology Inc.

TB017
THE PROGRAMMER in the same configuration as the pads on the board.
The application circuit is moved into position and the
PIC12C5XX MCUs only use serial programming and, fixture is moved such that the spring loaded test pins
therefore, all programmers supporting these devices come into contact with the board. This method might be
will support the ICSP. One issue with the programmer more suitable for an automated assembly line.
is the drive capability. As discussed before, it must be
After taking into consideration the issues with the
able to provide the specified rise rates on the ICSP sig-
application circuit, the programmer, and the program-
nals and also provide enough current to power the
ming environment, anyone can build a high quality,
application circuit. It is recommended that you buffer
reliable manufacturing line based on ICSP.
the programming signals.
Another point of consideration for the programmer is OTHER BENEFITS
what VDD levels are used to verify the memory contents
of the PICmicro MCU. For instance, the PRO MATE II ICSP provides several other benefits such as calibra-
verifies program memory at the minimum and maxi- tion and serialization. If program memory permits, it
mum VDD levels for the specified device and is there- would be cheaper and more reliable to store calibration
fore considered a production quality programmer. On constants in program memory instead of using an
the other hand, the PICSTART® Plus only verifies at 5V external serial EEPROM.
and is for prototyping use only. The PIC12C5XX pro- Field Programming of PICmicro OTP MCUs
gramming specifications state that the program mem-
An OTP device is not normally capable of being repro-
ory contents should be verified at both the minimum
grammed, but the PICmicro MCU architecture gives
and maximum VDD levels that the application circuit will
you this flexibility provided the size of your firmware is
be operating. This implies that the application circuit
less than half that of the desired device.
must be able to handle the varying VDD voltages.
This method involves using jump tables for the reset
There are also several third-party programmers that
and interrupt vectors. Example 1 shows the location of
are available. You should select a programmer based
a main routine and the reset vector for the first time a
on the features it has and how it fits into your program-
device with 0.5K-words of program memory is pro-
ming environment. The Microchip Development Sys-
grammed. Example 2 shows the location of a second
tems Ordering Guide (DS30177) provides detailed
main routine and its reset vector for the second time the
information on all our development tools. The Microchip
same device is programmed. You will notice that the
Third Party Guide (DS00104) provides information on
GOTO Main that was previously at location 0x0002 is
all of our third party development tool developers.
replaced with an NOP. An NOP is a program memory
Please consult these two references when selecting a
location with all the bits programmed as 0s. When the
programmer. Many options exist including serial or par-
reset vector is executed, it will execute an NOP and
allel PC host connection, stand-alone operation, and
then a GOTO Main1 instruction to the new code.
single or gang programmers.

PROGRAMMING ENVIRONMENT
The programming environment will affect the type of
programmer used, the programmer cable length, and
the application circuit interface. Some programmers
are well suited for a manual assembly line while others
are desirable for an automated assembly line. A gang
programmer should be chosen for programming multi-
ple MCUs at one time. The physical distance between
the programmer and the application circuit affects the
load capacitance on each of the programming signals.
This will directly affect the drive strength needed to pro-
vide the correct signal rise rates and current. Finally,
the application circuit interface to the programmer
depends on the size constraints of the application cir-
cuit itself and the assembly line. A simple header can
be used to interface the application circuit to the pro-
grammer. This might be more desirable for a manual
assembly line where a technician plugs the
programmer cable into the board.
A different method is the uses spring loaded test pins
(often referred as pogo-pins). The application circuit
has pads on the board for each of the programming sig-
nals. Then there is a movable fixture that has pogo pins

 2000 Microchip Technology Inc. Preliminary DS91017B-page 2-3

TB017
EXAMPLE 1: LOCATION OF THE FIRST MAIN ROUTINE AND ITS INTERRUPT VECTOR

PROGRAM MEMORY

0X000 MOVWF OSCAL RESET VECTOR

0X001 GOTO MAIN1

UNPROGRAMMED
0X040 MAIN1
MAIN1 ROUTINE

0X080

UNPROGRAMMED

0X1FF MOVLW XX CALIBRATION VALUE

LEGEND: XX = CALIBRATION VALUE

DS91017B-page 2-4 Preliminary  2000 Microchip Technology Inc.

TB017
EXAMPLE 2: LOCATION OF THE SECOND MAIN ROUTINE AND IT INTERRUPT VECTOR
(AFTER SECOND PROGRAMMING)

PROGRAM MEMORY

0X000 MOVWF OSCAL RESET VECTOR

0X001 NOP
0X002 GOTO MAIN2

UNPROGRAMMED

0X040
MAIN1

MAIN1 ROUTINE

0X080

UNPROGRAMMED

0X10E MAIN2

MAIN2 ROUTINE

0X136

0X1FF MOVLW XX CALIBRATION VALUE

LEGEND: XX = CALIBRATION VALUE

 2000 Microchip Technology Inc. Preliminary DS91017B-page 2-5

TB017
Since the program memory of the PIC12C5XX devices CONCLUSION
is organized in 256 x 12 word pages, placement of such
information as look-up tables and CALL instructions Microchip Technology Inc. is committed to supporting
must be taken into account. For further information, your ICSP needs by providing you with our many years
please refer to application note AN581, Implementing of experience and expertise in developing in-circuit sys-
Long Calls and application note AN556, Implementing tem programming solutions. Anyone can create a reli-
a Table Read. able in-circuit system programming station by coupling
our background with some forethought to the circuit
design and programmer selection issues previously
mentioned. Your local Microchip representative is avail-
able to answer any questions you have about the
requirements for ICSP.

DS91017B-page 2-6 Preliminary  2000 Microchip Technology Inc.

VCC

VCC 15V

EXTERNAL POWER SUPPLY R6

VPP_OUT
1
R2 Q1 TO CIRCUIT
2N3906
R9
33k 100
1 U1A
U1B 2 R9 VCC
6 R10 1
7 3

 2000 Microchip Technology Inc.

5 100 Q2
100 4 TLE2144A 2N2222
VPP_IN TLE2144A D1
C1 12.7V
FROM 1NF
PROGRAMMER R12
100k R13
5k C3
0.1µF

R15
VDD_OUT
1 TO CIRCUIT
R4 Q3
2N3906
R17
10k 100
9 U1C
U1D R18 VCC

Preliminary
13 R19 8
14 10
12 TLE2144A 100 Q4
100 2N2222
VDD_IN TLE2144A D2
C4 6.2V
APPENDIX A: SAMPLE DRIVER BOARD SCHEMATIC

FROM 1NF
PROGRAMMER R21
100k R22
5k C6
0.1µF

GP1_IN GP1_OUT GP0_IN GP0_OUT

*see text in technical brief. *see text in technical brief.
FROM TO CIRCUIT FROM TO CIRCUIT
PROGRAMMER PROGRAMMER

Note: The driver board design MUST be tested in the user’s

GND_IN GND_OUT application to determine the effects of the applications
FROM TO CIRCUIT circuit on the programming signals timing. Changes
PROGRAMMER may be required if the application places a significant
load on VDD, VPP, GP0 or GP1.
TB017

DS91017B-page 2-7
TB017
NOTES:

DS91017B-page 2-8 Preliminary  2000 Microchip Technology Inc.

TB013
How to Implement ICSP™ Using PIC16CXXX OTP MCUs
Application Circuit
Author: Rodger Richey
Microchip Technology Inc. The application circuit must be designed to allow all the
programming signals to be directly connected to the
PICmicro MCU. Figure 1 shows a typical circuit that is
a starting point for when designing with ICSP. The
INTRODUCTION application must compensate for the following issues:

In-Circuit Serial Programming™ (ICSP) is a great way 1. Isolation of the MCLR/VPP pin from the rest of
to reduce your inventory overhead and time-to-market the circuit.
for your product. By assembling your product with a 2. Isolation of pins RB6 and RB7 from the rest of
blank Microchip microcontroller (MCU), you can stock the circuit.
one design. When an order has been placed, these 3. Capacitance on each of the VDD, MCLR/VPP,
units can be programmed with the latest revision of RB6, and RB7 pins.
firmware, tested, and shipped in a very short time. This 4. Minimum and maximum operating voltage for
method also reduces scrapped inventory due to old VDD.
firmware revisions. This type of manufacturing system 5. PICmicro Oscillator.
can also facilitate quick turnarounds on custom orders
6. Interface to the programmer.
for your product.
The MCLR/VPP pin is normally connected to an RC cir-
Most people would think to use ICSP with PICmicro®
cuit. The pull-up resistor is tied to VDD and a capacitor
OTP MCUs only on an assembly line where the device
is tied to ground. This circuit can affect the operation of
is programmed once. However, there is a method by
ICSP depending on the size of the capacitor. It is, there-
which an OTP device can be programmed several
fore, recommended that the circuit in Figure 1 be used
times depending on the size of the firmware. This
when an RC is connected to MCLR/VPP. The diode
method, explained later, provides a way to field
should be a Schottky-type device. Another issue with
upgrade your firmware in a way similar to EEPROM- or
MCLR/VPP is that when the PICmicro MCU device is
Flash-based devices.
programmed, this pin is driven to approximately 13V
HOW DOES ICSP WORK? and also to ground. Therefore, the application circuit
Now that ICSP appeals to you, what steps do you take must be isolated from this voltage provided by the
to implement it in your application? There are three programmer.
main components of an ICSP system: Application
Circuit, Programmer and Programming Environment.

FIGURE 1: TYPICAL APPLICATION CIRCUIT

Application PCB Vdd Vdd
PIC16CXXX
MCLR/Vpp
ICSP Connector

Vdd
Vss
RB7
RB6

To application circuit
Isolation circuits

 2000 Microchip Technology Inc. Preliminary DS91013B-page 2-9

TB013
Pins RB6 and RB7 are used by the PICmicro MCU for The programmer must program the device at 5V and
serial programming. RB6 is the clock line and RB7 is must verify the program memory contents at both 2.7V
the data line. RB6 is driven by the programmer. RB7 is and 4.5V to ensure that proper programming margins
a bidirectional pin that is driven by the programmer have been achieved. This ensures the PICmicro MCU
when programming, and driven by the PICmicro MCU option over the voltage range of the system.
when verifying. These pins must be isolated from the This final issue deals with the oscillator circuit on the
rest of the application circuit so as not to affect the sig- application board. The voltage on MCLR/VPP must rise
nals during programming. You must take into consider- to the specified program mode entry voltage before the
ation the output impedance of the programmer when device executes any code. The crystal modes available
isolating RB6 and RB7 from the rest of the circuit. This on the PICmicro MCU are not affected by this issue
isolation circuit must account for RB6 being an input on because the Oscillator Start-up Timer waits for 1024
the PICmicro MCU, and for RB7 being bidirectional oscillations before any code is executed. However, RC
(can be driven by both the PICmicro MCU and the pro- oscillators do not require any startup time and, there-
grammer). For instance, PRO MATE® II has an output fore, the Oscillator Startup Timer is not used. The pro-
impedance of 1k¾. If the design permits, these pins grammer must drive MCLR/VPP to the program mode
should not be used by the application. This is not the entry voltage before the RC oscillator toggles four
case with most applications so it is recommended that times. If the RC oscillator toggles four or more times,
the designer evaluate whether these signals need to be the program counter will be incremented to some value
buffered. As a designer, you must consider what type of X. Now when the device enters programming mode,
circuitry is connected to RB6 and RB7 and then make the program counter will not be zero and the program-
a decision on how to isolate these pins. Figure 1 does mer will start programming your code at an offset of X.
not show any circuitry to isolate RB6 and RB7 on the There are several alternatives that can compensate for
application circuit because this is very application a slow rise rate on MCLR/VPP. The first method would
dependent. be to not populate the R, program the device, and then
The total capacitance on the programming pins affects insert the R. The other method would be to have the
the rise rates of these signals as they are driven out of programming interface drive the OSC1 pin of the
the programmer. Typical circuits use several hundred PICmicro MCU to ground while programming. This will
microfarads of capacitance on VDD which helps to prevent any oscillations from occurring during program-
dampen noise and ripple. However, this capacitance ming.
requires a fairly strong driver in the programmer to Now all that is left is how to connect the application cir-
meet the rise rate timings for VDD. Most programmers cuit to the programmer. This depends a lot on the
are designed to simply program the PICmicro MCU programming environment and will be discussed in that
itself and don’t have strong enough drivers to power the section.
application circuit. One solution is to use a driver board
between the programmer and the application circuit. Programmer
The driver board requires a separate power supply that The second consideration is the programmer.
is capable of driving the VPP and VDD pins with the PIC16CXXX MCUs only use serial programming and
correct rise rates and should also provide enough cur- therefore all programmers supporting these devices
rent to power the application circuit. RB6 and RB7 are will support ICSP. One issue with the programmer is the
not buffered on this schematic but may require buffer- drive capability. As discussed before, it must be able to
ing depending upon the application. A sample driver provide the specified rise rates on the ICSP signals and
board schematic is shown in Appendix A. also provide enough current to power the application
Note: The driver board design MUST be tested circuit. Appendix A shows an example driver board.
in the user’s application to determine the This driver schematic does not show any buffer circuitry
effects of the application circuit on the for RB6 and RB7. It is recommended that an evaluation
programming signals timing. Changes be performed to determine if buffering is required.
may be required if the application places Another issue with the programmer is what VDD levels
a significant load on VDD, VPP, RB6 OR are used to verify the memory contents of the PICmicro
RB7. MCU. For instance, the PRO MATE II verifies program
memory at the minimum and maximum VDD levels for
The Microchip programming specification states that the specified device and is therefore considered a pro-
the device should be programmed at 5V. Special con- duction quality programmer. On the other hand, the
siderations must be made if your application circuit PICSTART® Plus only verifies at 5V and is for prototyp-
operates at 3V only. These considerations may include ing use only. The Microchip programming specifica-
totally isolating the PICmicro MCU during program- tions state that the program memory contents should
ming. The other issue is that the device must be verified be verified at both the minimum and maximum VDD lev-
at the minimum and maximum voltages at which the els that the application circuit will be operating. This
application circuit will be operating. For instance, a bat- implies that the application circuit must be able to han-
tery operated system may operate from three 1.5V dle the varying VDD voltages.
cells giving an operating voltage range of 2.7V to 4.5V.

DS91013B-page 2-10 Preliminary  2000 Microchip Technology Inc.

TB013
There are also several third party programmers that are Other Benefits
available. You should select a programmer based on
ICSP provides other benefits, such as calibration and
the features it has and how it fits into your programming
serialization. If program memory permits, it would be
environment. The Microchip Development Systems
cheaper and more reliable to store calibration con-
Ordering Guide (DS30177) provides detailed informa-
stants in program memory instead of using an external
tion on all our development tools. The Microchip Third
serial EEPROM. For example, your system has a ther-
Party Guide (DS00104) provides information on all of
mistor which can vary from one system to another.
our third party tool developers. Please consult these
Storing some calibration information in a table format
two references when selecting a programmer. Many
allows the microcontroller to compensate in software
options exist including serial or parallel PC host con-
for external component tolerances. System cost can be
nection, stand-alone operation, and single or gang pro-
reduced without affecting the required performance of
grammers. Some of the third party developers include
the system by using software calibration techniques.
Advanced Transdata Corporation, BP Microsystems,
But how does this relate to ICSP? The PICmicro MCU
Data I/O, Emulation Technology and Logical Devices.
has already been programmed with firmware that per-
Programming Environment forms a calibration cycle. The calibration data is trans-
The programming environment will affect the type of ferred to a calibration fixture. When all calibration data
programmer used, the programmer cable length, and has been transferred, the fixture places the PICmicro
the application circuit interface. Some programmers MCU in programming mode and programs the
are well suited for a manual assembly line while others PICmicro MCU with the calibration data. Application
are desirable for an automated assembly line. You may note AN656, In-Circuit Serial Programming of Calibra-
want to choose a gang programmer to program multiple tion Parameters Using a PICmicro Microcontroller,
systems at a time. shows exactly how to implement this type of calibration
data programming.
The physical distance between the programmer and
the application circuit affects the load capacitance on The other benefit of ICSP is serialization. Each individ-
each of the programming signals. This will directly ual system can be programmed with a unique or ran-
affect the drive strength needed to provide the correct dom serial number. One such application of a unique
signal rise rates and current. This programming cable serial number would be for security systems. A typical
must also be as short as possible and properly system might use DIP switches to set the serial num-
terminated and shielded, or the programming signals ber. Instead, this number can be burned into program
may be corrupted by ringing or noise. memory, thus reducing the overall system cost and low-
ering the risk of tampering.
Finally, the application circuit interface to the program-
mer depends on the size constraints of the application Field Programming of PICmicro OTP MCUs
circuit itself and the assembly line. A simple header can An OTP device is not normally capable of being
be used to interface the application circuit to the pro- reprogrammed, but the PICmicro MCU architecture
grammer. This might be more desirable for a manual gives you this flexibility provided the size of your firm-
assembly line where a technician plugs the ware is at least half that of the desired device and the
programmer cable into the board. A different method is device is not code protected. If your target device does
the use of spring loaded test pins (commonly referred not have enough program memory, Microchip provides
to as pogo pins). The application circuit has pads on a wide spectrum of devices from 0.5K to 8K program
the board for each of the programming signals. Then memory with the same set of peripheral features that
there is a fixture that has pogo pins in the same config- will help meet the criteria.
uration as the pads on the board. The application circuit
The PIC16CXXX microcontrollers have two vectors,
or fixture is moved into position such that the pogo pins
reset and interrupt, at locations 0x0000 and 0x0004.
come into contact with the board. This method might be
When the PICmicro MCU encounters a reset or inter-
more suitable for an automated assembly line.
rupt condition, the code located at one of these two
After taking into consideration the issues with the appli- locations in program memory is executed. The first list-
cation circuit, the programmer, and the programming ing of Example 1 shows the code that is first pro-
environment, anyone can build a high quality, reliable grammed into the PICmicro MCU. The second listing of
manufacturing line based on ICSP. Example 1 shows the code that is programmed into the
PICmicro MCU for the second time.

 2000 Microchip Technology Inc. Preliminary DS91013B-page 2-11

DS91013B-page 2-12 Preliminary  2000 Microchip Technology Inc.

TB013
The example shows that to program the PICmicro MCU CONCLUSION
a second time the memory location 0x0000, originally
Microchip Technology Inc. is committed to supporting
goto Main (0x2808), is reprogrammed to all 0’s which
your ICSP needs by providing you with our many years
happens to be a nop instruction. This location cannot
of experience and expertise in developing ICSP
be reprogrammed to the new opcode (0x2860)
solutions. Anyone can create a reliable ICSP program-
because the bits that are 0’s cannot be reprogrammed
ming station by coupling our background with some
to 1’s, only bits that are 1’s can be reprogrammed to
forethought to the circuit design and programmer
0’s. The next memory location 0x0001 was originally
selection issues previously mentioned. Your local
blank (all 1’s) and now becomes a goto Main
Microchip representative is available to answer any
(0x2860). When a reset condition occurs, the PICmicro
questions you have about the requirements for ICSP.
MCU executes the instruction at location 0x0000 which
is the nop, a completely benign instruction, and then
executes the goto Main to start the execution of code.
The example also shows that all program memory loca-
tions after 0x005A are blank in the original program so
that the second time the PICmicro MCU is pro-
grammed, the revised code can be programmed at
these locations. The same descriptions can be given
for the interrupt vector at location 0x0004.
This method changes slightly for PICmicro MCUs with
>2K words of program memory. Each of the goto
Main and goto ISR instructions are replaced by the
following code segments due to paging on devices with
>2K words of program memory.
movlw <page> movlw <page>
movwf PCLATH movwf PCLATH
goto Main goto ISR
Now your one time programmable PICmicro MCU is
exhibiting more EEPROM- or Flash-like qualities.

 2000 Microchip Technology Inc. Preliminary DS91013B-page 2-13

VCC

VCC 15V

EXTERNAL POWER SUPPLY R6

VPP_OUT
TB013

1
R2 Q1 TO CIRCUIT
APPENDIX A:

DS91013B-page 2-14
2N3906
R9
33k 100
1 U1A
U1B 2 R9 VCC
6 R10 1
7 3
5 100 Q2
100 4 TLE2144A 2N2222
VPP_IN TLE2144A D1
C1 12.7V
FROM 1NF
PROGRAMMER R12
100k R13
5k C3
0.1µF

R15
VDD_OUT
1 TO CIRCUIT
R4 Q3
2N3906
R17
10k 100
9 U1C
U1D R18 VCC

Preliminary
13 R19 8
14 10
12 TLE2144A 100 Q4
100 2N2222
VDD_IN TLE2144A D2
C4 6.2V
FROM 1NF
SAMPLE DRIVER BOARD SCHEMATIC

PROGRAMMER R21
100k R22
5k C6
0.1µF

RB6_IN RB6_OUT RB7_IN RB7_OUT

*see text in technical brief. *see text in technical brief.
FROM TO CIRCUIT FROM TO CIRCUIT
PROGRAMMER PROGRAMMER

Note: The driver board design MUST be tested in the user’s

GND_IN GND_OUT application to determine the effects of the application
FROM TO CIRCUIT circuit on the programming signals timing. Changes
PROGRAMMER may be required if the application places a significant
load on Vdd, Vpp, RB6 or RB7.

 2000 Microchip Technology Inc.

TB015
How to Implement ICSP™ Using PIC17CXXX OTP MCUs

Author: Stan D’Souza

Implementation
Microchip Technology Inc. The PIC17CXXX devices have special instructions,
which enables the user to program and read the
PIC17CXXX's program memory. The instructions are
TABLWT and TLWT which implement the program mem-
INTRODUCTION ory write operation and TABLRD and TLRD which per-
form the program memory read operation. For more
PIC17CXXX microcontroller (MCU) devices can be details, please check the In-Circuit Serial Programming
serially programmed using an RS-232 or equivalent for PIC17CXXX OTP Microcontrollers Specification
serial interface. As shown in Figure 2, using just three (DS30273), PIC17C4X data sheet (DS30412) and
pins, the PIC17CXXX can be connected to an external PIC17C75X data sheet (DS30264).
interface and programmed. In-Circuit Serial Program-
When doing ICSP, the PIC17CXXX runs a boot code,
ming (ICSP™) allows for a greater flexibility in an appli-
which configures the USART port and receives data
cation as well as a faster time to market for the user's
serially through the RX line. This data is then pro-
product.
grammed at the address specified in the serial data
This technical brief will demonstrate the practical string. A high voltage (about 13V) is required for the
aspects associated with ICSP using the PIC17CXXX. It EPROM cell to get programmed, and this is usually
will also demonstrate some key capabilities of OTP supplied by the programming header as shown in
devices when used in conjunction with ICSP. Figure 2 and Figure 3. The PIC17CXXX's boot code
enables and disables the high voltage line using a ded-
icated I/O line.

FIGURE 2: PIC17CXXX IN-CIRCUIT SERIAL PROGRAMMING USING TABLE WRITE

INSTRUCTIONS

PIC17CXXX SYSTEM BOARD

I/O
13V Enable
Data Program
Memory Memory
VPP
13V
Data H:Data L

Boot
Data L Code
Data H
TX In-Circuit
Programming
USART RX Level Converter Connector

 2000 Microchip Technology Inc. Preliminary DS91015A-page 2-15

TB015
FIGURE 3: PIC17CXXX IN-CIRCUIT SERIAL PROGRAMMING SCHEMATIC
PIC17CXXX +5V

Vdd 7805

2N3905 13V
MCLR

RA2 Programming Header

+5V

Serial Port RX
TX
RX MAX232
Serial Port TX
Vss

ICSP Boot Code interrupt occurs. This delay ensures that the program-
ming pulse width of 1 ms (max.) is met. Once a location
The boot code is normally programmed, into the
is written, RA2 is driven high to disable further writes
PIC17CXXX device using a PRO MATE® or
and a verify operation is done using the Table read
PICSTART® Plus or any third party programmer. As
instruction. If the result is good, an acknowledge is sent
depicted in the flowchart in Figure 5, on power-up, or a
to the host. This process is repeated till all desired loca-
reset, the program execution always vectors to the boot
tions are programmed.
code. The boot code is normally located at the bottom
of the program memory space e.g. 0x700 for a In normal operation, when the ICSP header is not con-
PIC17C42A (Figure 4). nected, the boot code would still execute and the
PIC17CXXX would send out a request to the host.
Several methods could be used to reset the
However it would not get a response from the host, so
PIC17CXXX when the ICSP header is connected to the
it would abort the boot code and start normal code
system board. The simplest method, as shown in
execution.
Figure 3, is to derive the system 5V, from the 13V sup-
plied by the ICSP header. It is quite common in manu-
facturing lines, to have system boards programmed FIGURE 4: BOOT CODE EXAMPLE FOR
with only the boot code ready and available for testing, PIC17C42A
calibration or final programming. The ICSP header
would thus supply the 13V to the system and this 13V Program Memory
would then be stepped down to supply the 5V required Reset Vector
to power the system. Please note that the 13V supply
should have enough drive capability to supply power to
the system as well as maintain the programming volt-
age of 13V.
The first action of the boot code (as shown in flowchart
Figure 5) is to configure the USART to a known baud
rate and transmit a request sequence to the ICSP host
system. The host immediately responds with an
acknowledgment of this request. The boot code then
gets ready to receive ICSP data. The host starts send-
ing the data and address byte sequences to the
0x700
PIC17CXXX. On receiving the address and data
information, the 16-bit address is loaded into the Boot Code
TBLPTR registers and the 16-bit data is loaded into the 0x7FF
TABLAT registers. The RA2 pin is driven low to enable
13V at MCLR. The PIC17CXXX device then executes
a table write instruction. This instruction in turn causes
a long write operation, which disables further code exe-
cution. Code execution is resumed when an internal

DS91015A-page 2-16 Preliminary  2000 Microchip Technology Inc.

TB015
FIGURE 5: FLOWCHART FOR ICSP BOOT CODE

Start

Goto Boot Code

Configure USART
and send request

No No
Received Host’s Time-out complete?
ACK?

Yes Yes

Prepare to receive
ICSP data Start Code
Execution

No
Received Address
and Data info?

Yes

Do Table Write
operation

No
Interrupt?

Yes

Read Program
Location

Program location No Signal Programming

verified correctly? Error

Yes

END

No Last Data/Address Yes

sequence?

 2000 Microchip Technology Inc. Preliminary DS91015A-page 2-17

TB015
USING THE ICSP FEATURE ON Saving Field Calibration Information Using
PIC17CXXX OTP DEVICES ICSP
Sensors typically tend to drift and lose calibration over
The ICSP feature is a very powerful tool when used in time and usage. One expensive solution would be to
conjunction with OTP devices. replace the sensor with a new one. A more cost effec-
Saving Calibration Information Using ICSP tive solution however, is to re-calibrated the system and
save the new calibration parameter/constants into the
One key use of ICSP is to store calibration constants or
PIC17CXXX devices using ICSP. The user program
parameters in program memory. It is quite common to
however has to take into account certain issues:
interface a PIC17CXXX device to a sensor. Accurate,
pre-calibrated sensors can be used, but they are more 1. Un-programmed or blank locations have to be
expensive and have long lead times. Uncalibrated sen- reserved at each calibration constant location in
sors on the other hand are inexpensive and readily order to save new calibration parameters/con-
available. The only caveat is that these sensors have to stants.
be calibrated in the application. Once the calibration 2. The old calibration parameters/constants are all
constants have been determined, they would be unique programmed to 0, so the user program will have
to a given system, so they have to be saved in program to be “intelligent” and differentiate between blank
memory. These calibration parameters/constants can (0xFFFF), zero (0x0000), and programmed locations.
then be retrieved later during program execution and
Figure 6 shows how this can be achieved.
used to improve the accuracy of low cost un-calibrated
sensors. ICSP thus offers a cost reduction path for the Programming Unique Serial Numbers Using
end user in the application. ICSP
There are applications where each system needs to
have a unique and sometimes random serial number.
Example: security devices. One common solution is to
have a set of DIP switches which are then set to a
unique value during final test. A more cost effective
solution however would be to program unique serial
numbers into the device using ICSP. The user applica-
tion can thus eliminate the need for DIP switches and
subsequently reduce the cost of the system.

FIGURE 6: FIELD CALIBRATION USING ICSP

Factory Settings Field Calibrate #1 Field Calibrate #2

Parameter 1.1 0x0000 0x0000

0xFFFF Parameter 1.2 0x0000
0xFFFF 0xFFFF Parameter 1.3
0xFFFF 0xFFFF 0xFFFF
Parameter 2.1 0x0000 0x0000
0xFFFF Parameter 2.2 0x0000
0xFFFF 0xFFFF Parameter 2.3
0xFFFF 0xFFFF 0xFFFF

DS91015A-page 2-18 Preliminary  2000 Microchip Technology Inc.

TB015
Code Updates in the Field Using ICSP CONCLUSION
With fast time to market it is not uncommon to see
ICSP is a very powerful feature available on the
application programs which need to be updated or cor-
PIC17CXXX devices. It offers tremendous design flex-
rected for either enhancements or minor errors/bugs. If
ibility to the end user in terms of saving calibration con-
ROM parts were used, updates would be impossible
stants and updating code in final production as well as
and the product would either become outdated or
in the field, thus helping the user design a low-cost and
recalled from the field. A more cost effective solution
fast time-to-market product.
is to use OTP devices with ICSP and program them in
the field with the new updates. Figure 7 shows an
example where the user has allowed for one field
update to his program.
Here are some of the issues which need to be
addressed:
1. The user has to reserve sufficient blank memory
to fit his updated code.
2. At least one blank location needs to be saved at
the reset vector as well as for all the interrupts.
3. Program all the old “goto” locations (located at
the reset vector and the interrupts vectors) to 0
so that these instructions execute as NOPs.
4. Program new “goto” locations (at the reset vec-
tor and the interrupt vectors) just below the old
“goto” locations.
5. Finally, program the new updated code in the
blank memory space.

FIGURE 7: CODE UPDATES USING ICSP

Production Program Code Update #1

Goto Boot 0x0000 Goto Boot 0x0000

Main Goto Main1 Main 0x0000

0xFFFF Goto Main2
0xFFFF 0xFFFF

Main1
Main1
Main2

Boot Boot

Goto Main Goto Main

 2000 Microchip Technology Inc. Preliminary DS91015A-page 2-19

TB015
NOTES:

DS91015A-page 2-20 Preliminary  2000 Microchip Technology Inc.

TB016
How to Implement ICSP™ Using PIC16F8X FLASH MCUs

Author: Rodger Richey

Application Circuit
Microchip Technology Inc. The application circuit must be designed to allow all the
programming signals to be directly connected to the
PICmicro MCUs. Figure 1 shows a typical circuit that is
a starting point for when designing with ICSP. The
INTRODUCTION application must compensate for the following issues:
In-Circuit Serial Programming™ (ICSP) with 1. Isolation of the MCLR/VPP pin from the rest of
PICmicro® FLASH microcontrollers (MCU) is not only a the circuit.
great way to reduce your inventory overhead and time- 2. Isolation of pins RB6 and RB7 from the rest of
to-market for your product, but also to easily provide the circuit.
field upgrades of firmware. By assembling your product
3. Capacitance on each of the VDD, MCLR/VPP,
with a Microchip FLASH-based MCU, you can stock the
RB6, and RB7 pins.
shelf with one system. When an order has been placed,
these units can be programmed with the latest revision 4. Minimum and maximum operating voltage for
of firmware, tested, and shipped in a very short time. VDD.
This type of manufacturing system can also facilitate 5. PICmicro Oscillator.
quick turnarounds on custom orders for your product. 6. Interface to the programmer.
You don’t have to worry about scrapped inventory
The MCLR/VPP pin is normally connected to an RC cir-
because of the FLASH-based program memory. This
cuit. The pull-up resistor is tied to VDD and a capacitor
gives you the advantage of upgrading the firmware at
is tied to ground. This circuit can affect the operation of
any time to fix those “features” that pop up from time to
ICSP depending on the size of the capacitor. It is, there-
time.
fore, recommended that the circuit in Figure 1 be used
when an RC is connected to MCLR/VPP. The diode
HOW DOES ICSP WORK? should be a Schottky-type device. Another issue with
Now that ICSP appeals to you, what steps do you take MCLR/VPP is that when the PICmicro MCU device is
to implement it in your application? There are three programmed, this pin is driven to approximately 13V
main components of an ICSP system. and also to ground. Therefore, the application circuit
must be isolated from this voltage provided by the
These are the: Application Circuit, Programmer and
programmer.
Programming Environment.

FIGURE 1: TYPICAL APPLICATION CIRCUIT

Application PCB Vdd Vdd
PIC16F8X
MCLR/VPP
ICSP Connector

Vdd
Vss
RB7
RB6

To application circuit
Isolation circuits

PICmicro, PRO MATE, and PICSTART are registered trademarks of Microchip Technology Inc.
In-Circuit Serial Programming and ICSP are trademarks of Microchip Technology Inc.

 2000 Microchip Technology Inc. DS91016B-page 2-21

TB016
Pins RB6 and RB7 are used by the PICmicro MCU for cells giving an operating voltage range of 2.7V to 4.5V.
serial programming. RB6 is the clock line and RB7 is The programmer must program the device at 5V and
the data line. RB6 is driven by the programmer. RB7 is must verify the program memory contents at both 2.7V
a bidirectional pin that is driven by the programmer and 4.5V to ensure that proper programming margins
when programming, and driven by the PICmicro MCU have been achieved. This ensures the PICmicro MCU
when verifying. These pins must be isolated from the option over the voltage range of the system.
rest of the application circuit so as not to affect the sig- This final issue deals with the oscillator circuit on the
nals during programming. You must take into consider- application board. The voltage on MCLR/VPP must rise
ation the output impedance of the programmer when to the specified program mode entry voltage before the
isolating RB6 and RB7 from the rest of the circuit. This device executes any code. The crystal modes available
isolation circuit must account for RB6 being an input on on the PICmicro MCU are not affected by this issue
the PICmicro MCU and for RB7 being bidirectional (can because the Oscillator Start-up Timer waits for 1024
be driven by both the PICmicro MCU and the program- oscillations before any code is executed. However, RC
mer). For instance, PRO MATE® II has an output oscillators do not require any startup time and, there-
impedance of 1k¾. If the design permits, these pins fore, the Oscillator Startup Timer is not used. The pro-
should not be used by the application. This is not the grammer must drive MCLR/VPP to the program mode
case with most applications so it is recommended that entry voltage before the RC oscillator toggles four
the designer evaluate whether these signals need to be times. If the RC oscillator toggles four or more times,
buffered. As a designer, you must consider what type of the program counter will be incremented to some value
circuitry is connected to RB6 and RB7 and then make X. Now when the device enters programming mode,
a decision on how to isolate these pins. Figure 1 does the program counter will not be zero and the program-
not show any circuitry to isolate RB6 and RB7 on the mer will start programming your code at an offset of X.
application circuit because this is very application There are several alternatives that can compensate for
dependent. a slow rise rate on MCLR/VPP. The first method would
The total capacitance on the programming pins affects be to not populate the R, program the device, and then
the rise rates of these signals as they are driven out of insert the R. The other method would be to have the
the programmer. Typical circuits use several hundred programming interface drive the OSC1 pin of the
microfarads of capacitance on VDD which helps to PICmicro MCU to ground while programming. This will
dampen noise and ripple. However, this capacitance prevent any oscillations from occurring during program-
requires a fairly strong driver in the programmer to ming.
meet the rise rate timings for VDD. Most programmers Now all that is left is how to connect the application cir-
are designed to simply program the PICmicro MCU cuit to the programmer. This depends a lot on the
itself and don’t have strong enough drivers to power the programming environment and will be discussed in that
application circuit. One solution is to use a driver board section.
between the programmer and the application circuit.
The driver board requires a separate power supply that Programmer
is capable of driving the VPP and VDD pins with the cor- The second consideration is the programmer.
rect rise rates and should also provide enough current PIC16F8X MCUs only use serial programming and
to power the application circuit. RB6 and RB7 are not therefore all programmers supporting these devices
buffered on this schematic but may require buffering will support ICSP. One issue with the programmer is the
depending upon the application. A sample driver board drive capability. As discussed before, it must be able to
schematic is shown in Appendix A. provide the specified rise rates on the ICSP signals and
also provide enough current to power the application
circuit. Appendix A shows an example driver board.
Note: The driver board design MUST be tested
This driver schematic does not show any buffer circuitry
in the user’s application to determine the
for RB6 and RB7. It is recommended that an evalua-
effects of the application circuit on the
tion be performed to determine if buffering is required.
programming signals timing. Changes
Another issue with the programmer is what VDD levels
may be required if the application places
are used to verify the memory contents of the PICmicro
a significant load on Vdd, VPP, RB6 or
MCU. For instance, the PRO MATE II verifies program
RB7.
memory at the minimum and maximum VDD levels for
The Microchip programming specification states that the specified device and is therefore considered a pro-
the device should be programmed at 5V. Special con- duction quality programmer. On the other hand, the
siderations must be made if your application circuit PICSTART® Plus only verifies at 5V and is for prototyp-
operates at 3V only. These considerations may include ing use only. The Microchip programming specifica-
totally isolating the PICmicro MCU during program- tions state that the program memory contents should
ming. The other issue is that the device must be verified be verified at both the minimum and maximum VDD lev-
at the minimum and maximum voltages at which the els that the application circuit will be operating. This
application circuit will be operating. For instance, a bat- implies that the application circuit must be able to han-
tery operated system may operate from three 1.5V dle the varying VDD voltages.

DS91016B-page 2-22  2000 Microchip Technology Inc.

TB016
There are also several third party programmers that are Other Benefits
available. You should select a programmer based on
ICSP provides other benefits, such as calibration and
the features it has and how it fits into your programming
serialization. If program memory permits, it would be
environment. The Microchip Development Systems
cheaper and more reliable to store calibration con-
Ordering Guide (DS30177) provides detailed informa-
stants in program memory instead of using an external
tion on all our development tools. The Microchip Third
serial EEPROM. For example, your system has a ther-
Party Guide (DS00104) provides information on all of
mistor which can vary from one system to another.
our third party tool developers. Please consult these
Storing some calibration information in a table format
two references when selecting a programmer. Many
allows the microcontroller to compensate in software
options exist including serial or parallel PC host con-
for external component tolerances. System cost can be
nection, stand-alone operation, and single or gang pro-
reduced without affecting the required performance of
grammers. Some of the third party developers include
the system by using software calibration techniques.
Advanced Transdata Corporation, BP Microsystems,
But how does this relate to ICSP? The PICmicro MCU
Data I/O, Emulation Technology and Logical Devices.
has already been programmed with firmware that per-
Programming Environment forms a calibration cycle. The calibration data is trans-
The programming environment will affect the type of ferred to a calibration fixture. When all calibration data
programmer used, the programmer cable length, and has been transferred, the fixture places the PICmicro
the application circuit interface. Some programmers MCU in programming mode and programs the
are well suited for a manual assembly line while others PICmicro MCU with the calibration data. Application
are desirable for an automated assembly line. You may note AN656, In-Circuit Serial Programming of Calibra-
want to choose a gang programmer to program multiple tion Parameters Using a PICmicro Microcontroller,
systems at a time. shows exactly how to implement this type of calibration
data programming.
The physical distance between the programmer and
the application circuit affects the load capacitance on The other benefit of ICSP is serialization. Each individ-
each of the programming signals. This will directly ual system can be programmed with a unique or ran-
affect the drive strength needed to provide the correct dom serial number. One such application of a unique
signal rise rates and current. This programming cable serial number would be for security systems. A typical
must also be as short as possible and properly termi- system might use DIP switches to set the serial num-
nated and shielded or the programming signals may be ber. Instead, this number can be burned into program
corrupted by ringing or noise. memory thus reducing the overall system cost and low-
ering the risk of tampering.
Finally, the application circuit interface to the program-
mer depends on the size constraints of the application Field Programming of FLASH PICmicro MCUs
circuit itself and the assembly line. A simple header can With the ISP interface circuitry already in place, these
be used to interface the application circuit to the pro- FLASH-based PICmicro MCUs can be easily repro-
grammer. This might be more desirable for a manual grammed in the field. These FLASH devices allow you
assembly line where a technician plugs the to reprogram them even if they are code protected. A
programmer cable into the board. A different method is portable ISP programming station might consist of a
the use of spring loaded test pins (commonly referred laptop computer and programmer. The technician
to as pogo pins). The application circuit has pads on plugs the ISP interface cable into the application circuit
the board for each of the programming signals. Then and downloads the new firmware into the PICmicro
there is a fixture that has pogo pins in the same config- MCU. The next thing you know the system is up and
uration as the pads on the board. The application circuit running without those annoying “bugs”. Another
or fixture is moved into position such that the pogo pins instance would be that you want to add an additional
come into contact with the board. This method might be feature to your system. All of your current inventory can
more suitable for an automated assembly line. be converted to the new firmware and field upgrades
After taking into consideration the issues with the appli- can be performed to bring your installed base of sys-
cation circuit, the programmer, and the programming tems up to the latest revision of firmware.
environment, anyone can build a high quality, reliable
manufacturing line based on ICSP. CONCLUSION
Microchip Technology Inc. is committed to supporting
your ICSP needs by providing you with our many years
of experience and expertise in developing ICSP
solutions. Anyone can create a reliable ICSP program-
ming station by coupling our background with some
forethought to the circuit design and programmer
selection issues previously mentioned. Your local
Microchip representative is available to answer any
questions you have about the requirements for ICSP.

 2000 Microchip Technology Inc. DS91016B-page 2-23

Vcc

Vcc 15V

EXTERNAL POWER SUPPLY R6

VPP_OUT
TB016

1
R2 Q1 TO CIRCUIT
APPENDIX A:

DS91016B-page 2-24
2N3906
R9
33k 100
1 U1A
U1B 2 R9 Vcc
6 R10 1
7 3
5 100 Q2
100 4 TLE2144A 2N2222
VPP_IN TLE2144A D1
C1 12.7V
FROM 1NF
PROGRAMMER R12
100k R13
5k C3
0.1mF

R15
VDD_OUT
1 TO CIRCUIT
R4 Q3
2N3906
R17
10k 100
9 U1C
U1D R18 Vcc
13 R19 8
14 10
12 TLE2144A 100 Q4
100 2N2222
Vdd_IN TLE2144A D2
C4 6.2V
FROM 1NF
SAMPLE DRIVER BOARD SCHEMATIC

PROGRAMMER R21
100k R22
5k C6
0.1mF

RB6_IN RB6_OUT RB7_IN RB7_OUT

*see text in technical brief. *see text in technical brief.
FROM TO CIRCUIT from To Circuit
PROGRAMMER programmer

Note: The driver board design MUST be tested in the user’s

 2000 Microchip Technology Inc.

SECTION 3
PROGRAMMING SPECIFICATIONS

IN-CIRCUIT SERIAL PROGRAMMING FOR PIC12C5XX OTP MCUs .................................................. 3-1

IN-CIRCUIT SERIAL PROGRAMMING FOR PIC12C67X AND PIC12CE67X OTP MCUs ................. 3-15

IN-CIRCUIT SERIAL PROGRAMMING FOR PIC14000 OTP MCUs ................................................... 3-27

IN-CIRCUIT SERIAL PROGRAMMING FOR PIC16C55X OTP MCUs ................................................ 3-39

IN-CIRCUIT SERIAL PROGRAMMING FOR PIC16C6XX/7XX/9XX OTP MCUsS .............................. 3-51

IN-CIRCUIT SERIAL PROGRAMMING FOR PIC17C7XX OTP MCUs ................................................ 3-71

IN-CIRCUIT SERIAL PROGRAMMING FOR PIC18CXXX OTP MCUs ................................................ 3-97

IN-CIRCUIT SERIAL PROGRAMMING FOR PIC16F62X FLASH MCUs ..........................................3-135

IN-CIRCUIT SERIAL PROGRAMMING FOR PIC16F8X FLASH MCUs ............................................ 3-149

IN-CIRCUIT SERIAL PROGRAMMING FOR PIC16F8XX FLASH MCUs ..........................................3-165

 2000 Microchip Technology Inc. DS30277C-page 3-i

DS30277C-page 3-ii  2000 Microchip Technology Inc.
PIC12C5XX
In-Circuit Serial Programming for PIC12C5XX OTP MCUs
This document includes the programming Pin Diagram
specifications for the following devices: PDIP, SOIC, JW
• PIC12C508 • PIC12C508A • PIC12CE518

PIC12CE5XXA
PIC12C5XXA
PIC12C5XX
• PIC12C509 • PIC12C509A • PIC12CE519 VDD 1 8
VSS
GP5/OSC1/CLKIN 2 7 GP0
GP4/OSC2/CLKOUT 3 6 GP1
1.0 PROGRAMMING THE GP3/MCLR/Vpp 4 5 GP2/T0CKI

PIC12C5XX
The PIC12C5XX can be programmed using a serial
method. Due to this serial programming, the
PIC12C5XX can be programmed while in the user’s
system increasing design flexibility. This programming
specification applies to PIC12C5XX devices in all pack-
ages.

1.1 Hardware Requirements

The PIC12C5XX requires two programmable power
supplies, one for VDD (2.0V to 6.5V recommended) and
one for VPP (12V to 14V). Both supplies should have a
minimum resolution of 0.25V.

1.2 Programming Mode

The programming mode for the PIC12C5XX allows
programming of user program memory, special loca-
tions used for ID, and the configuration word for the
PIC12C5XX.

 2000 Microchip Technology Inc. DS30557E-page 3-1

PIC12C5XX
2.0 PROGRAM MODE ENTRY 5. Verify all locations (using speed verify mode) at
VDD = VDDmin
The program/verify test mode is entered by holding
6. Verify all locations at VDD = VDDmax
pins DB0 and DB1 low while raising MCLR pin from VIL
to VIHH. Once in this test mode the user program mem- VDDmin is the minimum operating voltage spec. for
ory and the test program memory can be accessed and the part. VDDmax is the maximum operating volt-
programmed in a serial fashion. The first selected age spec. for the part.
memory location is the fuses. GP0 and GP1 are
Schmitt trigger inputs in this mode. 2.1.2 SYSTEM REQUIREMENTS

Incrementing the PC once (using the increment Clearly, to implement this technique, the most stringent
address command) selects location 0x000 of the regu- requirements will be that of the power supplies:
lar program memory. Afterwards all other memory loca- VPP: VPP can be a fixed 13.0V to 13.25V supply. It
tions from 0x001-01FF (PIC12C508/CE518), 0x001- must not exceed 14.0V to avoid damage to the pin and
03FF (PIC12C509/CE519) can be addressed by incre- should be current limited to approximately 100mA.
menting the PC.
VDD: 2.0V to 6.5V with 0.25V granularity. Since this
If the program counter has reached the last user pro- method calls for verification at different VDD values, a
gram location and is incremented again, the on-chip programmable VDD power supply is needed.
special EPROM area will be addressed. (See
Figure 2-2 to determine where the special EPROM Current Requirement: 40mA maximum
area is located for the various PIC12C5XX devices). Microchip may release devices in the future with differ-
ent VDD ranges which make it necessary to have a pro-
2.1 Programming Method
grammable VDD.
The programming technique is described in the follow- It is important to verify an EPROM at the voltages
ing section. It is designed to guarantee good program- specified in this method to remain consistent with
ming margins. It does, however, require a variable M i c r o c h i p ' s t e s t s c r e e n i n g . Fo r ex a m p l e , a
power supply for VCC. PIC12C5XX specified for 4.5V to 5.5V should be
2.1.1 PROGRAMMING METHOD DETAILS tested for proper programming from 4.5V to 5.5V.

Essentially, this technique includes the following steps: Note: Any programmer not meeting the programma-
ble VDD requirement and the verify at VDDmax
1. Perform blank check at VDD = VDDmin. Report and VDDmin requirement may only be classi-
failure. The device may not be properly erased. fied as “prototype” or “development” program-
2. Program location with pulses and verify after mer but not a production programmer.
each pulse at VDD = VDDP:
where VDDP = VDD range required during pro- 2.1.3 SOFTWARE REQUIREMENTS
gramming (4.5V - 5.5V).
Certain parameters should be programmable (and
a) Programming condition:
therefore easily modified) for easy upgrade.
VPP = 13.0V to 13.25V
a) Pulse width
VDD = VDDP = 4.5V to 5.5V b) Maximum number of pulses, present limit 8.
VPP must be ≥ VDD + 7.25V to keep “programming c) Number of over-programming pulses: should be
mode” active. = (A • N) + B, where N = number of pulses
b) Verify condition: required in regular programming. In our current
algorithm A = 11, B = 0.
VDD = VDDP
VPP ≥ VDD + 7.5V but not to exceed 13.25V 2.2 Programming Pulse Width
If location fails to program after “N” pulses, (sug- Program Memory Cells: When programming one
gested maximum program pulses of 8) then report word of EPROM, a programming pulse width (TPW) of
error as a programming failure. 100µs is recommended.

Note: Device must be verified at minimum and The maximum number of programming attempts
maximum specified operating voltages as should be limited to 8 per word.
specified in the data sheet. After the first successful verify, the same location
3. Once location passes “Step 2", apply 11X over should be over-programmed with 11X over-program-
programming, i.e., apply 11 times the number of ming.
pulses that were required to program the loca- Configuration Word: The configuration word for oscil-
tion. This will guarantee a solid programming lator selection, WDT (watchdog timer) disable and
margin. The over programming should be made code protection, and MCLR enable, requires a pro-
“software programmable” for easy updates. gramming pulse width (TPWF) of 10ms. A series of
4. Program all locations. 100µs pulses is preferred over a single 10ms pulse.

DS30557E-page 3-2  2000 Microchip Technology Inc.

PIC12C5XX
FIGURE 2-1: PROGRAMMING METHOD FLOWCHART

Start

Blank Check
@ VDD = VDDmin

Report Possible Erase Failure

Continue Programming
No at user’s option
Pass?

Report Programming Failure

Yes Yes

Program 1 Location No
@ VPP = 13.0V to 13.25V N > 8?
VDD = VDDP

No
N=N+1
Pass? (N = # of program pulses)

Yes

Increment PC to point to Apply 11N additional

next location, N = 0 program pulses

All
locations
No done?

Yes

Verify all locations

@ VDD = VDDmin

No
Pass? Report verify failure
@ VDDmin

Yes

Verify all locations

@VV
DD DD= =
VDDVDDmax.
max

No
Report verify failure
Pass? @ VDDmax

Yes
Now program Verify Configuration Word
Configuration Word @ VDDmax & VDDmin

Done

 2000 Microchip Technology Inc. DS30557E-page 3-3

PIC12C5XX
FIGURE 2-2: PIC12C5XX SERIES PROGRAM MEMORY MAP IN PROGRAM/VERIFY MODE
Address 11 Bit Number 0
(Hex) 000

User Program Memory

(NNN + 1) x 12 bit
NNN

TTT 0 0 ID0
TTT + 1 0 0 ID1 For Customer Use
(4 x 4 bit usable)
TTT + 2 0 0 ID2
TTT + 3 0 0 ID3

For Factory Use

TTT + 3F

(FFF) Configuration Word 5 bits

NNN Highest normal EPROM memory address. NNN = 0x1FF for PIC12C508/CE518.
NNN = 0x3FF for PIC12C509/CE519.
Note that some versions will have an oscillator calibration value programmed at NNN
TTT Start address of special EPROM area and ID locations.

DS30557E-page 3-4  2000 Microchip Technology Inc.

PIC12C5XX
2.3 Special Memory Locations 2.4 Program/Verify Mode
The highest address of program memory space is The program/verify mode is entered by holding pins
reserved for the internal RC oscillator calibration value. GP1 and GP0 low while raising MCLR pin from VIL to
This location should not be overwritten except when VIHH (high voltage). Once in this mode the user pro-
this location is blank, and it should be verified, when gram memory and the configuration memory can be
programmed, that it is a MOVLW XX instruction. accessed and programmed in serial fashion. The mode
The ID Locations area is only enabled if the device is in of operation is serial. GP0 and GP1 are Schmitt Trigger
programming/verify mode. Thus, in normal operation inputs in this mode.
mode only the memory location 0x000 to 0xNNN will be The sequence that enters the device into the program-
accessed and the Program Counter will just roll over ming/verify mode places all other logic into the reset
from address 0xNNN to 0x000 when incremented. state (the MCLR pin was initially at VIL). This means
The configuration word can only be accessed immedi- that all I/O are in the reset state (High impedance
ately after MCLR going from VIL to VHH. The Program inputs).
Counter will be set to all ’1’s upon MCLR = VIL. Thus, Note: The MCLR pin should be raised from VIL to
it has the value “0xFFF” when accessing the configura- VIHH within 9 ms of VDD rise. This is to
tion EPROM. Incrementing the Program Counter once ensure that the device does not have the
causes the Program Counter to roll over to all '0's. PC incremented while in valid operation
Incrementing the Program Counter 4K times after reset range.
(MCLR = VIL) does not allow access to the configura-
tion EPROM.

2.3.1 CUSTOMER ID CODE LOCATIONS

Per definition, the first four words (address TTT to TTT

+ 3) are reserved for customer use. It is recommended
that the customer use only the four lower order bits (bits
0 through 3) of each word and filling the eight higher
order bits with '0's.
A user may want to store an identification code (ID) in
the ID locations and still be able to read this code after
the code protection bit was programmed.

EXAMPLE 2-1: CUSTOMER CODE 0xD1E2

The Customer ID code “0xD1E2” should be stored in
the ID locations 0x200-0x203 like this (PIC12C508/
508A/CE518):
200: 0000 0000 1101
201: 0000 0000 0001
202: 0000 0000 1110
203: 0000 0000 0010
Reading these four memory locations, even with the
code protection bit programmed would still output on
GP0 the bit sequence “1101”, “0001”, “1110”, “0010”
which is “0xD1E2”.
Note: All other locations in PICmicro® MCU con-
figuration memory are reserved and
should not be programmed.

 2000 Microchip Technology Inc. DS30557E-page 3-5

PIC12C5XX
2.4.1 PROGRAM/VERIFY OPERATION All commands are transmitted LSB first. Data words
are also transmitted LSB first. The data is transmitted
The GP1 pin is used as a clock input pin, and the GP0 on the rising edge and latched on the falling edge of the
pin is used for entering command bits and data input/ clock. To allow for decoding of commands and reversal
output during serial operation. To input a command, the of data pin configuration, a time separation of at least 1
clock pin (GP1) is cycled six times. Each command bit µs is required between a command and a data word (or
is latched on the falling edge of the clock with the least another command).
significant bit (LSB) of the command being input first.
The data on pin GP0 is required to have a minimum The commands that are available are listed in Table .
setup and hold time (see AC/DC specs) with respect to
the falling edge of the clock. Commands that have data
associated with them (read and load) are specified to
have a minimum delay of 1 µs between the command
and the data. After this delay the clock pin is cycled 16
times with the first cycle being a start bit and the last
cycle being a stop bit. Data is also input and output LSB
first. Therefore, during a read operation the LSB will be
transmitted onto pin GP0 on the rising edge of the sec-
ond cycle, and during a load operation the LSB will be
latched on the falling edge of the second cycle. A min-
imum 1 µs delay is also specified between consecutive
commands.

TABLE 2-1: COMMAND MAPPING

Command Mapping (MSB ... LSB) Data
Load Data 0 0 0 0 1 0 0, data(14), 0
Read Data 0 0 0 1 0 0 0, data(14), 0
Increment Address 0 0 0 1 1 0
Begin programming 0 0 1 0 0 0
End Programming 0 0 1 1 1 0
Note: The clock must be disabled during in-circuit programming.

DS30557E-page 3-6  2000 Microchip Technology Inc.

PIC12C5XX
2.4.1.1 LOAD DATA 2.5 Programming Algorithm Requires
Variable VDD
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as The PIC12C5XX uses an intelligent algorithm. The
described previously. Because this is a 12 bit core, the algorithm calls for program verification at VDDmin as
two msb’s of the data word are ignored. A timing dia- well as VDDmax. Verification at VDDmin guarantees
gram for the load data command is shown in good “erase margin”. Verification at VDDmax guaran-
Figure 5-1. tees good “program margin”.
2.4.1.2 READ DATA The actual programming must be done with VDD in the
VDDP range (4.75 - 5.25V).
After receiving this command, the chip will transmit
VDDP = VCC range required during programming.
data bits out of the memory currently accessed starting
with the second rising edge of the clock input. The GP0 VDD min. = minimum operating VDD spec for the part.
pin will go into output mode on the second rising clock VDDmax = maximum operating VDD spec for the part.
edge, and it will revert back to input mode (hi-imped-
Programmers must verify the PIC12C5XX at its speci-
ance) after the 16th rising edge. Because this is a 12-
fied VDDmax and VDDmin levels. Since Microchip may
bit core, the two MSB’s of the data are unused and read
introduce future versions of the PIC12C5XX with a
as ’0’. A timing diagram of this command is shown in
broader VDD range, it is best that these levels are user
Figure 5-2.
selectable (defaults are ok).
2.4.1.3 INCREMENT ADDRESS Note: Any programmer not meeting these
The PC is incremented when this command is requirements may only be classified as
received. A timing diagram of this command is shown “prototype” or “development” programmer
in Figure 5-3. but not a “production” quality programmer.

2.4.1.4 BEGIN PROGRAMMING

A load data command must be given before every

begin programming command. Programming of the
appropriate memory (test program memory or user
program memory) will begin after this command is
received and decoded. Programming should be per-
formed with a series of 100µs programming pulses. A
programming pulse is defined as the time between the
begin programming command and the end program-
ming command.

2.4.1.5 END PROGRAMMING

After receiving this command, the chip stops program-

ming the memory (configuration program memory or
user program memory) that it was programming at the
time.

 2000 Microchip Technology Inc. DS30557E-page 3-7

PIC12C5XX
3.0 CONFIGURATION WORD
The PIC12C5XX family members have several config-
uration bits. These bits can be programmed (reads ’0’)
or left unprogrammed (reads ’1’) to select various
device configurations. Figure 3-1 provides an overview
of configuration bits.

FIGURE 3-1: CONFIGURATION WORD BIT MAP

Bit 6 5 4 3 2 1 0
Number:
11 10 9 8 7
PIC12C5XX — — — — — — — MCLRE CP WDTE FOSC1 FOSC0
bit 11-5:Reserved, '–' write as '0' for PIC12C5XX
bit 4: MCLRE, Master Clear pin Enable Bit
0 = MCLR internally connected to Vdd
1 = MCLR pin enabled
bit 3: CP, Code Protect Enable Bit
1 = Code Memory Unprotected
0 = Code Memory Protected
bit 2: WDTE, WDT Enable Bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC<1:0>, Oscillator Selection Bit
11: ExtRC oscillator
10: IntRC oscillator
01: XT oscillator
00: LP oscillator

DS30557E-page 3-8  2000 Microchip Technology Inc.

PIC12C5XX
4.0 CODE PROTECTION segments, including ID locations and configuration
word, read normally. These locations can be pro-
The program code written into the EPROM can be programmed.
tected by writing to the CP bit of the configuration word.
Once code protection is enabled, all code protected
In PIC12C5XX, it is still possible to program and read locations read 0’s. All unprotected segments, including
locations 0x000 through 0x03F, after code protection. the internal oscillator calibration value, ID, and configu-
Once code protection is enabled, all protected seg- ration word read as normal.
ments read '0's (or “garbage values”) and are pre-
vented from further programming. All unprotected

4.1 Embedding Configuration Word and ID Information in the Hex File

To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex
file when loading the hex file. If configuration word information was not present in the hex file then a simple warning
message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included.
An option to not include this information may be provided.
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.

TABLE 4-1: CODE PROTECTION

PIC12C508
To code protect:
• (CP enable pattern: XXXXXXXX0XXX)
Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode
Configuration Word (0xFFF) Read Enabled, Write Enabled Read Enabled, Write Enabled
[0x00:0x3F] Read Enabled, Write Enabled Read Enabled, Write Enabled
[0x40:0x1FF] Read Disabled (all 0’s), Write Disabled Read Enabled, Write Enabled
ID Locations (0x200 : 0x203) Read Enabled, Write Enabled Read Enabled, Write Enabled

PIC12C508A
To code protect:
• (CP enable pattern: XXXXXXXX0XXX)

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled
[0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled
[0x40:0x1FE] Read disabled (all 0’s), Write Disabled Read enabled, Write Enabled
0x1FF Oscillator Calibration Value Read enabled, Write Enabled Read enabled, Write Enabled
ID Locations (0x200 : 0x203) Read enabled, Write Enabled Read enabled, Write Enabled
PIC12C509
To code protect:
• (CP enable pattern: XXXXXXXX0XXX))

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled
[0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled
[0x40:0x3FF] Read disabled (all 0’s), Write Disabled Read enabled, Write Enabled
ID Locations (0x400 : 0x403) Read enabled, Write Enabled Read enabled, Write Enabled

 2000 Microchip Technology Inc. DS30557E-page 3-9

PIC12C5XX
PIC12C509A
To code protect:
• (CP enable pattern: XXXXXXXX0XXX))
Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode
Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled
[0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled
[0x40:0x3FE] Read disabled (all 0’s), Write Disabled Read enabled, Write Enabled
0x3FF Oscillator Calibration Value Read enabled, Write Enabled Read enabled, Write Enabled
ID Locations (0x400 : 0x403) Read enabled, Write Enabled Read enabled, Write Enabled

PIC12CE518
To code protect:
• (CP enable pattern: XXXXXXXX0XXX)
Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode
Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled
[0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled
[0x40:0x1FE] Read disabled (all 0’s), Write Disabled Read enabled, Write Enabled
0x1FF Oscillator Calibration Value Read enabled, Write Enabled Read enabled, Write Enabled
ID Locations (0x200 : 0x203) Read enabled, Write Enabled Read enabled, Write Enabled

PIC12CE519
To code protect:
• (CP enable pattern: XXXXXXXX0XXX))
Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode
Configuration Word (0xFFF) Read enabled, Write Enabled Read enabled, Write Enabled
[0x00:0x3F] Read enabled, Write Enabled Read enabled, Write Enabled
[0x40:0x3FF] Read disabled (all 0’s), Write Disabled Read enabled, Write Enabled
ID Locations (0x400 : 0x403) Read enabled, Write Enabled Read enabled, Write Enabled

DS30557E-page 3-10  2000 Microchip Technology Inc.

PIC12C5XX
4.2 Checksum The following table describes how to calculate the
checksum for each device. Note that the checksum cal-
4.2.1 CHECKSUM CALCULATIONS culation differs depending on the code protect setting.
Since the program memory locations read out differ-
Checksum is calculated by reading the contents of the
ently depending on the code protect setting, the table
PIC12C5XX memory locations and adding up the
describes how to manipulate the actual program mem-
opcodes up to the maximum user addressable location,
ory values to simulate the values that would be read
(not including the last location which is reserved for the
from a protected device. When calculating a checksum
oscillator calibration value) e.g., 0x1FE for the
by reading a device, the entire program memory can
PIC12C508/CE518. Any carry bits exceeding 16-bits
simply be read and summed. The configuration word
are neglected. Finally, the configuration word (appropri-
and ID locations can always be read.
ately masked) is added to the checksum. Checksum
computation for each member of the PIC12C5XX fam- The oscillator calibration value location is not used in
ily is shown in Table 4-2. the above checksums.
The checksum is calculated by summing the following:
• The contents of all program memory locations
• The configuration word, appropriately masked
• Masked ID locations (when applicable)
The least significant 16 bits of this sum is the check-
sum.

TABLE 4-2: CHECKSUM COMPUTATION

0x723 at
Code Blank
Device Checksum* 0 and max
Protect Value
address
PIC12C508 OFF SUM[0x000:0x1FE] + CFGW & 0x01F EE20 DC68
ON SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EDF7 D363
PIC12C508A OFF SUM[0x000:0x1FE] + CFGW & 0x01F EE20 DC68
ON SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EDF7 D363
PIC12C509 OFF SUM[0x000:0x3FE] + CFGW & 0x01F EC20 DA68
ON SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EBF7 D163
PIC12C509A OFF SUM[0x000:0x3FE] + CFGW & 0x01F EC20 DA68
ON SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EBF7 D163
PIC12CE518 OFF SUM[0x000:0x1FE] + CFGW & 0x01F EE20 DC68
ON SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EDF7 D363
PIC12CE519 OFF SUM[0x000:0x3FE] + CFGW & 0x01F EC20 DA68
ON SUM[0x000:0x03F] + CFGW & 0x01F + SUM(IDS) EBF7 D163
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble.
For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND

 2000 Microchip Technology Inc. DS30557E-page 3-11

PIC12C5XX
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 5-1: AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +40°C, unless otherwise stated, (20°C recommended)
Operating Voltage: 4.5V ≤ VDD ≤ 5.5V, unless otherwise stated.

Parameter
Sym. Characteristic Min. Typ. Max. Units Conditions
No.
General
PD1 VDDP Supply voltage during programming 4.75 5.0 5.25 V
PD2 IDDP Supply current (from VDD) 20 mA
during programming
PD3 VDDV Supply voltage during verify VDDmin VDDmax V Note 1
PD4 VIHH1 Voltage on MCLR/VPP during 12.75 13.25 V Note 2
programming
PD5 VIHH2 Voltage on MCLR/VPP during verify VDD + 4.0 13.5
PD6 IPP Programming supply current (from 50 mA
VPP)
PD9 VIH1 (GP1, GP0) input high level 0.8 VDD V Schmitt Trigger input
PD8 VIL1 (GP1, GP0) input low level 0.2 VDD V Schmitt Trigger input

Serial Program Verify

P1 TR MCLR/VPP rise time (VSS to VHH) 8.0 µs
P2 Tf MCLR Fall time 8.0 µs
P3 Tset1 Data in setup time before clock ↓ 100 ns
P4 Thld1 Data in hold time after clock ↓ 100 ns
P5 Tdly1 Data input not driven to next clock 1.0 µs
input (delay required between com-
mand/data or command/command)
P6 Tdly2 Delay between clock ↓ to clock ↑ of 1.0 µs
next command or data
P7 Tdly3 Clock ↑ to date out valid 200 ns
(during read data)
P8 Thld0 Hold time after MCLR ↑ 2 µs
Note 1: Program must be verified at the minimum and maximum VDD limits for the part.
2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.

DS30557E-page 3-12  2000 Microchip Technology Inc.

PIC12C5XX
FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY)
VIHH
MCLR/VPP
100ns P6
P8
1 2 3 4 5 6 1ms min. 1 2 3 4 5 15
GP1
(CLOCK)
100ns
GP0 0 0 0 0
(DATA) 1 0 0 0
P5
P3 P4
P4 1ms min. P3

}
}
}

}
100ns 100ns
min. min.
Program/Verify Mode
Reset

FIGURE 5-2: READ DATA COMMAND (PROGRAM/VERIFY)

VIHH
MCLR/VPP 100ns P6
P8
1 2 3 4 5 6 1ms min. 1 2 3 4 5 15
GP1
(CLOCK)
100ns P7
GP0 0 0 1 0 0 0
(DATA) P5
P4
P3 1ms min.
}
}

100ns
min. GP0
GP0 = output input

Program/Verify Mode
Reset

FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

VIHH
MCLR/VPP
P6
Next Command
1ms min.
1 2 3 4 5 6 1 2
GP1
(CLOCK)

GP0
0 1 1 0 0 0 0 0
(DATA)
P5
P3 P4 1ms min.
}
}

100ns
min
Program/Verify Mode
Reset

 2000 Microchip Technology Inc. DS30557E-page 3-13

PIC12C5XX

DS30557E-page 3-14  2000 Microchip Technology Inc.

PIC12C67X AND PIC12CE67X
In-Circuit Serial Programming for PIC12C67X and PIC12CE67X OTP MCUs

This document includes the programming Pin Diagram:

specifications for the following devices:
PDIP, SOIC, JW
• PIC12C671
• PIC12C672

PIC12C67X
VDD 1 8 VSS
• PIC12CE673 GP5/OSC1/CLKIN 2 7 GP0/AN0
GP4/OSC2/AN3/
• PIC12CE674 CLKOUT 3 6 GP1/AN1/VREF
GP3/MCLR/VPP 4 5 GP2/T0CKI/
AN2/INT
1.0 PROGRAMMING THE
PIC12C67X AND PIC12CE67X
PDIP, JW
The PIC12C67X and PIC12CE67X can be pro-
grammed using a serial method. In serial mode the

PIC12CE67X
VDD 1 8 VSS
PIC12C67X and PIC12CE67X can be programmed GP5/OSC1/CLKIN 2 7 GP0/AN0
while in the users system. This allows for increased GP4/OSC2/AN3/
CLKOUT 3 6 GP1/AN1/VREF
design flexibility. GP3/MCLR/VPP 4 5 GP2/T0CKI/
AN2/INT
1.1 Hardware Requirements
The PIC12C67X and PIC12CE67X requires two pro-
grammable power supplies, one for VDD (2.0V to 6.0V
recommended) and one for VPP (12V to 14V). Both
supplies should have a minimum resolution of 0.25V.

1.2 Programming Mode

The programming mode for the PIC12C67X and
PIC12CE67X allows programming of user program
memory, special locations used for ID, and the configu-
ration word for the PIC12C67X and PIC12CE67X.

 2000 Microchip Technology Inc. DS40175B-page 3-15

PIC12C67X and PIC12CE67X
2.0 PROGRAM MODE ENTRY
2.1 User Program Memory Map
The user memory space extends from 0x0000 to
0x1FFF (8K). Table 2-1 shows actual implementation
of program memory in the PIC12C67X family.

TABLE 2-1: IMPLEMENTATION OF

PROGRAM MEMORY IN THE
PIC12C67X
Device Program Memory Size
PIC12C671/ 0x000 - 0x3FF (1K)
PIC12CE673
PIC12C672/ 0x000 - 0x7FF (2K)
PIC12CE674

When the PC reaches the last location of the imple-

mented program memory, it will wrap around and
address a location within the physically implemented
memory (see Figure 2-1).
In programming mode the program memory space
extends from 0x0000 to 0x3FFF, with the first half
(0x0000-0x1FFF) being user program memory and the
second half (0x2000-0x3FFF) being configuration
memory. The PC will increment from 0x0000 to 0x1FFF
and wrap to 0x000 or 0x2000 to 0x3FFF and wrap
around to 0x2000 (not to 0x0000). Once in configura-
tion memory, the highest bit of the PC stays a ’1’, thus
always pointing to the configuration memory. The only
way to point to user program memory is to reset the
part and reenter program/verify mode, as described in
Section 2.2.
The last location of the program memory space holds
the factory programmed oscillator calibration value.
This location should not be programmed except when
blank (a non-blank value should not cause the device to
fail a blank check). If blank, the programmer should pro-
gram it to a RETLW XX statement where “XX” is the
calibration value.
In the configuration memory space, 0x2000-0x20FF
are utilized. When in configuration memory, as in the
user memory, the 0x2000-0x2XFF segment is repeat-
edly accessed as the PC exceeds 0x2XFF (see
Figure 2-1).
A user may store identification information (ID) in four
ID locations. The ID locations are mapped in [0x2000:
0x2003].
Note 1: All other locations in PICmicro® MCU con-
figuration memory are reserved and should
not be programmed.
2: Due to the secure nature of the on-board
EEPROM memory in the PIC12CE673/674,
it can be accessed only by the user pro-
gram.

DS40175B-page 3-16  2000 Microchip Technology Inc.

PIC12C67X and PIC12CE67X
FIGURE 2-1: PROGRAM MEMORY MAPPING

2000 ID Location
0 1KW 2KW
1FF
3FF Implemented Implemented
2001 ID Location
400
7FF Implemented
2002 ID Location
800

2003 ID Location BFF

C00
2004 Reserved FFF
1000
2005 Reserved

2006 Reserved Reserved

Reserved
2007 Configuration Word

1FFF
2000
2008
Reserved Reserved
2100

Reserved Reserved

3FFF

 2000 Microchip Technology Inc. DS40175B-page 3-17

PIC12C67X and PIC12CE67X
2.2 Program/Verify Mode 2.2.1 PROGRAM/VERIFY OPERATION

The program/verify mode is entered by holding pins The GP1 pin is used as a clock input pin, and the GP0
GP1 and GP0 low while raising MCLR pin from VIL to pin is used for entering command bits and data input/
VIHH (high voltage). VDD is then raised from VIL to output during serial operation. To input a command, the
VIH.Once in this mode the user program memory and clock pin (GP1) is cycled six times. Each command bit
the configuration memory can be accessed and pro- is latched on the falling edge of the clock with the least
grammed in serial fashion. The mode of operation is significant bit (LSB) of the command being input first.
serial, and the memory that is accessed is the user pro- The data on pin GP0 is required to have a minimum
gram memory. GP1 is a Schmitt Trigger input in this setup and hold time (see AC/DC specs) with respect to
mode. the falling edge of the clock. Commands that have data
associated with them (read and load) are specified to
The sequence that enters the device into the program-
have a minimum delay of 1µs between the command
ming/verify mode places all other logic into the reset
and the data. After this delay the clock pin is cycled 16
state (the MCLR pin was initially at VIL). This means
times with the first cycle being a start bit and the last
that all I/O are in the reset state (High impedance
cycle being a stop bit. Data is also input and output LSB
inputs).
first. Therefore, during a read operation the LSB will be
Note 1:The MCLR pin must be raised from VIL transmitted onto pin GP0 on the rising edge of the sec-
to VIHH before VDD is applied. This is to ond cycle, and during a load operation the LSB will be
ensure that the device does not have the latched on the falling edge of the second cycle. A min-
PC incremented while in valid operation imum 1µs delay is also specified between consecutive
range. commands.
Note 2:Do not power GP2, GP4 or GP5 All commands are transmitted LSB first. Data words
before VDD is applied. are also transmitted LSB first. The data is transmitted
on the rising edge and latched on the falling edge of the
clock. To allow for decoding of commands and reversal
of data pin configuration, a time separation of at least
1µs is required between a command and a data word
(or another command).
The commands that are available are listed in Table .

2.2.1.1 LOAD CONFIGURATION

After receiving this command, the program counter

(PC) will be set to 0x2000. By then applying 16 cycles
to the clock pin, the chip will load 14-bits a “data word”
as described above, to be programmed into the config-
uration memory. A description of the memory mapping
schemes for normal operation and configuration mode
operation is shown in Figure 2-1. After the configura-
tion memory is entered, the only way to get back to the
user program memory is to exit the program/verify test
mode by taking MCLR low (VIL).

TABLE 1-1: COMMAND MAPPING

Command Mapping (MSB ... LSB) Data
Load Configuration 0 0 0 0 0 0 0, data(14), 0
Load Data 0 0 0 0 1 0 0, data(14), 0
Read Data 0 0 0 1 0 0 0, data(14), 0
Increment Address 0 0 0 1 1 0
Begin programming 0 0 1 0 0 0
End Programming 0 0 1 1 1 0

DS40175B-page 3-18  2000 Microchip Technology Inc.

PIC12C67X and PIC12CE67X
FIGURE 2-2: PROGRAM FLOW CHART - PIC12C67X AND PIC12CE67X PROGRAM MEMORY

Start

Set VPP = VIHH1

Set VDD = VDDP•

N=0

No
Yes Report Programming
Program Cycle N > 25 Failure

Read Data
Command N=N+1
N = # of Program Cycles

No
Increment Address
Command Data Correct?

Yes
Program Cycle
Apply 3N Additional
Program Cycles Load Data
Command

No
All Locations Done?
Begin Programming
Command
Yes

Verify all Locations

@ VDD MIN.•
VPP = VIHH2 Wait 100 µs

No Report Verify
Data Correct? @ VDD MIN. Error End Programming
Command
Yes

Verify all Locations

@ VDD MAX.
VPP = VIHH2

No
Report Verify
Data Correct? @ VDD MAX Error

Yes

Done

• VDDP = VDD range for programming (typically 4.75V - 5.25V).

VDD MIN. = Minimum VDD for device operation.
VDD MAX. = Maximum VDD for device operation.

 2000 Microchip Technology Inc. DS40175B-page 3-19

PIC12C67X and PIC12CE67X
FIGURE 2-3: PROGRAM FLOW CHART - PIC12C67X AND PIC12CE67X CONFIGURATION WORD
& ID LOCATIONS

Start

Set VPP = VIHH1

Load Configuration
Command

N=0

No Yes Read Data

Program ID Loc? Program Cycle Command

Increment Address No
Command N=N+1
N = # of Program Data Correct?
Cycles
Yes
No
Address = 2004 No
N > 25
Yes
Yes
Increment Address
Command ID/Configuration Apply 3N
Error Program Cycles

Increment Address
Command

Increment Address Program Cycle Read Data

Command 100 Cycles Command

No
Data Correct?

Yes

No Set VDD = VVDD

DDmin
min
Report Program Data Correct?
ID/Config. Error Read Data Command
Set VPP = VIHH2
Yes
No
Yes Set VDD = VVDD
DDmax
max
Done Data Correct? Read Data Command
Set VPP = VIHH2

DS40175B-page 3-20  2000 Microchip Technology Inc.

PIC12C67X and PIC12CE67X
2.2.1.2 LOAD DATA 2.3 Programming Algorithm Requires
Variable VDD
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as The PIC12C67X and PIC12CE67X uses an intelligent
described previously. A timing diagram for the load data algorithm. The algorithm calls for program verification
command is shown in Figure 5-1. at VDDmin as well as VDDmax. Verification at VDDmin
guarantees good “erase margin”. Verification at
2.2.1.3 READ DATA
VDDmax guarantees good “program margin”.
After receiving this command, the chip will transmit The actual programming must be done with VDD in the
data bits out of the memory currently accessed starting VDDP range (4.75 - 5.25V).
with the second rising edge of the clock input. The GP0
VDDP = VCC range required during programming.
pin will go into output mode on the second rising clock
edge, and it will revert back to input mode (hi-imped- VDD min. = minimum operating VDD spec for the part.
ance) after the 16th rising edge. A timing diagram of VDD max.= maximum operating VDD spec for the part.
this command is shown in Figure 5-2.
Programmers must verify the PIC12C67X and
2.2.1.4 INCREMENT ADDRESS PIC12CE67X at its specified VDDmax and VDDmin lev-
els. Since Microchip may introduce future versions of
The PC is incremented when this command is the PIC12C67X and PIC12CE67X with a broader VDD
received. A timing diagram of this command is shown range, it is best that these levels are user selectable
in Figure 5-3. (defaults are ok).

2.2.1.5 BEGIN PROGRAMMING Note: Any programmer not meeting these

requirements may only be classified as
A load command (load configuration or load data) “prototype” or “development” programmer
must be given before every begin programming but not a “production” quality programmer.
command. Programming of the appropriate memory
(test program memory or user program memory) will
begin after this command is received and decoded.
Programming should be performed with a series of
100µs programming pulses. A programming pulse is
defined as the time between the begin programming
command and the end programming command.

2.2.1.6 END PROGRAMMING

After receiving this command, the chip stops program-

ming the memory (configuration program memory or
user program memory) that it was programming at the
time.

 2000 Microchip Technology Inc. DS40175B-page 3-21

PIC12C67X and PIC12CE67X
3.0 CONFIGURATION WORD select various device configurations. Figure 3-1 pro-
vides an overview of configuration bits.
The PIC12C67X and PIC12CE67X family members
have several configuration bits. These bits can be pro-
grammed (reads ’0’) or left unprogrammed (reads ’1’) to

FIGURE 3-1: CONFIGURATION WORD

Bit Number:
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Register: CONFIG
CP1 CP0 CP1 CP0 CP1 CP0 MCLRE CP1 CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0
Address 2007h

bit 13-8, 6-5: CP1:CP0: Code Protection bits (1) (2)

11 = Code protection off
10 = 0400h-07FFh code protected;
01 = 0200h-07FFh code protected;
00 = 0000h-07FFh code protected;
bit 7: MCLRE: GP3/MCLR pin function select
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to Vdd
bit 4: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 3: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0: FOSC2:FOSC0: Oscillator Selection bits
111 = EXTRC oscillator / CLKOUT function on GP4/OSC2/CLKOUT pin
110 = EXTRC oscillator / GP4 function on GP4/OSC2/CLKOUT pin
101 = INTRC oscillator / CLKOUT function on GP4/OSC2/CLKOUT pin
100 = INTRC oscillator / GP4 function on GP4/OSC2/CLKOUT pin
011 = invalid selection
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
3: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
4: 07FFh is always uncode protected on the 12C672 and 03FFh is always uncode protected on the 12C671. This location
contains the RETLW xx calibration instruction for the INTRC.

DS40175B-page 3-22  2000 Microchip Technology Inc.

PIC12C67X and PIC12CE67X
4.0 CODE PROTECTION
The program code written into the EPROM can be pro-
tected by writing to the CP0 & CP1 bits of the configu-
ration word.
For PIC12C67X and PIC12CE67X devices, once code
protection is enabled, all protected segments read ’0’s
(or “garbage values”) and are prevented from further
programming. All unprotected segments, including ID
and configuration word locations, and calibration word
location read normally and can be programmed.

4.1 Embedding Configuration Word and ID Information in the Hex File

TABLE 1-2: CONFIGURATION WORD

PIC12C671, PIC12CE673
To code protect:
• Protect all memory 00 0000 X00X XXXX
• Protect 0200h-07FFh 01 0101 X01X XXXX
• No code protection 11 1111 X11X XXXX
Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode
Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Unprotected memory segment Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Protected memory segment Read All 0’s, Write Disabled Read Unscrambled, Write Enabled
ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
INTRC Calibration Word (0X3FF) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled

PIC12C672, PIC12CE674
To code protect:
• Protect all memory 00 0000 X00X XXXX
• Protect 0200h-07FFh 01 0101 X01X XXXX
• Protect 0400h-07FFh 10 1010 X10X XXXX
• No code protection 11 1111 X11X XXXX
Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode
Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Unprotected memory segment Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Protected memory segment Read All 0’s, Write Disabled Read Unscrambled, Write Enabled
ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
INTRC Calibration Word (0X7FF) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled

 2000 Microchip Technology Inc. DS40175B-page 3-23

PIC12C67X and PIC12CE67X
4.2 Checksum • Masked ID locations (when applicable)
The least significant 16 bits of this sum is the check-
4.2.1 CHECKSUM CALCULATIONS
sum.
Checksum is calculated by reading the contents of the The following table describes how to calculate the
PIC12C67X and PIC12CE67X memory locations and checksum for each device. Note that the checksum cal-
adding the opcodes up to the maximum user address- culation differs depending on the code protect setting.
able location, excluding the oscillator calibration loca- Since the program memory locations read out differ-
tion in the last address, e.g., 0x3FE for the PIC12C671/ ently depending on the code protect setting, the table
CE673. Any carry bits exceeding 16-bits are neglected. describes how to manipulate the actual program mem-
Finally, the configuration word (appropriately masked) ory values to simulate the values that would be read
is added to the checksum. Checksum computation for from a protected device. When calculating a checksum
each member of the PIC12C67X and PIC12CE67X by reading a device, the entire program memory can
devices is shown in Table 4-1. simply be read and summed. The configuration word
The checksum is calculated by summing the following: and ID locations can always be read.
• The contents of all program memory locations Note that some older devices have an additional value
• The configuration word, appropriately masked added in the checksum. This is to maintain compatibil-
ity with older device programmer checksums.
TABLE 4-1: CHECKSUM COMPUTATION
Ox25E6 at
Code Blank
Device Checksum* 0 and max
Protect Value
address
PIC12C671 OFF SUM[0x000:0x3FE] + CFGW & 0x3FFF 3B3F 070D
PIC12CE673 1/2 SUM[0x000:0x1FF] + CFGW & 0x3FFF + SUM_ID 4E5E 0013
ALL CFGW & 0x3FFF + SUM_ID 3B4E 071C
PIC12C672 OFF SUM[0x000:0x7FE] + CFGW & 0x3FFF 373F 030D
PIC12CE674 1/2 SUM[0x000:0x3FF] + CFGW & 0x3FFF + SUM_ID 5D6E 0F23
3/4 SUM[0x000:0x1FF] + CFGW & 0x3FFF + SUM_ID 4A5E FC13
ALL CFGW & 0x3FFF + SUM_ID 374E 031C
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble.
For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND

DS40175B-page 3-24  2000 Microchip Technology Inc.

PIC12C67X and PIC12CE67X
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 1-3: AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +40°C, unless otherwise stated, (25°C is recommended)
Operating Voltage: 4.5V ≤ VDD ≤ 5.5V, unless otherwise stated.

Parameter
Sym. Characteristic Min. Typ. Max. Units Conditions
No.
General
PD1 VDDP Supply voltage during programming 4.75 5.0 5.25 V
PD2 IDDP Supply current (from VDD) 20 mA
during programming
PD3 VDDV Supply voltage during verify VDDmin VDDmax V Note 1
PD4 VIHH1 Voltage on MCLR/VPP during 12.75 13.25 V Note 2
programming
PD5 VIHH2 Voltage on MCLR/VPP during verify VDD + 4.0 13.5
PD6 IPP Programming supply current (from 50 mA
VPP)
PD9 VIH1 (GP0, GP1) input high level 0.8 VDD V Schmitt Trigger input
PD8 VIL1 (GP0, GP1) input low level 0.2 VDD V Schmitt Trigger input

Serial Program Verify

P1 TR MCLR/VPP rise time (VSS to VIHH) 8.0 µs
for test mode entry
P2 Tf MCLR Fall time 8.0 µs
P3 Tset1 Data in setup time before clock ↓ 100 ns
P4 Thld1 Data in hold time after clock ↓ 100 ns
P5 Tdly1 Data input not driven to next clock 1.0 µs
input (delay required between com-
mand/data or command/command)
P6 Tdly2 Delay between clock ↓ to clock ↑ of 1.0 µs
next command or data
P7 Tdly3 Clock ↑ to data out valid 200 ns
(during read data)
P8 Thld0 Hold time after VDD↑ 2 µs
P9 TPPDP Hold time after VPP↑ 5 µs
Note 1: Program must be verified at the minimum and maximum VDD limits for the part.
2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.

 2000 Microchip Technology Inc. DS40175B-page 3-25

PIC12C67X and PIC12CE67X
FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY)
VDD
P9
VIHH
MCLR/VPP
100ns P6
P8 1 2 3 4 5 6 1 2 3 4 5 15
1µs min.
GP1
(CLOCK)
100ns
GP0 0 0 0 0
(DATA) 1 0 0 0
P5
P3
P4
P4 1µs min. P3

}
}
}

}
100ns 100ns
min. min.
Program/Verify Mode
Reset

FIGURE 5-2: READ DATA COMMAND (PROGRAM/VERIFY)

VDD
P9
VIHH
MCLR/V PP 100ns P6
P8
1 2 3 4 5 6 1µs min. 1 2 3 4 5 15
GP1
(CLOCK)
100ns P7
GP0 0 0 1 0 0 0
(DATA) P5
P4
P3 1µs min.
}
}

100ns
min. RB7
RB7 = output input

Program/Verify Mode
Reset

FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

VDD
P9
VIHH
MCLR/VPP
P6
Next Command
1µs min.
1 2 3 4 5 6 1 2
GP1
(CLOCK)

GP0
0 1 1 0 0 0 0 0
(DATA)
P5
P3 P4 1µs min.
}
}

100ns
min
Program/Verify Mode
Reset

DS40175B-page 3-26  2000 Microchip Technology Inc.

PIC14000
In-Circuit Serial Programming for PIC14000 OTP MCUs
This document includes the programming PIN DIAGRAM
specifications for the following devices:
• PIC14000 PDIP, SOIC, SSOP, Windowed CERDIP

RA1/AN1 •1 28 RA2/AN2
RA0/AN0 2 27 RA3/AN3
RD3/REFB 3 26 RD4/AN4
1.0 PROGRAMMING THE PIC14000 RD2/CMPB 4 25 RD5/AN5

PIC14000
RD1/SDAB 5 24 RD6/AN6
The PIC14000 can be programmed using a serial RD0/SCLB 6 23 RD7/AN7
OSC2/CLKOUT 7 22 CDAC
method. In serial mode the PIC14000 can be pro- 21
OSC1/PBTN 8 SUM
grammed while in the users system. This allows for VDD 9 20 VSS
increased design flexibility. This programming specifi- VREG 10 19 RC0/REFA
RC7/SDAA 11 18 RC1/CMPA
cation applies to PIC14000 devices in all packages. RC6/SCLA 12 17 RC2
RC5 13 16 RC3/T0CKI
1.1 Hardware Requirements MCLR/VPP 14 15 RC4

The PIC14000 requires two programmable power sup-

plies, one for VDD (2.0V to 6.5V recommended) and
one for VPP (12V to 14V).

1.2 Programming Mode

The programming mode for the PIC14000 allows pro-
gramming of user program memory, configuration
word, and calibration memory.

 2000 Microchip Technology Inc. DS30555B-page 3-27

PIC14000
2.0 PROGRAM MODE ENTRY In programming mode the program memory space
extends from 0x0000 to 0x3FFF, with the first half
2.1 User Program Memory Map (0x0000-0x1FFF) being user program memory and the
second half (0x2000-0x3FFF) being configuration
The program and calibration memory space extends memory. The PC will increment from 0x0000 to 0x1FFF
from 0x000 to 0xFFF (4096 words). Table 2-1 shows and wrap to 0x0000, or 0x2000 to 0x3FFF and wrap
actual implementation of program memory in the around to 0x2000 (not to 0x0000). Once in configura-
PIC14000. tion memory, the highest bit of the PC stays a ’1’, thus
always pointing to the configuration memory. The only
TABLE 2-1: IMPLEMENTATION OF
way to point to user program memory is to reset the
PROGRAM AND
part and reenter program/verify mode, as described in
CALIBRATION MEMORY IN Section 2.2.
THE PIC14000P
In the configuration memory space, 0x2000-0x20FF
Access to are utilized. When in configuration memory, as in the
Area Memory Space
Memory user memory, the 0x2000-0x2XFF segment is repeat-
Program 0x000-0xFBF PC<12:0> edly accessed as PC exceeds 0x2XFF (Figure 2-1).
Calibration 0xFC0 -0xFFF PC<12:0> A user may store identification information (ID) in four
ID locations. The ID locations are mapped in [0x2000:
When the PC reaches address 0xFFF, it will wrap 0x2003]. All other locations are reserved and should
around and address a location within the physically not be programmed.
implemented memory (see Figure 2-1). The ID locations read out normally, even after code pro-
tection. To understand how the devices behave, refer to
Table 4-1.
To understand the scrambling mechanism after code
protection, refer to Section 4.1.

DS30555B-page 3-28  2000 Microchip Technology Inc.

PIC14000
FIGURE 2-1: PROGRAM MEMORY MAPPING

0
Program

0FBF
2000 ID Location 0FC0
Calibration
0FFF
2001 ID Location

2002 ID Location

2003 ID Location

Reserved
2004 Reserved

2005 Reserved

2006 Reserved

2007 Configuration Word 1FFF

2000

Test
20FF

Reserved

3FFF

 2000 Microchip Technology Inc. DS30555B-page 3-29

PIC14000
2.2 Program/Verify Mode have a minimum delay of 1µs between the command
and the data. After this delay the clock pin is cycled 16
The program/verify mode is entered by holding pins times with the first cycle being a start bit and the last
RC6 and RC7 low while raising MCLR pin from VIL to cycle being a stop bit. Data is also input and output LSB
VIHH (high voltage). Once in this mode the user pro- first. Therefore, during a read operation the LSB will be
gram memory and the configuration memory can be transmitted onto pin RC7 on the rising edge of the sec-
accessed and programmed in serial fashion. The mode ond cycle, and during a load operation the LSB will be
of operation is serial, and the memory that is accessed latched on the falling edge of the second cycle. A min-
is the user program memory. RC6 and RC7 are both imum 1µs delay is also specified between consecutive
Schmitt Trigger inputs in this mode. commands.
The sequence that enters the device into the program- All commands are transmitted LSB first. Data words
ming/verify mode places all other logic into the reset are also transmitted LSB first. The data is transmitted
state (the MCLR pin was initially at VIL). This means on the rising edge and latched on the falling edge of the
that all I/O are in the reset state (High impedance clock. To allow for decoding of commands and reversal
inputs). of data pin configuration, a time separation of at least
Note: The MCLR pin should be raised as quickly 1µs is required between a command and a data word
as possible from VIL to VIHH. This is to (or another command).
ensure that the device does not have the The commands that are available are listed in Table .
PC incremented while in valid operation
range. 2.2.1.1 LOAD CONFIGURATION

2.2.1 PROGRAM/VERIFY OPERATION After receiving this command, the program counter
(PC) will be set to 0x2000. By then applying 16 cycles
The RB6 pin is used as a clock input pin, and the RB7 to the clock pin, the chip will load 14-bits a “data word”
pin is used for entering command bits and data input/ as described above, to be programmed into the config-
output during serial operation. To input a command, the uration memory. A description of the memory mapping
clock pin (RC6) is cycled six times. Each command bit schemes for normal operation and configuration mode
is latched on the falling edge of the clock with the least operation is shown in Figure 2-1. After the configura-
significant bit (LSB) of the command being input first. tion memory is entered, the only way to get back to the
The data on pin RC7 is required to have a minimum user program memory is to exit the program/verify test
setup and hold time (see AC/DC specs) with respect to mode by taking MCLR low (VIL).
the falling edge of the clock. Commands that have data
associated with them (read and load) are specified to
TABLE 2-1: COMMAND MAPPING
Command Mapping (MSB ... LSB) Data
Load Configuration 0 0 0 0 0 0 0, data(14), 0
Load Data 0 0 0 0 1 0 0, data(14), 0
Read Data 0 0 0 1 0 0 0, data(14), 0
Increment Address 0 0 0 1 1 0
Begin programming 0 0 1 0 0 0
End Programming 0 0 1 1 1 0
Note: The CPU clock must be disabled during in-circuit programming (to avoid incrementing the PC).

DS30555B-page 3-30  2000 Microchip Technology Inc.

PIC14000
FIGURE 2-2: PROGRAM FLOW CHART - PIC14000 PROGRAM MEMORY AND CALIBRATION

Start

Set VDD = VDDP*

N=0

No
Yes Report Programming
Program Cycle N > 25
Failure

Read Data
Command N=N+1 N=#
of Program Cycles

No
Increment Address Data Correct?
Command
Yes
Apply 3N Additional
Program Cycles
Program Cycle

Load Data
No
All Locations Done? Command

Yes
Verify all Locations Begin Programming
@ VDD min.* Command
VPP = VIHH2

Wait 100 µs
No Report Verify
Data Correct?
@ VDD min. Error
Yes End Programming
Verify all Locations Command
@ VDD max.
VPP = VIHH2

No Report Verify
Data Correct?
@ VDD max. Error
Yes
* VDDP = VDD range for programming (typically 4.75V - 5.25V).
VDDmin = Minimum VDD for deviceDone
operation.
VDDmax = Maximum VDD for device operation.

 2000 Microchip Technology Inc. DS30555B-page 3-31

PIC14000
FIGURE 2-3: PROGRAM FLOW CHART - PIC14000 CONFIGURATION WORD & ID LOCATIONS

Start

Load Configuration
Command

N=0

No Yes Read Data

Program ID Loc? Program Cycle Command

Increment Address No
Command N=N+1N=# Data Correct?
of Program Cycles
Yes
No
Address = 2004 No
N > 25
Yes
Yes
Increment Address
Command Report ID Apply 3N
Configuration Error Program Cycles

Increment Address
Command

Increment Address Program Cycle Read Data

Command 100 Cycles Command

No
Data Correct?

Yes

No Set VDD = VVDD

DDmin
min
Report Program Data Correct?
ID/Config. Error Read Data Command
Set VPP = VIHH2
Yes
No
Yes Set VDD = VVDD
DDmax
max
Done Data Correct? Read Data Command
Set VPP = VIHH2

DS30555B-page 3-32  2000 Microchip Technology Inc.

PIC14000
2.2.1.2 LOAD DATA 2.3 Programming Algorithm Requires
Variable VDD
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as The PIC14000 uses an intelligent algorithm. The algo-
described previously. A timing diagram for the load data rithm calls for program verification at VDDmin as well as
command is shown in Figure 5-1. VDDmax. Verification at VDDmin guarantees good
“erase margin”. Verification at VDDmax guarantees
2.2.1.3 READ DATA
good “program margin”.
After receiving this command, the chip will transmit The actual programming must be done with VDD in the
data bits out of the memory currently accessed starting VDDP range (4.75 - 5.25V).
with the second rising edge of the clock input. The RC7
VDDP = VCC range required during programming.
pin will go into output mode on the second rising clock
edge, and it will revert back to input mode (hi-imped- VDDmin = minimum operating VDD spec for the part.
ance) after the 16th rising edge. A timing diagram of VDDmax = maximum operating VDD spec for the part.
this command is shown in Figure 5-2.
Programmers must verify the PIC14000 at its specified
2.2.1.4 INCREMENT ADDRESS VDDmax and VDDmin levels. Since Microchip may
introduce future versions of the PIC14000 with a
The PC is incremented when this command is broader VDD range, it is best that these levels are user
received. A timing diagram of this command is shown selectable (defaults are ok).
in Figure 5-3.
Note: Any programmer not meeting these
2.2.1.5 BEGIN PROGRAMMING requirements may only be classified as
“prototype” or “development” programmer
A load command (load configuration or load data) but not a “production” quality programmer.
must be given before every begin programming
command. Programming of the appropriate memory
(test program memory or user program memory) will
begin after this command is received and decoded.
Programming should be performed with a series of
100µs programming pulses. A programming pulse is
defined as the time between the begin programming
command and the end programming command.

2.2.1.6 END PROGRAMMING

After receiving this command, the chip stops program-

ming the memory (configuration program memory or
user program memory) that it was programming at the
time.

 2000 Microchip Technology Inc. DS30555B-page 3-33

PIC14000
3.0 CONFIGURATION WORD
The PIC14000 has several configuration bits. These
bits can be programmed (reads ’0’) or left unpro-
grammed (reads ’1’) to select various device configura-
tions. Figure 3-1 provides an overview of configuration
bits.

FIGURE 3-1: CONFIGURATION WORD BIT MAP

Bit 6 5 4 3 2 1 0
Number:
13 12 11 10 9 8 7
PIC14000 CPC CPP1 CPP0 CPP0 CPP1 CPC CPC F CPP1 CPP0 PWRTE WDTE F FOSC

CPP<1:0>
11: All Unprotected
10: N/A
01: N/A
00: All Protected
bit 1,6: F Internal trim, factory programmed. DO NOT CHANGE! Program as ‘1’. Note 1.
bit 3: PWRTE, Power Up Timer Enable Bit
0 = Power up timer enabled
1 = Power up timer disabled (unprogrammed)
bit 2: WDTE, WDT Enable Bit
0 = WDT disabled
1 = WDT enabled (unprogrammed)
bit 0: FOSC<1:0>, Oscillator Selection Bit
0: HS oscillator (crystal/resonator)
1: Internal RC oscillator (unprogrammed)

Note 1: See Section 4.1.2 for cautions.

DS30555B-page 3-34  2000 Microchip Technology Inc.

PIC14000
4.0 CODE PROTECTION checksum is 0x0000, and the checksum of memory
[0x0000:0xFBF] is 0x2FBF, the part is effectively blank,
The memory space in the PIC14000 is divided into two and the programmer should indicate such.
areas: program space (0-0xFBF) and calibration space
(0xFC0-0xFFF). If the CPC bits are set to ‘1’, but the checksum of the
calibration memory is 0x0000, the programmer should
For program space or user space, once code protection NOT program locations in the calibration memory
is enabled, all protected segments read ‘0’s (or “gar- space, even if requested to do so by the operator. This
bage values”) and are prevented from further program- would be the case for a new JW device.
ming. All unprotected segments, including ID locations
and configuration word, read normally. These locations If the CPC bits are set to ‘1’, and the checksum of the
can be programmed. calibration memory is NOT 0x0000, the programmer is
allowed to program the calibration space as directed by
4.1 Calibration Space the operator.
The calibration space contains specially coded data
The calibration space can contain factory-generated
values used for device parameter calibration. The pro-
and programmed values. For non-JW devices, the CPC
grammer may wish to read these values and display
bits in the configuration word are set to ‘0’ at the factory,
them for the operator’s convenience. For further infor-
and the calibration data values are write-protected;
mation on these values and their coding, refer to
they may still be read out, but not programmed. JW
AN621 (DS00621B).
devices contain the factory values, but DO NOT have
the CPC bits set. 4.1.2 REPROGRAMMING CALIBRATION SPACE
Microchip does not recommend setting code protect
bits in windowed devices to ‘0’. Once code-protected, The operator should be allowed to read and store the
the device cannot be reprogrammed. data in the calibration space, for future reprogramming
of the device. This procedure is necessary for repro-
4.1.1 CALIBRATION SPACE CHECKSUM gramming a windowed device, since the calibration
data will be erased along with the rest of the memory.
The data in the calibration space has its own check- When saving this data, Configuration Word <1,6> must
sum. When properly programmed, the calibration also be saved, and restored when the calibration data
memory will always checksum to 0x0000. When this is reloaded.

4.2 Embedding Configuration Word and ID Information in the Hex File

TABLE 4-1: CODE PROTECT OPTIONS • Protect program memory

• Protect calibration memory X0000XXX00XXXX
0XXXX00XXXXXXX • No code protection
1111111X11XXXX
Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode
Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Unprotected memory segment Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Protected memory segment Read All 0’s, Write Disabled Read Unscrambled, Write Enabled
Protected calibration memory Read Unscrambled, Write Disabled Read Unscrambled, Write Enabled
ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Legend: X = Don’t care

 2000 Microchip Technology Inc. DS30555B-page 3-35

PIC14000
4.3 Checksum The following table describes how to calculate the
checksum for each device. Note that the checksum cal-
4.3.1 CHECKSUM CALCULATIONS culation differs depending on the code protect setting.
Since the program memory locations read out differ-
Checksum is calculated by reading the contents of the
ently depending on the code protect setting, the table
PIC14000 memory locations and adding up the
describes how to manipulate the actual program mem-
opcodes up to the maximum user addressable location,
ory values to simulate the values that would be read
0xFBF. Any carry bits exceeding 16-bits are neglected.
from a protected device. When calculating a checksum
Finally, the configuration word (appropriately masked)
by reading a device, the entire program memory can
is added to the checksum. Checksum computation for
simply be read and summed. The configuration word
the PIC14000 device is shown in Table 4-2:
and ID locations can always be read.
The checksum is calculated by summing the following:
Note that some older devices have an additional value
• The contents of all program memory locations added in the checksum. This is to maintain compatibil-
• The configuration word, appropriately masked ity with older device programmer checksums.
• Masked ID locations (when applicable) TABLE 4-2: CHECKSUM COMPUTATION
The least significant 16 bits of this sum is the check-
sum.

0x25E6 at
Code Blank
Checksum* 0 and max
Protect Value
address

OFF SUM[0000:0FBF] + CFGW & 0x3FBD 0x2FFD 0xFBCB

OFF OTP SUM[0000:0FBF] + CFGW & 0x3FBD 0x0E7D 0xDA4B
ON CFGW & 0x3FBD + SUM(IDs) 0x300A 0xFBD8

Legend: CFGW = Configuration Word

SUM[A:B] = [Sum of locations a through b inclusive]
SUM(ID) = ID locations masked by 0x7F then made into a 28-bit value with ID0 as the most significant byte
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND

DS30555B-page 3-36  2000 Microchip Technology Inc.

PIC14000
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 5-1: AC/DC CHARACTERISTICS
AC/DC TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +40°C, unless otherwise stated, (25°C recommended)
Operating Voltage: 4.5V ≤ VDD ≤ 5.5V, unless otherwise stated.

Parameter
Sym. Characteristic Min. Typ. Max. Units Conditions
No.
General
PD1 VDDP Supply voltage during programming 4.75 5.0 5.25 V
PD2 IDDP Supply current (from VDD) – – 20 mA
during programming
PD3 VDDV Supply voltage during verify VDDmin VDDmax V Note 1
PD4 VIHH1 Voltage on MCLR/VPP during 12.75 – 13.25 V Note 2
programming
PD5 VIHH2 Voltage on MCLR/VPP during verify VDD + 4.0 13.5
PD6 IPP Programming supply current (from – – 50 mA
VPP)
PD9 VIH1 (RC6, RC7) input high level 0.8 VDD – – V Schmitt Trigger input
PD8 VIL1 (RC6, RC7) input low level 0.2 VDD – – V Schmitt Trigger input

Serial Program Verify

P1 TR MCLR/VPP rise time (VSS to VHH) – – 8.0 µs
for test mode entry
P2 Tf MCLR Fall time – – 8.0 µs
P3 Tset1 Data in setup time before clock ↓ 100 – – ns
P4 Thld1 Data in hold time after clock ↓ 100 – – ns
P5 Tdly1 Data input not driven to next clock 1.0 – – µs
input (delay required between com-
mand/data or command/command)
P6 Tdly2 Delay between clock ↓ to clock ↑ of 1.0 – – µs
next command or data
P7 Tdly3 Clock ↑ to date out valid 200 – – ns
(during read data)
P8 Thld0 Hold time after MCLR ↑ 2 – – µs
Note 1: Program must be verified at the minimum and maximum VDD limits for the part.
Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.

 2000 Microchip Technology Inc. DS30555B-page 3-37

PIC14000
FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY)
VIHH
MCLR/VPP
100ns P6
P8
1 2 3 4 5 6 1µs min. 1 2 3 4 5 15
RC6
(CLOCK)
100ns
RC7 0 0 0 0
(DATA) 1 0 0 0
P5
P3
P4
P4 1µs min. P3

}
}
}

}
100ns 100ns
min. min.
Program/Verify Test Mode
Reset

FIGURE 5-2: READ DATA COMMAND (PROGRAM/VERIFY)

VIHH
MCLR/VPP 100ns P6
P8
1 2 3 4 5 6 1µs min. 1 2 3 4 5 15
RC6
(CLOCK)
100ns P7
RC7 0 0 1 0 0 0
(DATA) P5
P4
P3 1µs min.
}
}

100ns
min. RC7
RC7 = output input

Program/Verify Test Mode

Reset

FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

VIHH
MCLR/VPP
P6
Next Command
1µs min.
1 2 3 4 5 6 1 2
RC6
(CLOCK)

RC7
0 1 1 0 0 0 0 0
(DATA)
P5
P3 P4 1µs min.
}
}

100ns
min
Program/Verify Test Mode
Reset

DS30555B-page 3-38  2000 Microchip Technology Inc.

30261C.fm Page 39 Wednesday, May 3, 2000 12:18 PM

PIC16C55X
In-Circuit Serial Programming for PIC16C55X OTP MCUs
This document includes the programming PIN Diagrams
specifications for the following devices:
PDIP, SOIC, Windowed CERDIP
• PIC16C554
• PIC16C556
RA2 •1 18 RA1
• PIC16C558 RA3 2 17 RA0

PIC16C55X
RA4/T0CKI 3 16 OSC1/CLKIN
MCLR 4 15 OSC2/CLKOUT
VSS 5 14 VDD
1.0 PROGRAMMING THE RB0/INT
RB1
6
7
13
12
RB7
RB6
PIC16C55X RB2
RB3
8
9
11
10
RB5
RB4
The PIC16C55X can be programmed using a serial
method. In serial mode the PIC16C55X can be pro-
grammed while in the users system. This allows for
increased design flexibility. SSOP

1.1 Hardware Requirements RA2 •1 20 RA1

RA3 2 19 RA0

PIC16C55X
The PIC16C55X requires two programmable power RA4/T0CKI 3 18 OSC1/CLKIN
MCLR 4 17 OSC2/CLKOUT
supplies, one for VDD (2.0V to 6.5V recommended) and VSS 5 16 VDD
VSS 6 15 VDD
one for VPP (12V to 14V). Both supplies should have a RB0/INT 7 14 RB7
minimum resolution of 0.25V. RB1 8 13 RB6
RB2 9 12 RB5
RB3 10 11 RB4
1.2 Programming Mode
The programming mode for the PIC16C55X allows pro-
gramming of user program memory, special locations
used for ID, and the configuration word for the
PIC16C55X.

 2000 Microchip Technology Inc. DS30261C-page 3-39

30261C.fm Page 40 Wednesday, May 3, 2000 12:18 PM

PIC16C55X
2.0 PROGRAM MODE ENTRY
2.1 User Program Memory Map
The user memory space extends from 0x0000 to
0x1FFF (8K). Table 2-1 shows actual implementation
of program memory in the PIC16C55X family.
TABLE 2-1: IMPLEMENTATION OF
PROGRAM MEMORY IN THE
PIC16C55X
Access to
Device Program Memory Size Program
Memory
PIC16C554 0x000 - 0x1FF (0.5K) PC<8:0>
PIC16C556 0x000 - 0x3FF (1K) PC<9:0>
PIC16C558 0x000 - 0x7FF (2K) PC<10:0>

When the PC reaches the last location of the imple-

mented program memory, it will wrap around and
address a location within the physically implemented
memory (see Figure 2-1).
In programming mode the program memory space
extends from 0x0000 to 0x3FFF, with the first half
(0x0000-0x1FFF) being user program memory and the
second half (0x2000-0x3FFF) being configuration
memory. The PC will increment from 0x0000 to 0x1FFF
and wrap to 0x000 or 0x2000 to 0x3FFF and wrap
around to 0x2000 (not to 0x0000). Once in configura-
tion memory, the highest bit of the PC stays a ’1’, thus
always pointing to the configuration memory. The only
way to point to user program memory is to reset the
part and reenter program/verify mode, as described in
Section 2.2.
In the configuration memory space, 0x2000-0x20FF
are utilized. When in a configuration memory, as in the
user memory, the 0x2000-0x2XFF segment is repeat-
edly accessed as the PC exceeds 0x2XFF (see
Figure 2-1).
A user may store identification information (ID) in four
ID locations. The ID locations are mapped in [0x2000:
0x2003]. It is recommended that the user use only the
four least significant bits of each ID location. In some
devices, the ID locations read-out in a scrambled fash-
ion after code protection is enabled. For these devices,
it is recommended that ID location is written as “11
1111 1000 bbbb” where 'bbbb' is ID information.
Note: All other locations are reserved and should
not be programmed.
In other devices, the ID locations read out normally,
even after code protection. To understand how the
devices behave, refer to Table 4-1.
To understand the scrambling mechanism after code
protection, refer to Section 4.1.

DS30261C-page 3-40  2000 Microchip Technology Inc.

30261C.fm Page 41 Wednesday, May 3, 2000 12:18 PM

PIC16C55X
FIGURE 2-1: PROGRAM MEMORY MAPPING

0.5KW 1KW 2KW

0
1FF Implemented
2000 ID Location Implemented Implemented
3FF
400
2001 ID Location Implemented
7FF
800
2002 ID Location
BFF
C00
2003 ID Location
FFF Reserved
Reserved
1000
2004 Reserved Reserved

Reserved
2005 Reserved
Reserved
2006 Reserved

2007 Configuration Word

1FFF
2000
2008 Reserved Reserved Reserved

2100

Reserved Reserved Reserved

3FFF

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PIC16C55X
2.2 Program/Verify Mode setup and hold time (see AC/DC specs) with respect to
the falling edge of the clock. Commands that have data
The program/verify mode is entered by holding pins associated with them (read and load) are specified to
RB6 and RB7 low while raising MCLR pin from VIL to have a minimum delay of 1µs between the command
VIHH (high voltage). Once in this mode the user pro- and the data. After this delay the clock pin is cycled 16
gram memory and the configuration memory can be times with the first cycle being a start bit and the last
accessed and programmed in serial fashion. The mode cycle being a stop bit. Data is also input and output LSB
of operation is serial, and the memory that is accessed first. Therefore, during a read operation the LSB will be
is the user program and configuration memory. RB6 is transmitted onto pin RB7 on the rising edge of the sec-
a Schmitt Trigger input in this mode. ond cycle, and during a load operation the LSB will be
The sequence that enters the device into the program- latched on the falling edge of the second cycle. A min-
ming/verify mode places all other logic into the reset imum 1µs delay is also specified between consecutive
state (the MCLR pin was initially at VIL). This means commands.
that all I/O are in the reset state (High impedance The commands that are available are listed
inputs). in Table 2-1.
Note: The MCLR pin should be raised as quickly 2.2.1.1 LOAD CONFIGURATION
as possible from VIL to VIHH. this is to
ensure that the device does not have the After receiving this command, the program counter
PC incremented while in valid operation (PC) will be set to 0x2000. By then applying 16 cycles
range. to the clock pin, the chip will load 14-bits a “data word”
as described above, to be programmed into the config-
2.2.1 PROGRAM/VERIFY OPERATION uration memory. A description of the memory mapping
The RB6 pin is used as a clock input pin, and the RB7 schemes for normal operation and configuration mode
pin is used for entering command bits and data input/ operation is shown in Figure 2-1. After the configura-
output during serial operation. To input a command, the tion memory is entered, the only way to get back to the
clock pin (RB6) is cycled six times. Each command bit user program memory is to exit the program/verify test
is latched on the falling edge of the clock with the least mode by taking MCLR low (VIL).
significant bit (LSB) of the command being input first.
The data on pin RB7 is required to have a minimum
TABLE 2-1: COMMAND MAPPING
Command Mapping (MSB ... LSB) Data
Load Configuration 0 0 0 0 0 0 0, data(14), 0
Load Data 0 0 0 0 1 0 0, data(14), 0
Read Data 0 0 0 1 0 0 0, data(14), 0
Increment Address 0 0 0 1 1 0
Begin programming 0 0 1 0 0 0
End Programming 0 0 1 1 1 0
Note: The CPU clock must be disabled during in-circuit programming.

DS30261C-page3-42  2000 Microchip Technology Inc.

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PIC16C55X
FIGURE 2-2: PROGRAM FLOW CHART - PIC16C55X PROGRAM MEMORY

Start

Set VDD = VDDP*

N=0

No
Yes Report Programming
Program Cycle N > 25
Failure

Read Data
Command N=N+1 N=#
of Program Cycles

No
Increment Address Data Correct?
Command
Yes
Apply 3N Additional
Program Cycles
Program Cycle

Load Data
No
All Locations Done? Command

Yes
Verify all Locations Begin Programming
@ VDD min.* Command
VPP = VIHH2

Wait 100 µs
No Report Verify
Data Correct?
@ VDD min. Error
Yes End Programming
Verify all Locations Command
@ VDD max.
VPP = VIHH2

No Report Verify
Data Correct?
@ VDD max. Error
Yes

Done

* VDDP = VDD range for programming (typically 4.75V - 5.25V).

VDDmin = Minimum VDD for device operation.
VDDmax = Maximum VDD for device operation.

 2000 Microchip Technology Inc. DS30261C-page 3-43

30261C.fm Page 44 Wednesday, May 3, 2000 12:18 PM

PIC16C55X
FIGURE 2-3: PROGRAM FLOW CHART - PIC16C55X CONFIGURATION WORD & ID LOCATIONS

Start

Load Configuration
Command

N=0

No Yes Read Data

Program ID Loc? Program Cycle Command

Increment Address No
Command N=N+1N=# Data Correct?
of Program Cycles
Yes
No
Address = 2004 No
N > 25
Yes
Yes
Increment Address
Command ID/Configuration Apply 3N
Error Program Cycles

Increment Address
Command

Increment Address Program Cycle Read Data

Command 100 Cycles Command

No
Data Correct?

Yes

Report Program No Set VDD = VVDD

DDmin
min
Data Correct? Read Data Command
ID/Config. Error
Set VPP = VIHH2
Yes
No
Yes Set VDD = VVDD
DDmax
max
Done Data Correct? Read Data Command
Set VPP = VIHH2

DS30261C-page 3-44  2000 Microchip Technology Inc.

30261C.fm Page 45 Wednesday, May 3, 2000 12:18 PM

PIC16C55X
2.2.1.2 LOAD DATA 2.3 Programming Algorithm Requires
Variable VDD
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as The PIC16C55X uses an intelligent algorithm. The
described previously. A timing diagram for the load data algorithm calls for program verification at VDDmin as
command is shown in Figure 5-1. well as VDDmax. Verification at VDDmin guarantees
good “erase margin”. Verification at VDDmax guaran-
2.2.1.3 READ DATA
tees good “program margin”.
After receiving this command, the chip will transmit The actual programming must be done with VDD in the
data bits out of the memory currently accessed starting VDDP range (4.75 - 5.25V).
with the second rising edge of the clock input. The RB7
VDDP = VCC range required during programming.
pin will go into output mode on the second rising clock
edge, and it will revert back to input mode (hi-imped- VDD min. = minimum operating VDD spec for the part.
ance) after the 16th rising edge. A timing diagram of VDD max.= maximum operating VDD spec for the part.
this command is shown in Figure 5-2.
Programmers must verify the PIC16C55X at its speci-
2.2.1.4 INCREMENT ADDRESS fied VDDmax and VDDmin levels. Since Microchip may
introduce future versions of the PIC16C55X with a
The PC is incremented when this command is broader VDD range, it is best that these levels are user
received. A timing diagram of this command is shown selectable (defaults are ok).
in Figure 5-3.
Note: Any programmer not meeting these
2.2.1.5 BEGIN PROGRAMMING requirements may only be classified as
“prototype” or “development” programmer
A load command (load configuration or load data) but not a “production” quality programmer.
must be given before every begin programming
command. Programming of the appropriate memory
(test program memory or user program memory) will
begin after this command is received and decoded.
Programming should be performed with a series of
100µs programming pulses. A programming pulse is
defined as the time between the begin programming
command and the end programming command.

2.2.1.6 END PROGRAMMING

After receiving this command, the chip stops program-

ming the memory (configuration program memory or
user program memory) that it was programming at the
time.

 2000 Microchip Technology Inc. DS30261C-page 3-45

30261C.fm Page 46 Wednesday, May 3, 2000 12:18 PM

PIC16C55X
3.0 CONFIGURATION WORD
The PIC16C55X family members have several configu-
ration bits. These bits can be programmed (reads ’0’) or
left unprogrammed (reads ’1’) to select various device
configurations. Figure 3-1 provides an overview of con-
figuration bits.

FIGURE 3-1: CONFIGURATION WORD BIT MAP

Bit 6 5 4 3 2 1 0
Number:
13 12 11 10 9 8 7
PIC16C554/556/558 CP1 CP0 CP1 CP0 CP1 CP0 — 0 CP1 CP0 PWRTE WDTE FOSC1 FOSC0

bit 7: Reserved for future use

bit 6: Set to 0
bit 5-4: CP1:CP0, Code Protect
bit 8-13

Device CP1 CP0 Code Protection

PIC16C554 0 0 All memory protected
0 1 Do not use
1 0 Do not use
1 1 Code protection off
PIC16C556 0 0 All memory protected
0 1 Upper 1/2 memory protected
1 0 Do not use
1 1 Code protection off
PIC16C558 0 0 All memory protected
0 1 Upper 3/4 memory protected
1 0 Upper 1/2 memory protected
1 1 Code protection off

bit 3: PWRTE, Power Up Timer Enable Bit

PIC16C554/556/558:
0 = Power up timer enabled
1 = Power up timer disabled
bit 2: WDTE, WDT Enable Bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:FOSC<1:0>, Oscillator Selection Bit
11: RC oscillator
10: HS oscillator
01: XT oscillator
00: LP oscillator

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PIC16C55X
4.0 CODE PROTECTION 4.1 Programming Locations 0x0000 to
0x03F after Code Protection
The program code written into the EPROM can be pro-
tected by writing to the CP0 & CP1 bits of the configu- For PIC16C55X devices, once code protection is
ration word. enabled, all protected segments read '0's (or “garbage
values”) and are prevented from further programming.
All unprotected segments, including ID locations and
configuration word, read normally. These locations can
be programmed.

4.2 Embedding Configuration Word and ID Information in the Hex File

TABLE 4-1: CONFIGURATION WORD

PIC16C554
To code protect:
• Protect all memory 0000001000XXXX
• No code protection 1111111011XXXX
Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode
Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Protected memory segment Read All 0’s, Write Disabled Read Unscrambled, Write Enabled
ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled

PIC16C556
To code protect:
• Protect all memory 0000001000XXXX
• Protect upper 1/2 memory 0101011001XXXX
• No code protection 1111111011XXXX
Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode
Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Protected memory segment Read All 0’s, Write Disabled Read Unscrambled, Write Enabled
ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled

PIC16C558
To code protect:
• Protect all memory 0000001000XXXX
• Protect upper 3/4 memory 0101011001XXXX
• Protect upper 1/2 memory 1010101010XXXX
• No code protection 1111111011XXXX
Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode
Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
Protected memory segment Read All 0’s, Write Disabled Read Unscrambled, Write Enabled
ID Locations (0x2000 : 0x2003) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled

 2000 Microchip Technology Inc. DS30261C-page 3-47

30261C.fm Page 48 Wednesday, May 3, 2000 12:18 PM

PIC16C55X
4.3 Checksum The following table describes how to calculate the
checksum for each device. Note that the checksum cal-
4.3.1 CHECKSUM CALCULATIONS culation differs depending on the code protect setting.
Since the program memory locations read out differ-
Checksum is calculated by reading the contents of the
ently depending on the code protect setting, the table
PIC16C55X memory locations and adding up the
describes how to manipulate the actual program mem-
opcodes up to the maximum user addressable location,
ory values to simulate the values that would be read
e.g., 0x1FF for the PIC16C74. Any carry bits exceeding
from a protected device. When calculating a checksum
16-bits are neglected. Finally, the configuration word
by reading a device, the entire program memory can
(appropriately masked) is added to the checksum.
simply be read and summed. The configuration word
Checksum computation for each member of the
and ID locations can always be read.
PIC16C55X devices is shown in Table .
Note that some older devices have an additional value
The checksum is calculated by summing the following:
added in the checksum. This is to maintain compatibil-
• The contents of all program memory locations ity with older device programmer checksums.
• The configuration word, appropriately masked
• Masked ID locations (when applicable)
The least significant 16 bits of this sum is the check-
sum.

TABLE 4-2: CHECKSUM COMPUTATION

0x25E6 at
Code Blank
Device Checksum* 0 and max
Protect Value
address
PIC16C554 OFF SUM[0x000:0x1FF] + CFGW & 0x3F3F 3D3F 090D
ALL SUM_ID + CFGW & 0x3F3F 3D4E 091C
PIC16C556 OFF SUM[0x000:0x3FF] + CFGW & 0x3F3F 3B3F 070D
1/2 SUM[0x000:0x1FF] + CFGW & 0x3F3F + SUM_ID 4E5E 0013
ALL CFGW & 0x3F3F + SUM_ID 3B4E 071C
PIC16C558 OFF SUM[0x000:0x7FF] + CFGW & 0x3F3F 373F 030D
1/2 SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID 5D6E 0F23
3/4 SUM[0x000:0x1FF] + CFGW & 0x3F3F + SUM_ID 4A5E FC13
ALL CFGW & 0x3F3F + SUM_ID 374E 031C
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble.
For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND

DS30261C-page 3-48  2000 Microchip Technology Inc.

30261C.fm Page 49 Wednesday, May 3, 2000 12:18 PM

PIC16C55X
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 5-1: AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +40°C, unless otherwise stated, (25°C is recommended)
Operating Voltage: 4.5V ≤ VDD ≤ 5.5V, unless otherwise stated.

Parameter
Sym. Characteristic Min. Typ. Max. Units Conditions
No.
General
PD1 VDDP Supply voltage during programming 4.75 5.0 5.25 V
PD2 IDDP Supply current (from VDD) - - 20 mA
during programming
PD3 VDDV Supply voltage during verify VDDmin - VDDmax V Note 1
PD4 VIHH1 Voltage on MCLR/VPP during 12.75 - 13.25 V Note 2
programming
PD5 VIHH2 Voltage on MCLR/VPP during verify VDD + 4.0 - 13.5 -
PD6 IPP Programming supply current (from - - 50 mA
VPP)
PD9 VIH1 (RB6, RB7) input high level 0.8 VDD - - V Schmitt Trigger input
PD8 VIL1 (RB6, RB7) input low level 0.2 VDD - - V Schmitt Trigger input

Serial Program Verify

P1 TR MCLR/VPP rise time (VSS to VHH) - - 8.0 µs
for test mode entry
P2 Tf MCLR Fall time - - 8.0 µs
P3 Tset1 Data in setup time before clock ↓ 100 - - ns
P4 Thld1 Data in hold time after clock ↓ 100 - - ns
P5 Tdly1 Data input not driven to next clock 1.0 - - µs
input (delay required between com-
mand/data or command/command)
P6 Tdly2 Delay between clock ↓ to clock ↑ of 1.0 - - µs
next command or data
P7 Tdly3 Clock ↑ to date out valid 200 - - ns
(during read data)
P8 Thld0 Hold time after MCLR ↑ 2 - - µs
- Tpw Programming Pulse Width 10 100 1000 µs
Note 1: Program must be verified at the minimum and maximum VDD limits for the part.
2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.

 2000 Microchip Technology Inc. DS30261C-page 3-49

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PIC16C55X
FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY)
VIHH
MCLR/VPP
100ns P6
P8
1 2 3 4 5 6 1µs min. 1 2 3 4 5 15
RB6
(CLOCK)
100ns
RB7 0 0 0 0
(DATA) 1 0 0 0
P5
P3
P4
P4 1µs min. P3

}
}
}

}
100ns 100ns
min. min.
Program/Verify Test Mode
Reset

FIGURE 5-2: READ DATA COMMAND (PROGRAM/VERIFY)

VIHH
MCLR/VPP 100ns P6
P8
1 2 3 4 5 6 1µs min. 1 2 3 4 5 15
RB6
(CLOCK)
100ns P7
RB7 0 0 1 0 0 0
(DATA) P5
P4
P3 1µs min.
}
}

100ns
min. RB7
RB7 = output input

Program/Verify Test Mode

Reset

FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

VIHH
MCLR/VPP
P6
Next Command
1µs min.
1 2 3 4 5 6 1 2
RB6
(CLOCK)

RB7
0 1 1 0 0 0 0 0
(DATA)
P5
P3 P4 1µs min.
}
}

100ns
min
Program/Verify Test Mode
Reset

DS30261C-page 3-50  2000 Microchip Technology Inc.

PIC16C6XX/7XX/9XX
In-Circuit Serial Programming for PIC16C6XX/7XX/9XX OTP MCUs

This document includes the programming Pin Diagrams

specifications for the following devices: PDIP, Windowed CERDIP
• PIC16C61 • PIC16C72A • PIC16CE623 MCLR/VPP 1 40 RB7
• PIC16C62 • PIC16C73 • PIC16CE624 RA0 2 39 RB6

PIC16C74/74A/74B/77/765
PIC16C64/64A/65/65A/67
RA1 3 38 RB5
• PIC16C62A • PIC16C73A • PIC16CE625 RA2 4 37 RB4
RA3 5 36 RB3
• PIC16C62B • PIC16C73B • PIC16C710 RA4/T0CKI 6 35 RB2
RA5 7 34 RB1
• PIC16C63 • PIC16C74 • PIC16C711 RE0 8 33 RB0/INT
RE1 9 32 VDD
• PIC16C63A • PIC16C74A • PIC16C712 RE2 10 31 VSS
• PIC16C64 • PIC16C74B • PIC16C716 VDD
VSS
11
12
30
29
RD7
RD6
• PIC16C64A • PIC16C76 • PIC16C745 OSC1/CLKIN 13 28 RD5
OSC2/CLKOUT 14 27 RD4
• PIC16C65 • PIC16C77 • PIC16C765 RC0 15 26 RC7
RC1 16 25 RC6
• PIC16C65A • PIC16C620 • PIC16C773 RC2 17 24 RC5
RC3 18 23 RC4
• PIC16C65B • PIC16C620A • PIC16C774 RD0 19 22 RD3
RD1 20 21 RD2
• PIC16C66 • PIC16C621 • PIC16C923
• PIC16C67 • PIC16C621A • PIC16C924
PDIP, SOIC, Windowed CERDIP (300 mil)
• PIC16C71 • PIC16C622
28 RB7
• PIC16C72 • PIC16C622A MCLR/VPP •1

PIC16C73/73A/73B/76/745
PIC16C62/62A/63/66/72/72A
RA0 2 27 RB6
RA1 3 26 RB5
RA2 4 25 RB4
1.0 PROGRAMMING THE RA3 5 24 RB3

PIC16C6XX/7XX/9XX RA4/T0CKI
RA5
6
7
23
22
RB2
RB1
VSS 8 21 RB0/INT
The PIC16C6XX/7XX/9XX can be programmed using a OSC1/CLKIN 9 20 VDD
serial method. In serial mode the PIC16C6XX/7XX/ OSC2/CLKOUT 10 19 VSS
RC0 11 18 RC7
9XX can be programmed while in the users system. 17 RC6
RC1 12
This allows for increased design flexibility. This pro- RC2 13 16 RC5
gramming specification applies to PIC16C6XX/7XX/ RC3 14 15 RC4

9XX devices in all packages.

1.1 Hardware Requirements

The PIC16C6XX/7XX/9XX requires two programmable
power supplies, one for VDD (2.0V to 6.5V recom-
mended) and one for VPP (12V to 14V). Both supplies
should have a minimum resolution of 0.25V.

1.2 Programming Mode

The programming mode for the PIC16C6XX/7XX/9XX
allows programming of user program memory, special
locations used for ID, and the configuration word for the
PIC16C6XX/7XX/9XX.

 2000 Microchip Technology Inc. DS30228J-page 3-51

PIC16C6XX/7XX/9XX
Pin Diagrams (Con’t)

PDIP, SOIC, Windowed CERDIP 300 mil. SDIP, SOIC, Windowed CERDIP, SSOP

RA2 •1 18 RA1
MCLR/VPP •1 28 RB7

PIC16C710/711
2 17 RA0

PIC16C62X

PIC16C61/71
RA3 RA0/AN0 2 27 RB6
RA4/T0CKI 3 16 OSC1/CLKIN
RA1/AN1 3 26 RB5
MCLR/VPP 4 15 OSC2/CLKOUT RA2/AN2/VREF-/VRL 4 25 RB4
14 VDD

PIC16C773
VSS 5 RA3/AN3/VREF+/VRH 5 24 RB3/AN9/LVDIN

RB0/INT 6 13 RB7 RA4/T0CKI 6 23 RB2/AN8

7 12 RB6 AVDD 7 22 RB1/SS
RB1
11 AVSS 8 21 RB0/INT
RB2 8 RB5
OSC1/CLKIN 9 20 VDD
RB3 9 10 RB4
OSC2/CLKOUT 10 19 VSS
RC0/T1OSO/T1CKI 11 18 RC7/RX/DT
RC1/T1OSI/CCP2 12 17 RC6/TX/CK
RC2/CCP1 13 16 RC5/SDO
RC3/SCK/SCL 14 15 RC4/SDI/SDA

18 pin PDIP, SOIC, Windowed CERDIP

20 pin SSOP
RA2/AN2 •1 18 RA1/AN1
RA3/AN3/VREF 2 17 RA0/AN0
RA2/AN2 •1 20 RA1/AN1
RA4/T0CKI 3 16 OSC1/CLKIN
PIC16C716
PIC16C712

RA3/AN3/VREF 2 19 RA0/AN0
MCLR/VPP 4 15 OSC2/CLKOUT
RA4/T0CKI 3 18 OSC1/CLKIN

PIC16C716
PIC16C712
VSS 5 14 VDD
MCLR/VPP 4 17 OSC2/CLKOUT
RB0/INT 6 13 RB7
VSS 5 16 VDD
RB1/T1OSO/T1CKI 7 12 RB6
VSS 6 15 VDD
RB2/T1OSI 8 11 RB5
RB0/INT 7 14 RB7
RB3/CCP1 9 10 RB4
RB1/T1OSO/T1CKI 8 13 RB6
RB2/T1OSI 9 12 RB5
RB3/CCP1 10 11 RB4
RD7/SEG31/COM1
RD6/SEG30/COM2
RA3/AN3/VREF

MCLR/VPP
RA2/AN2

RA1/AN1
RA0/AN0

PLCC
COM0
RB2
RB3

RB4
RB5
RB7
RB6
VDD
VSS

N/C
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61

RA4/T0CKI 10 60 RD5/SEG29/COM3
RA5/AN4/SS 11 59 RG6/SEG26
RB1 12 58 RG5/SEG25
RB0/INT 13 57 RG4/SEG24
RC3/SCK/SCL 14 56 RG3/SEG23
RC4/SDI/SDA 15 55 RG2/SEG22
RC5/SDO 16 54 RG1/SEG21
C1
C2
17
18
PIC16C923 53
52
RG0/SEG20
RG7/SEG28
VLCD2
VLCD3
19
20
PIC16C924 51
50
RF7/SEG19
RF6/SEG18
AVDD 21 49 RF5/SEG17
VDD 22 48 RF4/SEG16
VSS 23 47 RF3/SEG15
OSC1/CLKIN 24 46 RF2/SEG14
OSC2/CLKOUT 25 45 RF1/SEG13
RC0/T1OSO/T1CKI 26 44 RF0/SEG12
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
VLCDADJ
RC1/T1OSI
RC2/CCP1
VLCD1

RD0/SEG00
RD1/SEG01
RD2/SEG02
RD3/SEG03
RD4/SEG04
RE7/SEG27
RE0/SEG05
RE1/SEG06
RE2/SEG07
RE3/SEG08
RE4/SEG09
RE5/SEG10
RE6/SEG11

DS30228J-page 3-52  2000 Microchip Technology Inc.

PIC16C6XX/7XX/9XX
2.0 PROGRAM MODE ENTRY When the PC reaches the last location of the imple-
mented program memory, it will wrap around and
2.1 User Program Memory Map address a location within the physically implemented
memory (see Figure 2-1).
The user memory space extends from 0x0000 to
Once in configuration memory, the highest bit of the PC
0x1FFF (8K). Table 2-1 shows actual implementation
stays a ’1’, thus always pointing to the configuration
of program memory in the PIC16C6XX/7XX/9XX fam-
memory. The only way to point to user program mem-
ily.
ory is to reset the part and reenter program/verify
TABLE 2-1: IMPLEMENTATION OF mode, as described in Section 2.2.
PROGRAM MEMORY IN THE A user may store identification information (ID) in four
PIC16C6XX/7XX/9XX ID locations. The ID locations are mapped in [0x2000:
0x2003]. It is recommended that the user use only the
Program Memory
Device four least significant bits of each ID location. In some
Size
devices, the ID locations read-out in a scrambled fash-
PIC16C61 0x000 – 0x3FF (1K) ion after code protection is enabled. For these devices,
PIC16C620/620A 0x000 – 0x1FF (0.5K) it is recommended that ID location is written as “11
1111 1bbb bbbb” where 'bbbb' is ID information.
PIC16C621/621A 0x000 – 0x3FF (1K)
PIC16C622/622A 0x000 – 0x7FF (2K) Note: All other locations are reserved and should
not be programmed.
PIC16C62/62A/62B 0x000 – 0x7FF (2K)
In other devices, the ID locations read out normally,
PIC16C63/63A 0x000 – 0xFFF (4K)
even after code protection. To understand how the
PIC16C64/64A 0x000 – 0x7FF (2K) devices behave, refer to Table 4-1.
PIC16C65/65A/65B 0x000 – 0xFFF (4K) To understand the scrambling mechanism after code
PIC16CE623 0x000 – 0x1FF (0.5K) protection, refer to Section 3.1.
PIC16CE624 0x000 – 0x3FF (1K)
PIC16CE625 0x000 – 0x7FF (2K)
PIC16C71 0x000 – 0x3FF (1K)
PIC16C710 0x000 – 0x1FF (0.5K)
PIC16C711 0x000 – 0x3FF (1K)
PIC16C712 0x000 – 0x3FF (1K)
PIC16C716 0x000 – 0x7FF (2K)
PIC16C72/72A 0x000 – 0x7FF (2K)
PIC16C73/73A/73B 0x000 – 0xFFF (4K)
PIC16C74/74A/74B 0x000 – 0xFFF (4K)
PIC16C66 0x000 – 0x1FFF (8K)
PIC16C67 0x000 – 0x1FFF (8K)
PIC16C76 0x000 – 0x1FFF (8K)
PIC16C77 0x000 – 0x1FFF (8K)
PIC16C745 0x000 – 0x1FFF (8K)
PIC16C765 0x000 – 0x1FFF (8K)
PIC16C773 0x000 – 0xFFF (4K)
PIC16C774 0x000 – 0xFFF (4K)
PIC16C923/924 0x000 – 0xFFF (4K)

 2000 Microchip Technology Inc. DS30228J-page 3-53

PIC16C6XX/7XX/9XX
FIGURE 2-1: PROGRAM MEMORY MAPPING

0.5K 1K 2K 4K 8K
words words words words words
2000h ID Location 0h
Implemented
1FFh Implemented Implemented Implemented Implemented
3FFh
2001h ID Location
400h
Implemented Implemented Implemented
7FFh
2002h ID Location
800h
Reserved Implemented Implemented
BFFh
2003h ID Location
C00h
Reserved Implemented Implemented
FFFh
2004h Reserved
1000h
Reserved Implemented
2005h Reserved
Reserved Implemented
2006h Reserved
Implemented
2007h Configuration Word
Implemented
1FFFh

2008h
Reserved Reserved Reserved Reserved Reserved

2100h

Reserved Reserved Reserved Reserved Reserved

3FFFh

DS30228J-page 3-54  2000 Microchip Technology Inc.

PIC16C6XX/7XX/9XX
2.2 Program/Verify Mode have a minimum delay of 1 µs between the command
and the data. After this delay the clock pin is cycled 16
The program/verify mode is entered by holding pins times with the first cycle being a start bit and the last
RB6 and RB7 low while raising MCLR pin from VSS to cycle being a stop bit. Data is also input and output LSb
the appropriate VIHH (high voltage). Once in this mode first. Therefore, during a read operation the LSb will be
the user program memory and the configuration mem- transmitted onto pin RB7 on the rising edge of the sec-
ory can be accessed and programmed in serial fash- ond cycle, and during a load operation the LSb will be
ion. The mode of operation is serial, and the memory latched on the falling edge of the second cycle. A min-
that is accessed is the user program memory. RB6 is a imum 1 µs delay is also specified between consecutive
Schmitt Trigger input in this mode. commands.
The sequence that enters the device into the program- All commands are transmitted LSb first. Data words are
ming/verify mode places all other logic into the reset also transmitted LSb first. The data is transmitted on
state (the MCLR pin was initially at VSS). This means the rising edge and latched on the falling edge of the
that all I/O are in the reset state (High impedance clock. To allow for decoding of commands and reversal
inputs). of data pin configuration, a time separation of at least
Note 1: The MCLR pin should be raised as quickly 1 µs is required between a command and a data word
as possible from VIL to VIHH. this is to (or another command).
ensure that the device does not have the The commands that are available are listed
PC incremented while in valid operation in Table 2-2.
range.
2.2.1.1 LOAD CONFIGURATION
2: Do not power any pin before VDD is
applied. After receiving this command, the program counter
(PC) will be set to 0x2000. By then applying 16 cycles
2.2.1 PROGRAM/VERIFY OPERATION to the clock pin, the chip will load 14-bits a “data word”
The RB6 pin is used as a clock input pin, and the RB7 as described above, to be programmed into the config-
pin is used for entering command bits and data input/ uration memory. A description of the memory mapping
output during serial operation. To input a command, the schemes for normal operation and configuration mode
clock pin (RB6) is cycled six times. Each command bit operation is shown in Figure 2-1. After the configura-
is latched on the falling edge of the clock with the least tion memory is entered, the only way to get back to the
significant bit (LSb) of the command being input first. user program memory is to exit the program/verify test
The data on pin RB7 is required to have a minimum mode by taking MCLR low (VIL).
setup and hold time (see AC/DC specs) with respect to TABLE 2-2: COMMAND MAPPING
the falling edge of the clock. Commands that have data
associated with them (read and load) are specified to

Command Mapping (MSb... LSb) Data

Load Configuration 0 0 0 0 0 0 0, data(14), 0
Load Data 0 0 0 0 1 0 0, data(14), 0
Read Data 0 0 0 1 0 0 0, data(14), 0
Increment Address 0 0 0 1 1 0
Begin programming 0 0 1 0 0 0
End Programming 0 0 1 1 1 0
Note: The clock must be disabled during In-Circuit Serial Programming.

 2000 Microchip Technology Inc. DS30228J-page 3-55

PIC16C6XX/7XX/9XX
FIGURE 2-2: PROGRAM FLOW CHART - PIC16C6XX/7XX/9XX PROGRAM MEMORY

Start

Set VDD = VDDP*

Set VPP = VIHH1

N=1

No
Program Cycle Yes Report programming
N > 25?
failure

Read Data
Command N=N+1 N=#
of Program Cycles

Increment Address No
Data correct?
Command
Yes
Apply 3N Additional
Program Cycles
Program Cycle

Load Data
No Command
All locations done?

Yes

Verify all locations Begin Programming

@ VDD min.* Command
VPP = VIHH2

Wait 100 µs
No Report verify
Data correct?
@ VDD min. Error
Yes
End Programming
Verify all locations Command
@ VDD max.*
VPP = VIHH2

No Report verify
Data correct? @ VDD max. Error

Yes

Done

* VDDP = VDD range for programming (typically 4.75V - 5.25V).

VDDmin = Minimum VDD for device operation.
VDDmax = Maximum VDD for device operation.

DS30228J-page 3-56  2000 Microchip Technology Inc.

PIC16C6XX/7XX/9XX
FIGURE 2-3: PROGRAM FLOW CHART - PIC16C6XX/7XX/9XX CONFIGURATION WORD & ID
LOCATIONS

Start

Set VDD = VDDP*

Set VPP = VIHH1

Load Configuration
Command

N=1

No Yes Read Data

Program ID Loc? Program Cycle Command

Increment Address No
Command N=N+1N=# Data Correct?
of Program Cycles
Yes
No
Address = 2004 No
N > 25
Yes
Yes
Increment Address
Command Report ID Apply 3N
Configuration Error Program Cycles

Increment Address
Command

Increment Address Program Cycle Read Data

Command 100 Cycles Command

No
Data Correct?

Yes

No Set VDD = VVDD

DDmin
min
Report Program Data Correct?
ID/Config. Error Read Data Command
Set VPP = VIHH2
Yes
No
Yes Set VDD = VVDD
DDmax
max
Done Data Correct? Read Data Command
Set VPP = VIHH2

VDDP = VDD Range for programming (Typically 4.25V – 5.25V)

VDDMIN = minimum VDD for device operation
VDDMAX = maximum VDD for device operation

 2000 Microchip Technology Inc. DS30228J-page 3-57

PIC16C6XX/7XX/9XX
2.2.1.2 LOAD DATA 2.3 Programming Algorithm Requires
Variable VDD
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as The PIC16C6XX/7XX/9XX uses an intelligent algo-
described previously. A timing diagram for the load data rithm. The algorithm calls for program verification at
command is shown in Figure 4-1. VDDmin as well as VDDmax. Verification at VDDmin
guarantees good “erase margin”. Verification at
2.2.1.3 READ DATA
VDDmax guarantees good “program margin”.
After receiving this command, the chip will transmit The actual programming must be done with VDD in the
data bits out of the memory currently accessed starting VDDP range (4.75 - 5.25V).
with the second rising edge of the clock input. The RB7
VDDP = VCC range required during programming.
pin will go into output mode on the second rising clock
edge, and it will revert back to input mode (hi-imped- VDD min. = minimum operating VDD spec for the part.
ance) after the 16th rising edge. A timing diagram of VDDmax = maximum operating VDD spec for the part.
this command is shown in Figure 4-2.
Programmers must verify the PIC16C6XX/7XX/9XX at
2.2.1.4 INCREMENT ADDRESS its specified VDDmax and VDDmin levels. Since
Microchip may introduce future versions of the
The PC is incremented when this command is PIC16C6XX/7XX/9XX with a broader VDD range, it is
received. A timing diagram of this command is shown best that these levels are user selectable (defaults are
in Figure 4-3. ok).

2.2.1.5 BEGIN PROGRAMMING Note: Any programmer not meeting these

2.2.1.6 END PROGRAMMING

After receiving this command, the chip stops program-

ming the memory (configuration program memory or
user program memory) that it was programming at the
time.

DS30228J-page 3-58  2000 Microchip Technology Inc.

PIC16C6XX/7XX/9XX
3.0 CONFIGURATION WORD
The PIC16C6XX/7XX/9XX family members have sev-
eral configuration bits. These bits can be programmed
(reads ’0’) or left unprogrammed (reads ’1’) to select
various device configurations. Figure 3-1 and
Figure 3-2 provides an overview of configuration bits.

 2000 Microchip Technology Inc. DS30228J-page 3-59

PIC16C6XX/7XX/9XX
FIGURE 3-1: CONFIGURATION WORD BIT MAP
Bit 6 5 4 3 2 1 0
Number:
13 12 11 10 9 8 7
PIC16C61/71 — — — — — — — — — CP0 PWRTE WDTE FOSC1 FOSC0
PIC16C62/64/65/73/74 — — — — — — — 0 CP1 CP0 PWRTE WDTE FOSC1 FOSC0
PIC16C62A/62B/63A/CR62/
63/
64A/CR64/65A/65B/66/67/
72/72A/73A/73B/74A/74B/76/
77/620/620A/621/621A/622/
622A/
712/716 CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0
PIC16C9XX/745/765 CP1 CP0 CP1 CP0 CP1 CP0 — — CP1 CP0 PWRTE WDTE FOSC1 FOSC0
Reserved, '–' write as '1' for PIC16C6XX/7XX/9XX
CP <1:0>, Code Protect

Device CP1 CP0 Code Protection

PIC16C622/622A
PIC16C62/62A/62B 0 0 All memory protected
PIC16C63/63A
0 1 Upper 3/4 memory protected
PIC16C64/64A/712/716
PIC16C65/65A/65B
1 0 Upper 1/2 memory protected
PIC16C66/67/72/72A
PIC16C73/73A/73B
PIC16C74/74A/74B/76/77
1 1 Code protection off
PIC16C745/765
PIC16C9XX
PIC16C61/71 — 0 All memory protected
PIC16C710/711 — 1 Off
PIC16C620 0 0 All memory protected
0 1 Do not use
1 0 Do not use
1 1 Code protection off
PIC16C621 0 0 All memory protected
1 0 Upper 1/2 memory protected
1 1 Code protection off

bit 6: BODEN, Brown Out Enable Bit

1 = Enabled
2 = Disable
bit 4: PWRTE/PWRTE, Power Up Timer Enable Bit
PIC16C61/62/64/65/71/73/74:
1 = Power up timer enabled
0 = Power up timer disabled
PIC16C620/620A/621/621A/622/622A/62A/63/63A/65A/65B/66/67/72/72A/73A/73B/74A/74B/76/77/710/
711/923/924/745/765:
0 = Power up timer enabled
1 = Power up timer disabled
bit 3-2: WDTE, WDT Enable Bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC<1:0>, Oscillator Selection Bit
11: RC oscillator
10: HS oscillator
01: XT oscillator
00: LP oscillator
bit 1-0: FOSC<1:0>, PIC16C745/765
11: E external clock with 4k PLL
10: H HS oscillator with 4k PL enabled
01: EC external clock, clkout on osc2
00: HS
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit
PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.

DS30228J-page 3-60  2000 Microchip Technology Inc.

PIC16C6XX/7XX/9XX
FIGURE 3-2: CONFIGURATION WORD FOR PIC16C773/774 DEVICE

CP1 CP0 BORV1 BORV0 CP1 CP0 - BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
Address 2007h
bit13 12 11 10 9 8 7 6 5 4 3 2 1 bit0

CP <1:0> Code Protection bits (2)

Device CP1 CP0 Code Protection

PIC16C773/774 0 0 All memory protected
0 1 Upper 3/4 memory protected
1 0 Upper 1/2 memory protected1
1 1 Code protection off

bit 11-10: BORV <1:0>: Brown-out Reset Voltage bits

11 = VBOR set to 2.5V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
bit 7: Unimplemented, Read as ’1’
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC <1:0>: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator

Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP <1:0> pairs have to be given the same value to enable the code protection scheme listed.

 2000 Microchip Technology Inc. DS30228J-page 3-61

PIC16C6XX/7XX/9XX
FIGURE 3-3: CONFIGURATION WORD, PIC16C710/711

CP0 CP0 CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 PWRTE WDTE FOSC1 FOSC0 Register: CONFIG
bit13 bit0 Address 2007h

bit 13-7 CP0: Code protection bits (2)

5-4: 1 = Code protection off
0 = All memory is code protected, but 00h - 3Fh is writable
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC <1:0>: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator

DS30228J-page 3-62  2000 Microchip Technology Inc.

PIC16C6XX/7XX/9XX
3.1 Embedding Configuration Word and ID Information in the Hex File.

 2000 Microchip Technology Inc. DS30228J-page 3-63

PIC16C6XX/7XX/9XX
3.2 Checksum The following table describes how to calculate the
checksum for each device. Note that the checksum cal-
3.2.1 CHECKSUM CALCULATIONS culation differs depending on the code protect setting.
Since the program memory locations read out differ-
Checksum is calculated by reading the contents of the
ently depending on the code protect setting, the table
PIC16C6XX/7XX/9XX memory locations and adding
describes how to manipulate the actual program mem-
up the opcodes up to the maximum user addressable
ory values to simulate the values that would be read
location, e.g., 0x1FF for the PIC16C74. Any carry bits
from a protected device. When calculating a checksum
exceeding 16-bits are neglected. Finally, the configura-
by reading a device, the entire program memory can
tion word (appropriately masked) is added to the check-
simply be read and summed. The configuration word
sum. Checksum computation for each member of the
and ID locations can always be read.
PIC16C6XX/7XX/9XX devices is shown in Table 3-1.
Note that some older devices have an additional value
The checksum is calculated by summing the following:
added in the checksum. This is to maintain compatibil-
• The contents of all program memory locations ity with older device programmer checksums.
• The configuration word, appropriately masked
• Masked ID locations (when applicable)
The least significant 16 bits of this sum is the check-
sum.

TABLE 3-1: CHECKSUM COMPUTATION

0x25E6 at
Code Blank
Device Checksum* 0 and max
Protect Value
address
PIC16C61 OFF SUM[0x000:0x3FF] + CFGW & 0x001F + 0x3FE0 0x3BFF 0x07CD
ON SUM_XNOR7[0x000:0x3FF] + (CFGW & 0x001F | 0x0060) 0xFC6F 0xFC15
PIC16C620 OFF SUM[0x000:0x1FF] + CFGW & 0x3F7F 0x3D7F 0x094D
ON SUM_ID + CFGW & 0x3F7F 0x3DCE 0x099C
PIC16C620A OFF SUM[0x000:0x1FF] + CFGW & 0x3F7F 0x3D7F 0x094D
ON SUM_ID + CFGW & 0x3F7F 0x3DCE 0x099C
PIC16C621 OFF SUM[0x000:0x3FF] + CFGW & 0x3F7F 0x3B7F 0x074D
1/2 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4EDE 0x0093
ALL CFGW & 0x3F7F + SUM_ID 0x3BCE 0x079C
PIC16C621A OFF SUM[0x000:0x3FF] + CFGW & 0x3F7F 0x3B7F 0x074D
1/2 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4EDE 0x0093
ALL CFGW & 0x3F7F + SUM_ID 0x3BCE 0x079C
PIC16C622 OFF SUM[0x000:0x7FF] + CFGW & 0x3F7F 0x377F 0x034D
1/2 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x5DEE 0x0FA3
3/4 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4ADE 0xFC93
ALL CFGW & 0x3F7F + SUM_ID 0x37CE 0x039C
PIC16C622A OFF SUM[0x000:0x7FF] + CFGW & 0x3F7F 0x377F 0x034D
1/2 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x5DEE 0x0FA3
3/4 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4ADE 0xFC93
ALL CFGW & 0x3F7F + SUM_ID 0x37CE 0x039C
PIC16CE623 OFF SUM[0x000:0x1FF] + CFGW & 0x3F7F 0x3D7F 0x094D
ON SUM_ID + CFGW & 0x3F7F 0x3DCE 0x099C
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR

DS30228J-page 3-64  2000 Microchip Technology Inc.

PIC16C6XX/7XX/9XX
TABLE 3-1: CHECKSUM COMPUTATION (CONTINUED)
0x25E6 at
Code Blank
Device Checksum* 0 and max
Protect Value
address
PIC16CE624 OFF SUM[0x000:0x3FF] + CFGW & 0x3F7F 0x3B7F 0x074D
1/2 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4EDE 0x0093
ALL CFGW & 0x3F7F + SUM_ID 0x3BCE 0x079C
PIC16CE625 OFF SUM[0x000:0x7FF] + CFGW & 0x3F7F 0x377F 0x034D
1/2 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x5DEE 0x0FA3
3/4 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4ADE 0xFC93
ALL CFGW & 0x3F7F + SUM_ID 0x37CE 0x039C
PIC16C62 OFF SUM[0x000:0x7FF] + CFGW & 0x003F + 0x3F80 0x37BF 0x038D
1/2 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:0x7FF] + CFGW & 0x003F + 0x37AF 0x1D69
3/4 0x3F80 0x379F 0x1D59
ALL SUM[0x000:0x1FF] + SUM_XNOR7[0x200:0x7FF] + CFGW & 0x003F + 0x378F 0x3735
0x3F80
SUM_XNOR7[0x000:0x7FF] + CFGW & 0x003F + 0x3F80
PIC16C62A OFF SUM[0x000:0x7FF] + CFGW & 0x3F7F 0x377F 0x034D
1/2 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x5DEE 0x0FA3
3/4 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4ADE 0xFC93
ALL CFGW & 0x3F7F + SUM_ID 0x37CE 0x039C
PIC16C62B OFF SUM[0x000:0x7FF] + CFGW & 0x3F7F 0x377F 0x034D
1/2 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x5DEE 0x0FA3
3/4 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4ADE 0xFC93
ALL CFGW & 0x3F7F + SUM_ID 0x37CE 0x039C
PIC16C63 OFF SUM[0x000:0xFFF] + CFGW & 0x3F7F 0x2F7F 0xFB4D
1/2 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x51EE 0x03A3
3/4 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x40DE 0xF293
ALL CFGW & 0x3F7F + SUM_ID 0x2FCE 0xFB9C
PIC16C63A OFF SUM[0x000:0xFFF] + CFGW & 0x3F7F 0x2F7F 0xFB4D
1/2 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x51EE 0x03A3
3/4 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x40DE 0xF293
ALL CFGW & 0x3F7F + SUM_ID 0x2FCE 0xFB9C
PIC16C64 OFF SUM[0x000:0x7FF] + CFGW & 0x003F + 0x3F80 0x37BF 0x038D
1/2 SUM[0x000:0x3FF] + SUM_XNOR7[0x400:0x7FF] + CFGW & 0x003F + 0x37AF 0x1D69
3/4 0x3F80 0x379F 0x1D59
ALL SUM[0x000:0x1FF] + SUM_XNOR7[0x200:0x7FF] + CFGW & 0x003F + 0x378F 0x3735
0x3F80
SUM_XNOR7[0x000:0x7FF] + CFGW & 0x003F + 0x3F80
PIC16C64A OFF SUM[0x000:0x7FF] + CFGW & 0x3F7F 0x377F 0x034D
1/2 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x5DEE 0x0FA3
3/4 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4ADE 0xFC93
ALL CFGW & 0x3F7F + SUM_ID 0x37CE 0x039C
PIC16C65 OFF SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 0x2FBF 0xFB8D
1/2 SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F + 0x2FAF 0x1569
3/4 0x3F80 0x2F9F 0x1559
ALL SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F + 0x2F8F 0x2F35
0x3F80
SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR

 2000 Microchip Technology Inc. DS30228J-page 3-65

PIC16C6XX/7XX/9XX
TABLE 3-1: CHECKSUM COMPUTATION (CONTINUED)
0x25E6 at
Code Blank
Device Checksum* 0 and max
Protect Value
address
PIC16C65A OFF SUM[0x000:0xFFF] + CFGW & 0x3F7F 0x2F7F 0xFB4D
1/2 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x51EE 0x03A3
3/4 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x40DE 0xF293
ALL CFGW & 0x3F7F + SUM_ID 0x2FCE 0xFB9C
PIC16C65B OFF SUM[0x000:0xFFF] + CFGW & 0x3F7F 0x2F7F 0xFB4D
1/2 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x51EE 0x03A3
3/4 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x40DE 0xF293
ALL CFGW & 0x3F7F + SUM_ID 0x2FCE 0xFB9C
PIC16C66 OFF SUM[0x000:0x1FFF] + CFGW & 0x3F7F 0x1F7F 0xEB4D
1/2 SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID 0x39EE 0xEBA3
3/4 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x2CDE 0xDE93
ALL CFGW & 0x3F7F + SUM_ID 0x1FCE 0xEB9C
PIC16C67 OFF SUM[0x000:0x1FFF] + CFGW & 0x3F7F 0x1F7F 0xEB4D
1/2 SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID 0x39EE 0xEBA3
3/4 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x2CDE 0xDE93
ALL CFGW & 0x3F7F + SUM_ID 0x1FCE 0xEB9C
PIC16C710 OFF SUM[0x000:0x1FF] + CFGW & 0x3FFF 0x3DFF 0x09CD
ON SUM[0x00:0x3F] + CFGW & 0x3FFF + SUM_ID 0x3E0E 0xEFC3
PIC16C71 OFF SUM[0x000:0x3FF] + CFGW & 0x001F + 0x3FE0 0x3BFF 0x07CD
ON SUM_XNOR7[0x000:0x3FF] + (CFGW & 0x001F | 0x0060) 0xFC6F 0xFC15
PIC16C711 OFF SUM[0x000:0x03FF] + CFGW & 0x3FFF 0x3BFF 0x07CD
ON SUM[0x00:0x3FF] + CFGW & 0x3FFF + SUM_ID 0x3C0E 0xEDC3
PIC16C712 OFF SUM[0x000:0x07FF] + CFGW & 0x3F7F 0x377F 0x034D
1/2 SUM[0x000:0x03FF] + CFGW & 3F7F + SUM_ID 0x5DEE 0xF58A
ALL CFGW & 0x3F7F + SUM_ID 0x37CE 0x039C
PIC16C716 OFF SUM[0x000:0x07FF] + CFGW & 0x3F7F 0x377F 0x034D
1/2 SUM[0x000:0x03FF] + CFGW & 0x3F7F + SUM_ID 0x5DEE 0x0FA3
3/4 SUM]0x000:0x01FF] + CFGW & 0x3F7F + SUM_ID 0x4ADE 0xFC93
ALL CFGW & 0x3F7F + SUM_ID 0x37CE 0x039C
PIC16C72 OFF SUM[0x000:0x7FF] + CFGW & 0x3F7F 0x377F 0x034D
1/2 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x5DEE 0x0FA3
3/4 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4ADE 0xFC93
ALL CFGW & 0x3F7F + SUM_ID 0x37CE 0x039C
PIC16C72A OFF SUM[0x000:0x7FF] + CFGW & 0x3F7F 0x377F 0x034D
1/2 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x5DEE 0x0FA3
3/4 SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID 0x4ADE 0xFC93
ALL CFGW & 0x3F7F + SUM_ID 0x37CE 0x039C
PIC16C73 OFF SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 0x2FBF 0xFB8D
1/2 SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F + 0x2FAF 0x1569
3/4 0x3F80 0x2F9F 0x1559
ALL SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F + 0x2F8F 0x2F35
0x3F80
SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
PIC16C73A OFF SUM[0x000:0xFFF] + CFGW & 0x3F7F 0x2F7F 0xFB4D
1/2 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x51EE 0x03A3
3/4 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x40DE 0xF293
ALL CFGW & 0x3F7F + SUM_ID 0x2FCE 0xFB9C
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR

DS30228J-page 3-66  2000 Microchip Technology Inc.

PIC16C6XX/7XX/9XX
TABLE 3-1: CHECKSUM COMPUTATION (CONTINUED)
0x25E6 at
Code Blank
Device Checksum* 0 and max
Protect Value
address
PIC16C73B OFF SUM[0x000:0xFFF] + CFGW & 0x3F7F 0x2F7F 0xFB4D
1/2 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x51EE 0x03A3
3/4 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x40DE 0xF293
ALL CFGW & 0x3F7F + SUM_ID 0x2FCE 0xFB9C
PIC16C74 OFF SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80 0x2FBF 0xFB8D
1/2 SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F + 0x2FAF 0x1569
3/4 0x3F80 0x2F9F 0x1559
ALL SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F + 0x2F8F 0x2F35
0x3F80
SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
PIC16C74A OFF SUM[0x000:0xFFF] + CFGW & 0x3F7F 0x2F7F 0xFB4D
1/2 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x51EE 0x03A3
3/4 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x40DE 0xF293
ALL CFGW & 0x3F7F + SUM_ID 0x2FCE 0xFB9C
PIC16C74B OFF SUM[0x000:0xFFF] + CFGW & 0x3F7F 0x2F7F 0xFB4D
1/2 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x51EE 0x03A3
3/4 SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID 0x40DE 0xF293
ALL CFGW & 0x3F7F + SUM_ID 0x2FCE 0xFB9C
PIC16C76 OFF SUM[0x000:0x1FFF] + CFGW & 0x3F7F 0x1F7F 0xEB4D
1/2 SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID 0x39EE 0xEBA3
3/4 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x2CDE 0xDE93
ALL CFGW & 0x3F7F + SUM_ID 0x1FCE 0xEB9C
PIC16C77 OFF SUM[0x000:0x1FFF] + CFGW & 0x3F7F 0x1F7F 0xEB4D
1/2 SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID 0x39EE 0xEBA3
3/4 SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID 0x2CDE 0xDE93
ALL CFGW & 0x3F7F + SUM_ID 0x1FCE 0xEB9C
PIC16C773 OFF SUM[0x000:0x0FFF] + CFGW & 0x3F7F 0x2F7F 0xFB4D
1/2 SUM[0x000:07FF] + CFGW & 0x3F7F + SUM_ID 0x55EE 0x07A3
3/4 SUM[0x000:03FF] + CFGW & 0x3F7F + SUM_ID 0x48DE 0xFA93
ALL CFGW & 0x3F7F + SUM_ID 0x3BCE 0x079C
PIC16C774 OFF SU:M[0x000:0FFF] + CFGW & 0x3F7F 0x2F7F 0xFB4D
1/2 SUM[0x000:07FF] + CFGW & 0x3F7F + SUM_ID 0X55EE 0x07A3
3/4 SUM[0x000:03FF] + CFGW & 0x3F7F + SUM_ID 0X48DE 0xFA93
ALL CFGW & 0x3F7F + SUM_ID 0x3BCE 0X079C
PIC16C923 OFF SUM[0x000:0xFFF] + CFGW & 0x3F3F 0x2F3F 0xFB0D
1/2 SUM[0x000:0x7FF] + CFGW & 0x3F3F + SUM_ID 0x516E 0x0323
3/4 SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID 0x405E 0xF213
ALL CFGW & 0x3F3F + SUM_ID 0x2F4E 0xFB1C
PIC16C924 OFF SUM[0x000:0xFFF] + CFGW & 0x3F3F 0x2F3F 0xFB0D
1/2 SUM[0x000:0x7FF] + CFGW & 0x3F3F + SUM_ID 0x516E 0x0323
3/4 SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID 0x405E 0xF213
ALL CFGW & 0x3F3F + SUM_ID 0x2F4E 0xFB1C
PIC16C745 OFF SUM(0000:1FFF) + CFGW & 0x3F3F 1F3F EB0D
1000:1FFF SUM(0000:0FFF) + CFGW & 0x3F3F+SUM_ID 396E EB23
800:1FFF SUM(0000:07FF) + CFGW & 0x3F3F + SUM_ID 2C5E DE13
ALL CFGW * 0x3F3F + SUM_ID 1F4E EB1C
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR

 2000 Microchip Technology Inc. DS30228J-page 3-67

PIC16C6XX/7XX/9XX
TABLE 3-1: CHECKSUM COMPUTATION (CONTINUED)
0x25E6 at
Code Blank
Device Checksum* 0 and max
Protect Value
address
PIC16c765 OFF SUM(0000:1FFF) + CFGW & 0x3F3F 1F3F EB0D
1000:1FFF SUM(0000:0FFF) + CFGW & 0x3F3F+SUM_ID 396E EB23
800:1FFF SUM(0000:07FF) + CFGW & 0x3F3F + SUM_ID 2C5E DE13
ALL CFGW * 0x3F3F + SUM_ID 1F4E EB1C
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR

DS30228J-page 3-68  2000 Microchip Technology Inc.

PIC16C6XX/7XX/9XX
4.0 PROGRAM/VERIFY MODE
TABLE 4-1: AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +40°C, unless otherwise stated, (20°C recommended)
Operating Voltage: 4.5V ≤ VDD ≤ 5.5V, unless otherwise stated.

Parameter
Sym. Characteristic Min. Typ. Max. Units Conditions
No.
General
PD1 VDDP Supply voltage during programming 4.75 5.0 5.25 V
PD2 IDDP Supply current (from VDD) – – 20 mA
during programming
PD3 VDDV Supply voltage during verify VDDmin – VDDmax V Note 1
PD4 VIHH1 Voltage on MCLR/VPP during 12.75 – 13.25 V Note 2
programming
PD5 VIHH2 Voltage on MCLR/VPP during verify VDD + 4.5 – 13.25 –
PD6 IPP Programming supply current (from – – 50 mA
VPP)
PD9 VIH (RB6, RB7) input high level 0.8 VDD – – V Schmitt Trigger input
PD8 VIL (RB6, RB7) input low level 0.2 VDD – – V Schmitt Trigger input

Serial Program Verify

P1 TR MCLR/VPP rise time (VSS to VHH) – – 8.0 µs
for test mode entry
P2 Tf MCLR Fall time – – 8.0 µs
P3 Tset1 Data in setup time before clock ↓ 100 – – ns
P4 Thld1 Data in hold time after clock ↓ 100 – – ns
P5 Tdly1 Data input not driven to next clock 1.0 – – µs
input (delay required between com-
mand/data or command/command)
P6 Tdly2 Delay between clock ↓ to clock ↑ of 1.0 – – µs
next command or data
P7 Tdly3 Clock ↑ to date out valid 200 – – ns
(during read data)
P8 Thld0 Hold time after MCLR ↑ 2 – – µs
Note 1: Program must be verified at the minimum and maximum VDD limits for the part.
2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.

 2000 Microchip Technology Inc. DS30228J-page 3-69

PIC16C6XX/7XX/9XX
FIGURE 4-1: LOAD DATA COMMAND (PROGRAM/VERIFY)
VIHH
MCLR/VPP
100ns P6
P8
1 2 3 4 5 6 1µs min. 1 2 3 4 5 15
RB6
(CLOCK)
100ns
RB7 0 0 0 0
(DATA) 1 0 0 0
P5
P3 P3
P4 1µs min.
P4

}
}

}
}
100ns 100ns
min. min.
Program/Verify Test Mode
Reset

FIGURE 4-2: READ DATA COMMAND (PROGRAM/VERIFY)

VIHH
MCLR/VPP 100ns P6
P8
1 2 3 4 5 6 1µs min. 1 2 3 4 5 15
RB6
(CLOCK)
100ns P7
RB7 0 0 1 0 0 0
(DATA) P5
P4
P3 1µs min.
}
}

100ns
min. RB7
RB7 = output input

Program/Verify Test Mode

Reset

FIGURE 4-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

VIHH
MCLR/VPP
P6
Next Command
1µs min.
1 2 3 4 5 6 1 2
RB6
(CLOCK)

RB7
0 1 1 0 0 0 0 0
(DATA)
P5
P3 P4 1µs min.
}
}

100ns
min
Program/Verify Test Mode
Reset

DS30228J-page 3-70  2000 Microchip Technology Inc.

PIC17C7XX
In-Circuit Serial Programming for PIC17C7XX OTP MCUs
This document includes the programming 1.1 Hardware Requirements
specifications for the following devices:
Since the PIC17C7XX under programming is actually
• PIC17C752 executing code from “boot ROM,” a clock must be pro-
• PIC17C756 vided to the part. Furthermore, the PIC17C7XX under
• PIC17C756A programming may have any oscillator configuration
• PIC17C762 (EC, XT, LF or RC). Therefore, the external clock driver
must be able to overdrive pulldown in RC mode. CMOS
• PIC17C766
drivers are required since the OSC1 input has a
Schmitt trigger input with levels (typically) of 0.2 VDD
1.0 PROGRAMMING THE and 0.8 VDD. See the PIC17C7XX data sheet
PIC17C7XX (DS30289) for exact specifications.
The PIC17C7XX requires two programmable power
The PIC17C7XX is programmed using the TABLWT supplies, one for VDD (3.0V to 5.5V recommended) and
instruction. The table pointer points to the internal one for VPP (13 ± 0.25V). Both supplies should have a
EPROM location start. Therefore, a user can program minimum resolution of 0.25V.
an EPROM location while executing code (even from
The PIC17C7XX uses an intelligent algorithm. The
internal EPROM). This programming specification
algorithm calls for program verification at VDDmin as
applies to PIC17C7XX devices in all packages.
well as VDDmax. Verification at VDDmin guarantees
For the convenience of a programmer developer, a good “erase margin”. Verification at VDDmax guaran-
“program & verify” routine is provided in the on-chip test tees good “program margin.” Three times (3X)
program memory space. The program resides in ROM additional pulses will increase program margin beyond
and not EPROM, therefore, it is not erasable. The “pro- VDDmax and insure safe operation in user system.
gram/verify” routine allows the user to load any
The actual programming must be done with VDD in the
address, program a location, verify a location or incre-
VDDP range (Parameter PD1).
ment to the next location. It allows variable program-
ming pulse width. VDDP = VDD range required during programming.
The PIC17C7XX group of the High End Family has VDDmin. = minimum operating VDD spec. for the part.
added a feature that allows the serial programming of VDDmax. = maximum operating VCC spec for the part.
the device. This is very useful in applications where it is
desirable to program the device after it has been man- Programmers must verify the PIC17C7XX at its speci-
ufactured into the users system (In-circuit Serial Pro- fied VDDmax and VDDmin levels. Since Microchip may
gramming (ISP)). This allows the product to be shipped introduce future versions of the PIC17C7XX with a
with the most current version of the firmware, since the broader VDD range, it is best that these levels are user
microcontroller can be programmed just before final selectable (defaults are ok). Blank checks should be
test as opposed to before board manufacture. Devices performed at VDDMIN.
may be serialized to make the product unique, “special” Note: Any programmer not meeting these
variants of the product may be offered, and code requirements may only be classified as
updates are possible. This allows for increased design “prototype” or “development” programmer
flexibility. but not a “production” quality programmer.

 2000 Microchip Technology Inc. DS30274B-page 3-71

PIC17C7XX
FIGURE 1-1: PIC17C752/756/756A/762/766 LCC

RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15

RC2/AD2

RC5/AD5
RC6/AD6
RC7/AD7
RC1/AD1

RC3/AD3
RC4/AD4
RC0/AD0
RH1
RH0

VDD

VSS

RJ7
RJ6
NC
1110 9 8 7 6 5 4 3 2 1 84 83828180 7978777675
RH2 12 74 RJ5
RH3 13 73 RJ4
RD1/AD9 14 72 RA0/INT
RD0/AD8 15 71 RB0/CAP1
RE0/ALE 16 70 RB1/CAP2
RE1/OE 17 69 RB3/PWM2
RE2/WR 18 68 RB4/TCLK12
RE3/CAP4 19
PIC17C762/766 67 RB5/TCLK3
MCLR/VPP 20 66 RB2/PWM1
TEST 21 65 VSS
NC 22 Top View 64 NC
VSS 23 63 OSC2/CLKOUT
VDD 24 62 OSC1/CLKIN
RF7/AN11 25 61 VDD
RF6/AN10 26 60 RB7/SDO
RF5/AN9 27 59 RB6/SCK
RF4/AN8 28 58 RA3/SDI/SDA
RF3/AN7 29 57 RA2/SS/SCL
RF2/AN6 30 56 RA1/T0CKI
RH4/AN12 31 55 RJ3
RH5/AN13 32 54 RJ2
3334353637383940414243444546 474849 50 51 52 53

RD2/AD10
RD3/AD11
RD4/AD12
RD5/AD13
RD6/AD14
RD7/AD15
RC0/AD0

RC1/AD1
RC2/AD2
RC3/AD3
RC4/AD4
RC5/AD5
RC6/AD6
RC7/AD7
RJ1
AVDD
AVSS

VSS
VDD
RH6/AN14
RH7/AN15

RJ0
RG3/AN0/VREF+

NC
RF1/AN5
RF0/AN4

RG1/AN2
RG0/AN3

RG4/CAP3
RG5/PWM3

RG6/RX2/DT2

RA4/RX1/DT1
RG7/TX2/CK2

RA5/TX1/CK1
RG2/AN1/VREF-

VDD

VSS
NC
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
RD1/AD9 10 60 RA0/INT
RD0/AD8 11 59 RB0/CAP1
RE0/ALE 12 58 RB1/CAP2
RE1/OE 13 57 RB3/PWM2
RE2/WR 14 56 RB4/TCLK12
RE3/CAP4 15 55 RB5/TCLK3
MCLR/VPP 16 PIC17C752/756/756A 54 RB2/PWM1
TEST 17 53 VSS
NC 18 Top View 52 NC
VSS 19 51 OSC2/CLKOUT
VDD 20 50 OSC1/CLKIN
RF7/AN11 21 49 VDD
RF6/AN10 22 48 RB7/SDO
RF5/AN9 23 47 RB6/SCK
RF4/AN8 24 46 RA3/SDI/SDA
RF3/AN7 25 45 RA2/SS/SCL
RF2/AN6 26 44 RA1/T0CKI

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AVSS

VSS
AVDD

VDD
RF1/AN5
RF0/AN4

RG1/AN2
RG0/AN3

RG4/CAP3
RG5/PWM3
RG7/TX2/CK2
RG6/RX2/DT2
RA5/TX1/CK1
RA4/RX1/DT1
NC
RG3/AN0/VREF+
RG2/AN1/VREF-

TABLE 1-1: PIN DESCRIPTIONS (DURING PROGRAMMING IN PARALLEL MODE): PIC17C7XX

During Programming
Pin Name Pin Name Pin Type Pin Description
RA4:RA0 RA4:RA0 I Necessary in programming mode
TEST TEST I Must be set to “high” to enter programming mode
PORTB<7:0> DAD15:DAD8 I/O Address & data: high byte
PORTC<7:0> DAD7:DAD0 I/O Address & data: low byte
MCLR/VPP VPP P Programming Power
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power

DS30274B-page 3-72  2000 Microchip Technology Inc.

PIC17C7XX
2.0 PARALLEL MODE PROGRAM 2.1 Program/Verify Mode
ENTRY The program/verify mode is intended for full-feature
To execute the programming routine, the user must hold programmers. This mode offers the following capabili-
TEST pin high, RA2, RA3 must be low and RA4 must ties:
be high (after power-up) while keeping MCLR low and a) Load any arbitrary 16-bit address to start pro-
then raise MCLR pin from VIL to VDD or VPP. This will gram and/or verify at that location.
force FFE0h in the program counter and execution will
b) Increment address to program/verify the next
begin at that location (the beginning of the boot code)
location.
following reset.
c) Allows arbitrary length programming pulse width.
d) Following a “verify” allows option to program the
Note: The Oscillator must not have 72 OSC same location or increment and verify the next
clocks while the device MCLR is between location.
VIL and VIHH. e) Following a “program” allows options to program
the same location again, verify the same loca-
All unused pins during programming are in hi-imped-
tion or to increment and verify the next location.
ance state.
PORTB (RB pins) has internal weak pull-ups which are
active during the programming mode. When the TEST
pin is high, the Power-up timer (PWRT) and Oscillator
Start-up Timers (OST) are disabled.

FIGURE 2-1: PROGRAMMING/VERIFY STATE DIAGRAM

Pulse
RA1 Increment
Address

Pulse RA1
Pulse Pulse (Raise RA1
Jump to RA1 RA1 after RA0↓)
Program Load
Reset Reset
Routine Address

RA0↑

Pulse RA0
Raise RA1 Program (RA0 pulse
before RA0↓ width is
programming time)

 2000 Microchip Technology Inc. DS30274B-page 3-73

PIC17C7XX
2.1.1 LOADING NEW ADDRESS 2.1.3 PROGRAM CYCLE

The program allows new address to be loaded right out “Program cycle” is entered from “verify cycle” or pro-
of reset. A 16-bit address is presented on ports B (high gram cycle” itself. After a verify, pulsing RA0 will begin
byte) and C (low byte) and the RA1 is pulsed (0 → 1, a program cycle. 16-bit data must be presented on
then 1 → 0). The address is latched on the rising edge PORTB (high byte) and PORTC (low byte) before RA0
of RA1. See timing diagrams for details. After loading is raised.
an address, the program automatically goes into a “ver- The data is sampled 3 TCY cycles after the rising edge
ify cycle.” To load a new address at any time, the of RA0. Programming continues for the duration of RA0
PIC17C7XX must be reset and the programming mode pulse.
re-entered.
At the end of programming, the user can choose one of
2.1.2 VERIFY (OR READ) MODE three different routes. If RA1 is kept low and RA0 is
pulsed again, the same location will be programmed
“Verify mode” can be entered from “Load address” again. This is useful for applying over programming
mode, “program mode” or “verify mode.” In verify mode pulses. If RA1 is raised before RA0 falling edge, then a
pulsing RA1 will turn on PORTB and PORTC output verify cycle is started without address increment. Rais-
drivers and output the 16-bit value from the current ing RA1 after RA0 goes low will increment address and
location. Pulsing RA1 again will increment location begin verify cycle on the next address.
count and be ready for the next verify cycle. Pulsing
RA0 will begin a program cycle.

FIGURE 2-2: PIC17C7XX PROGRAM MEMORY MAP

PIC17C752 PIC17C756/756A PIC17C762 PIC17C766

0000h
FE00h FOSC0 On-chip On-chip On-chip On-chip
Program Program Program Program
FE01h FOSC1 EPROM EPROM EPROM EPROM
1FFFh
FE02h WDTPS0

FE03h WDTPS1

FE04h PM0 3FFFh

FE05h Reserved

FE06h PM1

FE07h Reserved

FE08h Reserved

FE09h Reserved

FE0Eh BODEN FE00h Configuration Configuration Configuration Configuration

FE0Fh Word Word Word Word
FE0Fh PM2

FFFFh

DS30274B-page 3-74  2000 Microchip Technology Inc.

PIC17C7XX
3.0 PARALLEL MODE PROGRAMMING SPECIFICATIONS

FIGURE 3-1: PROGRAMMING ROUTINE FLOWCHART

RESET

NO
RA2 = 0 RA1 = 0
RA3 = 0
RA4 = 1
YES

NO
RA1 = 1
MCLR = 1
Bport = 0xE1
(hold for 10 TCY) YES

NO
Read MSB of data RA1 = 0
Present address
on ports RB, RC from portB.
hold TCY after Read LSB of data
from portC YES
RA1 changes
to 1 Enable RA0 to end
program cycle B and C
ports not
driven by part
NO
RA1 = 0 Program
16-bit
data If programming is desired
YES force portB = MSB of data
force portC = LSB of data
(hold 10 Tcy after RA0
NO
RA1 = 1 is raised)
NO
RA0 = 0
YES
YES YES
YES RA0 = 1
Stop driving
address on ports YES
RA1 = 0 RA0 = 1 NO

NO
NO NO RA1 = 1
NO
RA1 = 0 NO
RA1 = 1 YES

YES
Increment
Address
NO
RA1 = 1

YES Bport = xxx

- B port is forced by the part
B port =
MSB of Data
C port =
LSB of Data

Bport = xxx - B port tristate, should be forced by user

Min RA + high or low = 10 TCY

 2000 Microchip Technology Inc. DS30274B-page 3-75

PIC17C7XX
FIGURE 3-2: RECOMMENDED PROGRAMMING ALGORITHM FOR USER EPROM

Start

Load new address

Pulse-count = 0

Set VDD = VDDMIN

Verify blank

Pulse NO
Blank Issue “Blank check fail”
Check? error message

YES

Load new data

Set VDD = VDDMIN
Program error message
Issue error message
Set VDD to VDDP “Fail verify @ VDDMIN/MAX”

Program using 100 µs

pulse increment YES
pulse-count
NO
Pass?

Set VDD = VDDMIN

verify location(s)

Verify location Set VDD = VDDMIN

for correct date verify location

Apply (3x Pulse-count)

YES more 100 µs programming
Pass?
pulses for margin
(Over programming)
NO
NO
Pulse-
Count
>25

YES

Location fails
programming issue error
message “Unable to
programming location”

DS30274B-page 3-76  2000 Microchip Technology Inc.

PIC17C7XX
FIGURE 3-3: RECOMMENDED PROGRAMMING ALGORITHM FOR CONFIGURATION WORDS

Start

Load new address

Pulse-count = 0

Set VDD = VDDmin

Verify blank

Pass NO
Blank Issue “blank check fail”
check? error message

YES

Load new data Programming error:

Set VDD = VDDMIN
Issue error message
“Fail verify @ VDDmin/max”

Set VDD = VDDP

YES
Program using 100 µs NO
pulse increment Pass?
pulse-count

YES Set VDD = VDDmax

Pulse
count Verify location(s)
<100

NO SetVVDD==VVDDminmin
Set DD DD
Verify location for Verify location
correct data

YES
Pass?

Location fails
programming, issue error
message “Unable to
program location”

 2000 Microchip Technology Inc. DS30274B-page 3-77

PIC17C7XX
4.0 SERIAL MODE PROGRAM 4.2 Serial Program Mode Entry
ENTRY To place the device into the serial programming test
mode, two pins will need to be placed at VIHH. These
4.1 Hardware Requirements
are the TEST pin and the MCLR/VPP pins. Also, the fol-
Certain design criteria must be taken into account for lowing sequence of events must occur:
ISP. Seven pins are required for the interface. These 1. The TEST pin is placed at VIHH.
are shown in Table 4-1. 2. The MCLR/VPP pin is placed at VIHH.
There is a setup time between step 1 and step 2 that
must be meet (See “Electrical Specifications for Serial
Programming Mode” on page 93.)
After this sequence the Program Counter is pointing to
Program Memory Address 0xFF60. This location is in
the Boot ROM. The code initializes the USART/SCI so
that it can receive commands. For this the device must
be clocked. The device clock source in this mode is the
RA1/T0CKI pin. Once the USART/SCI has been initial-
ized, commands may be received. The flow is show in
these 3 steps:
1. The device clock source starts.
2. Wait 80 device clocks for Boot ROM code
to configure the USART/SCI.
3. Commands may be sent now.

TABLE 4-1: ISP Interface Pins

During Programming

Name Function Type Description

RA4/RX/DT DT I/O Serial Data
RA5/TX/CK CK I Serial Clock
RA1/T0CKI OSCI I Device Clock Source
TEST TEST I Test mode selection control input. Force to VIHH,
MCLR/VPP MCLR/VPP P Programming Power
VDD VDD P Power Supply
VSS VSS P Ground

DS30274B-page 3-78  2000 Microchip Technology Inc.

PIC17C7XX
4.3 Software Commands 4.3.1 RESET PROGRAM MEMORY POINTER

This feature is similar to that of the PIC16CXXX mid- This is used to clear the address pointer to the Program
range family, but the programming commands have Memory. This ensures that the pointer is at a known
been implemented in the device Boot ROM. The Boot state as well as pointing to the first location in program
ROM is located in the program memory from 0xFF60 to memory.
0xFFFF. The ISP mode is entered when the TEST pin
has a VIHH voltage applied. Once in ISP mode, the 4.3.2 INCREMENT ADDRESS
USART/SCI module is configured as a synchronous This is used to increment the address pointer to the
slave receiver, and the device waits for a command to Program Memory. This is used after the current location
be received. The ISP firmware recognizes eight com- has been programmed (or read).
mands. These are shown in Table 4-2.
TABLE 4-2: ISP COMMANDS
Command Value
RESET PROGRAM 0000 0000
MEMORY POINTER
LOAD DATA 0000 0010
READ DATA 0000 0100
INCREMENT ADDRSS 0000 0110
BEGIN PROGRAMMING 0000 1000
LOAD ADDRESS 0000 1010
READ ADDRESS 0000 1100
END PROGRAMMING 0000 1110

FIGURE 4-1: RESET ADDRESS POINTER COMMAND (PROGRAM/VERIFY)

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2

RA5 (Clock)
PS6
PS4PS5

RA4 (Data) 0 0 0 0 0 0 0 0

RA4 = Input

Reset
Program/Verify Test Mode

FIGURE 4-2: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2

RA5 (Clock)
PS6
PS4PS5
RA4 (Data) 0 1 1 0 0 0 0 0

RA4 = Input

Reset
Program/Verify Test Mode

 2000 Microchip Technology Inc. DS30274B-page 3-79

PIC17C7XX
4.3.3 LOAD ADDRESS 4.3.4 READ ADDRESS

This is used to load the address pointer to the Program This is used so that the current address in the Program
Memory with a specific 16-bit value. This is useful when Memory pointer can be determined. This can be used
a specific range of locations are to be accessed. to increase the robustness of the ISP programming
(ensure that the Program Memory pointers are still in
sync).

FIGURE 4-3: LOAD ADDRESS COMMAND

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2 3 15 16 1

RA5 (Clock)
PS7 PS6
PS4PS5

RA4 (Data) 0 1 0 1 0 0 0 0

RA4 = Input

Reset
Program/Verify Test Mode

FIGURE 4-4: READ ADDRESS COMMAND

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2 3 15 16 1

RA5 (Clock)
PS8 PS6
PS4PS5

PS9
RA4 (Data) 0 0 1 1 0 0 0 0

RA4 = Input RA4 = Output

Reset
Program/Verify Test Mode

DS30274B-page 3-80  2000 Microchip Technology Inc.

PIC17C7XX
4.3.5 LOAD DATA 4.3.6 READ DATA

This is used to load the 16-bit data that is to be pro- This is used to read the data in Program Memory that
grammed into the Program Memory location. The Pro- is pointed to by the current address pointer. This is use-
gram Memory address may be modified after the data ful for doing a verify of the programming cycle and can
is loaded. This data will not be programmed until a be used to determine the number for programming
BEGIN PROGRAMMING command is executed. cycles that are required for the 3X overprogramming.

FIGURE 4-5: LOAD DATA COMMAND

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2 3 15 16 1

RA5 (Clock)
PS7 SP6
PS4PS5

RA4 (Data) 0 1 0 0 0 0 0 0

RA4 = Input

Reset
Program/Verify Test Mode

FIGURE 4-6: READ DATA COMMAND

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2 3 15 16 1

RA5 (Clock)
PS8 PS6
PS4PS5

PS9
RA4 (Data) 0 0 1 0 0 0 0 0

RA4 = Input RA4 = Output

Reset
Program/Verify Test Mode

 2000 Microchip Technology Inc. DS30274B-page 3-81

PIC17C7XX
4.3.7 BEGIN PROGRAMMING 4.3.8 3X OVERPROGRAMMING

This is used to program the current 16-bit data (last Once a location has been both programmed and veri-
data sent with LOAD DATA Command) into the Pro- fied over a range of voltages, 3X overprogramming
gram Memory at the address specified by the current should be applied. In other words, apply three times the
address pointer. The programming cycle time is speci- number of programming pulses that were required to
fied by specification P10. After this time has elapsed, program a location in memory, to ensure a solid pro-
any command must be sent, which wakes the proces- gramming margin.
sor from the Long Write cycle. This command will be This means that every location will be programmed a
the next executed command. minimum of 4 times (1 + 3X overprogramming).

FIGURE 4-7: BEGIN PROGRAMMING COMMAND (PROGRAM)

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2 7 8

RA5 (Clock)
PS10
PS4PS5

RA4 (Data) 0 0 0 1 0 0 0 0

RA4 = Input

Reset
Program/Verify Test Mode

DS30274B-page 3-82  2000 Microchip Technology Inc.

PIC17C7XX
FIGURE 4-8: RECOMMENDED PROGRAMMING FLOWCHART

TEST = MCLR = RA4 = RA5 = Vss

START 4.75V < VDD < 5.25V

TEST = Vihh

MCLR = Vihh

Start Device Clock (on RA0),

Wait 80 Device Clocks

ISP Command
RESET ADDRESS

ISP Command
INCREMENT ADDRESS
N=1
or
LOAD ADDRESS

ISP Command
LOAD DATA

ISP Command No Yes Report

BEGIN PROGRAMMING N > 25? Programming
Failure

Wait approx 100 ms

ISP Command
READ DATA

No
Data Correct? N=N+1
Yes

N = 3N

ISP Command
BEGIN PROGRAMMING

Verify all Locations

@ Vddmin
Wait approx 100 ms
Report
No
Verify
Data Correct?
N=N-1 Error
Yes @ Vddmin
No Verify all Locations
N = 0?
@ Vddmax
Yes
Yes Report
No Programmed all Yes No Verify
required locations? Data Correct?
Error
@ Vddmax

DONE

 2000 Microchip Technology Inc. DS30274B-page 3-83

PIC17C7XX
5.0 CONFIGURATION WORD 5.1 Reading Configuration Word
Configuration bits are mapped into program memory. The PIC17C7XX has seven configuration locations
Each bit is assigned one memory location. In erased (Table 5-1). These locations can be programmed (read
condition, a bit will read as ‘1’. To program a bit, the as ‘0’) or left unprogrammed (read as ‘1’) to select var-
user needs to write to the memory address. The data is ious device configurations. Any write to a configuration
immaterial; the very act of writing will program the bit. location, regardless of the data, will program that con-
The configuration word locations are shown in figuration bit. Reading any configuration location
Table 5-3. The programmer should not program the between 0xFE00 and 0xFE07 will place the low byte of
reserved locations to avoid unpredictable results the configuration word (Table 5-2) into DAD<7:0>
and to be compatible with future variations of the (PORTC). DAD<15:8> (PORTD) will be set to 0xFF.
PIC17C7XX. It is also mandatory that configuration Reading a configuration location between 0xFE08 and
locations are programmed in the strict order start- 0xFE0F will place the high byte of the configuration
ing from the first location (0xFE00) and ending with word into DAD<7:0> (PORTC). DAD<15:8> (PORTD)
the last (0xFE0F). Unpredictable results may occur will be set to 0xFF.
if the sequence is violated.
TABLE 5-1: CONFIGURATION BIT
PROGRAMMING LOCATIONS
Bit Address
FOSC0 0xFE00
FOSC1 0xFE01
WDTPS0 0xFE02
WDTPS1 0xFE03
PM0 0xFE04
PM1 0xFE06
BODEN 0xFE0E
PM2 0xFE0F

TABLE 5-2: READ MAPPING OF CONFIGURATION BITS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 — PM1 — PM0 WDTPS1 WDTPS0 FOSC1 FOSC0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 PM2 BODEN PM2 PM2 PM2 PM2 PM2 PM2

—=Unused
PM<2:0>, Processor Mode Select bits
111 = Microprocessor mode
110 = Microcontroller mode
101 = Extended Microcontroller mode
000 = Code protected microcontroller mode
BODEN, Brown-out Detect Enable
1 = Brown-out Detect Circuitry enabled
0 = Brown-out Detect Circuitry disabled
WDTPS1:WDTPS0, WDT Prescaler Select bits.
11 = WDT enabled, postscaler = 1
10 = WDT enabled, postscaler = 256
01 = WDT enabled, postscaler = 64
00 = WDT disabled, 16-bit overflow timer
FOSC1:FOSC0, Oscillator Select bits
11 = EC oscillator
10 = XT oscillator
01 = RC oscillator
00 = LF oscillator

DS30274B-page 3-84  2000 Microchip Technology Inc.

PIC17C7XX
5.2 Embedding Configuration Word Information in the Hex File

To allow portability of code, a PIC17C7XX programmer is required to read the configuration word locations from the
hex file when loading the hex file. If the configuration word information was not present in the hex file, then a simple
warning message may be issued. Similarly, while saving a hex file, all configuration word information must be included.
An option to not include the configuration word information may be provided. When embedding configuration word
information in the hex file, it should be to address FE00h.
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.

5.3 Reading From and Writing To a Code

Protected Device
When a device is code-protected, writing to program
memory is disabled. If program memory is read, the
value returned is the XNOR8 result of the actual pro-
gram memory word. The XNOR8 result is the upper
eight bits of the program memory word XNOR’d with
the lower eight bits of the same word. This 8-bit result
is then duplicated into both the upper and lower 8-bits
of the read value. The configuration word can always
be read and written.

 2000 Microchip Technology Inc. DS30274B-page 3-85

PIC17C7XX
5.4 CHECKSUM COMPUTATION ulate the values that would be read from a protected
device. When calculating a checksum by reading a
The checksum is calculated by summing the following: device, the entire program memory can simply be read
• The contents of all program memory locations and summed. The configuration word and ID locations
• The configuration word, appropriately masked can always be read.
• Masked ID locations (when applicable) Note: Some older devices have an additional
The least significant 16 bits of this sum is the check- value added in the checksum. This is to
sum. maintain compatibility with older device
programmer checksums.
Table describes how to calculate the checksum for
each device. Note that the checksum calculation differs
depending on the code protect setting. Since the pro-
gram memory locations read out differently, depending
on the code protect setting, the table describes how to
manipulate the actual program memory values to sim-

TABLE 5-3: CHECKSUM COMPUTATION

0xC0DE at 0
Code Blank
Device Checksum* and max
Protect Value
address
PIC17C752 MP mode SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) 0xA05F 0x221D
MC mode SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) 0xA04F 0x220D
EMC mode SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) 0xA01F 0x21DD
PMC mode SUM_XNOR8[0x0000:0x1FFF] + (CONFIG & 0xC05F) 0x200F 0xE3D3
PIC17C756 MP mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x805F 0x021D
MC mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x804F 0x020D
EMC mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x801F 0x01DD
PMC mode SUM_XNOR8[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x000F 0xC3D3
PIC17C756A MP mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x805F 0x021D
MC mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x804F 0x020D
EMC mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x801F 0x01DD
PMC mode SUM_XNOR8[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x000F 0xC3D3
PIC17C762 MP mode SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) 0xA05F 0x221D
MC mode SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) 0xA04F 0x220D
EMC mode SUM[0x0000:0x1FFF] + (CONFIG & 0xC05F) 0xA01F 0x21DD
PMC mode SUM_XNOR8[0x0000:0x1FFF] + (CONFIG & 0xC05F) 0x200F 0xE3D3
PIC17C766 MP mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x805F 0x021D
MC mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x804F 0x020D
EMC mode SUM[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x801F 0x01DD
PMC mode SUM_XNOR8[0x0000:0x3FFF] + (CONFIG & 0xC05F) 0x000F 0xC3D3
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_XNOR8(a:b) = [Sum of 8-bit wide XNOR copied into upper and lower byte, of locations a to b inclusive]
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND

DS30274B-page 3-86  2000 Microchip Technology Inc.

PIC17C7XX
5.5 Device ID Register
Program memory location FDFFh is preprogrammed
during the fabrication process with information on the
device and revision information. These bits are
accessed by a TABLR0 instruction, and are access
when the TEST pin is high. As as a result, the device ID
bits can be read when the part is code protected.

TABLE 5-4: DEVICE ID REGISTER DECODE

Resultant Device

Device ID Value
Device
DEV REV
PIC17C766 0000 0001 001 X XXXX
PIC17C762 0000 0001 101 X XXXX
PIC17C756 0000 0000 001 X XXXX
PIC17C756A 0000 0010 001 X XXXX
PIC17C752 0000 0010 101 X XXXX

 2000 Microchip Technology Inc. DS30274B-page 3-87

PIC17C7XX
6.0 PARALLEL MODE AC/DC CHARACTERISTICS AND TIMING
REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +70°C, unless otherwise stated, (25°C is recommended)
Operating Voltage: 4.5V ≤ VDD ≤ 5.25V, unless otherwise stated.
Parameter
Sym. Characteristic Min. Typ. Max. Units Conditions/Comments
No.
PD1 VDDP Supply voltage during pro- 4.75 5.0 5.25 V
gramming
PD2 IDDP Supply current during pro- — — 50 mA Freq = 10MHz, VDD = 5.5V
gramming
PD3 VDDV Supply voltage during verify VDD — VDD V Note 2
min. max.
PD4 VPP Voltage on VPP/MCLR pin 12.75 — 13.25 V Note 1
during programming
PD6 IPP Programming current on — 25 50 mA
VPP/MCLR pin
P1 FOSCP Osc/clockin frequency dur- 4 — 10 MHz
ing programming
P2 TCY Instruction cycle 1 — 0.4 µs TCY = 4/FOSCP
P3 TIRV2TSH RA0, RA1, RA2, RA3, RA4 1 — — µs
setup before TEST↑
P4 TTSH2MCH TEST↑ to MCLR↑ 1 — — µs
P5 TBCV2IRH RC7:RC0, RB7:RB0 valid to 0 — — µs
RA1 or RA0↑:Address/Data
input setup time
P6 TIRH2BCL RA1 or RA0↑ to RB7:RB0, 10 TCY — — µs
RC7:RC0 invalid; Address
data hold time;
P7 T0CKIL2RBCZ RT↓ to RB7:RB0, RC7:RC0 — — 8TCY
hi-impedance
P8 T0CKIH2BCV RA1↑ to data out valid — — 10 TCY
P9 TPROG Programming pulse width 100 1000 µs
P10 TIRH2IRL RA0, RA1 high pulse width 10 TCY — — µs
P11 TIRL2IRH RA0, RA1 low pulse width 10 TCY — — µs
P12 T0CKIV2INL RA1↑ before INT↓ (to go 0 — — µs
from prog cycle to verify w/o
increment)
P13 TINL2RTL RA1 valid after RA0 (to 10 TCY — — µs
select increment or no
increment going from pro-
gram to verify cycle
P14 TVPPS VPP setup time before RA0↑ 100 — — µs Note 1
P15 TVPPH VPP hold time after INT↓ 0 — — µs Note 1
P16 TVDV2TSH VDD stable to TEST↑ 10 — — ms
P17 TRBV2MCH RB input (E1h) valid to VPP/ 0 — — µs
MCLR↑
P18 TMCH2RBI RB input (E1h) hold after 10TCY — — ns
VPP/MCLR↑
P19 TVPL2VDL VDD power down after VPP 10 — — ms
power down
Note 1: VPP/MCLR pin must only be equal to or greater than VDD at times other than programming.
2: Program must be verified at the minimum and maximum VDD limits for the part.

DS30274B-page 3-88  2000 Microchip Technology Inc.

FIGURE 6-1:

Test
13V

MCLR 5V
P14 P15
P4 P9
P5

 2000 Microchip Technology Inc.

P10 P11 INC
ADDR
RA1
P18
P9
RA0 P7

RB<7:0> E1H ADDR_HI DATA_HI OUT DATA_HI OUT DDATA_HI OUT DATA_HI OUT
Jump Address
Input

RC<7:0> ADDR_LO DATA_LO OUT DATA_LO OUT DATA_LO OUT DATA_LO OUT

P5
P6

Program location X + !
Verify location X
Programming Do not increment PC
Load Address X Increment Address to X + 1 Verify location X + 1 Verify location X + 1
Mode Entry by raising RA1 before
by pulsing RA1
RA0
PARALLEL MODE PROGRAMMING AND VERIFY TIMINGS I

Note: RA2 = 0
RA3 = 0
RA4 = 1
PIC17C7XX

DS30274B-page 3-89
Test
FIGURE 6-2:

13V

DS30274B-page 3-90
5V
P14
VPP/MCLR P15
PIC17C7XX

P9 P9 P9

RA1

RA0

RB<7:0> E1H ADDR_HI DATA_HI OUT DATA_HI_IN DATA_HI_IN DATA_HI_IN DATA_HI OUT
Jump Address
Input

RC<7:0> ADDR_LO DATA_LO OUT DATA_LO_IN DATA_LO_IN DATA_LO_IN DATA_LO OUT

Program location X
Move to verify cycle
Programming
Load address X Verify location X Program location X Prevent increment of Verify location X
mode entry
PC by raising RA1
before RA0
PARALLEL MODE PROGRAMMING AND VERIFY TIMINGS II

Note: RA2 = 0
RA3 = 0
RA4 = 1

 2000 Microchip Technology Inc.

FIGURE 6-3:

P13 P13

P12

 2000 Microchip Technology Inc.

RA1
INC PC INC PC INC PC

RA0

RB<7:0> DATA_HIOUT DATA_HI IN DATA_HI OUT DATA_HI IN DATA_HI OUT DATA_HI IN

RC<7:0> DATA_LO OUT DATA_LO IN DATA_LO OUT DATA_LO IN DATA_LO OUT DATA_LO IN

Program location X
Program location X Verify location X + 1
Do not increment
Verify location X Verify location X Raise RA1 after RA0 Pulse RA1 to increment Verify location X + 2
PC Raise RA1 before
to increment location X + 1 address to X + 2
RA0 to do this

Note: Device in PGM mode

Test = +6
PARALLEL MODE PROGRAMMING AND VERIFY TIMINGS III

VPP/MCLR = VPP
RA2 = 0
RA3 = 0
RA4 = 1
PIC17C7XX

DS30274B-page 3-91
PIC17C7XX
FIGURE 6-4: POWER-UP/DOWN SEQUENCE FOR PROGRAMMING

VDD P19

P16

VPP/MCLR

Test

RA4

RA2

RA3

RA0

RB<7:0> E1H
P17

P18

DS30274B-page 3-92  2000 Microchip Technology Inc.

PIC17C7XX
7.0 ELECTRICAL SPECIFICATIONS FOR SERIAL PROGRAMMING MODE
All parameters apply across the specified operating ranges Vcc = 2.5V to 5.5V
unless otherwise noted. Commercial (C): Tamb = 0° to +70°C
Industrial (I): Tamb = -40°C to +85°C
Parameter Sym Characteristic Min Typ† Max Units Conditions
No.
VIHH Programming Voltage on VPP/ 12.75 — 13.75 V
MCLR pin and TEST pin.
IPP Programming current on MCLR pin — 25 50 mA
FOSC Input OSC frequency on RA1 — — 8 MHz

TCY Instruction Cycle Time — 4/FOSC —

PS1 TVH2VH Setup time between TEST = VIHH 1 — — µs
and MCLR = VIHH
PS2 TSER Serial setup time 20 — — TCY
PS3 TSCLK Serial Clock period 1 — — TCY
PS4 TSET1 Input Data Setup Time to serial 15 — — ns
clock ↓
PS5 THLD1 Input Data Hold Time from serial 15 — — ns
clock ↓
PS6 TDLY1 Delay between last clock ↓ to first 20 — — TCY
clock ↑ of next command
PS7 TDLY2 Delay between last clock ↓ of com- 20 — — TCY
mand byte to first clock ↑ of read of
data word
PS8 TDLY3 Delay between last clock ↓ of com- 30 — — TCY
mand byte to first clock ↑ of write of
data word
PS9 TDLY4 Data input not driven to next clock 1 — — TCY
input
PS10 TDLY5 Delay between last begin program- 100 — — µs
ming clock ↓ to last clock ↓ of next
command (minimum programming
time)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

 2000 Microchip Technology Inc. DS30274B-page 3-93

PIC17C7XX
FIGURE 7-1: RESET ADDRESS POINTER COMMAND (PROGRAM/VERIFY)

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)
PS1 1 2 3 4 5 6 7 8 1 2

RA5 (Clock)
PS6
PS4PS5

RA4 (Data) 0 0 0 0 0 0 0 0

RA4 = Input

Reset
Program/Verify Test Mode

FIGURE 7-2: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2

RA5 (Clock)
PS6
PS4PS5
RA4 (Data) 0 1 1 0 0 0 0 0

RA4 = Input

Reset
Program/Verify Test Mode

DS30274B-page 3-94  2000 Microchip Technology Inc.

PIC17C7XX
FIGURE 7-3: LOAD ADDRESS COMMAND

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2 3 15 16 1

RA5 (Clock)
PS7 PS6
PS4PS5

RA4 (Data) 0 1 0 1 0 0 0 0

RA4 = Input

Reset
Program/Verify Test Mode

FIGURE 7-4: READ ADDRESS COMMAND

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2 3 15 16 1

RA5 (Clock)
PS8 PS6
PS4PS5

PS9
RA4 (Data) 0 0 1 1 0 0 0 0

RA4 = Input RA4 = Output

Reset
Program/Verify Test Mode

 2000 Microchip Technology Inc. DS30274B-page 3-95

PIC17C7XX
FIGURE 7-5: LOAD DATA COMMAND

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2 3 15 16 1

RA5 (Clock)
PS7 PS6
PS4PS5

RA4 (Data) 0 1 0 0 0 0 0 0

RA4 = Input

Reset
Program/Verify Test Mode

FIGURE 7-6: READ DATA COMMAND

RA1T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2 3 15 16 1

RA5 (Clock)
PS8 PS6
PS4PS5

PS9
RA4 (Data) 0 0 1 0 0 0 0 0

RA4 = Input RA4 = Output

Reset
Program/Verify Test Mode

FIGURE 7-7: BEGIN PROGRAMMING COMMAND (PROGRAM)

RA1/T0CKI
VIHH
Test PS2

VIHH
MCLR/VPP PS3 (NEXT COMMAND)

PS1 1 2 3 4 5 6 7 8 1 2 7 8

RA5 (Clock)
PS10
PS4PS

RA4 (Data) 0 0 0 1 0 0 0 0

RA4 = Input

Reset
Program/Verify Test Mode

DS30274B-page 3-96  2000 Microchip Technology Inc.

PIC18CXXX
In-Circuit Serial Programming for PIC18CXXX OTP MCUs
This document includes the programming Pin Diagram
specifications for the following devices: PDIP, Windowed CERDIP
• PIC18C452 • PIC18C242
MCLR/VPP 1 40 RB7
• PIC18C252 • PIC18C442 RA0 2 39 RB6
RA1 3 38 RB5
RA2 4 37 RB4
RA3 5 36 RB3
1.0 PROGRAMMING THE RA4/T0CKI 6 35 RB2
RA5 7 34 RB1
PIC18CXXX

PIC18C4XX
RE0 8 33 RB0/INT
RE1 9 32 VDD
RE2 10 31 VSS
The PIC18CXXX can be programmed using a serial VDD 11 30 RD7
VSS 12 29 RD6
method. while in the users system. This allows for OSC1/CLKIN 13 28 RD5
increased design flexibility. This programming specifi- OSC2/CLKOUT 14 27 RD4
RC0 15 26 RC7
cation applies to PIC18CXXX devices in all package RC1 16 25 RC6
RC2 17 24 RC5
types. RC3 18 23 RC4
RD0 19 22 RD3
RD1 20 21 RD2
1.1 Hardware Requirements
The PIC18CXXX requires two programmable power PDIP, SOIC, Windowed CERDIP (300 mil)
supplies, one for VDD (2.0V to 5.5V recommended) and MCLR/VPP •1 28 RB7
one for VPP (12V to 14V). Both supplies should have a RA0 2 27 RB6
RA1 3 26 RB5
minimum resolution of 0.25V. 25 RB4
RA2 4
RA3 5 24 RB3

PIC18C2XX
1.2 Programming Mode RA4/T0CKI 6 23 RB2
RA5 7 22 RB1

The programming mode for the PIC18CXXX allows VSS 8 21 RB0/INT

OSC1/CLKIN 9 20 VDD
programming of user program memory, special loca- OSC2/CLKOUT 10 19 VSS
tions used for ID, and the configuration word for the RC0 11 18 RC7
RC1 12 17 RC6
PIC18CXXX. 16 RC5
RC2 13
RC3 14 15 RC4

TABLE 1-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC18C242/252/442/452

During Programming
Pin Name
Pin Name Pin Type Pin Description
MCLR/VPP VPP P Programming Power
VDD VDD P Power Supply
Vss VSS P Ground
RB6 RB6 I Serial Clock
RB7 RB7 I/O Serial Data
Legend: I = Input, O = Output, P = Power

 2000 Microchip Technology Inc. DS39028A-page 3-97

PIC18CXXX
2.0 IN-CIRCUIT SERIAL 2.2 ICSP OPERATION
PROGRAMMING MODE (ICSP) In ICSP mode, instruction execution takes place
through a serial interface using RB6 and RB7. RB7 is
2.1 Introduction
used to shift in instructions and shift out data from the
Serial programming mode is entered by asserting TABLAT register. RB6 is used as the serial shift clock
MCLR/VPP = VIHH and RB6, RB7 = 0. and the CPU execution clock. Instructions and data
are shifted in LSb first.
Instructions are fed into the CPU serially on RB7, and
are shifted in on the rising edge of the serial clock pre- In this mode all instructions are shifted serially, then
sented on RB6. Programming and verification are per- loaded into the instruction register, and executed. No
formed by executing TBLRD and TBLWT instructions. program fetching occurs from internal or external pro-
The address pointer to the program memory is simply gram memory. 8-bit data bytes are read from the
the table pointer. The address pointer can be incre- TABLAT register via the same serial interface.
mented and decremented by executing table reads and
2.2.1 4-BIT SERIAL INSTRUCTIONS
writes with auto-decrement and auto-increment.
A set of 4-bit instructions are provided for ICSP mode,
so that the most common instructions used for ICSP
can be fetched quickly, and thus reduce the amount of
time required to program a device. The 4-bit opcode is
shifted in while the previous instruction fetched exe-
cutes. The 4-bit instruction contains the lower 4-bits of
an instruction opcode. The upper 12-bits default as all
0’s. Instructions with all 0’s in the upper byte of the
instruction word, are by default considered special
instructions. The serial instructions are decoded as
shown in Table 2-1:

TABLE 2-1: SPECIAL INSTRUCTIONS FOR SERIAL INSTRUCTION EXECUTION AND ICSP
Mnemonic, Status
Description Cycles 4-Bit Opcode
Operands Affected
NOP No Operation (Shift in16-bit instruction) 1 0000 None
TBLRD * Table Read (no change to TBLPTR) 2 1000 None
TBLRD *+ Table Read (post-increment TBLPTR) 2 1001 None
TBLRD *- Table Read (post-decrement TBLPTR) 2 1010 None
TBLRD +* Table Read (pre-increment TBLPTR) 2 1011 None
TBLWT * Table Write (no change to TBLPTR) 2 1100 None
TBLWT *+ Table Write (post-increment TBLPTR) 2 1101 None
TBLWT *- Table Write (post-decrement TBLPTR) 2 1110 None
TBLWT +* Table Write (pre-increment TBLPTR) 2 1111 None
Legend: Refer to the PIC18CXXX Data Sheet (DS39026) for opcode field descriptions.
Note: All special instructions not included in this table are decoded as NOP’s

In-Circuit Serial Programming™ (ICSP) is a trademark of Microchip Technology Inc.

DS39028A-page 3-98  2000 Microchip Technology Inc.

PIC18CXXX
2.2.2 INITIAL SERIAL INSTRUCTION Following the FNOP instruction execution and the next
OPERATION shifting in of the next instruction, the serial state
machine will do one of three things depending upon
Upon ICSP mode entry, the CPU is idle. The execution the 4-bit instruction that was fetched:
of the CPU is governed by a state machine. The CPU
clock source comes from RB6 which also acts as the 1. If the instruction fetched was a NOP, the state
serial shift clock. The first clock transition on RB6 is machine will suspend the CPU awaiting a 16-bit
absorbed after RESET. While the first instruction is wide instruction to be shifted in.
being clocked in, a forced NOP is executed. 2. If the instruction is a TBLWT, the state machine
suspends the CPU from execution while sixteen
bits of data are shifted in as data for the TBLWT
instruction.
3. If the instruction is a TBLRD, then execution of
the TBLRD instruction begins immediately for
eight clock cycles, followed by eight clock cycles
where the contents of the TABLAT register is
shifted out onto RB7.
Once sixteen clock cycles have elapsed, the next 4-bit
instruction is fetched while the current instruction is
executed. Each instruction type is described in later
sections.

FIGURE 2-1: SERIAL INSTRUCTION TIMING AFTER RESET

Q Cycles Q1 Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4
P1

VIHH

P2
MCLR/VPP
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
RB6 (Clock) P9
P5 P5
P3P4

RB7 (Data) 1 1 0 1 1 1 0 1

Execute FNOP 16-bit Instruction Load or Execute Instruction,

Fetch 4-bit Instruction 16-bit data Fetch or Fetch Next 4-bit
(TBLWT **) Perform TABLRD followed by shift data out Instruction

Reset
RB7 = Input or Output depending upon instruction

ICSP Mode

 2000 Microchip Technology Inc. DS39028A-page 3-99

PIC18CXXX
2.2.3 NOP SERIAL INSTRUCTION EXECUTION 2.2.4 ONE CYCLE 16-BIT INSTRUCTIONS

The NOP serial instruction is used to allow execution of If the instruction fetched is a one cycle instruction,
all other instructions not included in Table 2-1. When then the instruction operation will be completed in the
the NOP instruction is fetched, the serial execution 4 clock cycles following the instruction fetched. During
state machine suspends the CPU for 16 clock cycles. instruction execution, the next 4-bit serial instruction is
During these 16 clock cycles, all 16-bits of an instruc- fetched (See Figure 2-2).
tion are fed into the CPU and the NOP instruction is
discarded. Once all 16 bits have been shifted in the
state machine will allow the instruction to be executed
for the next 4 clock cycles.
Note: 16-bit TBLWT and TBLRD instructions are
not permitted. They will cause timing prob-
lems with the serial state machine. If the
user wishes to perform a TBLWT or TBLRD
instruction, it must be performed as a 4-bit
instruction.

FIGURE 2-2: SERIAL INSTRUCTION TIMING FOR 1 CYCLE 16-BIT INSTRUCTIONS

Q Cycles Q1 Q2 Q3 Q4 Q4 Q1 Q2 Q3 Q4

MCLR/VPP = VIHH
P2

1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
RB6 (Clock)
P5 P5
P3P4

RB7 (Data) 0 0 0 0 1 1 0 1

Execute PC-2, 16-bit Instruction Fetch Execute 16-bit Instruction,

Fetch NOP to enable Fetch Next Serial
16-bit Instruction fetch 4-bit Instruction
RB7 = Input

ICSP Mode

DS39028A-page 3-100  2000 Microchip Technology Inc.

PIC18CXXX
FIGURE 2-3: 16-BIT 1 CYCLE SERIAL INSTRUCTION FLOW AFTER RESET

Start

Execute 16-bit Instruction,

and shift in next
MCLR = VSS,
RB6, RB7 = 0 4-bit instruction,
Num_Clk = 1,

MCLR = VIHH

Clock No
Transition
Shift in 1st RB6?
4-bit instruction, Yes
Num_Clk = 1,

Shift(R) RB7
Num_Clk = Num_Clk + 1

Clock No
Transition
RB6? End
Yes

Shift(R) RB7
Num_Clk = Num_Clk + 1

4-bit instruction = NOP,

Shift in 16-bit instruction,
Num_Clk = 1

Clock No
Transition
RB6?
Yes

Shift(R) RB7
Num_Clk = Num_Clk + 1

No
Num_Clk = 16?

Yes

 2000 Microchip Technology Inc. DS39028A-page 3-101

PIC18CXXX
FIGURE 2-4: 16-BIT 1 CYCLE SERIAL INSTRUCTION FLOW

Start

execute (PC - 2),

and shift in next
4-bit instruction, execute 16-bit Instruction,
Num_Clk = 1, and shift in next
4-bit instruction,
Num_Clk = 1,

Clock No
Transition
RB6? Clock No
Yes Transition
RB6?
Yes
Shift(R) RB7
Num_Clk = Num_Clk + 1
Shift(R) RB7
Num_Clk = Num_Clk + 1
4-bit instruction = NOP,
Shift in 16-bit instruction,
Num_Clk = 1
End

Clock No
Transition
RB6?
Yes

Shift(R) RB7
into ROMLAT<15>,
Num_Clk = Num_Clk + 1

No
Num_Clk = 16?

Yes

DS39028A-page 3-102  2000 Microchip Technology Inc.

PIC18CXXX
2.3 Serial Instruction Execution For Two
Cycle, One Word Instructions
When a NOP instruction is fetched, the serial execution
state machine suspends the CPU for 16 clock cycles.
During these 16 clock cycles, all 16-bits of an instruc-
tion are fed in and the NOP instruction is discarded.
If the instruction fetched is a two cycle, one word
instruction, then the instruction operation will require a
second “dummy fetch” to be performed before the
instruction execution can be completed. The first cycle
of the instruction will be executed in the 4 clock cycles
following the instruction fetched. During the first cycle
of instruction execution, the next 4-bit serial instruction
is fetched. In order to perform the second half of the
two cycle instruction, this 4-bit instruction loaded in
must be a NOP, so that state machine will remain idle
for the second half of the instruction. Following the
fetch of the second NOP, the state machine will shift
16-bits of data that will be discarded. After the 16-bits
of data is shifted in, the state machine will release the
CPU, and allow it to perform the second half of the two
cycle instruction. During the second half of the two
cycle instruction execution, the next 4-bit instruction is
loaded (See Figure 2-5).

FIGURE 2-5: 2 CYCLE 1 WORD 16-BIT INSTRUCTION SEQUENCE

Q Cycles Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

MCLR/VPP P2

1 2 3 4 1 2 15 16 1 2 3 4 1 2 15 16 1 2 3 4

RB6 (Clock)
P5 P5 P5 P5
P3P4

RB7 (Data) 0 0 0 0 1 1 0 1

Execute PC-2 Fetch 16-bit Instruction Fetch 4-bit NOP, Fetch 2nd 16-bit Execute 2nd Cycle,
Fetch 4-bit NOP Execute 1st Cycle Operand Word (discarded) Fetch Next 4-bit Instruction
of 16-bit Instruction
RB7 = Input

ICSP Mode

 2000 Microchip Technology Inc. DS39028A-page 3-103

PIC18CXXX
2.4 Serial Instruction Execution For Two
Word, Two Cycle Instructions
After a NOP instruction is fetched, the serial execution
state machine suspends the CPU in the Q4 state for
16 clock cycles. During these 16 clock cycles, all 16-
bits of an instruction are fed in and the NOP instruction
is discarded.
If the 16-bit instruction fetched is a two cycle, two word
instruction, then the instruction operation will require a
second operand fetch to be performed before the
instruction execution can be completed. The first cycle
of the instruction will be executed in the 4 clock cycles
following the 16-bit instruction fetch. During the first
cycle of instruction execution, the next 4-bit serial
instruction is fetched. In order to perform the second
half of the two cycle instruction, this 4-bit instruction
loaded in must also be a NOP, so that the state
machine will remain idle for the second half of the
instruction. Following the fetch of the second NOP, the
state machine will shift 16-bits of data that will be used
as an operand for the two cycle instruction. After the
16-bits of data are shifted in, the state machine will
release the CPU, and allow it to execute the second
half of the two cycle instruction. During the second half
of the two cycle instruction execution, the next 4-bit
instruction is loaded (see Figure 2-6).

FIGURE 2-6: 16-BIT 2 CYCLE 2 WORD INSTRUCTION SEQUENCE

Q Cycles Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

MCLR/VPP = VIHH
P2

1 2 3 4 1 2 3 15 16 1 2 3 4 1 2 15 16 1 2 3 4

RB6 (Clock)
P5 P5 P5 P5
P3P4

RB7 (Data) 0 0 0 0 0 0 0 0 1 1 0 1

Execute PC-2, Fetch 1st word Execute 1st Cycle, Fetch 2nd word Execute 2nd Cycle,
Fetch 4-bit NOP Fetch 4-bit NOP Fetch next 4-bit
Instruction
RB7 = Input

ICSP Mode

DS39028A-page 3-104  2000 Microchip Technology Inc.

PIC18CXXX
FIGURE 2-7: 16-BIT 2 CYCLE 2 WORD SERIAL INSTRUCTION FLOW AFTER RESET

Start

MCLR = VPP,
RB6, RB7 = 0 Clock No
Transition
RB6?
MCLR = VIHH
Yes

Shift(R) RB7,
execute FNOP and shift in
1st 4-bit instruction, Num_Clk = Num_Clk + 1
Num_Clk = 1,

4-bit instruction = NOP,

Shift in 2nd 16-bit operand,
Clock Num_Clk = 1
No
Transition
RB6?
Yes
Clock No
Transition
Shift(R) RB7, RB6?
Num_Clk = Num_Clk + 1 Yes

Shift(R) RB7,
4-bit instruction = NOP, Num_Clk = Num_Clk + 1
Shift in 16-bit instruction,
Num_Clk = 1

No
Num_Clk = 16?
Clock No
Transition Yes
RB6?
Yes execute 2nd cycle of 16-bit
instruction, and shift in
Shift(R) RB7, next 4-bit instruction
Num_Clk = 1
Num_Clk = Num_Clk + 1

No Clock No
Num_Clk = 16? Transition
RB6?
Yes Yes

Shift(R) RB7,
Enable CPU,
Num_Clk = Num_Clk + 1
execute 1st cycle of 16-bit
instruction, and shift in next
4-bit instruction,
Num_Clk = 1, End

 2000 Microchip Technology Inc. DS39028A-page 3-105

PIC18CXXX
FIGURE 2-8: 16-BIT 2 CYCLE 2 WORD SERIAL INSTRUCTION FLOW

Clock No
Transition
RB6?
Start Yes

execute (PC-2)and shift in Shift(R) RB7,

4-bit instruction, Num_Clk = Num_Clk + 1
Num_Clk = 1,

4-bit instruction = NOP,

Shift in 2nd 16-bit operand,
Clock No Num_Clk = 1
Transition
RB6?
Yes
Clock No
Transition
Shift(R) RB7, RB6?
Num_Clk = Num_Clk + 1
Yes

Shift(R) RB7,
4-bit instruction = NOP, Num_Clk = Num_Clk + 1
Shift in 16-bit instruction,
Num_Clk = 1

No
Num_Clk = 16?

Clock No
Transition Yes
RB6?
Yes execute 2nd cycle of 16-bit
instruction, and shift in
next 4-bit instruction
Shift(R) RB7, Num_Clk = 1
Num_Clk = Num_Clk + 1

No Clock No
Num_Clk = 16? Transition
RB6?
Yes Yes

Shift(R) RB7,
execute 1st cycle of 16-bit Num_Clk = Num_Clk + 1
instruction, and shift in next
4-bit instruction,
Num_Clk = 1, End

DS39028A-page 3-106  2000 Microchip Technology Inc.

PIC18CXXX
2.5 TBLWT Instruction The TBLWT instruction is used in ICSP mode to pro-
gram the EPROM array. When writing a 16-bit value
The TBLWT instruction is a unique two cycle instruc- to the EPROM, ID locations, or configuration locations,
tion. the device, RB6, must be held high for the appropriate
All forms of TBLWT instructions (post/pre-increment, programming time during the TBLWT instruction as
post decrement, etc.) are encoded as 4-bit special specified by parameter P9.
instructions. This is useful as TBLWT instructions are When RB6 is asserted low the device will cease pro-
used repeatedly in ICSP mode. A 4-bit instruction will gramming the specified location.
minimize the total number of clock cycles required to
After RB6 is asserted low, RB6 is held low for the time
perform programming algorithms.
specified by parameter P10, to allow high voltage dis-
The TBLWT instruction sequence operates as follows: charge of the program memory array.
1. The 4-bit TBLWT instruction is read in by the
state machine on RB7 during the 4 clock cycle
execution of the instruction fetched previous to
the TBLWT (which is an FNOP if the TBLWT is
executed following a reset).
2. Once the state machine recognizes that the
instruction fetched is a TBLWT, the state
machine proceeds to fetch in the 16-bits of data
that will be written into the program memory
location pointed to by the TBLPTR.
3. The serial state machine releases the CPU to
execute the first cycle of the TBLWT instruction
while the first 4 bits of the 16-bit data word are
shifted in. After the first cycle of TBLWT instruc-
tion has completed the state machine shifts in
the remaining 12 of the sixteen bits of data. The
data word will not be used until the second cycle
of the instruction.
4. After all 16-bits of data are shifted in and the first
cycle of the TBLWT is performed, the CPU is
allowed to execute the second cycle of the
TBLWT operation, programming the current
memory location with the 16-bit value. The next
instruction following the TBLWT instruction is
shifted in during the execution of the second
cycle (See Figure 2-9).

FIGURE 2-9: TBLWT INSTRUCTION SEQUENCE

Q Cycles Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

MCLR/VPP = VIHH P2
P10
1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4
RB6 (Clock) P9
P5 P5
P3P4

RB7 (Data) 1 1 0 0 0 0 0 0 1 1 0 1

Execute 1st
Execute PC-2 Cycle TBLWT Execute 2nd Cycle TBLWT
Fetch TBLWT and fetch next 4-bit
instruction

Load TBLWT Data

RB7 = Input

ICSP Mode

 2000 Microchip Technology Inc. DS39028A-page 3-107

PIC18CXXX
FIGURE 2-10: TBLWT SERIAL INSTRUCTION FLOW AFTER RESET

Start
Clock No
Transition
MCLR = VSS, RB6?
RB6, RB7 = 0
Yes

MCLR = VIHH Shift(R) RB7

Num_Clk = Num_Clk + 1

Execute FNOP,
and shift in 4-bit No
TBLWT instruction, Num_Clk = 12?
Num_Clk = 1,
Yes

Execute 2nd cycle of TBLWT

Clock No instruction and shift in next
Transition 4-bit instruction,
RB6? Num_Clk = 1,
Yes

Shift(R) RB7
Num_Clk = Num_Clk + 1 Clock No
Transition
RB6?
Yes
4-bit instruction = TBLWT,
Execute 1st cycle of TBLWT,
Begin Shifting in TBLWT data, Shift(R) RB7
Num_Clk = 1 Num_Clk = Num_Clk + 1

End
Clock No
Transition
RB6?
Yes

Shift(R) RB7
Num_Clk = Num_Clk + 1

No
Num_Clk = 4?

Yes

shift in last 12 bits

of TBLWT data,
Num_Clk = 1,

DS39028A-page 3-108  2000 Microchip Technology Inc.

PIC18CXXX
FIGURE 2-11: TBLWT SERIAL INSTRUCTION FLOW

Clock No
Transition
RB6?
Yes

Shift(R) RB7
Start
Num_Clk = Num_Clk + 1

Execute (PC-2),
and shift in 4-bit No
TBLWT instruction, Num_Clk = 12?
Num_Clk = 1,
Yes

Execute 2nd cycle of TBLWT

Clock No instruction and shift in next
Transition 4-bit instruction,
RB6? Num_Clk = 1,
Yes

Shift(R) RB7
Num_Clk = Num_Clk + 1 Clock No
Transition
RB6?
4-bit instruction = TBLWT, Yes
Execute 1st cycle of TBLWT,
Begin Shifting in TBLWT data, Shift(R) RB7
Num_Clk = 1 Num_Clk = Num_Clk + 1

Clock End
No
Transition
RB6?
Yes

Shift(R) RB7
Num_Clk = Num_Clk + 1

No
Num_Clk = 4?

Yes

Shift in last 12 bits

of TBLWT data,
Num_Clk = 1,

 2000 Microchip Technology Inc. DS39028A-page 3-109

PIC18CXXX
2.6 TBLRD Instruction The TBLRD instruction sequence operates as follows:
1. The 4-bit TBLRD instruction is read in by the
The TBLRD instruction is another unique two cycle
state machine on RB7 during the 4 clock cycle
instruction.
execution of the instruction fetched previous to
All forms of TBLRD instructions (post/pre-increment, the TBLRD (which is an FNOP if the TBLRD is
post decrement, etc.) are encoded as 4-bit special executed following a reset).
instructions. This is useful as TBLRD instructions are 2. Once the state machine recognizes that the
used repeatedly in ICSP mode. A 4-bit instruction will instruction fetched is a TBLRD, the state
minimize the total number of clock cycles required to machine releases the CPU and allows execu-
perform programming algorithms. tion of the first and second cycles of the TBLRD
instruction for eight clock cycles. When the
TBLRD is performed, the contents of the pro-
gram memory byte pointed to by the TBLPTR is
loaded into the TABLAT register.
3. After eight clock cycles have transitioned on
RB6, and the TBLRD instruction has completed,
the state machine will suspend the CPU for eight
clock cycles. During these eight clock cycles,
the state machine configures RB7 as an output,
and will shift out the contents of the TABLAT reg-
ister onto RB7 LSb first.
4. When the state machine has shifted out all eight
bits of data, the state machine suspends the
CPU to allow an instruction pre-fetch. Four (4)
clock cycles are required on RB6 to shift in the
next 4-bit instruction.

FIGURE 2-12: TBLRD INSTRUCTION SEQUENCE

Q Cycles Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

MCLR/VPP = VIHH

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 5 6 7 8 1 2 3 4
RB6 (Clock)
P5 P6 P5

RB7 (Data) 1 0 0 1 LSb 1 2 3 4 5 6 MSb 1 0 0 1

Execute PC-2 Execute Cycle 1 Execute Cycle 2 Shift Data Out From TABLAT No Execution takes place,
Fetch TBLRD TBLRD TBLRD Fetch Next 4-bit instruction
RB7 = Input RB7 = Output RB7 = Input
ICSP Mode

DS39028A-page 3-110  2000 Microchip Technology Inc.

PIC18CXXX
FIGURE 2-13: TBLRD SERIAL INSTRUCTION FLOW AFTER RESET

Start

Clock No
MCLR = VSS, Transition
RB6, RB7 = 0
RB6?
Yes
MCLR = VIHH
Shift(R) TABLAT<0>
out onto RB7
Num_Clk = Num_Clk + 1
Execute FNOP,
and shift in 4-bit
TBLRD instruction,
Num_Clk = 1, No
Num_Clk = 8?

Yes

Clock No Shift in next

Transition
4-bit instruction
RB6?
Yes

Shift(R) RB7
Num_Clk = Num_Clk + 1
Clock No
Transition
RB6?
Enable CPU, Yes
execute 1st and 2nd
cycle TBLRD instruction
Shift(R) RB7
Num_Clk = Num_Clk + 1

Clock No
Transition No
RB6? Num_Clk = 4?
Yes
Yes
TBLRD instruction execution
takes place here
Num_Clk = Num_Clk + 1 End

No
Num_Clk = 8?

Yes

Shift out 8-bits

of data to RB7

 2000 Microchip Technology Inc. DS39028A-page 3-111

PIC18CXXX
FIGURE 2-14: TBLRD SERIAL INSTRUCTION FLOW

Start

Clock No
Execute (PC-2), Transition
and shift in 4-bit RB6?
TBLRD instruction, Yes
Num_Clk = 1,
Shift(R) TABLAT<0>
out onto RB7
Num_Clk = Num_Clk + 1

Clock No
Transition
RB6? No
Num_Clk = 8?
Yes
Yes
Shift(R) RB7
Num_Clk = Num_Clk + 1 Shift in next
4-bit instruction

Execute 1st and 2nd

cycle TBLRD instruction

Clock No
Transition
RB6?
Clock No
Transition Yes
RB6?
Yes Shift(R) RB7
Num_Clk = Num_Clk + 1
TBLRD instruction execution
takes place here
Num_Clk = Num_Clk + 1
No
Num_Clk = 4?

No Yes
Num_Clk = 8?

Yes End

Shift out 8-bits

of data to RB7

DS39028A-page 3-112  2000 Microchip Technology Inc.

PIC18CXXX
2.6.1 SOFTWARE COMMANDS

ICSP commands of the PICmicro® MCU are supported

in the PIC18CXXX family by simply combining CPU
instructions. Once in In-Circuit Serial Programming
(ICSP) mode, the instructions are loaded into a shift
register, and the device waits for a command to be
received. The ICSP commands for the PIC16CXXX
family are now “pseudo-commands” and are shown in
Table 2-2. The following sections are a description of
how the pseudo-commands can be implemented using
CPU instructions.

TABLE 2-2: ICSP PSEUDO COMMAND MAPPING

ICSP Command Golden Gate Instructions
Load Configuration MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF
#Address1 TBLPTRL #Address2 TBLPTRH #Address3 TBLPTRU
Load Data Not needed. Data encoded in 4-bit TBLWT instruction sequence.
Read Data TBLRD instruction
Increment Address Not needed. Use TBLWT with increment/decrement (TBLWT *+/*-).
Load Address MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF
#Addr_low TBLPTRL #Addr_high TBLPTRH #Addr_upper TBLPTRU
Reset Address MOVLW MOVWF MOVWF MOVWF
#Data TBLPTRH TBLPTRL TBLPTRU
Begin programming TBLWT
End Programming Not needed. Programming will cease at the end of TBLWT execution.

 2000 Microchip Technology Inc. DS39028A-page 3-113

PIC18CXXX
2.6.2 RESET ADDRESS

A reset of the program memory pointer is a write to the

upper, high, and low bytes of the TBLPTR. To reset the
program memory pointer, the following instruction
sequence is used.
NOP ;(4-BIT INSTRUCTION)
MOVLW 00h
NOP ;(4-BIT INSTRUCTION)
MOVWF TBLPTRU, 0
NOP ;(4-BIT INSTRUCTION)
MOVWF TBLPTRH, 0
NOP ;(4-BIT INSTRUCTION)
MOVWF TBLPTRL, 0

DS39028A-page 3-114  2000 Microchip Technology Inc.

PIC18CXXX
FIGURE 2-15: RESET ADDRESS SERIAL INSTRUCTION SEQUENCE

Start

execute (PC - 2), 4-bit instruction = NOP,

shift in next 4-bit instruction, (NOP) Shift in 16-bit MOVWF instruction,
Num_Clk = 1, Num_Clk = 1

On rising edge RB6 On rising edge RB6

Shift(R) RB7 Shift(R) RB7
into Shift Reg<3>, into Shift Reg<15>,
Num_Clk = Num_Clk + 1 Num_Clk = Num_Clk + 1 MOVWF
(NOP) TBLPTRM,0

No No
Num_Clk = 4? Num_Clk = 16?

Yes Yes

4-bit instruction = NOP,

Shift in 16-bit MOVLW instruction, (NOP) execute MOVWF Instruction,
Num-Clk = 1 shift in 4-bit NOP instruction,
Num_Clk = 1,

On rising edge RB6

Shift(R) RB7 On rising edge RB6
into Shift Reg<15>, Shift(R) RB7
Num_Clk = Num_Clk + 1 into Shift Reg<3>,
Num_Clk = Num_Clk + 1
MOVLW 00h (NOP)
No
Num_Clk = 16? No
Num_Clk = 4?

Yes
Yes

4-bit instruction = NOP,

Execute MOVLW Instruction, Shift in 16-bit MOVWF instruction,
shift in 4-bit NOP instruction, (NOP) Num_Clk = 1
Num_Clk = 1,

On rising edge RB6

On rising edge RB6
Shift(R) RB7
Shift(R) RB7
into Shift Reg<15>,
into Shift Reg<3>,
Num_Clk = Num_Clk + 1
Num_Clk = Num_Clk + 1 MOVWF
(NOP) TBLPTRM,0
No
No Num_Clk = 16?
Num_Clk = 4?
Yes
Yes

Execute MOVWF Instruction,

shift in next 4-bit instruction,
Num_Clk = 1,

End

 2000 Microchip Technology Inc. DS39028A-page 3-115

PIC18CXXX
2.6.3 LOAD ADDRESS

This is used to load the address pointer to the Program

Memory with a specific 22-bit value. This is useful when
a specific range of locations are to be accessed. To
load the address into the table pointer, the following
commands must be used:

NOP ; 4-bit instruction

MOVLW Low_Address
NOP ; 4-bit instruction
MOVWF TBLPTRL, 0
NOP ; 4-bit instruction
MOVLW High_Address
NOP ; 4-bit instruction
MOVWF TBLPTRH, 0
NOP ; 4-bit instruction
MOVLW Upper_Address
NOP ; 4-bit instruction
MOVWF TBLPTRU, 0

DS39028A-page 3-116  2000 Microchip Technology Inc.

PIC18CXXX
FIGURE 2-16: LOAD ADDRESS SERIAL INSTRUCTION SEQUENCE

Start

execute (PC - 2), 4-bit instruction = NOP,

shift in next 4-bit instruction, Shift in 16-bit MOVWF instruction,
Num_Clk = 1, Num_Clk = 1

On rising edge RB6 On rising edge RB6

Shift(R) RB7 Shift(R) RB7
into Shift Reg<3>, into Shift Reg<15>,
Num_Clk = Num_Clk + 1 Num_Clk = Num_Clk + 1 MOVWF
(NOP) TBLPTRL,0

No No
Num_Clk = 4? Num_Clk = 16?

Yes Yes

4-bit instruction = NOP,

Shift in 16-bit MOVLW instruction, execute MOVWF Instruction,
Num_Clk = 1 shift in 4-bit NOP instruction,
Num_Clk = 1,

On rising edge RB6

Shift(R) RB7 On rising edge RB6
into Shift Reg<15>, Shift(R) RB7
Num_Clk = Num_Clk + 1 into Shift Reg<3>,
MOVLW Num_Clk = Num_Clk + 1
LOW_Address (NOP)
No
Num_Clk = 16? No
Num_Clk = 4?
Yes
Yes

execute MOVLW Instruction, 4-bit instruction = NOP,

shift in 4-bit NOP instruction, Shift in 16-bit MOVWF instruction,
Num_Clk = 1, Num_Clk = 1

On rising edge RB6 On rising edge RB6

Shift(R) RB7 Shift(R) RB7
into Shift Reg<3>, into Shift Reg<15>,
Num_Clk = Num_Clk + 1 Num_Clk = Num_Clk + 1
MOVLW
(NOP) HIGH_Address
No
No Num_Clk = 16?
Num_Clk = 4?
Yes
Yes

execute MOVWF Instruction,

shift in next 4-bit instruction,
Num_Clk = 1,

End

 2000 Microchip Technology Inc. DS39028A-page 3-117

PIC18CXXX
2.6.4 ICSP BEGIN PROGRAMMING The sequence for programming a location could occur
as follows:
Programming is performed by executing a TBLWT
instruction. In ICSP mode the TBLWT instruction 1. Setup the TLBPTR with the first ok address to
sequence will include 16-bits of data that are shifted be programmed (even or odd byte).
into a data buffer, and then written to the word location 2. Shift in a 4 bit TBLWT instruction.
that is addressed by the TBLPTR. Although the 3. 16-bits of data are then shifted in for program-
TBLPTR addresses the program memory on a byte ming both high and low byte of the first pro-
wide boundary, all 16-bits of data that are shifted in dur- grammed location.
ing the TBLWT sequence are written at once. The 4. Execute TBLWT instruction to program location.
16-bits are shifted into the TABLAT and buffer registers. 5. Verify high byte (odd address) by executing
The TBLPTR points to the word that will be pro- TLBRD *- (post-decrement). (If TBLPTR point-
grammed; it can point to either the high or the low byte. ing at odd address.)
(See Figure 2-17).
6. Verify low byte (even address) by executing
TLBRD *+ (post-increment). TBLPTR is point-
ing to odd address again.
7. If location doesn’t verify, go back to step 4.
8. If location does verify, begin 3x overprogram-
ming.
The TBLWT instruction offers flexibility with multiple
addressing modes: pre-increment, post-increment,
post decrement, and no change of the TBLPTR. These
modes eliminate the need for the increment address
command sequence.

FIGURE 2-17: DATA BUFFERING SCHEME FOR ICSP

Program Memory Program Memory

bank 0 bank 1
(Even Address) (Odd Address)

TBLWT TBLWT
Odd or Even Odd or Even Data shifted into
address address TABLAT and
Buffer registers
Buffer Register TABLAT Register
TBLRD RB7

TBLRD Odd Even

DS39028A-page 3-118  2000 Microchip Technology Inc.

PIC18CXXX
2.6.5 PROGRAMMING INSTRUCTION 2.6.6 VERIFY SEQUENCE
SEQUENCE
The table pointer = 000001h in the last example. A
The series of instructions needed to execute a pro- TBLRD will then read the odd address byte of the cur-
gramming sequence is as follows. Many of the instruc- rent program word address location first. The verify
tion sequences used in the following example are also sequence will be as follows:
shown in previous sections. ; Read/verify high byte first
NOP ; 4-bit instruction TBLRD*-
; Set up low byte ; TBLPTR = 0000 post-dec
; of program address ; Read/verify low byte
MOVLW Low_Byte_Address ; = 00 TBLRD*
NOP ; 4-bit instruction The first TBLRD decrements the table pointer to point to
MOVWF TBLPTRL, 0
the even address byte of the current program word.
NOP ; 4-bit instruction
; Set up high byte
After the first and second cycle of the TBLRD are per-
; of program formed, all 8-bits of data are shifted out on RB7. The
; address fetch of the second TBLRD occurs on the next 4 clock
MOVLW High_Byte_Address ; = 00 cycles. The second TBLRD does not modify the table
NOP ; 4-bit instruction pointer address. This allows another programming
MOVWF TBLPTRH, 0 cycle (TBLWT+*) to take place if the verify doesn’t
NOP ; 4-bit instruction match the program data without having to update the
; Set up upper byte table pointer.
; of program
; address If the contents of the verify do not match the intended
MOVLW Upper_Byte_Address; = 00 program data word, then the TBLWT instruction must be
NOP ; 4-bit instruction repeated with the correct contents of the current pro-
MOVWF TBLPTRU, 0 ; Program data byte gram word. Therefore, only one instruction needs to be
; included in TBLWT performed to repeat the programming cycle:
; instruction
TBLWT+*
; sequence
2.6.7 3X OVER PROGRAMMING
TBLWT+* ; TBLPTR = 000000h
Once a location has been both programmed and veri-
A write of a program memory location with an odd or an fied over a range of voltages, 3x over programming
even address causes a long write cycle in ICSP mode. should be applied. In other words, apply three times the
The 16-bit data is encoded in the TBLWT sequence and number of programming pulses that were required to
is loaded into the temporary buffer register for word program a location in memory, to ensure a solid pro-
wide writes. gramming margin.
The user must wait 100 µs for the long write to com- This means that every location will be programmed a
plete before the next instruction is executed. minimum of 4 times (1 + 3x over programming).

 2000 Microchip Technology Inc. DS39028A-page 3-119

PIC18CXXX
FIGURE 2-18: DETAILED PROGRAMMING FLOW CHART – PROGRAM MEMORY

Execute 1st cycle

Start TBLWT +*, and shift in
first 4-bits of data B
MCLR = VPP, for 4 clock cycles
RB6, RB7 = 0

N=0 Shift in last 12-bits of data

for 12 clock cycles

Execute FNOP Execute 2nd cycle

for four clock cycles TBLWT +* for 4 clock cycles
shift in 4-bit NOP Shift in TBLRD *-
for 4 clock cycles

Hold RB6
4-bit instruction = NOP, Clock high
Shift in 16-bit MOVLW Low_Addr
instruction for 16 clock cycles
Wait 100 µsec to
ensure programming

Execute MOVLW Clock Low

for 4 clock cycles for Discharge
and shift in 4-bit NOP

Hold RB6
Clock high (P10)
4-bit instruction = NOP, Execute MOVWF
Shift in 16-bit MOVWF TBLPTRL for 4 clock cycles
instruction for 16 clock cycles and shift in 4-bit NOP Execute 1st and 2nd cycle
TBLRD *- for 8 clock cycles

Shift Data Out

Execute MOVWF 4-bit instruction = NOP, for 8 clock cycles
for 4 clock cycles Shift in 16-bit MOVLW Upper_Addr
and shift in 4-bit NOP instruction for 16 clock cycles
Hold CPU,
Shift in TBLRD *
for 4 clock cycles
4-bit instruction = NOP, Execute MOVLW
Shift in 16-bit MOVLW High_Addr for 4 clock cycles
instruction for 16 clock cycles and shift in 4-bit NOP Execute 1st and 2nd cycle
TBLRD * for 8 clock cycles

Execute MOVLW Shift Data Out

for 4 clock cycles 4-bit instruction = NOP, for 8 clock cycles
and shift in 4-bit NOP Shift in 16-bit MOVWF TBLPTRU
instruction for 16 clock cycles

Yes
Verify? A
4-bit instruction = NOP,
Execute current instruction
Shift in 16-bit MOVWF TBLPTRH for 4 clock cycles, and
instruction for 16 clock cycles shift in 4-bit TBLWT+* No

N=N+1

Yes
N > 25?

Report
No Programming
Failure

DS39028A-page 3-120  2000 Microchip Technology Inc.

PIC18CXXX
FIGURE 2-19: DETAILED PROGRAMMING FLOW CHART – PROGRAM MEMORY (CONTINUED)

N=3*N

Execute current instruction,

Shift in TBLWT *+
for 4 clock cycles

Execute 1st cycle

TBLWT *+ or *, and shift in
first 4-bits of data
for 4 clock cycles

Shift in last 12-bits of data

for 12 clock cycles

No
N = 1?

Execute 2nd cycle

TBLWT * for 4 clock cycles
Yes Shift in TBLWT *
for 4 clock cycles
Execute 2nd cycle
TBLWT * for 4 clock cycles
Shift in TBLWT *+ Hold RB6 high
for 4 clock cycles

Shift in last 12-bits of data Wait 100 µS

for 12 clock cycles
Clock Low
for Discharge

Execute current instruction

for 4 clock cycles, and N=N-1
shift in 4-bit TBLRD+*

Hold RB6 high

Verify all Locations

Wait 100 µsec to @ VDDMIN
ensure programming
Report
No Verify
Data Correct?
Error
Yes @ VDDMIN
All locations Yes
programmed? Verify all Locations
@ VDDMAX

No Yes Report
No Verify
Data Correct?
To B Error
@ VDDMAX
End

 2000 Microchip Technology Inc. DS39028A-page 3-121

PIC18CXXX
2.6.8 LOAD CONFIGURATION 2.6.9 END PROGRAMMING

The Configuration registers are located in ok memory, When programming occurs, 16 bits of data are pro-
and are only addressable when the high address bit of grammed into memory. The 16-bits of data are shifted
the TBLPTR (bit 21) is set. Test program memory con- in during the TBLWT sequence. After the programming
tains test memory, configuration registers, calibration command (TBLWT) has been executed, the user must
registers, and ID locations. The desired address must wait for 100 µs until programming is complete, before
be loaded into all three bytes of the table pointer to pro- another command can be executed by the CPU. There
gram specific ID locations or the configuration bits. To is no command to end programming.
program the configuration registers, the following RB6 must remain high for as long as programming is
sequence must be followed: desired. When RB6 is lowered programming will cease.
NOP ; 4-bit instruction
After the falling edge occurs on RB6, RB6 must be held
; shift in 16-bit
; MOVLW instruction
low for a period of time so that a high voltage discharge
MOVLW 03h can be performed to ensure that the program array isn’t
NOP ; 4-bit instruction stressed at high voltage during execution of the next
; shift in 16-bit instruction. The high voltage discharge will occur while
; MOVWF instruction RB6 is low following the programming time.
; Enable Test memory
MOVWF TBLPTRU, 0
NOP ; 4-bit instruction
; shift in 16-bit
; MOVLW instruction
MOVLW Low_Config_Address
NOP ; 4-bit instruction
; shift in 16-bit
; MOVWF instruction
MOVWF TBLPTRL, 0
NOP ; 4-bit instruction
; shift in 16-bit
; MOVLW instruction
MOVLW ; High_Config_Address
NOP ; 4-bit instruction
; shift in 16-bit
; MOVWF instruction
MOVWF TBLPTRH, 0
NOP ; 4-bit instruction
; shift in 16-bit
; MOVLW instruction
TBLWT *+
; 16-bits of data are
; shifted in for write
; of config1L and
; config1H TBLWT is a
; 4-bit special
; instruction Wait
; 100 µsec for programming

DS39028A-page 3-122  2000 Microchip Technology Inc.

PIC18CXXX
FIGURE 2-20: SYMBOLIC PROGRAMMING FLOW CHART – CONFIG WORD / ID LOCATION

START

MCLR = VSS
4.75V < VDD < 5.25V

MCLR = VIHH

ICSP Command
LOAD CONFIGURATION
Address = 300000h

N=0 ICSP Command

LOAD DATA
No Yes
Program ID Loc?
ICSP Command
BEGIN PROGRAMMING

ICSP Command
LOAD ADDRESS
Wait approx 100 µs
Address = 300000h

ICSP Command ICSP Command

LOAD DATA READ DATA

No
N = 100 N > 25? Data Correct?
Yes Yes
Report N = 3N
ICSP Command Programming
BEGIN PROGRAMMING
Failure
ICSP Command
BEGIN PROGRAMMING
Wait approx 100 µs N=0

N=N-1 Address = 300000h? Wait approx 100 µs

No
N = 0? ICSP Command N=N-1
INCREMENT ADDRESS
Yes
No
ICSP Command N = 0?
READ DATA Yes

No Report Verify all Locations

Data Correct? Programming @ VDDMIN
Failure Report
Yes
Verify
Data Correct? Error
@ VDDMIN
Verify all Locations
@ VDDMAX
Report
No Verify
Data Correct?
Error
@ VDDMAX
DONE

 2000 Microchip Technology Inc. DS39028A-page 3-123

PIC18CXXX
FIGURE 2-21: DETAILED PROGRAMMING FLOW CHART – CONFIG WORD

START
Execute MOVLW
for 4 clock cycles
and shift in 4-bit NOP
MCLR = VSS
4.75V < VDD < 5.25V

4-bit instruction = NOP,

MCLR = VIHH Shift in 16-bit MOVWF TBPLTRL
instruction for 16 clock cycles
TBPLTR = 0x300000h
Execute FNOP CONFIG1L and CONFIG1H
for four clock cycles
shift in 4-bit NOP
N = 99 B
4-bit instruction = NOP,
Shift in 16-bit MOVLW 30 Execute last fetched inst.
instruction for 16 clock cycles for 4 clock cycles
and shift in 4-bit TBLWT+*

Execute MOVLW Execute 1st cycle

for 4 clock cycles TBLWT, and shift in
and shift in 4-bit NOP first 4-bits of config. reg.
for 4 clock cycles

4-bit instruction = NOP,

Shift in 16-bit MOVWF TBLPTRU Shift in last 12-bits of data
instruction for 16 clock cycles for 12 clock cycles

Execute MOVWF Yes

for 4 clock cycles N = 1?
and shift in 4-bit NOP

No
4-bit instruction = NOP, Execute 2nd cycle
Shift in 16-bit MOVLW 00 TBLWT for 4 clock cycles
instruction for 16 clock cycles Shift in TBLWT *
for 4 clock cycles

Execute MOVLW RB6 High

for 4 clock cycles
and shift in 4-bit NOP
Wait 100 µsec to
ensure programming

4-bit instruction = NOP, Clock Low

Shift in 16-bit MOVWF TBLPTRH for Discharge
instruction for 16 clock cycles
N=N-1

Execute MOVWF Execute 2nd cycle

for 4 clock cycles
TBLWT* for 4 clock cycles
and shift in 4-bit NOP Shift in TBLWT *-
for 4 clock cycles

4-bit instruction = NOP,

Wait 100 µsec to
Shift in 16-bit MOVLW 00 ensure programming A
instruction for 16 clock cycles

DS39028A-page 3-124  2000 Microchip Technology Inc.

PIC18CXXX
FIGURE 2-22: DETAILED PROGRAMMING FLOW CHART – CONFIG WORD

Execute 1st cycle

TBLWT*-, and shift in
first 4-bits of config. reg.
for 4 clock cycles
No Report
Verify? Verify
Error
Shift in last 12-bits of data
for 12 clock cycles Yes

All
Execute 2nd cycle locations No
TBLWT *- for 4 clock cycles programmed? B
Shift in TBLRD*+
for 4 clock cycles
Yes

Wait 100 µsec to Verify all ID_Locations

ensure programming @ VDDMIN

Execute 1st and 2nd cycle Report

TBLRD*+ for 8 clock cycles Verify
Data Correct? No
Error
@ VDDMIN
Shift Data Out
Yes
for 8 clock cycles

Verify all Locations

@ VDDMAX
Shift in TBLRD*+
for 4 clock cycles
Report
No Verify
Data Correct? Error
Execute 1st and 2nd cycle
TBLRD*+ for 8 clock cycles @ VDDMAX

Yes

Shift Data Out

DONE
for 8 clock cycles

 2000 Microchip Technology Inc. DS39028A-page 3-125

PIC18CXXX
FIGURE 2-23: DETAILED PROGRAMMING FLOW CHART – ID LOCATION

Start

MCLR = VPP,
Execute 1st cycle
RB6, RB7 = 0
TBLWT +*, and shift in
first 4-bits of data B
N=0 for 4 clock cycles

Execute FNOP Shift in last 12-bits of data

for four clock cycles for 12 clock cycles
shift in 4-bit NOP

Execute 2nd cycle

TBLWT +* for 4 clock cycles
4-bit instruction = NOP, Shift in TBLRD *-
Shift in 16-bit MOVLW Low_Addr for 4 clock cycles
instruction for 16 clock cycles
Wait 100 µsec to
ensure programming
Execute MOVLW
for 4 clock cycles
Execute 1st and 2nd cycle
and shift in 4-bit NOP
TBLRD *- for 8 clock cycles

Shift Data Out

4-bit instruction = NOP, for 8 clock cycles
Shift in 16-bit MOVWF TBLPTRL
instruction for 16 clock cycles Execute MOVWF
for 4 clock cycles
and shift in 4-bit NOP Shift in TBLRD *
for 4 clock cycles
Execute MOVWF
for 4 clock cycles
and shift in 4-bit NOP 4-bit instruction = NOP, Execute 1st and 2nd cycle
TBLRD * for 8 clock cycles
Shift in 16-bit MOVLW Upper_Addr
instruction for 16 clock cycles
Shift Data Out
4-bit instruction = NOP, for 8 clock cycles
Shift in 16-bit MOVLW High_Addr
instruction for 16 clock cycles Execute MOVLW
for 4 clock cycles
and shift in 4-bit NOP
Yes
Execute MOVLW Verify? A
for 4 clock cycles
and shift in 4-bit NOP
4-bit instruction = NOP, No
Shift in 16-bit MOVWF TBLPTRU
instruction for 16 clock cycles N=N+1
4-bit instruction = NOP,
Shift in 16-bit MOVWF TBLPTRH
instruction for 16 clock cycles
Execute current instruction
for 4 clock cycles, and Yes
N > 25?
shift in 4-bit TBLWT+*
Report
No Programming
Failure

DS39028A-page 3-126  2000 Microchip Technology Inc.

PIC18CXXX
FIGURE 2-24: DETAILED PROGRAMMING FLOW CHART – ID LOCATIONS (CONTINUED)

N=3*N

Execute current instruction,

Shift in TBLWT *+
for 4 clock cycles

Execute 1st cycle

TBLWT *+ or *, and shift in
first 4-bits of data
for 4 clock cycles

Shift in last 12-bits of data

for 12 clock cycles

No
N = 1?

Wait 100 µsec to

Yes ensure programming
Execute 2nd cycle
TBLWT * for 4 clock cycles Execute 2nd cycle
Shift in TBLWT *+ TBLWT * for 4 clock cycles
for 4 clock cycles Shift in TBLWT *
for 4 clock cycles

Execute 1st cycle

TBLWT *+, and shift in N=N-1
first 4-bits of data
for 4 clock cycles

Shift in last 12-bits of data

for 12 clock cycles

Execute 2nd cycle TBLWT *+

for 4 clock cycles, and
shift in 4-bit TBLWT +*
Verify all Locations
@ VDDMIN
Wait 100 µsec to Report
ensure programming No Verify
Data Correct? Error
Yes @ VDDMIN

Yes Verify all Locations

All locations @ VDDMAX
programmed?
Yes Report
No Verify
No Data Correct?
Error
@ VDDMAX
B
End

 2000 Microchip Technology Inc. DS39028A-page 3-127

PIC18CXXX
3.0 CONFIGURATION WORD
The configuration bits can be programmed (read as ’0’)
or left unprogrammed (read as ’1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h – 3FFFFFh).

TABLE 3-1: CONFIGURATION BITS AND DEVICE IDS

Default /
Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 unprogrammed
value
300000h CONFIG1L CP CP CP CP CP CP CP CP 1111 1111
300001h CONFIG1H RES1 RES1 OSCSEN — — FOSC2 FOSC1 FOSC0 111- -111
300002h CONFIG2L — — — — BORV1 BORV0 BODEN PWRTEN ---- 1111
300003h CONFIG2H — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111
300005h CONFIG3H — — — — — — — CCP2MX ---- ---1
300006h CONFIG4L — — — — — — RES1 STVREN ---- --11
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 ---- ----
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, grayed cells are unimplemented read
as 0
Note 1: Resvered – Read as 1.

DS39028A-page 3-128  2000 Microchip Technology Inc.

PIC18CXXX
Register 3-1: Configuration Register 1 High (CONFIG1H: Byte Address 300001h)

R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1

Reserved Reserved OSCSEN — — FOSC2 FOSC1 FOSC0
bit 7 bit 0

bit 7-6 Reserved: Read as ’1’

bit 5 OSCSEN: Oscillator System Clock Switch Enable bit
1 =Oscillator system clock switch option is disabled (OSCA is source)
0 =Oscillator system clock switch option is enabled
(OSCA → OSCB, OSCB → OSCA switching is enabled)
bit 4-3 Reserved: Read as ’0’
bit 2-0 FOSC2:FOSC0: Oscillator Selection bits
111 = RC oscillator w/ OSC2 configured as RA6
110 = HS oscillator with PLL enabled/CLock frequency = (4 x Fosc1)
101 = EC oscillator w/ OSC2 configured as RA6
100 = EC oscillator w/ OSC2 configured as divide by 4 clock output
011 = RC oscillator
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator

Legend
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state

Register 3-2: Configuration Register 1 Low (CONFIG1L: Byte Address 300000h)

R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1

CP CP CP CP CP CP CP CP
bit 7 bit 0

CP: Code Protection bits (apply when in Code Protected Microcontroller Mode)
1 = Program memory code protection off
0 = All of program memory code protected

Legend
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state

 2000 Microchip Technology Inc. DS39028A-page 3-129

PIC18CXXX
Register 3-3: Configuration Register 2 High (CONFIG2H: Byte Address 300003h)

U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1

— — — — WDTPS2 WDTPS1 WDTPS0 WDTEN
bit 7 bit 0

bit 7-4 Reserved: Read as ’0’

bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
bit 0 WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on the SWDTE bit)

Legend
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state

Register 3-4: Configuration Register 2 Low (CONFIG2L: Byte Address 300002h)

U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1

— — — — BORV1 BORV0 BOREN PWRTEN
bit 7 bit 0

bit 7-4 Reserved: Read as ’0’

bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits
11 = VBOR set to 2.5V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
bit 1 BOREN: Brown-out Reset Enable bit (1)
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of
bit PWRTEN. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
bit 0 PWRTEN: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of
bit PWRTEN. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.

Legend
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state

DS39028A-page 3-130  2000 Microchip Technology Inc.

PIC18CXXX
Register 3-5: Configuration Register 3 High (CONFIG3H: Byte Address 300005h)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/P-1

— — — — — — — CCP2MX
bit 7 bit 0

bit 7-1 Reserved: Read as ’0’

bit 0 CCP2MX: CCP2 Mux bit
1 = CCP2 input/output is multiplexed with RC1
0 = CCP2 input/output is multiplexed with RB3

Legend
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state

Register 3-6: Configuration Register 4 Low (CONFIG3H: Byte Address 300006h)

U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1

— — — — — — Reserved STVREN
bit 7 bit 0

bit 7-2 Reserved: Read as ’0’

bit 1 Reserved: Maintain this bit set.
bit 0 STVREN: Stack Full/Underflow Reset Enable bit
1 = Stack Full/Underflow will cause reset
0 = Stack Full/Underflow will not cause reset

Legend
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
- n = Value when device is unprogrammed u = Unchanged from programmed state

3.1 ID Locations
A user may store identification information (ID) in 8 ID
locations. The ID locations are mapped in
[0x200000:0x200007]. It is recommended that the user
use only the 4 least significant bits of each ID location.
The ID locations do not read out in a scrambled fashion
after code protection is enabled. For all devices it is rec-
ommended that all ID locations are written as ‘1111
bbbb’ where bbbb is the ID information. When the
upper four bits of an ID location is written as ‘1111’, the
resulting opcode when executed is read as a NOP. This
allows Reset testing of test program memory after ID
locations have been programmed.

 2000 Microchip Technology Inc. DS39028A-page 3-131

PIC18CXXX
3.2 Embedding Configuration Word Information in the Hex File

To allow portability of code, a PIC18C4X programmer is required to read the configuration word locations from the hex
file when loading the hex file. If configuration word information was not present in the hex file then a simple warning
message may be issued. Similarly, while saving a hex file, all configuration word information must be included. An
option to not include the configuration word information may be provided. When embedding configuration word infor-
mation in the hex file, it should be to address FE00h.
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.

3.3 CHECKSUM COMPUTATION ently depending on the code protect setting, the table
describes how to manipulate the actual program mem-
The checksum is calculated by summing the following: ory values to simulate the values that would be read
• The contents of all program memory locations from a protected device. When calculating a checksum
• The configuration word, appropriately masked by reading a device, the entire program memory can
simply be read and summed. The configuration word
• Masked ID locations (when applicable)
and ID locations can always be read.
The least significant 16 bits of this sum is the check-
Note that some older devices have an additional value
sum.
added in the checksum. This is to maintain compatibil-
The following table describes how to calculate the ity with older device programmer checksums.
checksum for each device. Note that the checksum cal-
culation differs depending on the code protect setting.
Since the program memory locations read out differ-
TABLE 3-2: CHECKSUM COMPUTATION
0xAA at 0
Code Blank
Device Checksum* and max
Protect Value
address
Disable SUM[0C000:0x7FFF] + CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 0x8148 0x809E
& 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 +
CFGW6 & 0x03 + CFGW7 & 0x00
PIC18C452
Enabled CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0xF + CFGW3 & 0x0F 0x005E 0x0068
+ CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 + CFGW7 &
0x00 + SUM_ID
Disable SUM[0x000:0x3FFF] + CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 0xC148 0xC09E
& 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 +
CFGW6 & 0x03 + CFGW7 & 0x00
PIC18C442
Enabled CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0x0F + CFGW3 & 0x0062 0x006C
0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 +
CFGW7 & 0x00 + SUM_ID
Disable SUM[0x000:0x7FFF] + CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 0x8148 0x809E
& 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 +
CFGW6 & 0x03 + CFGW7 & 0x00
PIC18C252
Enabled CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0x0F + CFGW3 & 0x005E 0x0068
0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 +
CFGW7 & 0x00 + SUM_ID
Disable SUM[0x000:0x3FFF] + CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 0xC148 0xC09E
& 0x0F + CFGW3 & 0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 +
CFGW6 & 0x03 + CFGW7 & 0x00
PIC18C242
Enabled CFGW0 & 0xFF + CFGW1 & 0x27 + CFGW2 & 0x0F + CFGW3 & 0x0062 0x006C
0x0F + CFGW4 & 0x00 + CFGW5 & 0x01 + CFGW6 & 0x03 +
CFGW7 & 0x00 + SUM_ID
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = Byte-wise sum of lower four bits of all ID locations
+ = Addition
& = Bitwise AND

DS39028A-page 3-132  2000 Microchip Technology Inc.

PIC18CXXX
4.0 AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +70°C, unless otherwise stated, (25°C is recommended)
Operating Voltage: 4.5V ≤ VDD ≤ 5.25V, unless otherwise stated.
Parameter
Sym Characteristic Min Typ† Max Units Conditions
No.
VIHH Programming Voltage on VPP/ VDD + 4.0 — 13.25 V
MCLR pin and TEST pin.
IPP Programming current on MCLR pin 25 50 mA

P1 TSER Serial setup time 20 — — ns

P2 TSCLK Serial Clock period 100 — — ns
P3 TSET1 Input Data Setup Time to serial 15 — — ns
clock ↓
P4 THLD1 Input Data Hold Time from serial 15 — — ns
clock ↓
P5 TDLY1 Delay between last clock ↓ to first 20 — — ns
clock ↑ of next command
P6 TDLY2 Delay between last clock ↓ of com- 20 — — ns
mand byte to first clock ↑ of read of
data word
P8 TDLY4 Data input not driven to next clock 1 — — ns
input
P9 TDLY5 RB6 high time (minimum program- 100 — — µs
ming time)
P10 TDLY6 RB6 low time after programming 100 — — ns
(high voltage discharge time)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25×C unless otherwise stated. These parameters are for design guidance only and are not
tested.

 2000 Microchip Technology Inc. DS39028A-page 3-133

PIC18CXXX
NOTES:

DS39028A-page 3-134  2000 Microchip Technology Inc.

PIC16F62X
In-Circuit Serial Programming for PIC16F62X FLASH MCUs

This document includes the programming PIN Diagram

specifications for the following devices:
• PIC16F627 PDIP, SOIC
• PIC16F628 RA2/AN2/VREF •1 18 RA1/AN1

• PIC16LF627 RA3/AN3/CMP1 2 17 RA0/AN0

• PIC16LF628 RA4/T0CKI/CMP2 3 16 RA7/OSC1/CLKIN

PIC16F62X
RA5/MCLR/THV 4 15 RA6/OSC2/CLKOUT

1.0 PROGRAMMING THE VSS 5 14 VDD

RB0/INT RB7/T1OSI
PIC16F62X 6 13

RB1/RX/DT 7 12 RB6/T1OSO/T1CKI
The PIC16F62X is programmed using a serial method. RB2/TX/CK 8 11 RB5
The serial mode will allow the PIC16F62X to be pro- RB3/CCP1 9 10 RB4/PGM
grammed while in the users system. This allows for
increased design flexibility. This programming specifi-
cation applies to PIC16F62X devices in all packages.
PIC16F62X devices may be programmed using a sin- RA2/AN2/VREF •1 20 RA1/AN1

gle +5 volt supply (low voltage programming mode). RA3/AN3/CMP1 2 19 RA0/AN0

RA4/T0CKI/CMP2 3 18 RA7/OSC1/CLKIN

PIC16F62X
1.1 Hardware Requirements RA5/MCLR/THV 4 17 RA6/OSC2/CLKOUT

VSS 5 16 VDD
The PIC16F62X requires one programmable power
VSS 6 VDD
supply for VDD (4.5V to 5.5V) and a VPP of 12V to 14V 15

RB0/INT 7 14
or VPP of (4.5V to 5.5V) when using low voltage. Both RB7/T1OSI
RB1/RX/DT 8
RB6/T1OSO/T1CKI
supplies should have a minimum resolution of 0.25V. 13

RB2/TX/CK 9 12
RB5

1.2 Programming Mode RB3/CCP1 10 11 RB4/PGM

The programming mode for the PIC16F62X allows pro-

gramming of user program memory, data memory, spe-
cial locations used for ID, and the configuration word.

PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F62X

During Programming

Pin Name Function Pin Type Pin Description

RB4 PGM I Low voltage programming input if configuration bit
equals 1
RB6 CLOCK I Clock input
RB7 DATA I/O Data input/output
MCLR VTEST MODE P* Program Mode Select
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
*In the PIC16F62X, the programming high voltage is internally generated. To activate the programming mode, high voltage needs
to be applied to MCLR input. Since the MCLR is used for a level source, this means that MCLR does not draw any significant current.

 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-135

PIC16F62X
2.0 PROGRAM MODE ENTRY 2.2 ID Locations

2.1 User Program Memory Map A user may store identification information (ID) in four
ID locations. The ID locations are mapped in [0x2000 :
The user memory space extends from 0x0000 to 0x2003]. It is recommended that the user use only the
0x7FFF. In programming mode the program memory four least significant bits of each ID location. In some
space extends from 0x0000 to 0x3FFF, with the first devices, the ID locations read-out in an unscrambled
half (0x0000-0x7FFF) being user program memory and fashion after code protection is enabled. For these
the second half (0x2000-0x3FFF) being configuration devices, it is recommended that ID location is written as
memory. The PC will increment from 0x0000 to 0x7FFF “11 1111 1000 bbbb” where ‘bbbb’ is ID information.
and wrap to 0x000, 0x2000 to 0x3FFF and wrap In other devices, the ID locations read out normally,
around to 0x2000 (not to 0x0000). Once in configura- even after code protection. To understand how the
tion memory, the highest bit of the PC stays a ‘1’, thus devices behave, refer to Table 4-1.
always pointing to the configuration memory. The only
way to point to user program memory is to reset the To understand the scrambling mechanism after code
part and reenter program/verify mode as described in protection, refer to Section 3-1.
Section 2.3.
In the configuration memory space, 0x2000-0x200F
are physically implemented. However, only locations
0x2000 through 0x2007 are available. Other locations
are reserved. Locations beyond 0x200F will physically
access user memory. (See Figure 2-1).

FIGURE 2-1: PROGRAM MEMORY MAPPING

1 KW 2 KW

0x1FF

Implemented Implemented

1FFF
2000 ID Location
2000
Implemented Implemented
2001
ID Location 2008

2002
ID Location

2003
ID Location

2004
Reserved
Not Implemented
2005
Reserved

2006
Reserved

2007
Configuration Word 3FFF

DS30034A-page 3-136 Preliminary  2000 Microchip Technology Inc.

PIC16F62X
2.3 Program/Verify Mode 2.3.2 SERIAL PROGRAM/VERIFY OPERATION

2.3.1 LOW-VOLTAGE PROGRAMMING MODE The commands that are available are:

When LVP bit is set to ‘1’, the low-voltage programming 2.3.2.1 LOAD CONFIGURATION
entry is enabled. Since the LVP configuration bit allows After receiving this command, the program counter
low voltage programming entry in its erased state, an (PC) will be set to 0x2000. By then applying 16 cycles
erased device will have the LVP bit enabled at the fac- to the clock pin, the chip will load 14-bits in a “data
tory. While LVP is ‘1’, RB4 is dedicated to low voltage word,” as described above, to be programmed into the
programming. Bring MCLR to VDD and then RB4 to configuration memory. A description of the memory
VDD to enter programming mode. All other specifica- mapping schemes of the program memory for normal
tions for high-voltage ICSP™ apply. operation and configuration mode operation is shown
To disable low voltage mode, the LVP bit must be pro- in Figure 2-1. After the configuration memory is
grammed to ‘0’. This must be done while entered with entered, the only way to get back to the user program
high voltage entry mode (LVP bit= 1). RB4 is now a memory is to exit the program/verify test mode by tak-
general purpose I/O pin. ing MCLR low (VIL).

 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-137

PIC16F62X
2.3.2.2 LOAD DATA FOR PROGRAM MEMORY

After receiving this command, the chip will load in a

14-bit “data word” when 16 cycles are applied, as
described previously. A timing diagram for the load data
command is shown in Figure 5-1.

TABLE 2-1: COMMAND MAPPING FOR PIC16F627/PIC16F628

Command Mapping (MSB … LSB) Data
Load Configuration X X 0 0 0 0 0, data (14), 0
Load Data for Program Memory X X 0 0 1 0 0, data (14), 0
Read Data from Program Memory X X 0 1 0 0 0, data (14), 0
Increment Address X X 0 1 1 0
Begin Erase Programming Cycle 0 0 1 0 0 0
Begin Programming Only Cycle 0 1 1 0 0 0
Load Data for Data Memory X X 0 0 1 1 0, data (14), 0
Read Data from Data Memory X X 0 1 0 1 0, data (14), 0
Bulk Erase Program Memory X X 1 0 0 1
Bulk Erase Data Memory X X 1 0 1 1

DS30034A-page 3-138 Preliminary  2000 Microchip Technology Inc.

PIC16F62X
FIGURE 2-2: PROGRAM FLOW CHART - PIC16F62X PROGRAM MEMORY

Start

Set VDD = VDDP

Program Cycle

PROGRAM CYCLE

Read Data
Command Load Data
Command

No Report
Data Correct? Programming Begin
Failure Programming
Command

Increment No All Locations

Address
Done?
Command Wait 2 ms

Verify all
Locations @
VDDMIN

Report Verify No
Error @ Data Correct?
VDDMIN

Verify all
Locations @
VDDMAX

Report Verify No
Error @ Data Correct?
VDDMAX

Done

 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-139

PIC16F62X
FIGURE 2-3: PROGRAM FLOW CHART - PIC16F62X CONFIGURATION MEMORY

Start

Load
Configuration
Data

No Program ID Yes Read Data

Location? Program Cycle Command

Increment Report No
Address Programming Data Correct?
Command Failure

Yes

No Address =
0x2004?

Yes

Increment
Address
Command

Increment Program
Set VDD =
Address Cycle
VDDMAX
Command (Config. Word)

Report Program No Read Data

Configuration Data Correct? Command
Word Error

Yes

Set VDD =
VDDMAX

Yes Read Data

Done Data Correct? Command

DS30034A-page 3-140 Preliminary  2000 Microchip Technology Inc.

PIC16F62X
2.3.2.3 LOAD DATA FOR DATA MEMORY 2.3.2.8 BEGIN PROGRAMMING

After receiving this command, the chip will load in a 14- A load command must be given before every begin
bit “data word” when 16 cycles are applied. However, programming command. Programming of the appro-
the data memory is only 8-bits wide, and thus only the priate memory (test program memory, user program
first 8-bits of data after the start bit will be programmed memory or data memory) will begin after this command
into the data memory. It is still necessary to cycle the is received and decoded. An internal timing mechanism
clock the full 16 cycles in order to allow the internal cir- executes a write. The user must allow for program cycle
cuitry to reset properly. The data memory contains 64 time for programming to complete. No “end program-
words. Only the lower 8-bits of the PC are decoded by ming” command is required.
the data memory, and therefore if the PC is greater than This command is similar to the ERASE/PROGRAM
0x3F, it will wrap around and address a location within CYCLE command, except that a word erase is not
the physically implemented memory. If the device is done. It is recommended that a bulk erase be per-
code protected, the data is read as all zeros. formed before starting a series of programming only
2.3.2.4 READ DATA FROM PROGRAM cycles.
MEMORY 2.3.2.9 BULK ERASE PROGRAM MEMORY
After receiving this command, the chip will transmit After this command is performed, the next program
data bits out of the program memory (user or configu- command will erase the entire program memory.
ration) currently accessed starting with the second ris-
ing edge of the clock input. The RB7 pin will go into To perform a bulk erase of the program memory, the fol-
output mode on the second rising clock edge, and it will lowing sequence must be performed.
revert back to input mode (hi-impedance) after the 16th 1. Do a “Load Data All 1’s” command.
rising edge. A timing diagram of this command is 2. Do a “Bulk Erase User Memory” command.
shown in Figure 5-2.
3. Do a “Begin Programming” command.
2.3.2.5 READ DATA FROM DATA MEMORY 4. Wait 10 ms to complete bulk erase.
If the address is pointing to the test program memory
After receiving this command, the chip will transmit
(0x2000 - 0x200F), then both the user memory and the
data bits out of the data memory starting with the sec-
test memory will be erased. The configuration word will
ond rising edge of the clock input. The RB7 pin will go
not be erased, even if the address is pointing to location
into output mode on the second rising edge, and it will
0x2007.
revert back to input mode (hi-impedance) after the 16th
rising edge. As previously stated, the data memory is 8- Note: If the device is code-protected, the BULK
bits wide, and therefore, only the first 8-bits that are out- ERASE command will not work.
put are actual data.
2.3.2.10 BULK ERASE DATA MEMORY
2.3.2.6 INCREMENT ADDRESS
To perform a bulk erase of the data memory, the follow-
The PC is incremented when this command is ing sequence must be performed.
received. A timing diagram of this command is shown
1. Do a “Load Data All 1’s” command.
in Figure 5-3.
2. Do a “Bulk Erase Data Memory” command.
2.3.2.7 BEGIN ERASE/PROGRAM CYCLE 3. Do a “Begin Programming” command.
4. Wait 10 ms to complete bulk erase.
A load command must be given before every begin
programming command. Programming of the appro-
priate memory (test program memory, user program
Note: All BULK ERASE operations must take
memory or data memory) will begin after this command
place at 4.5 to 5.5 VDD range.
is received and decoded. An internal timing mechanism
executes an erase before write. The user must allow for
both erase and programming cycle times for program-
ming to complete. No “end programming” command is
required.

 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-141

PIC16F62X
2.4 Programming Algorithm Requires
Variable VDD
The PIC16F62X uses an intelligent algorithm. The
algorithm calls for program verification at VDDmin. as
well as VDDmax. Verification at VDDmin. guarantees
good “erase margin”. Verification at VDDmax guaran-
tees good “program margin”.
The actual programming must be done with VDD in the
VDDP range (See Table 5-1).
VDDP = VCC range required during programming.
VDDmin. = minimum operating VDD spec for the part.
VDDmax.= maximum operating VDD spec for the part.
Programmers must verify the PIC16F62X at its speci-
fied VDD max. and VDDmin levels. Since Microchip may
introduce future versions of the PIC16F62X with a
broader VDD range, it is best that these levels are user
selectable (defaults are ok).
Note: Any programmer not meeting these
requirements may only be classified as
“prototype” or “development” programmer
but not a “production” quality programmer.

DS30034A-page 3-142 Preliminary  2000 Microchip Technology Inc.

PIC16F62X
3.0 CONFIGURATION WORD TABLE 3-1:
The PIC16F62X has several configuration bits. These Device ID Value
Device
bits can be set (reads ‘0’) or left unchanged (reads ‘1’) Dev Rev
to select various device configurations.
PIC16F627 00 0111 111 x xxxx
3.1 Device ID Word PIC16F628 00 0111 001 x xxxx

The device ID word for the PIC16F62X is located at

2006h.

FIGURE 3-1: CONFIGURATION WORD FOR PIC16F877/876/873

CP1 CP0 CP1 CP0 - CPD LVP BODEN MCLRE FOSC2 PWRTE WDTE F0SC1 F0SC0 Register: CONFIG
Address 2007h
bit13 bit0

bit 13-10: CP1:CP0: Code Protection bits (2)

Code protection for 2K program memory
11 = Program memory code protection off
10 = 0400h-07FFh code protected
01 = 0200h-07FFh code protected
00 = 0000h-07FFhcode protected
Code protection for 1K program memory
11 = Program memory code protection off
10 = Program memory code protection off
01 = 0200h-03FFh code protected
00 = 0000h-03FFh code protected
bit 8: CPD: Data Code Protection bit(3)
1 = Data memory code protection off
0 = Data memory code protected
bit 7: LVP: Low Voltage Programming Enable
1 = RB4/PGM pin has PGM function, low voltage programming enabled
0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming
bit 6: BODEN: Brown-out Detect Reset Enable bit (1)
1 = BOD reset enabled
0 = BOD reset disabled
bit 5: MCLRE: RA5/MCLR pin function select
1 = RA5/MCLR pin function is MCLR
0 = RA5/MCLR pin function is digital I/O, MCLR internally tied to VDD
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 4,1-0: FOSC2:FOSC0: Oscillator Selection bits(4)
111 = ER oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
110 = ER oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
101 = INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EXTCLK: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN

Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure
the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. The entire pro-
gram EEPROM will be erased if the code protection is reduced.
3: The entire data EEPROM will be erased when the code protection is turned off. The calibration space in the test memory
is not erased.
4: When MCLR is asserted in INTRC or ER mode, the internal clock oscillator is disabled.

 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-143

PIC16F62X
4.0 CODE PROTECTION Procedure to disable code protect:
For PIC16F62X devices, once code protection is a) Execute load configuration (with a ‘1’ in bit 4,
enabled, all program memory locations read all 0’s. code protect).
The ID locations and the configuration word read out in b) Increment to configuration word location
an unscrambled fashion. Further programming is dis- (0x2007)
abled for the entire program memory as well as data c) Execute command (000001)
memory. It is possible to program the ID locations and d) Execute command (000111)
the configuration word.
e) Execute ‘Begin Programming’ (001000)
4.1 Disabling Code-Protection f) Wait 10 ms
g) Execute command (000001)
It is recommended that the following procedure be per-
h) Execute command (000111)
formed before any other programming is attempted. It
is also possible to turn code protection off (code protect
bit = 1) using this procedure; however, all data within
the program memory and the data memory will be
erased when this procedure is executed, and thus,
the security of the data or code is not compro-
mised.

4.2 Embedding Configuration Word and ID Information in the Hex File

To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex
file when loading the hex file. If configuration word information was not present in the hex file then a simple warning
message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included.
An option to not include this information may be provided.
Specifically for the PIC16F62X, the EEPROM data memory should also be embedded in the hex file (see
Section 5.1).
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.

DS30034A-page 3-144 Preliminary  2000 Microchip Technology Inc.

PIC16F62X
4.3 CHECKSUM COMPUTATION The least significant 16 bits of this sum is the check-
sum.
4.3.1 CHECKSUM
The following table describes how to calculate the
Checksum is calculated by reading the contents of the checksum for each device. Note that the checksum cal-
PIC16F62X memory locations and adding up the culation differs depending on the code protect setting.
opcodes up to the maximum user addressable location, Since the program memory locations read out differ-
e.g., 0x1FF for the PIC16F62X. Any carry bits exceed- ently depending on the code protect setting, the table
ing 16-bits are neglected. Finally, the configuration describes how to manipulate the actual program mem-
word (appropriately masked) is added to the check- ory values to simulate the values that would be read
sum. Checksum computation for each member of the from a protected device. When calculating a checksum
PIC16F62X devices is shown in Table 4-1. by reading a device, the entire program memory can
simply be read and summed. The configuration word
The checksum is calculated by summing the following:
and ID locations can always be read.
• The contents of all program memory locations
Note that some older devices have an additional value
• The configuration word, appropriately masked added in the checksum. This is to maintain compatibil-
• Masked ID locations (when applicable) ity with older device programmer checksums.

TABLE 4-1: CHECKSUM COMPUTATION

0x25E6 at 0
Code Blank
Checksum* and max
Device Protect Value
address
PIC16F627 OFF SUM[0x0000:0x3FFF] + CFGW & 0x3DFF 0x39FF 0x05CD
0x200 : 0x3FF SUM[0x0000:0x01FF] + CFGW & 0x3DFF + SUM_ID 0x4DFE 0xFFB3
ALL 0x3BFE 0x07CC
PIC16F628 OFF SUM[0x0000:0x07FF] + CFGW & 0x3DFF 0x35FF 0x01CD
0x400 : 0xFFF SUM[0x0000:0x03FF] + CFGW & 0x3DFF +SUM_ID 0x5BFE 0x0DB3
0x200 : 0x7FF SUM[0x0000:0x01FF] + CFGW & 0x3DFF + SUM_ID 0x49FE 0xFBB3
ALL CFGW & 0x3DFF + SUM_ID 0x37FE 0x03CC
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND

 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-145

PIC16F62X
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
5.1 Embedding Data EEPROM Contents in Hex File
The programmer should be able to read data EEPROM information from a hex file and conversely (as an option) write
data EEPROM contents to a hex file along with program memory information and fuse information.
The 64 data memory locations are logically mapped starting at address 0x2100. The format for data memory storage
is one data byte per address location, LSB aligned.

TABLE 5-1: AC/DC CHARACTERISTICS

TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
Standard Operating Conditions (unless otherwise stated)
Operating Temperature: 0°C ≤ TA ≤ +70°C
Operating Voltage: 4.5V ≤ VDD ≤ 5.5V
Characteristics Sym Min Typ Max Units Conditions/Comments
General
VDD level for word operations, program
memory VDD 2.0 5.5 V
VDD level for word operations, data mem-
ory VDD 2.0 5.5 V
VDD level for bulk erase/write operations,
program and data memory VDD 4.5 5.5 V
High voltage on MCLR and
RA4/T0CKI for test-mode entry VIHH VDD + 3.5 13.5 V
MCLR rise time (VSS to VHH) for test tVHHR 1.0 µs
mode entry
(RB6, RB7) input high level VIH1 0.8VDD V Schmitt Trigger input
(RB6, RB7) input low level VIL1 0.2VDD V Schmitt Trigger input
RB<7:4> setup time before MCLR↑ tset0 100 ns
(test mode selection pattern setup time)
RB<7:4> hold time after MCLR↑ thld0 5 µs
(test mode selection pattern setup time)
Serial Program/Verify
Data in setup time before clock↓ tset1 100 ns
Data in hold time after clock↓ thld1 100 ns
Data input not driven to next clock input tdly1 1.0 µs
(delay required between command/data or
command/command)
Delay between clock↓ to clock↑ of next tdly2 1.0 µs
command or data
Clock↑ to data out valid (during read data) tdly3 80 ns
Parallel Program/Verify
Data in setup time before clock↓ tset0 1.0 µs
Data in hold time after clock↓ thld0 1.0 µs
RB6 and RB7 setup time before clock↓ tset1 1.0 µs
RB6 and RB7 hold time after clock↓ thld1 1.0 µs
RA4/T0CKI (clock)↓ to (clock)↑ tdly4 2.0 µs
RB7 (data/command select input) setup tset2 1.0 µs
before RA4/T0CKI (clock)↑
RB7 (data/command select input) hold time thld2 1.0 µs
after RA4/T0CKI (clock)↓
RA4/T0CKI (clock)↑ to data out valid tdly5 1.0 µs
RB6 (hi/lo select) valid to data out valid tdly6 1.0 µs
Erase cycle time tera 2 5 ms
Programming cycle time tprog 2 5 ms
Time delay from program to compare (HV tdis 0.5 µs
discharge time)

DS30034A-page 3-146 Preliminary  2000 Microchip Technology Inc.

PIC16F62X
FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY)

VIHH
MCLR 1µs min.
tset0 1 2 3 4 5 6 1 2 3 4 5 15 16
tdly2
RB6
(CLOCK)
thld0

RB7 0 1 0 0 X X strt_bit stp_bit

(DATA)
tset1 tdly1 tset1
thld1 1µs min. thld1
}
}

}
}
100ns min. 100ns min.

Reset Program/Verify Test Mode

FIGURE 5-2: READ DATA COMMAND (PROGRAM/VERIFY)

VIHH
MCLR
tdly2
tset0
thld0 1µs min.
1 2 3 4 5 6 1 2 3 4 5 15 16
RB6
(CLOCK)
tdly3
RB7 1 0 1 0 X X stp_bit
(DATA) strt_bit

tset1 tdly1

thld1
1µs min.
}
}

100ns min. RB7

RB7 = input RB7 = output input

Reset Program/Verify Test Mode

FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

VIHH
MCLR
tdly2
Next Command
1µs min.
1 2 3 4 5 6 1 2
RB6
(CLOCK)

RB7
0 1 1 0 X X X 0
(DATA)
tset1 tdly1
thld1 1µs min.
}
}

100ns min.

Reset Program/Verify Test Mode

 2000 Microchip Technology Inc. Preliminary DS30034A-page 3-147

PIC16F62X
NOTES:

DS30034A-page 3-148 Preliminary  2000 Microchip Technology Inc.

PIC16F8X
In-Circuit Serial Programming for PIC16F8X FLASH MCUs

This document includes the programming Pin Diagram

specifications for the following devices:
• PIC16F83 PDIP, SOIC
• PIC16CR83
RA2 •1 18 RA1
• PIC16F84 RA3 2 17 RA0

PIC16F8X
• PIC16CR84 RA4/T0CKI 3 16 OSC1/CLKIN
MCLR 4 15 OSC2/CLKOUT
• PIC16F84A VSS 5 14 VDD
RB0/INT 6 13 RB7
• PIC16F877 RB1 7 12 RB6
RB2 8 11 RB5
RB3 9 10 RB4
1.0 PROGRAMMING THE PIC16F8X
The PIC16F8X is programmed using a serial method.
The serial mode will allow the PIC16F8X to be pro- MCLR/VPP 1 40 RB7
grammed while in the users system. This allows for RA0/AN0 2 39 RB6
increased design flexibility. This programming specifi- RA1/AN1 3 38 RB5
RA2/AN2/VREF 4 37 RB4
cation applies to PIC16F8X devices in all packages.
RA3/AN3/VREF 5 36 RB3
RA4/T0CKI 6 35 RB2
1.1 Hardware Requirements RA5/AN4/SS 7 34 RB1

PIC16F877
RE0/RD/AN5 8 33 RB0/INT
The PIC16F8X requires one programmable power sup- RE1/WR/AN6 9 32 VDD
ply for VDD (4.5V to 5.5V) and a VPP of 12V to 14V. Both RE2/CS/AN7 10 31 VSS
supplies should have a minimum resolution of 0.25V. VDD 11 30 RD7/PSP7
VSS 12 29 RD6/PSP6
1.2 Programming Mode OSC1/CLKIN 13 28 RD5/PSP5
OSC2/CLKOUT 14 27 RD4/PSP4

The programming mode for the PIC16F8X allows pro- RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
RC1/T1OSI/CCP2 16 25 RC6/TX/CK
gramming of user program memory, data memory, spe- RC2/CCP1 RC5/SDO
17 24
cial locations used for ID, and the configuration word. RC3/SCK/SCL 18 23 RC4/SDI/SDA
RD0/PSP0 19 22 RD3/PSP3
RD1/PSP1 20 21 RD2/PSP2

PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F8X

During Programming

Pin Name Function Pin Type Pin Description

RB6 CLOCK I Clock input
RB7 DATA I/O Data input/output
MCLR VTEST MODE P* Program Mode Select
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
*In the PIC16F8X, the programming high voltage is internally generated. To activate the programming mode, high voltage needs to
be applied to MCLR input. Since the MCLR is used for a level source, this means that MCLR does not draw any significant current.

 2000 Microchip Technology Inc. DS30262C-page 3-149

PIC16F8X
2.0 PROGRAM MODE ENTRY 2.2 ID Locations

2.1 User Program Memory Map A user may store identification information (ID) in four
ID locations. The ID locations are mapped in [0x2000 :
The user memory space extends from 0x0000 to 0x2003]. It is recommended that the user use only the
0x1FFF (8K), of which 1K (0x0000 - 0x03FF) is physi- four least significant bits of each ID location. In some
cally implemented. In actual implementation the on- devices, the ID locations read-out in an unscrambled
chip user program memory is accessed by the lower fashion after code protection is enabled. For these
10-bits of the PC, with the upper 3-bits of the PC devices, it is recommended that ID location is written as
ignored. Therefore if the PC is greater than 0x3FF, it will “11 1111 1000 bbbb” where ‘bbbb’ is ID information.
wrap around and address a location within the physi- In other devices, the ID locations read out normally,
cally implemented memory. (See Figure 2-1). even after code protection. To understand how the
In programming mode the program memory space devices behave, refer to Table 4-2.
extends from 0x0000 to 0x3FFF, with the first half To understand the scrambling mechanism after code
(0x0000-0x1FFF) being user program memory and the protection, refer to Section 4.0.
second half (0x2000-0x3FFF) being configuration
memory. The PC will increment from 0x0000 to 0x1FFF
and wrap to 0x000 or 0x2000 to 0x3FFF and wrap
around to 0x2000 (not to 0x0000). Once in configura-
tion memory, the highest bit of the PC stays a ‘1’, thus
always pointing to the configuration memory. The only
way to point to user program memory is to reset the
part and reenter program/verify mode as described in
Section 2.3.
In the configuration memory space, 0x2000-0x200F
are physically implemented. However, only locations
0x2000 through 0x2007 are available. Other locations
are reserved. Locations beyond 0x200F will physically
access user memory. (See Figure 2-1).

DS30262C-page 3-150  2000 Microchip Technology Inc.

PIC16F8X
FIGURE 2-1: PROGRAM MEMORY MAPPING
0.5 KW 1 KW 8 KW
0
Implemented
1FF Implemented
3FF
400

Not Implemented Not Implemented Implemented

1FFF
2000
Implemented Implemented Implemented

ID Location 2008
2000

ID Location
2001

ID Location
2002

ID Location
2003

Reserved Not Implemented Not Implemented Not Implemented

2004

Reserved
2005

Reserved
2006

Configuration Word
2007
3FFF

 2000 Microchip Technology Inc. DS30262C-page 3-151

PIC16F8X
2.3 Program/Verify Mode Therefore, during a read operation the LSB will be
transmitted onto pin RB7 on the rising edge of the sec-
The program/verify mode is entered by holding pins ond cycle, and during a load operation the LSB will be
RB6 and RB7 low while raising MCLR pin from VIL to latched on the falling edge of the second cycle. A min-
VIHH (high voltage). Once in this mode the user pro- imum 1µs delay is also specified between consecutive
gram memory and the configuration memory can be commands.
accessed and programmed in serial fashion. The mode
All commands are transmitted LSB first. Data words
of operation is serial, and the memory that is accessed
are also transmitted LSB first. The data is transmitted
is the user program memory. RB6 and RB7 are Schmitt
on the rising edge and latched on the falling edge of
Trigger Inputs in this mode.
the clock. To allow for decoding of commands and
Note: The OSC must not have 72 osc clocks reversal of data pin configuration, a time separation of
while the device MCLR is between VIL and at least 1 µs is required between a command and a
VIHH. data word (or another command).
The sequence that enters the device into the program- The commands that are available are:
ming/verify mode places all other logic into the reset
state (the MCLR pin was initially at VIL). This means 2.3.1.1 LOAD CONFIGURATION
that all I/O are in the reset state (High impedance
After receiving this command, the program counter
inputs).
(PC) will be set to 0x2000. By then applying 16 cycles
The normal sequence for programming is to use the to the clock pin, the chip will load 14-bits in a “data
load data command to set a value to be written at the word,” as described above, to be programmed into the
selected address. Issue the begin programming com- configuration memory. A description of the memory
mand followed by read data command to verify, and mapping schemes of the program memory for normal
then increment the address. operation and configuration mode operation is shown
in Figure 2-1. After the configuration memory is
2.3.1 SERIAL PROGRAM/VERIFY OPERATION entered, the only way to get back to the user program
The RB6 pin is used as a clock input pin, and the RB7 memory is to exit the program/verify test mode by tak-
pin is used for entering command bits and data input/ ing MCLR low (VIL).
output during serial operation. To input a command, the
clock pin (RB6) is cycled six times. Each command bit
is latched on the falling edge of the clock with the least
significant bit (LSB) of the command being input first.
The data on pin RB7 is required to have a minimum
setup and hold time (see AC/DC specifications) with
respect to the falling edge of the clock. Commands that
have data associated with them (read and load) are
specified to have a minimum delay of 1 µs between the
command and the data. After this delay, the clock pin is
cycled 16 times with the first cycle being a start bit and
the last cycle being a stop bit. Data is also input and
output LSB first.

DS30262C-page 3-152  2000 Microchip Technology Inc.

PIC16F8X
2.3.1.2 LOAD DATA FOR PROGRAM MEMORY

After receiving this command, the chip will load in a

14-bit “data word” when 16 cycles are applied, as
described previously. A timing diagram for the load data
command is shown in Figure 5-1.

TABLE 2-1: COMMAND MAPPING FOR PIC16F83/CR83/F84/CR84

Command Mapping (MSB … LSB) Data
Load Configuration 0 0 0 0 0 0 0, data (14), 0
Load Data for Program Memory 0 0 0 0 1 0 0, data (14), 0
Read Data from Program Memory 0 0 0 1 0 0 0, data (14), 0
Increment Address 0 0 0 1 1 0
Begin Programming 0 0 1 0 0 0
Load Data for Data Memory 0 0 0 0 1 1 0, data (14), 0
Read Data from Data Memory 0 0 0 1 0 1 0, data (14), 0
Bulk Erase Program Memory 0 0 1 0 0 1
Bulk Erase Data Memory 0 0 1 0 1 1

TABLE 2-2: COMMAND MAPPING FOR PIC16F84A/PIC16F877

 2000 Microchip Technology Inc. DS30262C-page 3-153

PIC16F8X
FIGURE 2-2: PROGRAM FLOW CHART - PIC16F8X PROGRAM MEMORY

Start

Set VDD = VDDP

Program Cycle

PROGRAM CYCLE

Read Data
Command Load Data
Command

No Report
Data Correct? Programming Begin
Failure Programming
Command

Increment No All Locations

Address
Done?
Command Wait 10 ms

Verify all
Locations @
VDDMIN

Report Verify No
Error @ Data Correct?
VDDMIN

Verify all
Locations @
VDDMAX

Report Verify No
Error @ Data Correct?
VDDMAX

Done

DS30262C-page 3-154  2000 Microchip Technology Inc.

PIC16F8X
FIGURE 2-3: PROGRAM FLOW CHART - PIC16F8X CONFIGURATION MEMORY

Start

Load
Configuration
Data

No Program ID Yes Read Data

Location? Program Cycle Command

Increment Report No
Address Programming Data Correct?
Command Failure

Yes

No Address =
0x2004?

Yes

Increment
Address
Command

Increment Program
Set VDD =
Address Cycle
VDDMAX
Command (Config. Word)

Report Program No Read Data

Configuration Data Correct? Command
Word Error

Yes

Set VDD =
VDDMAX

Yes Read Data

Done Data Correct? Command

 2000 Microchip Technology Inc. DS30262C-page 3-155

PIC16F8X
2.3.1.3 LOAD DATA FOR DATA MEMORY 2.3.1.8 BEGIN PROGRAMMING

After receiving this command, the chip will transmit 2.3.1.9 BULK ERASE PROGRAM MEMORY
data bits out of the program memory (user or configu- After this command is performed, the next program
ration) currently accessed starting with the second ris- command will erase the entire program memory.
ing edge of the clock input. The RB7 pin will go into
output mode on the second rising clock edge, and it will To perform a bulk erase of the program memory, the fol-
revert back to input mode (hi-impedance) after the 16th lowing sequence must be performed.
rising edge. A timing diagram of this command is 1. Do a “Load Data All 1’s” command.
shown in Figure 5-2. 2. Do a “Bulk Erase User Memory” command.
2.3.1.5 READ DATA FROM DATA MEMORY 3. Do a “Begin Programming” command.
4. Wait 10 ms to complete bulk erase.
After receiving this command, the chip will transmit
If the address is pointing to the test program memory
data bits out of the data memory starting with the sec-
(0x2000 - 0x200F), then both the user memory and the
ond rising edge of the clock input. The RB7 pin will go
test memory will be erased. The configuration word will
into output mode on the second rising edge, and it will
not be erased, even if the address is pointing to location
revert back to input mode (hi-impedance) after the 16th
0x2007
rising edge. As previously stated, the data memory is 8-
bits wide, and therefore, only the first 8-bits that are out- For PIC16F84 perform the following commands:
put are actual data. 1. Issue Command 2 (write program memory).
2.3.1.6 INCREMENT ADDRESS 2. Send out 3FFFH data.
3. Issue Command 1 (toggle select even rows).
The PC is incremented when this command is 4. Issue Command 7 (toggle select even rows).
received. A timing diagram of this command is shown
5. Issue Command 8 (begin programming)
in Figure 5-3.
6. Delay 10 ms
2.3.1.7 BEGIN ERASE/PROGRAM CYCLE 7. Issue Command 1 (toggle select even rows).
A load command must be given before every begin 8. Issue Command 7 (toggle select even rows).
programming command. Programming of the appro- Note: If the device is code-protected
priate memory (test program memory, user program (PIC16F84A), the BULK ERASE com-
memory or data memory) will begin after this command mand will not work.
is received and decoded. An internal timing mechanism
executes an erase before write. The user must allow for
both erase and programming cycle times for program-
ming to complete. No “end programming” command is
required.

DS30262C-page 3-156  2000 Microchip Technology Inc.

PIC16F8X
2.3.1.10 BULK ERASE DATA MEMORY 2.4 Programming Algorithm Requires
Variable VDD
To perform a bulk erase of the data memory, the follow-
ing sequence must be performed. The PIC16F8X uses an intelligent algorithm. The algo-
1. Do a “Load Data All 1’s” command. rithm calls for program verification at VDDmin. as well
2. Do a “Bulk Erase Data Memory” command. as VDDmax. Verification at VDDmin. guarantees good
“erase margin”. Verification at VDDmax guarantees
3. Do a “Begin Programming” command.
good “program margin”.
4. Wait 10 ms to complete bulk erase.
The actual programming must be done with VDD in the
For PIC16F84 perform the data memory). VDDP range (See Table 5-1).
5. Send out 3FFFH data. VDDP = VCC range required during programming.
6. Issue Command 1 (toggle select even rows).
VDDmin. = minimum operating VDD spec for the part.
7. Issue Command 7 (toggle select even rows).
VDDmax.= maximum operating VDD spec for the part.
8. Issue Command 8 (begin data)
9. Delay 10 ms Programmers must verify the PIC16F8X at its specified
VDD max. and VDDmin levels. Since Microchip may
10. Issue Command 1 (toggle select even rows).
introduce future versions of the PIC16F8X with a
Issue Command 7 (toggle select even rows). broader VDD range, it is best that these levels are user
selectable (defaults are ok).
Note: All BULK ERASE operations must take
place at 4.5 to 5.5 VDD range. Note: Any programmer not meeting these
requirements may only be classified as
“prototype” or “development” programmer
but not a “production” quality programmer.

 2000 Microchip Technology Inc. DS30262C-page 3-157

PIC16F8X
3.0 CONFIGURATION WORD 3.1 Device ID Word
The PIC16F8X has five configuration bits. These bits The device ID word for the PIC16F8XX is located at
can be set (reads ‘0’) or left unchanged (reads ‘1’) to 2006h.
select various device configurations.
TABLE 3-1:
Device ID Value
Device
Dev Rev
PIC16F84A 00 0101 010 0 0000
PIC16F877 00 1001 101 0 0000

FIGURE 3-1: CONFIGURATION WORD BIT MAP FOR PIC16F83/CR83/F84/CR84/F84A

Bit 6 5 4 3 2 1 0
Number:
13 12 11 10 9 8 7
PIC16F83/ CP CP CP CP CP PWRTE WDTE FOSC1 FOSC0
CP CP CP CP CP
F84/F84A
PIC16CR83/ CP CP CP CP CP PWRTE WDTE FOSC1 FOSC0
CP CP DP CP CP
CR84
bit 4-13: CP, Code Protection Configuration Bits
1 = code protection off
0 = code protection on
bit 7: PIC16CR83/CR84 only
DP, Data Memory Code Protection Bit
1 = code protection off
0 = data memory is code protected
bit 3: PWRTE, Power Up Timer Enable Configuration Bit
1 = Power up timer disabled
0 = Power up timer enabled
bit 2: WDTE, WDT Enable Configuration Bits
1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC<1:0>, Oscillator Selection Configuration Bits
11: RC oscillator
10: HS oscillator
01: XT oscillator
00: LP oscillator

DS30262C-page 3-158  2000 Microchip Technology Inc.

PIC16F8X
FIGURE 3-2: CONFIGURATION WORD FOR PIC16F877

CP1 CP0 BKBUG - WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 Register: CONFIG
bit13 bit0 Address 2007h

bit 13-12:
bit 11: BKBUG: Background Debugger Mode (This bit documented as reserved in data sheet)
1 = Background debugger functions not enabled
0 = Background debugger functional.
bit 5-4: CP1:CP0: Flash Program Memory Code Protection bits (2)
11 = Code protection off
10 = 1F00h to 1FFFh code protected
01 = 1000h to 1FFFh code protected
00 = 0000h to 1FFFh code protected
bit 11: Reserved: Set to ‘1’ for normal operation
bit 10: Unimplemented: Read as ‘1’
bit 9: WRT: Flash Program Memory Write Enable
1 = Unprotected program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8: CPD: Data EE Memory Code Protection
1 = Code protection off
0 = Data EE memory code protected
bit 7: LVP: Low voltage programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator

 2000 Microchip Technology Inc. DS30262C-page 3-159

PIC16F8X
4.0 CODE PROTECTION Procedure to disable code protect:
For PIC16F8X devices, once code protection is a) Execute load configuration (with a ‘1’ in bit 4,
enabled, all program memory locations read all 0’s. code protect).
The ID locations and the configuration word read out in b) Increment to configuration word location
an unscrambled fashion. Further programming is dis- (0x2007)
abled for the entire program memory as well as data c) Execute command (000001)
memory. It is possible to program the ID locations and d) Execute command (000111)
the configuration word.
e) Execute ‘Begin Programming’ (001000)
4.1 Disabling Code-Protection f) Wait 10 ms
g) Execute command (000001)
It is recommended that the following procedure be per-
h) Execute command (000111)
formed before any other programming is attempted. It
is also possible to turn code protection off (code protect
bit = 1) using this procedure; however, all data within
the program memory and the data memory will be
erased when this procedure is executed, and thus,
the security of the data or code is not compro-
mised.

4.2 Embedding Configuration Word and ID Information in the Hex File

To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex
file when loading the hex file. If configuration word information was not present in the hex file then a simple warning
message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included.
An option to not include this information may be provided.
Specifically for the PIC16F8X, the EEPROM data memory should also be embedded in the hex file (see Section 5.1).
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.

TABLE 4-1: CONFIGURATION WORD

PIC16F83
To code protect: 0000000000XXXX

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

Configuration Word (0x2007) Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled
All memory Read All 0’s, Write Disabled Read Unscrambled, Write Enabled
ID Locations [0x2000 : 0x2003] Read Unscrambled, Write Enabled Read Unscrambled, Write Enabled

PIC16CR83
To code protect: 0000000000XXXX

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

Configuration Word (0x2007) Read Unscrambled Read Unscrambled
All memory Read All 0’s for Program Memory, Read Unscrambled, Data Memory -
Read All 1’s for Data Memory - Write Enabled
Write Disabled
ID Locations [0x2000 : 0x2003] Read Unscrambled Read Unscrambled

DS30262C-page 3-160  2000 Microchip Technology Inc.

PIC16F8X
PIC16CR84
To code protect: 0000000000XXXX

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

PIC16F84A
To code protect: 0000000000XXXX

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

PIC16F8XX
To code protect: 00X1XXXX00XXXX

Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode

Legend: X = Don’t care

 2000 Microchip Technology Inc. DS30262C-page 3-161

PIC16F8X
4.3 CHECKSUM COMPUTATION The least significant 16 bits of this sum is the check-
sum.
4.3.1 CHECKSUM
The following table describes how to calculate the
Checksum is calculated by reading the contents of the checksum for each device. Note that the checksum cal-
PIC16F8X memory locations and adding up the culation differs depending on the code protect setting.
opcodes up to the maximum user addressable location, Since the program memory locations read out differ-
e.g., 0x1FF for the PIC16F8X. Any carry bits exceeding ently depending on the code protect setting, the table
16-bits are neglected. Finally, the configuration word describes how to manipulate the actual program mem-
(appropriately masked) is added to the checksum. ory values to simulate the values that would be read
Checksum computation for each member of the from a protected device. When calculating a checksum
PIC16F8X devices is shown in Table 4-2. by reading a device, the entire program memory can
simply be read and summed. The configuration word
The checksum is calculated by summing the following:
and ID locations can always be read.
• The contents of all program memory locations
Note that some older devices have an additional value
• The configuration word, appropriately masked added in the checksum. This is to maintain compatibil-
• Masked ID locations (when applicable) ity with older device programmer checksums.

TABLE 4-2: CHECKSUM COMPUTATION

0x25E6 at 0
Code Blank
Checksum* and max
Device Protect Value
address
PIC16F83 OFF SUM[0x000:0x1FF] + CFGW & 0x3FFF 0x3DFF 0x09CD
ON CFGW & 0x3FFF + SUM_ID 0x3E0E 0x09DC
PIC16CR83 OFF SUM[0x000:0x1FF] + CFGW & 0x3FFF 0x3DFF 0x09CD
ON CFGW & 0x3FFF + SUM_ID 0x3E0E 0x09DC
PIC16F84 OFF SUM[0x000:0x3FF] + CFGW & 0x3FFF 0x3BFF 0x07CD
ON CFGW & 0x3FFF + SUM_ID 0x3C0E 0x07DC
PIC16CR84 OFF SUM[0x000:0x3FF] + CFGW & 0x3FFF 0x3BFF 0x07CD
ON CFGW & 0x3FFF + SUM_ID 0x3C0E 0x07DC
PIC16F84A OFF SUM[0x000:0x3FF] + CFGW & 0x3FFF 0x3BFF 0x07CD
ON CFGW & 0x3FFF + SUM_ID 0x3C0E 0x07DC
PIC16F877 OFF SUM[0x0000:0x1FFF] + CFGW & 0x3BFF 0x1BFF 0xE7CD
0X1F00 SUM[0x0000:0x1EFF] + CFGW & 0x3BFF +SUM_ID 0x28EE 0xDAA3
–
0X1FFF
0x1000 SUM[0x0000:0x0FFF] + CFGW & 0x3BFF + SUM_ID 0x27DE 0xD993
–
0x1FFF
ALL CFGW & 0x3BFF + SUM_ID 0x27CE 0xF39C
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND

DS30262C-page 3-162  2000 Microchip Technology Inc.

PIC16F8X
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
5.1 Embedding Data EEPROM Contents in Hex File
The programmer should be able to read data EEPROM information from a hex file and conversely (as an option) write
data EEPROM contents to a hex file along with program memory information and fuse information.
The 64 data memory locations are logically mapped starting at address 0x2100. The format for data memory storage
is one data byte per address location, LSB aligned.

TABLE 5-1: AC/DC CHARACTERISTICS

TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +40°C, unless otherwise stated, (25°C is recommended)
Operating Voltage: 4.5V ≤ VDD ≤ 5.5V, unless otherwise stated.

Paramet
Conditions/
er Sym. Characteristic Min. Typ. Max. Units
Comments
No.
VDDP Supply voltage during programming 4.5 5.0 5.5 V
VDDV Supply voltage during verify VDDmin VDDmax V Note 1
VIHH High voltage on MCLR for test mode 12 14.0 V Note 2
entry
IDDP Supply current (from VDD) during 50 mA
program/verify
IHH Supply current from VIHH (on MCLR) 200 µA
VIH1 (RB6, RB7) input high level 0.8 VDD V Schmitt Trigger input
VIL1 (RB6, RB7) input low level MCLR 0.2 VDD V Schmitt Trigger input
(test mode selection)
P1 TvHHR MCLR rise time (VSS to VHH) for test 8.0 µs
mode entry
P2 Tset0 RB6, RB7 setup time (before pattern 100 ns
setup time)
P3 Tset1 Data in setup time before clock ↓ 100 ns
P4 Thld1 Data in hold time after clock ↓ 100 ns
P5 Tdly1 Data input not driven to next clock 1.0 µs
input (delay required between com-
mand/data or command/command)
P6 Tdly2 Delay between clock ↓ to clock ↑ of 1.0 µs
next command or data
P7 Tdly3 Clock to data out valid (during read 80 ns
data)
P8 Thld0 RB <7:6> hold time after MCLR ↑ 100 ns
- - Erase cycle time - - 10 ms
- - Program cycle time - - 10 ms
Note 1: Program must be verified at the minimum and maximum VDD limits for the part.
Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.

 2000 Microchip Technology Inc. DS30262C-page 3-163

PIC16F8X
FIGURE 5-1: LOAD DATA COMMAND (PROGRAM/VERIFY)
VIHH
MCLR
100ns P6
P2
1 2 3 4 5 6 1µs min. 1 2 3 4 5 15
RB6 P8
(CLOCK)
100ns
RB7 0 0 0 0
(DATA) 1 0 0 0
P5
P3
P4
P4 1µs min. P3

}
}
}

}
100ns 100ns
min. min.
Program/Verify Test Mode
Reset

FIGURE 5-2: READ DATA COMMAND (PROGRAM/VERIFY)

VIHH
MCLR 100ns P6
P2
1 2 3 4 5 6 1µs min. 1 2 3 4 5 15
RB6 P8
(CLOCK)
100ns P7
RB7 0 0 1 0 0 0
(DATA) P5
P4
P3 1µs min.
}
}

100ns
min. RB7
RB7 = output input

Program/Verify Test Mode

Reset

FIGURE 5-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)

VIHH
MCLR
P6
Next Command
1µs min.
1 2 3 4 5 6 1 2
RB6
(CLOCK)

RB7
0 1 1 0 0 0 0 0
(DATA)
P5
P3 P4 1µs min.
}
}

100ns
min
Program/Verify Test Mode
Reset

DS30262C-page 3-164  2000 Microchip Technology Inc.

PIC16F8XX
In-Circuit Serial Programming for PIC16F8XX FLASH MCUs

This document includes the programming Pin Diagram

specifications for the following devices:
PDIP, SOIC
• PIC16F870 • PIC16F874
MCLR/VPP 1 28 RB7
• PIC16F871 • PIC16F876 RA0/AN0 2 27 RB6

PIC16F876/873/872/870
RA1/AN1 3 26 RB5
• PIC16F872 • PIC16F877 RA2/AN2/VREF 4 25 RB4
RA3/AN3/VREF 5 24 RB3
• PIC16F873 RA4/T0CKI 6 23 RB2
RA5/AN4/SS 7 22 RB1
VSS 8 21 RB0/INT

1.0 PROGRAMMING THE OSC1/CLKIN

OSC2/CLKOUT
9
10
20
19
VDD
VSS
PIC16F8XX RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
11
12
18
17
RC7/RX/DT
RC6/TX/CK
RC2/CCP1 13 16 RC5/SDO
The PIC16F8XX is programmed using a serial method. RC4/SDI/SDA
RC3/SCK/SCL 14 15
The serial mode will allow the PIC16F8XX to be pro-
grammed while in the users system. This allows for
increased design flexibility. This programming specifi- MCLR/VPP 1 40 RB7
cation applies to PIC16F8XX devices in all packages. RA0/AN0 2 39 RB6
RA1/AN1 3 38 RB5
PIC16F8XX devices may be programmed using a sin- RA2/AN2/VREF 4 37 RB4
gle +5 volt supply (low voltage programming mode). RA3/AN3/VREF 5 36 RB3
RA4/T0CKI 6 35 RB2
1.1 Hardware Requirements RA5/AN4/SS 7 34 RB1

PIC16F877/874/871
RE0/RD/AN5 8 33 RB0/INT
The PIC16F8XX requires one programmable power RE1/WR/AN6 9 32 VDD
RE2/CS/AN7 10 31 VSS
supply for VDD (4.5V to 5.5V) and a VPP of 12V to 14V VDD 11 30 RD7/PSP7
or VPP of (4.5V to 5.5V) when using low voltage In-Cir- VSS 12 29 RD6/PSP6
cuit Serial Programming™ (ICSP™). Both supplies OSC1/CLKIN 13 28 RD5/PSP5
should have a minimum resolution of 0.25V. OSC2/CLKOUT 14 27 RD4/PSP4
RC0/T1OSO/T1CKI 15 26 RC7/RX/DT
1.2 Programming Mode RC1/T1OSI/CCP2 16 25 RC6/TX/CK
RC2/CCP1 17 24 RC5/SDO
RC3/SCK/SCL 18 23 RC4/SDI/SDA
The programming mode for the PIC16F8XX allows pro-
RD0/PSP0 19 22 RD3/PSP3
gramming of user program memory, data memory, spe- RD1/PSP1 20 21 RD2/PSP2
cial locations used for ID, and the configuration word.

PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F8XX

During Programming
Pin Name
Function Pin Type Pin Description
RB3 PGM I Low voltage ICSP programming input if
configuration bit equals 1
RB6 CLOCK I Clock input
RB7 DATA I/O Data input/output
MCLR VTEST MODE P* Program Mode Select
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
*In the PIC16F8XX, the programming high voltage is internally generated. To activate the programming mode, high voltage needs
to be applied to MCLR input. Since the MCLR is used for a level source, this means that MCLR does not draw any significant current.

In-circuit Serial Programming (ICSP) is a trademark of Microchip Technology Inc.

 2000 Microchip Technology Inc. DS39025D-page 3-165

PIC16F8XX
2.0 PROGRAM MODE ENTRY
2.1 User Program Memory Map
The user memory space extends from 0x0000 to
0x1FFF (8K). In programming mode the program mem-
ory space extends from 0x0000 to 0x3FFF, with the first
half (0x0000-0x1FFF) being user program memory and
the second half (0x2000-0x3FFF) being configuration
memory. The PC will increment from 0x0000 to 0x1FFF
and wrap to 0x000, 0x2000 to 0x3FFF and wrap
around to 0x2000 (not to 0x0000). Once in configura-
tion memory, the highest bit of the PC stays a ‘1’, thus
always pointing to the configuration memory. The only
way to point to user program memory is to reset the
part and reenter program/verify mode as described in
Section 2.3.
In the configuration memory space, 0x2000-0x200F
are physically implemented. However, only locations
0x2000 through 0x2007 are available. Other locations
are reserved. Locations beyond 0x200F will physically
access user memory. (See Figure 2-1).

2.2 ID Locations
A user may store identification information (ID) in four
ID locations. The ID locations are mapped in [0x2000 :
0x2003]. It is recommended that the user use only the
four least significant bits of each ID location. In some
devices, the ID locations read-out in an unscrambled
fashion after code protection is enabled. For these
devices, it is recommended that ID location is written as
“11 1111 1000 bbbb” where ‘bbbb’ is ID information.
In other devices, the ID locations read out normally,
even after code protection. To understand how the
devices behave, refer to Table 4-1.
To understand the scrambling mechanism after code
protection, refer to Section 4.0.

DS39025D-page 3-166  2000 Microchip Technology Inc.

PIC16F8XX
FIGURE 2-1: PROGRAM MEMORY MAPPING

2K 4K 8K
words words words
2000h ID Location 0h
1FFh Implemented Implemented Implemented
3FFh
2001h ID Location
400h
Implemented Implemented Implemented
7FFh
2002h ID Location
800h
Implemented Implemented
BFFh
2003h ID Location
C00h
Implemented Implemented
FFFh
2004h Reserved
1000h
Reserved Implemented
2005h Reserved
Reserved Implemented
2006h Device ID
Implemented
2007h Configuration Word
Implemented
1FFFh

2008h
Reserved Reserved Reserved

2100h

Reserved Reserved Reserved

3FFFh

 2000 Microchip Technology Inc. DS39025D-page 3-167

PIC16F8XX
2.3 Program/Verify Mode 2.3.2 SERIAL PROGRAM/VERIFY OPERATION

The program/verify mode is entered by holding pins The RB6 pin is used as a clock input pin, and the RB7
RB6 and RB7 low while raising MCLR pin from VIL to pin is used for entering command bits and data input/
VIHH (high voltage). In this mode, the state of the RB3 output during serial operation. To input a command, the
pin does not effect programming. Low-voltage ICSP clock pin (RB6) is cycled six times. Each command bit
programming mode is entered by applying VDD to is latched on the falling edge of the clock with the least
MCLR and raising RB3 from VIL to VDD. Once in this significant bit (LSB) of the command being input first.
mode the user program memory and the configuration The data on pin RB7 is required to have a minimum
memory can be accessed and programmed in serial setup and hold time (see AC/DC specifications) with
fashion. The mode of operation is serial, and the mem- respect to the falling edge of the clock. Commands that
ory that is accessed is the user program memory. RB6 have data associated with them (read and load) are
and RB7 are Schmitt Trigger Inputs in this mode. specified to have a minimum delay of 1 µs between the
command and the data. After this delay, the clock pin is
Note: The OSC must not have 72 osc clocks cycled 16 times with the first cycle being a start bit and
while the device MCLR is between VIL and the last cycle being a stop bit. Data is also input and
VIHH. output LSB first.
The sequence that enters the device into the program- Therefore, during a read operation the LSB will be
ming/verify mode places all other logic into the reset transmitted onto pin RB7 on the rising edge of the sec-
state (the MCLR pin was initially at VIL). This means ond cycle, and during a load operation the LSB will be
that all I/O are in the reset state (High impedance latched on the falling edge of the second cycle. A min-
inputs). imum 1µs delay is also specified between consecutive
The normal sequence for programming is to use the commands.
load data command to set a value to be written at the All commands are transmitted LSB first. Data words
selected address. Issue the begin programming com- are also transmitted LSB first. The data is transmitted
mand followed by read data command to verify, and on the rising edge and latched on the falling edge of
then increment the address. the clock. To allow for decoding of commands and
A device reset will clear the PC and set the address to reversal of data pin configuration, a time separation of
0. The “increment address” command will increment at least 1 µs is required between a command and a
the PC. The “load configuration” command will se the data word (or another command).
PC to 0x2000. The available commands are shown in The commands that are available are:
Table 2-1.
2.3.2.1 LOAD CONFIGURATION
2.3.1 LOW-VOLTAGE ICSP PROGRAMMING
MODE After receiving this command, the program counter
(PC) will be set to 0x2000. By then applying 16 cycles
When LVP bit is set to ‘1’, the low-voltage ICSP pro- to the clock pin, the chip will load 14-bits in a “data
gramming entry is enabled. Since the LVP configura- word,” as described above, to be programmed into the
tion bit allows low voltage ICSP programming entry in configuration memory. A description of the memory
its erased state, an erased device will have the LVP bit mapping schemes of the program memory for normal
enabled at the factory. While LVP is ‘1’, RB3 is dedi- operation and configuration mode operation is shown
cated to low voltage ICSP programming. Bring MCLR in Figure 2-1. After the configuration memory is
to VDD and then RB3 to VDD to enter programming entered, the only way to get back to the user program
mode. All other specifications for high-voltage ICSP™ memory is to exit the program/verify test mode by tak-
apply. ing MCLR low (VIL).
To disable low voltage ICSP mode, the LVP bit must be
programmed to ‘0’. This must be done while entered
with high voltage entry mode (LVP bit= 1). RB3 is now
a general purpose I/O pin.

DS39025D-page 3-168  2000 Microchip Technology Inc.

PIC16F8XX
2.3.2.2 LOAD DATA FOR PROGRAM MEMORY

After receiving this command, the chip will load in a

14-bit “data word” when 16 cycles are applied, as
described previously. A timing diagram for the load data
command is shown in Figure 5-1.

TABLE 2-1: COMMAND MAPPING FOR PIC16F84A/PIC16F877

 2000 Microchip Technology Inc. DS39025D-page 3-169

PIC16F8XX
FIGURE 2-2: PROGRAM FLOW CHART - PIC16F8XX PROGRAM MEMORY

Start

Set VDD = VDDP

Program Cycle

PROGRAM CYCLE

Read Data
Command Load Data
Command

No Report
Data Correct? Programming Begin
Failure Programming
Command

Increment No All Locations

Address
Done?
Command Wait tprog

Verify all
Locations @
VDDMIN

Report Verify No
Error @ Data Correct?
VDDMIN

Verify all
Locations @
VDDMAX

Report Verify No
Error @ Data Correct?
VDDMAX

Done

DS39025D-page 3-170  2000 Microchip Technology Inc.

PIC16F8XX
FIGURE 2-3: PROGRAM FLOW CHART - PIC16F8XX CONFIGURATION MEMORY

Start

Load
Configuration
Data

No Program ID Yes Read Data

Location? Program Cycle Command

Increment Report No
Address Programming Data Correct?
Command Failure

Yes

No Address =
0x2004?

Yes

Increment
Address
Command

Increment Program
Set VDD =
Address Cycle
VDDMAX
Command (Config. Word)

Report Program No Read Data

Configutation Data Correct? Command
Word Error

Yes

Set VDD =
VDDMAX

Yes Read Data

Done Data Correct? Command

 2000 Microchip Technology Inc. DS39025D-page 3-171

PIC16F8XX
2.3.2.3 LOAD DATA FOR DATA MEMORY 2.3.2.8 BEGIN PROGRAMMING

After receiving this command, the chip will load in a 14- A load command must be given before every begin
bit “data word” when 16 cycles are applied. However, programming command. Programming of the appro-
the data memory is only 8-bits wide, and thus only the priate memory (test program memory, user program
first 8-bits of data after the start bit will be programmed memory or data memory) will begin after this command
into the data memory. It is still necessary to cycle the is received and decoded. An internal timing mechanism
clock the full 16 cycles in order to allow the internal cir- executes a write. The user must allow for program cycle
cuitry to reset properly. The data memory contains 64 time for programming to complete. No “end program-
words. Only the lower 8-bits of the PC are decoded by ming” command is required.
the data memory, and therefore if the PC is greater than This command is similar to the ERASE/PROGRAM
0x3F, it will wrap around and address a location within CYCLE command, except that a word erase is not
the physically implemented memory. If the device is done. It is recommended that a bulk erase be per-
code protected, the data is read as all zeros. formed before starting a series of programming only
2.3.2.4 READ DATA FROM PROGRAM cycles.
MEMORY 2.3.2.9 BULK ERASE PROGRAM MEMORY
After receiving this command, the chip will transmit After this command is performed, the next program
data bits out of the program memory (user or configu- command will erase the entire program memory.
ration) currently accessed starting with the second ris-
ing edge of the clock input. The RB7 pin will go into To perform a bulk erase of the program memory, the fol-
output mode on the second rising clock edge, and it will lowing sequence must be performed.
revert back to input mode (hi-impedance) after the 16th 1. Do a “Load Data All 1’s” command.
rising edge. A timing diagram of this command is 2. Do a “Bulk Erase Program Memory” command.
shown in Figure 5-2.
3. Do a “Begin Programming” command.
2.3.2.5 READ DATA FROM DATA MEMORY 4. Wait 10 ms to complete bulk erase.
If the address is pointing to the test program memory
After receiving this command, the chip will transmit
(0x2000 - 0x200F), then both the user memory and the
data bits out of the data memory starting with the sec-
test memory will be erased. The configuration word will
ond rising edge of the clock input. The RB7 pin will go
not be erased, even if the address is pointing to location
into output mode on the second rising edge, and it will
0x2007.
revert back to input mode (hi-impedance) after the 16th
rising edge. As previously stated, the data memory is 8- Note: If the device is code-protected, the BULK
bits wide, and therefore, only the first 8-bits that are out- ERASE command will not work.
put are actual data.
2.3.2.10 BULK ERASE DATA MEMORY
2.3.2.6 INCREMENT ADDRESS
To perform a bulk erase of the data memory, the follow-
The PC is incremented when this command is ing sequence must be performed.
received. A timing diagram of this command is shown
1. Do a “Load Data All 1’s” command.
in Figure 5-3.
2. Do a “Bulk Erase Data Memory” command.
2.3.2.7 BEGIN ERASE/PROGRAM CYCLE 3. Do a “Begin Programming” command.
4. Wait 10 ms to complete bulk erase.
A load command must be given before every begin
programming command. Programming of the appro-
priate memory (test program memory, user program
Note: All BULK ERASE operations must take
memory or data memory) will begin after this command
place at 4.5 to 5.5 VDD range.
is received and decoded. An internal timing mechanism
executes an erase before write. The user must allow for
both erase and programming cycle times for program-
ming to complete. No “end programming” command is
required.

DS39025D-page 3-172  2000 Microchip Technology Inc.

PIC16F8XX
2.4 Programming Algorithm Requires
Variable VDD
The PIC16F8XX uses an intelligent algorithm. The
algorithm calls for program verification at VDDmin. as
well as VDDmax. Verification at VDDmin. guarantees
good “erase margin”. Verification at VDDmax guaran-
tees good “program margin”.
The actual programming must be done with VDD in the
VDDP range (See Table 5-1).
VDDP = VCC range required during programming.
VDDmin. = minimum operating VDD spec for the part.
VDDmax.= maximum operating VDD spec for the part.
Programmers must verify the PIC16F8XX at its speci-
fied VDD max. and VDDmin levels. Since Microchip may
introduce future versions of the PIC16F8XX with a
broader VDD range, it is best that these levels are user
selectable (defaults are ok).
Note: Any programmer not meeting these
requirements may only be classified as
“prototype” or “development” programmer
but not a “production” quality programmer.

 2000 Microchip Technology Inc. DS39025D-page 3-173

PIC16F8XX
3.0 CONFIGURATION WORD TABLE 3-1: DEVICE ID VALUE
The PIC16F8XX has several configuration bits. These Device ID Value
bits can be set (reads ‘0’) or left unchanged (reads ‘1’) Device
to select various device configurations. Dev Rev
PIC16F870 00 1101 000 x xxxx
3.1 Device ID Word
PIC16F871 00 1101 001 x xxxx
The device ID word for the PIC16F8XX is located at PIC16F872 00 1000 111 x xxxx
2006h. PIC16F873 00 1001 011 x xxxx
PIC16F874 00 1001 001 x xxxx
PIC16F876 00 1001 111 x xxxx
PIC16F877 00 1001 101 x xxxx

FIGURE 3-1: CONFIGURATION WORD FOR PIC16F873/874/876/877

CP1 CP0 RESV - WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 Register: CONFIG
bit13 bit0 Address 2007h

bit 13-12:
bit 11: Reserved: Set to ‘1’ for normal operation
bit 5-4: CP1:CP0: Flash Program Memory Code Protection bits (2)
4K Devices:
11 = Code protection off
10 = not supported
01 = not supported
00 = 0000h to 0FFFh code protected
8K Devices:
11 = Code protection off
10 = 1F00h to 1FFFh code protected
01 = 1000h to 1FFFh code protected
00 = 0000h to 1FFFh code protected
bit 11: Reserved: Set to ‘1’ for normal operation
bit 10: Unimplemented: Read as ‘1’
bit 9: WRT: Flash Program Memory Write Enable
1 = Unprotected program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8: CPD: Data EE Memory Code Protection
1 = Code protection off
0 = Data EE memory code protected
bit 7: LVP: Low voltage programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator

DS39025D-page 3-174  2000 Microchip Technology Inc.

PIC16F8XX
FIGURE 3-2: CONFIGURATION WORD FOR PIC16F870/871/872

CP1 CP0 RESV - WRT CPD LVP BODEN CP1 CP0 PWRTE WDTE F0SC1 F0SC0 Register: CONFIG
bit13 bit0 Address 2007h

bit 13-12:
bit 5-4: CP1:CP0: Flash Program Memory Code Protection bits (2)
11 = Code protection off
10 = not supported
01 = not supported
00 = 0000h to 07FFh code protected
bit 11: Reserved: Set to ‘1’ for normal operation
bit 10: Unimplemented: Read as ‘1’
bit 9: WRT: Flash Program Memory Write Enable
1 = Unprotected program memory may be written to by EECON control
0 = Unprotected program memory may not be written to by EECON control
bit 8: CPD: Data EE Memory Code Protection
1 = Code protection off
0 = Data EE memory code protected
bit 7: LVP: Low voltage programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3 is digital I/O, HV on MCLR must be used for programming
bit 6: BODEN: Brown-out Reset Enable bit (1)
1 = BOR enabled
0 = BOR disabled
bit 3: PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator

 2000 Microchip Technology Inc. DS39025D-page 3-175

PIC16F8XX
4.0 CODE PROTECTION Procedure to disable code protect:
For PIC16F8XX devices, once code protection is a) Execute load configuration (with a ‘1’ in bit 13-4,
enabled, all program memory locations read all 0’s. code protect).
The ID locations and the configuration word read out in b) Increment to configuration word location
an unscrambled fashion. Further programming is dis- (0x2007)
abled for the entire program memory as well as data c) Execute command (000001)
memory. It is possible to program the ID locations and d) Execute command (000111)
the configuration word.
e) Execute ‘Begin Programming’ (001000)
4.1 Disabling Code-Protection f) Wait 12 ms
g) Execute command (000001)
It is recommended that the following procedure be per-
h) Execute command (000111)
formed before any other programming is attempted. It
is also possible to turn code protection off (code protect
bit = 1) using this procedure; however, all data within
the program memory and the data memory will be
erased when this procedure is executed, and thus,
the security of the data or code is not compro-
mised.

4.2 Embedding Configuration Word and ID Information in the Hex File

To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex
file when loading the hex file. If configuration word information was not present in the hex file then a simple warning
message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included.
An option to not include this information may be provided.
Specifically for the PIC16F8XX, the EEPROM data memory should also be embedded in the hex file (see
Section 5.1).
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.

DS39025D-page 3-176  2000 Microchip Technology Inc.

PIC16F8XX
4.3 CHECKSUM COMPUTATION
4.3.1 CHECKSUM

Checksum is calculated by reading the contents of the

PIC16F8XX memory locations and adding up the
opcodes up to the maximum user addressable location,
e.g., 0x1FF for the PIC16F8XX. Any carry bits exceed-
ing 16-bits are neglected. Finally, the configuration
word (appropriately masked) is added to the check-
sum. Checksum computation for each member of the
PIC16F8XX devices is shown in Table 4-1.
The checksum is calculated by summing the following:
• The contents of all program memory locations
• The configuration word, appropriately masked
• Masked ID locations (when applicable)
The least significant 16 bits of this sum is the check-
sum.
The following table describes how to calculate the
checksum for each device. Note that the checksum cal-
culation differs depending on the code protect setting.
Since the program memory locations read out differ-
ently depending on the code protect setting, the table
describes how to manipulate the actual program mem-
ory values to simulate the values that would be read
from a protected device. When calculating a checksum
by reading a device, the entire program memory can
simply be read and summed. The configuration word
and ID locations can always be read.
Note that some older devices have an additional value
added in the checksum. This is to maintain compatibil-
ity with older device programmer checksums.

 2000 Microchip Technology Inc. DS39025D-page 3-177

PIC16F8XX
TABLE 4-1: CHECKSUM COMPUTATION
0x25E6 at 0
Code Blank”V
Device Checksum* and max
Protect alue
address
PIC16F870 OFF SUM[0x0000:0x07FFF] + CFGW & 0x3BFF 0x33FF 0xFFCD
ALL CFGW & 0x3BFF + SUM_ID 0x3FCE 0x0B9C
PIC16F871 OFF SUM[0x0000:0x07FFF] + CFGW & 0x3BFF 0x33FF 0xFFCD
ALL CFGW & 0x3BFF + SUM_ID 0x3FCE 0x0B9C
PIC16F872 OFF SUM[0x0000:0x07FFF] + CFGW & 0x3BFF 0x33FF 0xFFCD
ALL CFGW & 0x3BFF + SUM_ID 0x3FCE 0x0B9C
PIC16F873 OFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF 0x2BFF 0xF7CD
0x0F00 : 0xFFF SUM[0x0000:0x0EFF] + CFGW & 0x3BFF +SUM_ID 0x48EE 0xFAA3
0x0800 : 0xFFF SUM[0x0000:0x07FF] + CFGW & 0x3BFF + SUM_ID 0x3FDE 0xF193
ALL CFGW & 0x3BFF + SUM_ID 0x37CE 0x039C
PIC16F874 OFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF 0x2BFF 0xF7CD
0x0F00 : 0xFFF SUM[0x0000:0x0EFF] + CFGW & 0x3BFF +SUM_ID 0x48EE 0xFAA3
0x0800 : 0xFFF SUM[0x0000:0x07FF] + CFGW & 0x3BFF + SUM_ID 0x3FDE 0xF193
ALL CFGW & 0x3BFF + SUM_ID 0x37CE 0x039C
PIC16F876 OFF SUM[0x0000:0x1FFF] + CFGW & 0x3BFF 0x1BFF 0xE7CD
0x1F00 : 0x1FFF SUM[0x0000:0x1EFF] + CFGW & 0x3BFF +SUM_ID 0x28EE 0xDAA3
0x1000 : 0x1FFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF + SUM_ID 0x27DE 0xD993
ALL CFGW & 0x3BFF + SUM_ID 0x27CE 0xF39C
PIC16F877 OFF SUM[0x0000:0x1FFF] + CFGW & 0x3BFF 0x1BFF 0xE7CD
0x1F00 : 0x1FFF SUM[0x0000:0x1EFF] + CFGW & 0x3BFF +SUM_ID 0x28EE 0xDAA3
0x1000 : 0x1FFF SUM[0x0000:0x0FFF] + CFGW & 0x3BFF + SUM_ID 0x27DE 0xD993
ALL CFGW & 0x3BFF + SUM_ID 0x27CE 0xF39C
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND

DS39025D-page 3-178  2000 Microchip Technology Inc.

PIC16F8XX
5.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
5.1 Embedding Data EEPROM Contents in Hex File
The programmer should be able to read data EEPROM information from a hex file and conversely (as an option) write
data EEPROM contents to a hex file along with program memory information and fuse information.
The 256 data memory locations are logically mapped starting at address 0x2100. The format for data memory storage
is one data byte per address location, LSB aligned.

TABLE 5-1: AC/DC CHARACTERISTICS

TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE
Standard Operating Conditions (unless otherwise stated)
Operating Temperature: 0°C ≤ TA ≤ +70°C
Operating Voltage: 4.5V ≤ VDD ≤ 5.5V
Characteristics Sym Min Typ Max Units Conditions/Comments
General
VDD level for word operations, program
memory VDD 2.0 5.5 V
VDD level for word operations, data mem-
ory VDD 2.0 5.5 V
VDD level for bulk erase/write operations,
program and data memory VDD 4.5 5.5 V
High voltage on MCLR for
high-voltage programming entry VIHH VDD + 3.5 13.5 V
Voltage on MCLR for VIH 4.5 5.5 V
low-voltage programming entry
MCLR rise time (VSS to VHH) for test tVHHR 1.0 µs
mode entry
(RB6, RB7) input high level VIH1 0.8VDD V Schmitt Trigger input
(RB6, RB7) input low level VIL1 0.2VDD V Schmitt Trigger input
RB<7:4> setup time before MCLR↑ tset0 100 ns
(test mode selection pattern setup time)
RB<7:4> hold time after MCLR↑ thld0 5 µs
(test mode selection pattern setup time)
Serial Program/Verify
Data in setup time before clock↓ tset1 100 ns
Data in hold time after clock↓ thld1 100 ns
Data input not driven to next clock input tdly1 1.0 µs
(delay required between command/data or
command/command)
Delay between clock↓ to clock↑ of next tdly2 1.0 µs
command or data
Clock↑ to data out valid (during read data) tdly3 80 ns
Erase cycle time tera 2 5 ms
Programming cycle time tprog 2 5 ms

 2000 Microchip Technology Inc. DS39025D-page 3-179

PIC16F8XX
FIGURE 5-1: LOAD DATA COMMAND HIGH-VOLTAGE MODE (PROGRAM/VERIFY)

VIHH
MCLR 1µs min.
tset0 1 2 3 4 5 6 1 2 3 4 5 15 16
tdly2
RB6
(CLOCK)
thld0

RB7 0 1 0 0 X X strt_bit stp_bit

(DATA)
tset1 tdly1 tset1
thld1 1µs min. thld1
}
}

}
}
100ns min. 100ns min.

Reset Program/Verify Test Mode

FIGURE 5-2: READ DATA COMMAND HIGH-VOLTAGE MODE (PROGRAM/VERIFY)

VIHH
MCLR
tdly2
tset0
thld0 1µs min.
1 2 3 4 5 6 1 2 3 4 5 15 16
RB6
(CLOCK)
tdly3
RB7 0 0 1 0 X X stp_bit
(DATA) strt_bit

tset1 tdly1

thld1
1µs min.
}
}

100ns min. RB7

RB7 = input RB7 = output input

Reset Program/Verify Test Mode

FIGURE 5-3: INCREMENT ADDRESS COMMAND HIGH-VOLTAGE MODE (PROGRAM/VERIFY)

VIHH
MCLR
tdly2
Next Command
1µs min.
1 2 3 4 5 6 1 2
RB6
(CLOCK)

RB7 0
0 1 1 X X X 0
(DATA)
tset1 tdly1
thld1 1µs min.
}
}

100ns min.

Reset Program/Verify Test Mode

DS39025D-page 3-180  2000 Microchip Technology Inc.

PIC16F8XX
FIGURE 5-4: LOAD DATA COMMAND LOW-VOLTAGE MODE (PROGRAM/VERIFY)

VIH
MCLR 1µs min.
tset0 1 2 3 4 5 6 1 2 3 4 5 15 16
tdly2
RB6
(CLOCK)
thld0

RB7 0 1 0 0 X X strt_bit stp_bit

(DATA)
tset1 tdly1 tset1
thld1 1µs min. thld1
}
}

}
}
100ns min. 100ns min.

RB3

Reset Program/Verify Test Mode

FIGURE 5-5: READ DATA COMMAND LOW-VOLTAGE MODE (PROGRAM/VERIFY)

VIH
MCLR
tdly2
tset0
thld0 1µs min.
1 2 3 4 5 6 1 2 3 4 5 15 16
RB6
(CLOCK)
tdly3
RB7 0 0 1 0 X X stp_bit
(DATA) strt_bit

tset1 tdly1

thld1
1µs min.
}
}

100ns min. RB7

RB7 = input RB7 = output input

RB3
Reset Program/Verify Test Mode

FIGURE 5-6: INCREMENT ADDRESS COMMAND LOW-VOLTAGE MODE (PROGRAM/VERIFY)

VIH
MCLR
tdly2
Next Command
1µs min.
1 2 3 4 5 6 1 2
RB6
(CLOCK)

RB7
0 1 1 0 X X X 0
(DATA)
tset1 tdly1
thld1 1µs min.
}
}

100ns min.
RB3

Reset Program/Verify Test Mode

 2000 Microchip Technology Inc. DS39025D-page 3-181

PIC16F8XX
NOTES:

DS39025D-page 3-182  2000 Microchip Technology Inc.

SECTION 4
APPLICATION NOTES

IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) OF CALIBRATION PARAMETERS

USING A PICmicro® MICROCONTROLLER ......................................................................................... 4-1

 2000 Microchip Technology Inc. DS30277C-page 4-i

DS30277C-page 4-ii  2000 Microchip Technology Inc.
AN656
In-Circuit Serial Programming™ (ICSP™) of Calibration Parameters
Using a PICmicro® Microcontroller

PROGRAMMING FIXTURE
Author: John Day
Microchip Technology Inc. A programming fixture is needed to assist with the self
programming operation. This is typically a small re-
usable module that plugs into the application PCB
INTRODUCTION being calibrated. Only five pin connections are needed
and this programming fixture can draw its power from
Many embedded control applications, where sensor the application PCB to simplify the connections.
offsets, slopes and configuration information are mea-
sured and stored, require a calibration step. Tradition-
ally, potentiometers or Serial EEPROM devices are
used to set up and store this calibration information.
This application note will show how to construct a pro-
gramming jig that will receive calibration parameters
from the application mid-range PICmicro® microcon-
trollers (MCU) and program this information into the
application baseline PICmicro MCU using the In-Circuit
Serial Programming (ICSP) protocol. This method uses
the PIC16CXXX In-Circuit Serial Programming algo-
rithm of the 14-bit core microcontrollers.

FIGURE 1:

Customer Application PCB Calibration Programming Jig

+5V +5V +5V
+13V VPP
Generator
Sensor(s)
PIC16CXXX 10k VDD
MCLR
GND_ON
RAX VPP
MCLR/VPP VPP_ON VSS
VDD
VDD 1k
VSS
VSS
Application I/O RB7
RB7
RBX RB6
RB6

PIC16C58
RC osc RB1 Wait
RB7
RB6
RB5 RB2 Done
RB4 RB3
To Application Input(s)
Optional PC Connection

 2000 Microchip Technology Inc. DS00656B-page 4-1

AN656
Electrical Interface Programming Issues
There are a total of five electrical connections needed The PIC16CXXX programming specification suggests
between the application PIC16CXXX microcontroller verification of program memory at both Maximum and
and the programming jig: Minimum VDD for each device. This is done to ensure
• MCLR/VPP - High voltage pin used to place appli- proper programming margins and to detect (and reject)
cation PIC16CXXX into programming mode any improperly programmed devices. All production
quality programmers vary VDD from VDDmin to VDDmax
• VDD - +5 volt power supply connection to the
after programming and verify the device under each of
application PIC16CXXX
these conditions.
• VSS - Ground power supply connection to the
application PIC16CXXX Since both the application voltage and it’s tolerances
are known, it is not necessary to verify the PIC16CXXX
• RB6 - PORTB, bit6 connection to application
calibration parameters at the device VDDmax and
PIC16CXXX used to clock programming data
VDDmin. It is only necessary to verify at the application
• RB7 - PORTB, bit7 connection to application power supply Max and Min voltages. This application
PIC16CXXX used to send programming data note shows the nominal (+5V) verification routine and
This programming jig is intended to grab power from hardware. If the power supply is a regulated +5V, this
the application power supply through the VDD connec- is adequate and no additional hardware or software is
tion. The programming jig will require 100 mA of peak needed. If the application power supply is not regulated
current during programming. The application will need (such as a battery powered or poorly regulated system)
to set RB6 and RB7 as inputs, which means external it is important to complete a VDDmin and VDDmax veri-
devices cannot drive these lines. The calibration data fication cycle following the +5V verification cycle. See
will be sent to the programming jig by the application programming specifications for more details on VDD
PIC16CXXX through RB6 and RB7. The programming verification procedures.
jig will later use these lines to clock the calibration data • PIC16C5X Programming Specifications -
into the application PIC16CXXX. DS30190
• PIC16C55X Programming Specifications -
DS30261
• PIC16C6X/7X/9XX Programming Specifications -
DS30228
• PIC16C84 Programming Specifications -
DS30189
Note: The designer must consider environmental
conditions, voltage ranges, and aging
issues when determining VDD min/max
verification levels. Please refer to the pro-
gramming specification for the application
device.
The calibration programming and initial verification
MUST occur at +5V. If the application is intended to run
at lower (or higher voltages), a second verification pass
must be added where those voltages are applied to
VDD and the device is verified.

DS00656B-page 4-2  2000 Microchip Technology Inc.

AN656
Communication Format (Application is accomplished through the RB6 and RB7 lines. The
Microcontroller to Programming Jig) format is a simple synchronous clock and data format
as shown in Figure 2.
Unused program memory, in the application
PIC16CXXX, is left unprogrammed as all 1s; therefore A pull-down on the clock line is used to hold it low. The
the unprogrammed program memory for the calibration application microcontroller needs to send the high and
look-up table would contain 3FFF (hex). This is inter- low bytes of the target start address of the calibration
preted as an “ADDLW FF”. The application microcon- constants to the calibration jig. Next, the data bytes are
troller simply needs one “RETLW FF” instruction at the sent followed by a checksum of the entire data transfer
end of the space allocated in program memory for the as shown in Figure 1.
calibration parameter look-up table. When the applica- Once the data transfer is complete, the checksum is
tion microcontroller is powered up, it will receive a “FFh” verified by the programming jig and the data printed at
for each calibration parameter that is looked up; there- 9600 baud, 8-bits, no parity, 1 stop bit through RB3. A
fore, it can detect that it is uncalibrated and jump to the connection to this pin is optional. Next the programming
calibration code. jig applies +13V, programs and verifies the application
Once the calibration constants are calculated by the PIC16CXXX calibration parameters.
application PICmicro MCU, they need to be communi-
cated to the (PIC16C58A based) programming jig. This

FIGURE 2:

RB6

RB7 CALbit7 CALbit6 CALbit5 CALbit4 CALbit3 CALbit2 CALbit1 CALbit0

FIGURE 1:

AddrH AddrL Data 0 Data 1 Data N CKSUM

 2000 Microchip Technology Inc. DS00656B-page 4-3

AN656
LED Operation
When the programming jig is waiting for communication
from the application PICmicro MCU, both LEDs are
OFF. Once a valid data stream is received (with at least
one calibration byte and a correct checksum) the
WORK LED is lit while the calibration parameters are
printed through the optional RB3 port. Next, the DONE
LED is lit to indicate that these parameters are being
programmed and verified by the programming jig. Once
the programming is finished, the WORK LED is extin-
guished and the DONE LED remains lit. If any param-
eters fail programming, the DONE LED is extinguished;
therefore both LEDs would remain off.

FIGURE 3: ISP CALIBRATION JIG PROGRAMMER SCHEMATIC

VCC VCC
VCC

VCC

T0CKI

VSS VDD

VCC

VPP

VIN
VCC VCC

VREF

VPP

DS00656B-page 4-4  2000 Microchip Technology Inc.

AN656
Code Protection the application PIC16CXXX, places it into program-
ming mode and programs/verifies each calibration
Selection of the code protection configuration bits on
word.
PIC16CXXX microcontrollers prevents further pro-
gramming of the program memory array. This would
CONCLUSION
prevent writing self calibration parameters if the device
is code protected prior to calibration. There are two Typically, calibration information about a system is
ways to address this issue: stored in EEPROM. For calibration data that does not
1. Do not code protect the device when program- change over time, the In-circuit Serial Programming
ming it with the programmer. Add additional capability of the PIC16CXXX devices provide a simple,
code (See the PIC16C6X/7X programming cost effective solution to an external EEPROM. This
Spec) to the ISPPRGM.ASM to program the code method not only decreases the cost of a design, but
protection bit after complete verification of the also reduces the complexity and possible failure points
calibration parameters of the application.
2. Only code protect 1/2 or 3/4 of the program
memory with the programmer. Place the calibra-
tion constants into the unprotected part of pro-
gram memory.
Software Routines
There are two source code files needed for this appli-
cation note:
1. ISPTEST.ASM (Appendix A) Contains the source
code for the application PIC16CXXX, sets up the cali-
bration look-up table and implements the communica-
tion protocol to the programming jig.
2. ISPPRGM.ASM (Appendix B) Source code for a
PIC16C58A to implement the programming jig. This
waits for and receives the calibration parameters from

TABLE 1: PARTS LIST FOR PIC16CXXX ISP CALIBRATION JIG

Bill of Material
Item Quantity Reference Part
1 2 C1,C2 15 pF
2 1 C3 620 pF
3 1 C4 0.1 mF
4 2 C5,C6 220 mF
5 2 D1,D2 LED
6 1 E1 PIC16C58
7 1 E2 LM78S40
8 1 J1 CON5
9 1 L1 270 mH
10 2 Q1,Q2 2N2222
11 2 Q3,Q4 2N2907
12 5 R1,R2,R3,R4,R15 1k
13 4 R5,R6,R12,R14 10k
14 2 R7,R8 270
15 1 R9 180
16 1 R10 23.7k
17 1 R11 2.49k
18 1 R13 2.2k
19 1 Y1 4.0 MHz

 2000 Microchip Technology Inc. DS00656B-page 4-5

AN656
APPENDIX A:
MPASM 01.40.01 Intermediate ISPPRGM.ASM 3-31-1997 10:57:03 PAGE 1

LOC OBJECT CODE LINE SOURCE TEXT

VALUE

00001 ; Filename: ISPPRGM.ASM

00002 ; **********************************************
00003 ; * Author: John Day *
00004 ; * Sr. Field Applications Engineer *
00005 ; * Microchip Technology *
00006 ; * Revision: 1.0 *
00007 ; * Date August 25, 1995 *
00008 ; * Part: PIC16C58 *
00009 ; * Compiled using MPASM V1.40 *
00010 ; **********************************************
00011 ; * Include files: *
00012 ; * P16C5X.ASM *
00013 ; **********************************************
00014 ; * Fuses: OSC: XT (4.0 Mhz xtal) *
00015 ; * WDT: OFF *
00016 ; * CP: OFF *
00017
;*********************************************************************************
00018 ; This program is intended to be used as a self programmer
00019 ; to store calibration constants into a lookup table
00020 ; within the main system processor. A 4 Mhz crystal
00021 ; is needed and an optional 9600 baud seiral port will
00022 ; display the parameters to be programmed.
00023 ;
;*********************************************************************************
00024 ; * Program Memory: *
00025 ; * Words - communication with test jig *
00026 ; * 17 Words - calibration look-up table (16 bytes of data) *
00027 ; * 13 Words - Test Code to generate Calibration Constants *
00028 ; * RAM memory: *
00029 ; * 64 Bytes - Store up to 64 bytes of calibration constant *
00030 ; * 9 Bytes - Store 9 bytes of temp variables (reused) *
00031 ;
;****************************************************************************
00032
00033 list p=16C58A
00034 include <p16C5x.inc>
00001 LIST
00002 ; P16C5X.INC Standard Hdr File, Version 3.30 Microchip Technology, Inc.
00224 LIST
0FFF 0FF9 00035 __CONFIG _CP_OFF&_WDT_OFF&_XT_OSC
00036
00037 ; ************************************
00038 ; * Port A (RA0-RA4) bit definitions *
00039 ; ************************************
00040 ; No PORT A pins are used in this design
00041
00042 ; ************************************
00043 ; * Port B (RB0-RB7) bit definitions *
00044 ; ************************************
00000006 00045 ISPCLOCK EQU 6 ; Clock line for ISP and parameter comm
00000007 00046 ISPDATA EQU 7 ; Data line for ISP and parameter comm
00000005 00047 VPPON EQU 5 ; Apply +13V VPP voltage to MCLR (test mode)
00000004 00048 GNDON EQU 4 ; Apply +0V (gnd) voltage to MCLR (reset)
00000003 00049 SEROUT EQU 3 ; Optional RS-232 TX output (needs 12V driver)
00000002 00050 DONELED EQU 2 ; Turns on LED when done sucessfully program
00000001 00051 WORKLED EQU 1 ; On during programming, off when done
00052 ; RB0 is not used in this design
00053

DS00656B-page 4-6  2000 Microchip Technology Inc.

AN656
00054 ; *************************************************
00055 ; * RAM register definition: *
00056 ; * 07h - 0Fh - used for internal counters, vars *
00057 ; * 10h - 7Fh - 64 bytes for cal param storage *
00058 ; *************************************************
00059 ; ***
00060 ; *** The following VARS are used during ISP programming:
00061 ; ***
00000007 00062 HIADDR EQU 07h ; High address of CAL params to be stored
00000008 00063 LOADDR EQU 08h ; Low address of CAL params to be stored
00000007 00064 HIDATA EQU 07h ; High byte of data to be sent via ISP
00000008 00065 LODATA EQU 08h ; Low byte of data to be sent via ISP
00000009 00066 HIBYTE EQU 09h ; High byte of data received via ISP
0000000A 00067 LOBYTE EQU 0Ah ; Low byte of data received via ISP
0000000B 00068 PULSECNT EQU 0Bh ; Number of times PIC has been pulse programmed
0000000C 00069 TEMPCOUNT EQU 0Ch ; TEMP var used in counters
0000000D 00070 TEMP EQU 0Dh ; TEMP var used throughout program
00071 ; ***
00072 ; *** The following VARS are used to receive and store CAL params:
00073 ; ***
00000007 00074 COUNT EQU 07h ; Counter var used to receive cal params
00000008 00075 TEMP1 EQU 08h ; TEMP var used for RS-232 comm
00000009 00076 DATAREG EQU 09h ; Data register used for RS-232 comm
0000000A 00077 CSUMTOTAL EQU 0Ah ; Running total of checksum (addr + data)
0000000B 00078 TIMEHIGH EQU 0Bh ; Count how long CLOCK line is high
0000000C 00079 TIMELOW EQU 0Ch ; Count how long CLOCK line is low
0000000E 00080 ADDRPTR EQU 0Eh ; Pointer to next byte of CAL storage
0000000F 00081 BYTECOUNT EQU 0Fh ; Number of CAL bytes received
00082
00083 ; *************************************
00084 ; * Various constants used in program *
00085 ; *************************************
00000001 00086 DATISPOUT EQU b’00000001’ ; tris settings for ISP data out
00000081 00087 DATISPIN EQU b’10000001’ ; tris settings for ISP data in
00000006 00088 CMDISPCNT EQU 6 ; Number of bits for ISP command
00000010 00089 STARTCALBYTE EQU 10h ; Address in RAM where CAL byte data stored
00000007 00090 VFYYES EQU PA2 ; Flag bit enables verification (STATUS)
00000006 00091 CMDISPINCRADDR EQU b’00000110’ ; ISP Pattern to increment address
00000008 00092 CMDISPPGMSTART EQU b’00001000’ ; ISP Pattern to start programming
0000000E 00093 CMDISPPGMEND EQU b’00001110’ ; ISP Pattern to end programming
00000002 00094 CMDISPLOAD EQU b’00000010’ ; ISP Pattern to load data for program
00000004 00095 CMDISPREAD EQU b’00000100’ ; ISP Pattern to read data for verify
00000034 00096 UPPER6BITS EQU 034h ; Upper 6 bits for retlw instruction
00097
00098 ; *************************************
00099 ; * delaybit macro *
00100 ; * Delays for 104 uS (at 4 Mhz clock)*
00101 ; * for 9600 baud communications *
00102 ; * RAM used: COUNT *
00103 ; *************************************
00104 delaybit macro
00105 local dlylabels
00106 ; 9600 baud, 8 bit, no parity, 104 us per bit, 52 uS per half bit
00107 ; (8) shift/usage + (2) setup + (1) nop + (3 * 31) literal = (104) 4Mhz
00108 movlw .31 ; place 31 decimal literal into count
00109 movwf COUNT ; Initialize COUNT with loop count
00110 nop ; Add one cycle delay
00111 dlylabels
00112 decfsz COUNT,F ; Decrement count until done
00113 goto dlylabels ; Not done delaying - go back!
00114 ENDM ; Done with Macro
00115
00116 ; ************************************************
00117 ; * addrtofsr macro *
00118 ; * Converts logical, continuous address 10h-4Fh *
00119 ; * to FSR address as follows for access to (4) *

 2000 Microchip Technology Inc. DS00656B-page 4-7

AN656
00120 ; * banks of file registers in PIC16C58: *
00121 ; * Logical Address FSR Value *
00122 ; * 10h-1Fh 10h-1Fh *
00123 ; * 20h-2Fh 30h-3Fh *
00124 ; * 30h-3Fh 50h-5Fh *
00125 ; * 40h-4Fh 70h-7Fh *
00126 ; * Variable Passed: Logical Address *
00127 ; * RAM used: FSR *
00128 ; * W *
00129 ; ************************************************
00130 addrtofsr macro TESTADDR
00131 movlw STARTCALBYTE ; Place base address into W
00132 subwf TESTADDR,w ; Offset by STARTCALBYTE
00133 movwf FSR ; Place into FSR
00134 btfsc FSR,5 ; Shift bits 4,5 to 5,6
00135 bsf FSR,6
00136 bcf FSR,5
00137 btfsc FSR,4
00138 bsf FSR,5
00139 bsf FSR,4
00140 endm
00141
00142
00143 ; **************************************
00144 ; * The PC starts at the END of memory *
00145 ; **************************************
07FF 00146 ORG 7FFh
Message[306]: Crossing page boundary -- ensure page bits are set.
07FF 0A00 00147 goto start
00148
00149 ; **************************************
00150 ; * Start of CAL param read routine *
00151 ; **************************************
0000 00152 ORG 0h
0000 00153 start
0000 0C0A 00154 movlw b’00001010’ ; Serial OFF, LEDS OFF, VPP OFF
0001 0026 00155 movwf PORTB ; Place “0” into port b latch register
0002 0CC1 00156 movlw b’11000001’ ; RB7;:RB6, RB0 set to inputs
0003 0006 00157 tris PORTB ; Move to tris registers
0004 0040 00158 clrw ; Place 0 into W
0005 0065 00159 clrf PORTA ; Place all ZERO into latch
0006 0005 00160 tris PORTA ; Make all pins outputs to be safe..
0007 0586 00161 bsf PORTB,GNDON ; TEST ONLY-RESET PIC-NOT NEEDED IN REAL DESIGN!
0008 00162 clearram
0008 0C10 00163 movlw 010h ; Place start of buffer into W
0009 0027 00164 movwf COUNT ; Use count for RAM pointer
000A 00165 loopclrram
00166 addrtofsr COUNT ; Set up FSR
000A 0C10 M movlw STARTCALBYTE ; Place base address into W
000B 0087 M subwf COUNT,w ; Offset by STARTCALBYTE
000C 0024 M movwf FSR ; Place into FSR
000D 06A4 M btfsc FSR,5 ; Shift bits 4,5 to 5,6
000E 05C4 M bsf FSR,6
000F 04A4 M bcf FSR,5
0010 0684 M btfsc FSR,4
0011 05A4 M bsf FSR,5
0012 0584 M bsf FSR,4
0013 0060 00167 clrf INDF ; Clear buffer value
0014 02A7 00168 incf COUNT,F ; Move to next reg
0015 0C50 00169 movlw 050h ; Move end of buffer addr to W
0016 0087 00170 subwf COUNT,W ; Check if at last MEM
0017 0743 00171 btfss STATUS,Z ; Skip when at end of counter
0018 0A0A 00172 goto loopclrram ; go back to next location
0019 0486 00173 bcf PORTB,GNDON ; TEST ONLY-LET IT GO-NOT NEEDED IN REAL DESIGN!
001A 00174 calget
001A 006A 00175 clrf CSUMTOTAL ; Clear checksum total byte

DS00656B-page 4-8  2000 Microchip Technology Inc.

AN656
001B 0069 00176 clrf DATAREG ; Clear out data receive register
001C 0C10 00177 movlw STARTCALBYTE ; Place RAM start address of first cal byte
001D 002E 00178 movwf ADDRPTR ; Place this into ADDRPTR
001E 00179 waitclockpulse
001E 07C6 00180 btfss PORTB,ISPCLOCK ; Wait for CLOCK high pulse - skip when high
001F 0A1E 00181 goto waitclockpulse ; CLOCK is low - go back and wait!
0020 00182 loopcal
0020 0C08 00183 movlw .8 ; Place 8 into W (8 bits/byte)
0021 0027 00184 movwf COUNT ; set up counter register to count bits
0022 00185 loopsendcal
0022 006B 00186 clrf TIMEHIGH ; Clear timeout counter for high pulse
0023 006C 00187 clrf TIMELOW ; Clear timeout counter for low pulse
0024 00188 waitclkhi
0024 06C6 00189 btfsc PORTB,ISPCLOCK ; Wait for CLOCK high - skip if it is low
0025 0A29 00190 goto waitclklo ; Jump to wait for CLOCK low state
0026 02EB 00191 decfsz TIMEHIGH,F ; Decrement counter - skip if timeout
0027 0A24 00192 goto waitclkhi ; Jump back and wait for CLOCK high again
0028 0A47 00193 goto timeout ; Timed out waiting for high - check data!
0029 00194 waitclklo
0029 07C6 00195 btfss PORTB,ISPCLOCK ; Wait for CLOCK low - skip if it is high
002A 0A2E 00196 goto clockok ; Got a high to low pulse - jump to clockok
002B 02EC 00197 decfsz TIMELOW,F ; Decrement counter - skip if timeout
002C 0A29 00198 goto waitclklo ; Jump back and wait for CLOCK low again
002D 0A47 00199 goto timeout ; Timed out waiting for low - check data!
002E 00200 clockok
002E 0C08 00201 movlw .8 ; Place initial count value into W
002F 0087 00202 subwf COUNT,W ; Subtract from count, place into W
0030 0743 00203 btfss STATUS,Z ; Skip if we are at count 8 (first value)
0031 0A34 00204 goto skipcsumadd ; Skip checksum add if any other count value
0032 0209 00205 movf DATAREG,W ; Place last byte received into W
0033 01EA 00206 addwf CSUMTOTAL,F ; Add to checksum
0034 00207 skipcsumadd
0034 0503 00208 bsf STATUS,C ; Assume data bit is high
0035 07E6 00209 btfss PORTB,ISPDATA ; Skip if the data bit was high
0036 0403 00210 bcf STATUS,C ; Set data bit to low
0037 0369 00211 rlf DATAREG,F ; Rotate next bit into DATAREG
0038 02E7 00212 decfsz COUNT,F ; Skip after 8 bits
0039 0A22 00213 goto loopsendcal ; Jump back and send next bit
00214 addrtofsr ADDRPTR ; Convert pointer address to FSR
003A 0C10 M movlw STARTCALBYTE ; Place base address into W
003B 008E M subwf ADDRPTR,w ; Offset by STARTCALBYTE
003C 0024 M movwf FSR ; Place into FSR
003D 06A4 M btfsc FSR,5 ; Shift bits 4,5 to 5,6
003E 05C4 M bsf FSR,6
003F 04A4 M bcf FSR,5
0040 0684 M btfsc FSR,4
0041 05A4 M bsf FSR,5
0042 0584 M bsf FSR,4
0043 0209 00215 movf DATAREG,W ; Place received byte into W
0044 0020 00216 movwf INDF ; Move recv’d byte into CAL buffer location
0045 02AE 00217 incf ADDRPTR,F ; Move to the next cal byte
0046 0A20 00218 goto loopcal ; Go back for next byte
0047 00219 timeout
0047 0C14 00220 movlw STARTCALBYTE+4 ; check if we received (4) params
0048 008E 00221 subwf ADDRPTR,W ; Move current address pointer to W
0049 0703 00222 btfss STATUS,C ; Skip if we have at least (4)
004A 0A93 00223 goto sendnoise ; not enough params - print and RESET!
004B 0200 00224 movf INDF,W ; Move received checksum into W
004C 00AA 00225 subwf CSUMTOTAL,F ; Subtract received Checksum from calc’d checksum
004D 0743 00226 btfss STATUS,Z ; Skip if CSUM OK
004E 0A9F 00227 goto sendcsumbad ; Checksum bad - print and RESET!
004F 00228 csumok
004F 0426 00229 bcf PORTB,WORKLED ; Turn on WORK LED
0050 0C10 00230 movlw STARTCALBYTE ; Place start pointer into W
0051 008E 00231 subwf ADDRPTR,W ; Subtract from current address
0052 002F 00232 movwf BYTECOUNT ; Place into number of bytes into BYTECOUNT

 2000 Microchip Technology Inc. DS00656B-page 4-9

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0053 002B 00233 movwf TIMEHIGH ; TEMP store into timehigh reg
0054 0C10 00234 movlw STARTCALBYTE ; Place start address into W
0055 002E 00235 movwf ADDRPTR ; Set up address pointer
0056 00236 loopprintnums
00237 addrtofsr ADDRPTR ; Set up FSR
0056 0C10 M movlw STARTCALBYTE ; Place base address into W
0057 008E M subwf ADDRPTR,w ; Offset by STARTCALBYTE
0058 0024 M movwf FSR ; Place into FSR
0059 06A4 M btfsc FSR,5 ; Shift bits 4,5 to 5,6
005A 05C4 M bsf FSR,6
005B 04A4 M bcf FSR,5
005C 0684 M btfsc FSR,4
005D 05A4 M bsf FSR,5
005E 0584 M bsf FSR,4
005F 0380 00238 swapf INDF,W ; Place received char into W
0060 0E0F 00239 andlw 0Fh ; Strip off upper digits
0061 002D 00240 movwf TEMP ; Place into TEMP
0062 0C0A 00241 movlw .10 ; Place .10 into W
0063 00AD 00242 subwf TEMP,F ; Subtract 10 from TEMP
0064 0603 00243 btfsc STATUS,C ; Skip if TEMP is less than 9
0065 0A6D 00244 goto printhiletter ; Greater than 9 - print letter instead
0066 00245 printhinumber
0066 0380 00246 swapf INDF,W ; Place received char into W
0067 0E0F 00247 andlw 0Fh ; Strip off upper digits
0068 002D 00248 movwf TEMP ; Place into TEMP
0069 0C30 00249 movlw ‘0’ ; Place ASCII ‘0’ into W
006A 01CD 00250 addwf TEMP,w ; Add to TEMP, place into W
006B 09AE 00251 call putchar ; Send out char
006C 0A73 00252 goto printlo ; Jump to print next char
006D 00253 printhiletter
006D 0380 00254 swapf INDF,W ; Place received char into W
006E 0E0F 00255 andlw 0Fh ; Strip off upper digits
006F 002D 00256 movwf TEMP ; Place into TEMP
0070 0C37 00257 movlw ‘A’-.10 ; Place ASCII ‘A’ into W
0071 01CD 00258 addwf TEMP,w ; Add to TEMP, place into W
0072 09AE 00259 call putchar ; send out char
0073 00260 printlo
0073 0200 00261 movf INDF,W ; Place received char into W
0074 0E0F 00262 andlw 0Fh ; Strip off upper digits
0075 002D 00263 movwf TEMP ; Place into TEMP
0076 0C0A 00264 movlw .10 ; Place .10 into W
0077 00AD 00265 subwf TEMP,F ; Subtract 10 from TEMP
0078 0603 00266 btfsc STATUS,C ; Skip if TEMP is less than 9
0079 0A81 00267 goto printloletter ; Greater than 9 - print letter instead
007A 00268 printlonumber
007A 0200 00269 movf INDF,W ; Place received char into W
007B 0E0F 00270 andlw 0Fh ; Strip off upper digits
007C 002D 00271 movwf TEMP ; Place into TEMP
007D 0C30 00272 movlw ‘0’ ; Place ASCII ‘0’ into W
007E 01CD 00273 addwf TEMP,w ; Add to TEMP, place into W
007F 09AE 00274 call putchar ; send out char
0080 0A87 00275 goto printnext ; jump to print next char
0081 00276 printloletter
0081 0200 00277 movf INDF,W ; Place received char into W
0082 0E0F 00278 andlw 0Fh ; Strip off upper digits
0083 002D 00279 movwf TEMP ; Place into TEMP
0084 0C37 00280 movlw ‘A’-.10 ; Place ASCII ‘A’ into W
0085 01CD 00281 addwf TEMP,w ; Add to TEMP, place into W
0086 09AE 00282 call putchar ; send out char
0087 00283 printnext
0087 0C7C 00284 movlw ‘|’ ; Place ASCII ‘|’ into W
0088 09AE 00285 call putchar ; Send out character
0089 028E 00286 incf ADDRPTR,W ; Go to next buffer value
008A 0E0F 00287 andlw 0Fh ; And with F

008B 0643 00288 btfsc STATUS,Z ; Skip if this is NOT multiple of 16

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AN656
008C 09A9 00289 call printcrlf ; Print CR and LF every 16 chars
008D 02AE 00290 incf ADDRPTR,F ; go to next address
008E 02EF 00291 decfsz BYTECOUNT,F ; Skip after last byte
008F 0A56 00292 goto loopprintnums ; Go back and print next char
0090 09A9 00293 call printcrlf ; Print CR and LF
0091 05A3 00294 bsf STATUS,PA0 ; Set page bit to page 1
Message[306]: Crossing page boundary -- ensure page bits are set.
0092 0A6B 00295 goto programpartisp ; Go to program part through ISP
0093 00296 sendnoise
0093 0C4E 00297 movlw ‘N’ ; Place ‘N’ into W
0094 09AE 00298 call putchar ; Send char in W to terminal
0095 0C4F 00299 movlw ‘O’ ; Place ‘O’ into W
0096 09AE 00300 call putchar ; Send char in W to terminal
0097 0C49 00301 movlw ‘I’ ; Place ‘I’ into W
0098 09AE 00302 call putchar ; Send char in W to terminal
0099 0C53 00303 movlw ‘S’ ; Place ‘S’ into W
009A 09AE 00304 call putchar ; Send char in W to terminal
009B 0C45 00305 movlw ‘E’ ; Place ‘E’ into W
009C 09AE 00306 call putchar ; Send char in W to terminal
009D 09A9 00307 call printcrlf ; Print CR and LF
009E 0A1A 00308 goto calget ; RESET!
009F 00309 sendcsumbad
009F 0C43 00310 movlw ‘C’ ; Place ‘C’ into W
00A0 09AE 00311 call putchar ; Send char in W to terminal
00A1 0C53 00312 movlw ‘S’ ; Place ‘S’ into W
00A2 09AE 00313 call putchar ; Send char in W to terminal
00A3 0C55 00314 movlw ‘U’ ; Place ‘U’ into W
00A4 09AE 00315 call putchar ; Send char in W to terminal
00A5 0C4D 00316 movlw ‘M’ ; Place ‘M’ into W
00A6 09AE 00317 call putchar ; Send char in W to terminal
00A7 09A9 00318 call printcrlf ; Print CR and LF
00A8 0A1A 00319 goto calget ; RESET!
00320
00321 ; ******************************************
00322 ; * printcrlf *
00323 ; * Sends char .13 (Carrage Return) and *
00324 ; * char .10 (Line Feed) to RS-232 port *
00325 ; * by calling putchar. *
00326 ; * RAM used: W *
00327 ; ******************************************
00A9 00328 printcrlf
00A9 0C0D 00329 movlw .13 ; Value for CR placed into W
00AA 09AE 00330 call putchar ; Send char in W to terminal
00AB 0C0A 00331 movlw .10 ; Value for LF placed into W
00AC 09AE 00332 call putchar ; Send char in W to terminal
00AD 0800 00333 retlw 0 ; Done - return!
00334
00335 ; ******************************************
00336 ; * putchar *
00337 ; * Print out the character stored in W *
00338 ; * by toggling the data to the RS-232 *
00339 ; * output pin in software. *
00340 ; * RAM used: W,DATAREG,TEMP1 *
00341 ; ******************************************
00AE 00342 putchar
00AE 0029 00343 movwf DATAREG ; Place character into DATAREG
00AF 0C09 00344 movlw 09h ; Place total number of bits into W
00B0 0028 00345 movwf TEMP1 ; Init TEMP1 for bit counter
00B1 0403 00346 bcf STATUS,C ; Set carry to send start bit
00B2 0AB4 00347 goto putloop1 ; Send out start bit
00B3 00348 putloop
00B3 0329 00349 rrf DATAREG,F ; Place next bit into carry
00B4 00350 putloop1
00B4 0703 00351 btfss STATUS,C ; Skip if carry was set
00B5 0466 00352 bcf PORTB,SEROUT ; Clear RS-232 serial output bit
00B6 0603 00353 btfsc STATUS,C ; Skip if carry was clear

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00B7 0566 00354 bsf PORTB,SEROUT ; Set RS-232 serial output bit
00355 delaybit ; Delay for one bit time
0000 M local dlylabels
M ; 9600 baud, 8 bit, no parity, 104 us per bit, 52 uS per half bit
M ; (8) shift/usage + (2) setup + (1) nop + (3 * 31) literal = (104) 4Mhz
00B8 0C1F M movlw .31 ; place 31 decimal literal into count
00B9 0027 M movwf COUNT ; Initialize COUNT with loop count
00BA 0000 M nop ; Add one cycle delay
00BB M dlylabels
00BB 02E7 M decfsz COUNT,F ; Decrement count until done
00BC 0ABB M goto dlylabels ; Not done delaying - go back!
00BD 02E8 00356 decfsz TEMP1,F ; Decrement bit counter, skip when done!
00BE 0AB3 00357 goto putloop ; Jump back and send next bit
00BF 0566 00358 bsf PORTB,SEROUT ; Send out stop bit
00359 delaybit ; delay for stop bit
0000 M local dlylabels
M ; 9600 baud, 8 bit, no parity, 104 us per bit, 52 uS per half bit
M ; (8) shift/usage + (2) setup + (1) nop + (3 * 31) literal = (104) 4Mhz
00C0 0C1F M movlw .31 ; place 31 decimal literal into count
00C1 0027 M movwf COUNT ; Initialize COUNT with loop count
00C2 0000 M nop ; Add one cycle delay
00C3 M dlylabels
00C3 02E7 M decfsz COUNT,F ; Decrement count until done
00C4 0AC3 M goto dlylabels ; Not done delaying - go back!
00C5 0800 00360 retlw 0 ; Done - RETURN
00361
00362 ; *******************************************************************
00363 ; * ISP routines from PICSTART-16C *
00364 ; * Converted from PIC17C42 to PIC16C5X code by John Day *
00365 ; * Originially written by Jim Pepping *
00366 ; *******************************************************************
0200 00367 ORG 200 ; ISP routines stored on page 1
00368
00369 ; *******************************************************************
00370 ; * poweroffisp *
00371 ; * Power off application PIC - turn off VPP and reset device after *
00372 ; * programming pass is complete *
00373 ; *******************************************************************
0200 00374 poweroffisp
0200 04A6 00375 bcf PORTB,VPPON ; Turn off VPP 13 volts
0201 0586 00376 bsf PORTB,GNDON ; Apply 0 V to MCLR to reset PIC
0202 0CC1 00377 movlw b’11000001’ ; RB6,7 set to inputs
0203 0006 00378 tris PORTB ; Move to tris registers
0204 0486 00379 bcf PORTB,GNDON ; Allow MCLR to go back to 5 volts, deassert reset
0205 0526 00380 bsf PORTB,WORKLED ; Turn off WORK LED
0206 0800 00381 retlw 0 ; Done so return!
00382
00383 ; *******************************************************************
00384 ; * testmodeisp *
00385 ; * Apply VPP voltage to place application PIC into test mode. *
00386 ; * this enables ISP programming to proceed *
00387 ; * RAM used: TEMP *
00388 ; *******************************************************************
0207 00389 testmodeisp
0207 0C08 00390 movlw b’00001000’ ; Serial OFF, LEDS OFF, VPP OFF
0208 0026 00391 movwf PORTB ; Place “0” into port b latch register
0209 04A6 00392 bcf PORTB,VPPON ; Turn off VPP just in case!
020A 0586 00393 bsf PORTB,GNDON ; Apply 0 volts to MCLR
020B 0C01 00394 movlw b’00000001’ ; RB6,7 set to outputs
020C 0006 00395 tris PORTB ; Move to tris registers
020D 0206 00396 movf PORTB,W ; Place PORT B state into W
020E 002D 00397 movwf TEMP ; Move state to TEMP
020F 048D 00398 bcf TEMP,4 ; Turn off MCLR GND
0210 05AD 00399 bsf TEMP,5 ; Turn on VPP voltage
0211 020D 00400 movf TEMP,W ; Place TEMP into W
0212 0026 00401 movwf PORTB ; Turn OFF GND and ON VPP

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AN656
0213 0546 00402 bsf PORTB,DONELED ; Turn ON GREEN LED
0214 0800 00403 retlw 0 ; Done so return!
00404
00405 ; *******************************************************************
00406 ; * p16cispout *
00407 ; * Send 14-bit data word to application PIC for writing this data *
00408 ; * to it’s program memory. The data to be sent is stored in both *
00409 ; * HIBYTE (6 MSBs only) and LOBYTE. *
00410 ; * RAM used: TEMP, W, HIBYTE (inputs), LOBYTE (inputs) *
00411 ; *******************************************************************
0215 00412 P16cispout
0215 0C0E 00413 movlw .14 ; Place 14 into W for bit counter
0216 002D 00414 movwf TEMP ; Use TEMP as bit counter
0217 04C6 00415 bcf PORTB,ISPCLOCK ; Clear CLOCK line
0218 04E6 00416 bcf PORTB,ISPDATA ; Clear DATA line
0219 0C01 00417 movlw DATISPOUT ; Place tris value for data output
021A 0006 00418 tris PORTB ; Set tris latch as data output
021B 04E6 00419 bcf PORTB,ISPDATA ; Send a start bit (0)
021C 05C6 00420 bsf PORTB,ISPCLOCK ; Set CLOCK output
021D 04C6 00421 bcf PORTB,ISPCLOCK ; Clear CLOCK output (clock start bit)
021E 00422 P16cispoutloop
021E 0403 00423 bcf STATUS,C ; Clear carry bit to start clean
021F 04E6 00424 bcf PORTB,ISPDATA ; Clear DATA bit to start (assume 0)
0220 0329 00425 rrf HIBYTE,F ; Rotate HIBYTE output
0221 032A 00426 rrf LOBYTE,F ; Rotate LOBYTE output
0222 0603 00427 btfsc STATUS,C ; Skip if data bit is zero
0223 05E6 00428 bsf PORTB,ISPDATA ; Set DATA line to send a one
0224 05C6 00429 bsf PORTB,ISPCLOCK ; Set CLOCK output
0225 04C6 00430 bcf PORTB,ISPCLOCK ; Clear CLOCK output (clock bit)
0226 02ED 00431 decfsz TEMP,F ; Decrement bit counter, skip when done
0227 0A1E 00432 goto P16cispoutloop ; Jump back and send next bit
0228 04E6 00433 bcf PORTB,ISPDATA ; Send a stop bit (0)
0229 05C6 00434 bsf PORTB,ISPCLOCK ; Set CLOCK output
022A 04C6 00435 bcf PORTB,ISPCLOCK ; Clear CLOCK output (clock stop bit)
022B 0800 00436 retlw 0 ; Done so return!
00437
00438 ; *******************************************************************
00439 ; * p16cispin *
00440 ; * Receive 14-bit data word from application PIC for reading this *
00441 ; * data from it’s program memory. The data received is stored in *
00442 ; * both HIBYTE (6 MSBs only) and LOBYTE. *
00443 ; * RAM used: TEMP, W, HIBYTE (output), LOBYTE (output) *
00444 ; *******************************************************************
022C 00445 P16cispin
022C 0C0E 00446 movlw .14 ; Place 14 data bit count value into W
022D 002D 00447 movwf TEMP ; Init TEMP and use for bit counter
022E 0069 00448 clrf HIBYTE ; Clear recieved HIBYTE register
022F 006A 00449 clrf LOBYTE ; Clear recieved LOBYTE register
0230 0403 00450 bcf STATUS,C ; Clear carry bit to start clean
0231 04C6 00451 bcf PORTB,ISPCLOCK ; Clear CLOCK output
0232 04E6 00452 bcf PORTB,ISPDATA ; Clear DATA output
0233 0C81 00453 movlw DATISPIN ; Place tris value for data input into W
0234 0006 00454 tris PORTB ; Set up tris latch for data input
0235 05C6 00455 bsf PORTB,ISPCLOCK ; Send a single clock to start things going
0236 04C6 00456 bcf PORTB,ISPCLOCK ; Clear CLOCK to start receive
0237 00457 P16cispinloop
0237 05C6 00458 bsf PORTB,ISPCLOCK ; Set CLOCK bit
0238 0000 00459 nop ; Wait one cycle
0239 0403 00460 bcf STATUS,C ; Clear carry bit, assume 0 read
023A 06E6 00461 btfsc PORTB,ISPDATA ; Check the data, skip if it was zero
023B 0503 00462 bsf STATUS,C ; Set carry bit if data was one
023C 0329 00463 rrf HIBYTE,F ; Move recevied bit into HIBYTE
023D 032A 00464 rrf LOBYTE,F ; Update LOBYTE
023E 04C6 00465 bcf PORTB,ISPCLOCK ; Clear CLOCK line
023F 0000 00466 nop ; Wait one cycle
0240 0000 00467 nop ; Wait one cycle

 2000 Microchip Technology Inc. DS00656B-page 4-13

AN656
0241 02ED 00468 decfsz TEMP,F ; Decrement bit counter, skip when zero
0242 0A37 00469 goto P16cispinloop ; Jump back and receive next bit
0243 05C6 00470 bsf PORTB,ISPCLOCK ; Clock a stop bit (0)
0244 0000 00471 nop ; Wait one cycle
0245 04C6 00472 bcf PORTB,ISPCLOCK ; Clear CLOCK to send bit
0246 0000 00473 nop ; Wait one cycle
0247 0403 00474 bcf STATUS,C ; Clear carry bit
0248 0329 00475 rrf HIBYTE,F ; Update HIBYTE with the data
0249 032A 00476 rrf LOBYTE,F ; Update LOBYTE
024A 0403 00477 bcf STATUS,C ; Clear carry bit
024B 0329 00478 rrf HIBYTE,F ; Update HIBYTE with the data
024C 032A 00479 rrf LOBYTE,F ; Update LOBYTE with the data
024D 04C6 00480 bcf PORTB,ISPCLOCK ; Clear CLOCK line
024E 04E6 00481 bcf PORTB,ISPDATA ; Clear DATA line
024F 0C01 00482 movlw DATISPOUT ; Place tris value for data output into W
0250 0006 00483 tris PORTB ; Set tris to data output
0251 0800 00484 retlw 0 ; Done so RETURN!
00485
00486 ; *******************************************************************
00487 ; * commandisp *
00488 ; * Send 6-bit ISP command to application PIC. The command is sent *
00489 ; * in the W register and later stored in LOBYTE for shifting. *
00490 ; * RAM used: LOBYTE, W, TEMP *
00491 ; *******************************************************************
0252 00492 commandisp
0252 002A 00493 movwf LOBYTE ; Place command into LOBYTE
0253 0C06 00494 movlw CMDISPCNT ; Place number of command bits into W
0254 002D 00495 movwf TEMP ; Use TEMP as command bit counter
0255 04E6 00496 bcf PORTB,ISPDATA ; Clear DATA line
0256 04C6 00497 bcf PORTB,ISPCLOCK ; Clear CLOCK line
0257 0C01 00498 movlw DATISPOUT ; Place tris value for data output into W
0258 0006 00499 tris PORTB ; Set tris to data output
0259 00500 P16cispcmmdoutloop
0259 0403 00501 bcf STATUS,C ; Clear carry bit to start clean
025A 04E6 00502 bcf PORTB,ISPDATA ; Clear the DATA line to start
025B 032A 00503 rrf LOBYTE,F ; Update carry with next CMD bit to send
025C 0603 00504 btfsc STATUS,C ; Skip if bit is supposed to be 0
025D 05E6 00505 bsf PORTB,ISPDATA ; Command bit was a one - set DATA to one
025E 05C6 00506 bsf PORTB,ISPCLOCK ; Set CLOCK line to clock the data
025F 0000 00507 nop ; Wait one cycle
0260 04C6 00508 bcf PORTB,ISPCLOCK ; Clear CLOCK line to clock data
0261 02ED 00509 decfsz TEMP,F ; Decement bit counter TEMP, skip when done
0262 0A59 00510 goto P16cispcmmdoutloop ; Jump back and send next cmd bit
0263 0000 00511 nop ; Wait one cycle
0264 04E6 00512 bcf PORTB,ISPDATA ; Clear DATA line
0265 04C6 00513 bcf PORTB,ISPCLOCK ; Clear CLOCK line
0266 0C81 00514 movlw DATISPIN ; Place tris value for data input into W
0267 0006 00515 tris PORTB ; set as input to avoid any contention
0268 0000 00516 nop ; Wait one cycle
0269 0000 00517 nop ; Wait one cycle
026A 0800 00518 retlw 0 ; Done - return!
00519
00520 ; ********************************************************************
00521 ; * programpartisp *
00522 ; * Main ISP programming loop. Reads data starting at STARTCALBYTE *
00523 ; * and calls programming subroutines to program and verify this *
00524 ; * data into the application PIC. *
00525 ; * RAM used: LOADDR, HIADDR, LODATA, HIDATA, FSR, LOBYTE, HIBYTE*
00526 ; ********************************************************************
026B 00527 programpartisp
026B 0907 00528 call testmodeisp ; Place PIC into test/program mode
026C 0064 00529 clrf FSR ; Point to bank 0
026D 0210 00530 movf STARTCALBYTE,W ; Upper order address of data to be stored into W
026E 0027 00531 movwf HIADDR ; place into counter
026F 0211 00532 movf STARTCALBYTE+1,W ; Lower order address byte of data to be stored
0270 0028 00533 movwf LOADDR ; place into counter

DS00656B-page 4-14  2000 Microchip Technology Inc.

AN656
0271 00E8 00534 decf LOADDR,F ; Subtract one from loop constant
0272 02A7 00535 incf HIADDR,F ; Add one for loop constant
0273 00536 programsetptr
0273 0C06 00537 movlw CMDISPINCRADDR ; Increment address command load into W
0274 0952 00538 call commandisp ; Send command to PIC
0275 02E8 00539 decfsz LOADDR,F ; Decrement lower address
0276 0A73 00540 goto programsetptr ; Go back again
0277 02E7 00541 decfsz HIADDR,F ; Decrement high address
0278 0A73 00542 goto programsetptr ; Go back again
0279 0C03 00543 movlw .3 ; Place start pointer into W, offset address
027A 008B 00544 subwf TIMEHIGH,W ; Restore byte count into W
027B 002F 00545 movwf BYTECOUNT ; Place into byte counter
027C 0C12 00546 movlw STARTCALBYTE+2 ; Place start of REAL DATA address into W
027D 002E 00547 movwf ADDRPTR ; Update pointer
027E 00548 programisploop
027E 0C34 00549 movlw UPPER6BITS ; retlw instruction opcode placed into W
027F 0027 00550 movwf HIDATA ; Set up upper bits of program word
00551 addrtofsr ADDRPTR ; Set up FSR to point to next value
0280 0C10 M movlw STARTCALBYTE ; Place base address into W
0281 008E M subwf ADDRPTR,w ; Offset by STARTCALBYTE
0282 0024 M movwf FSR ; Place into FSR
0283 06A4 M btfsc FSR,5 ; Shift bits 4,5 to 5,6
0284 05C4 M bsf FSR,6
0285 04A4 M bcf FSR,5
0286 0684 M btfsc FSR,4
0287 05A4 M bsf FSR,5
0288 0584 M bsf FSR,4
0289 0200 00552 movf INDF,W ; Place next cal param into W
028A 0028 00553 movwf LODATA ; Move it out to LODATA
028B 0208 00554 movf LODATA,W ; Place LODATA into LOBYTE
028C 002A 00555 movwf LOBYTE ;
028D 0207 00556 movf HIDATA,W ; Place HIDATA into HIBYTE
028E 0029 00557 movwf HIBYTE ;
028F 006B 00558 clrf PULSECNT ; Clear pulse counter
0290 00559 pgmispcntloop
0290 05E3 00560 bsf STATUS,VFYYES ; Set verify flag
0291 09B1 00561 call pgmvfyisp ; Program and verify this byte
0292 02AB 00562 incf PULSECNT,F ; Increment pulse counter
0293 0C19 00563 movlw .25 ; Place 25 count into W
0294 008B 00564 subwf PULSECNT,w ; Subtract pulse count from 25
0295 0643 00565 btfsc STATUS,Z ; Skip if NOT 25 pulse counts
0296 0AA9 00566 goto pgmispfail ; Jump to program failed - only try 25 times
0297 0209 00567 movf HIBYTE,w ; Subtract programmed and read data
0298 0087 00568 subwf HIDATA,w
0299 0743 00569 btfss STATUS,Z ; Skip if programmed is OK
029A 0A90 00570 goto pgmispcntloop ; Miscompare - program it again!
029B 020A 00571 movf LOBYTE,w ; Subtract programmed and read data
029C 0088 00572 subwf LODATA,w
029D 0743 00573 btfss STATUS,Z ; Skip if programmed is OK
029E 0A90 00574 goto pgmispcntloop ; Miscompare - program it again!
029F 0040 00575 clrw ; Clear W reg
02A0 01CB 00576 addwf PULSECNT,W ; now do 3 times overprogramming pulses
02A1 01CB 00577 addwf PULSECNT,W
02A2 01CB 00578 addwf PULSECNT,W
02A3 002B 00579 movwf PULSECNT ; Add 3X pulsecount to pulsecount
02A4 00580 pgmisp3X
02A4 04E3 00581 bcf STATUS,VFYYES ; Clear verify flag
02A5 09B1 00582 call pgmvfyisp ; Program this byte
02A6 02EB 00583 decfsz PULSECNT,F ; Decrement pulse counter, skip when done
02A7 0AA4 00584 goto pgmisp3X ; Loop back and program again!
02A8 0AAA 00585 goto prgnextbyte ; Done - jump to program next byte!
02A9 00586 pgmispfail
02A9 0446 00587 bcf PORTB,DONELED ; Failure - clear green LED!
02AA 00588 prgnextbyte
02AA 0C06 00589 movlw CMDISPINCRADDR ; Increiment address command load into W
02AB 0952 00590 call commandisp ; Send command to PIC

 2000 Microchip Technology Inc. DS00656B-page 4-15

AN656
02AC 02AE 00591 incf ADDRPTR,F ; Increment pointer to next address
02AD 02EF 00592 decfsz BYTECOUNT,F ; See if we sent last byte
02AE 0A7E 00593 goto programisploop ; Jump back and send next byte
02AF 0900 00594 call poweroffisp ; Done - power off PIC and reset it!
02B0 00595 self
02B0 0AB0 00596 goto self ; Done with programming - wait here!
00597
00598
00599
00600 ; *******************************************************************
00601 ; * pgmvfyisp *
00602 ; * Program and/or Veryify a word in program memory on the *
00603 ; * application PIC. The data to be programmed is in HIDATA and *
00604 ; * LODATA. *
00605 ; * RAM used: HIBYTE, LOBYTE, HIDATA, LODATA, TEMP *
00606 ; *******************************************************************
02B1 00607 pgmvfyisp
02B1 00608 loadcisp
02B1 0C02 00609 movlw CMDISPLOAD ; Place load data command into W
02B2 0952 00610 call commandisp ; Send load data command to PIC
02B3 0000 00611 nop ; Wait one cycle
02B4 0000 00612 nop ; Wait one cycle
02B5 0000 00613 nop ; Wait one cycle
02B6 0208 00614 movf LODATA,w ; Place LODATA byte into W
02B7 002A 00615 movwf LOBYTE ; Move it to LOBYTE reg
02B8 0207 00616 movf HIDATA,w ; Place HIDATA byte into W
02B9 0029 00617 movwf HIBYTE ; Move it to HIBYTE reg
02BA 0915 00618 call P16cispout ; Send data to PIC
02BB 0C08 00619 movlw CMDISPPGMSTART ; Place start programming command into W
02BC 0952 00620 call commandisp ; Send start programming command to PIC
02BD 00621 delay100us
02BD 0C20 00622 movlw .32 ; Place 32 into W
02BE 0000 00623 nop ; Wait one cycle
02BF 002D 00624 movwf TEMP ; Move it to TEMP for delay counter
02C0 00625 loopprgm
02C0 02ED 00626 decfsz TEMP,F ; Decrement TEMP, skip when delay done
02C1 0AC0 00627 goto loopprgm ; Jump back and loop delay
02C2 0C0E 00628 movlw CMDISPPGMEND ; Place stop programming command into W
02C3 0952 00629 call commandisp ; Send end programming command to PIC
02C4 07E3 00630 btfss STATUS,VFYYES ; Skip if we are supposed to verify this time
02C5 0800 00631 retlw 0 ; Done - return!
02C6 0000 00632 nop ; Wait one cycle
02C7 00633 readcisp
02C7 0C04 00634 movlw CMDISPREAD ; Place read data command into W
02C8 0952 00635 call commandisp ; Send read data command to PIC
02C9 092C 00636 call P16cispin ; Read programmed data
02CA 0800 00637 retlw 0 ; Done - return!
00638 END

DS00656B-page 4-16  2000 Microchip Technology Inc.

AN656
MEMORY USAGE MAP (‘X’ = Used, ‘-’ = Unused)

0000 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX

0040 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
0080 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
00C0 : XXXXXX---------- ---------------- ---------------- ----------------
0200 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
0240 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
0280 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
02C0 : XXXXXXXXXXX----- ---------------- ---------------- ----------------
07C0 : ---------------- ---------------- ---------------- ---------------X
0FC0 : ---------------- ---------------- ---------------- ---------------X

All other memory blocks unused.

Program Memory Words Used: 402

Program Memory Words Free: 1646

Errors : 0
Warnings : 0 reported, 0 suppressed
Messages : 2 reported, 0 suppressed

 2000 Microchip Technology Inc. DS00656B-page 4-17

AN656
APPENDIX B:
MPASM 01.40.01 Intermediate ISPTEST.ASM 3-31-1997 10:55:57 PAGE 1

LOC OBJECT CODE LINE SOURCE TEXT

VALUE

00001 ; Filename: ISPTEST.ASM

00002 ; **********************************************
00003 ; * Author: John Day *
00004 ; * Sr. Field Applications Engineer *
00005 ; * Microchip Technology *
00006 ; * Revision: 1.0 *
00007 ; * Date August 25, 1995 *
00008 ; * Part: PIC16CXX *
00009 ; * Compiled using MPASM V1.40 *
00010 ; **********************************************
00011 ; * Include files: *
00012 ; * P16CXX.ASM *
00013 ; **********************************************
00014 ; * Fuses: OSC: XT (4.0 Mhz xtal) *
00015 ; * WDT: OFF *
00016 ; * CP: OFF *
00017 ; * PWRTE: OFF *
00018 ; **************************************************************************
00019 ; * This program is intended to be used as a code example to *
00020 ; * show how to comunicate with a manufacturing test jig that *
00021 ; * allows this PIC16CXX device to self program. The RB6 and RB7 *
00022 ; * lines of this PIC16CXX device are used to clock the data from *
00023 ; * this device to the test jig (running ISPPRGM.ASM). Once the *
00024 ; * PIC16C58 running ISPPRGM in the test jig receives the data, *
00025 ; * it places this device in test mode and programs these parameters. *
00026 ; * The code with comments “TEST -“ is used to create some fakecalibration *
00027 ; * parameters that are first written to addresses STARTCALBYTE through *
00028 ; * ENDCALBYTE and later used to call the self-programming algorithm. *
00029 ; * Replace this code with your parameter calculation procedure, *
00030 ; * placing each parameter into the STARTCALBYTE to ENDCALBYTE *
00031 ; * file register addresses (16 are used in this example). The address *
00032 ; * “lookuptable” is used by the main code later on for the final lookup *
00033 ; * table of calibration constants. 16 words are reserved for this lookup *
00034 ; * table. *
00035 ; **************************************************************************
00036 ; * Program Memory: *
00037 ; * 49 Words - communication with test jig *
00038 ; * 17 Words - calibration look-up table (16 bytes of data) *
00039 ; * 13 Words - Test Code to generate Calibration Constants *
00040 ; * RAM Memory: *
00041 ; * 16 Bytes -Temporary- Store 16 bytes of calibration constant*
00042 ; * 4 Bytes -Temporary- Store 4 bytes of temp variables *
00043 ; **************************************************************************
00044
Warning[217]: Hex file format specified on command line.
00045 list p=16C71,f=inhx8m
00046 include <p16C71.inc>
00001 LIST
00002 ; P16C71.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
00142 LIST
2007 3FF1 00047 __CONFIG _CP_OFF&_WDT_OFF&_XT_OSC&_PWRTE_OFF
00048
00049 ; ************************************
00050 ; * Port A (RA0-RA4) bit definitions *
00051 ; ************************************
00052 ; Port A is not used in this test program
00053
00054 ; ************************************

DS00656B-page 4-18  2000 Microchip Technology Inc.

AN656
00055 ; * Port B (RB0-RB7) bit definitions *
00056 ; ************************************
00057 #define CLOCK 6 ; clock line for ISP
00058 #define DATA 7 ; data line for ISP
00059 ; Port pins RB0-5 are not used in this test program
00060
00061 ; ************************************
00062 ; * RAM register usage definition *
00063 ; ************************************
0000000C 00064 CSUMTOTAL EQU 0Ch ; Address for checksum var
0000000D 00065 COUNT EQU 0Dh ; Address for COUNT var
0000000E 00066 DATAREG EQU 0Eh ; Address for Data output register var
0000000F 00067 COUNTDLY EQU 0Fh ; Address for clock delay counter
00068
00069 ; These two symbols are used for the start and end address
00070 ; in RAM where the calibration bytes are stored. There are 16 bytes
00071 ; to be stored in this example; however, you can increase or
00072 ; decrease the number of bytes by changing the STARTCALBYTE or ENDCALBYTE
00073 ; address values.
00074
00000010 00075 STARTCALBYTE EQU 10h ; Address pointer for start CAL byte
0000002F 00076 ENDCALBYTE EQU 2Fh ; Address pointer for end CAL byte
00077
00078 ; Table length of lookup table (number of CAL parameters to be stored)
00079
00000020 00080 CALTABLELENGTH EQU ENDCALBYTE - STARTCALBYTE + 1
00081
0000 00082 ORG 0
00083 ; ******************************************************************
00084 ; * testcode routine *
00085 ; * TEST code - sets up RAM register with register address as data *
00086 ; * Uses file register STARTCALBYTE through ENDCALBYTE to store the*
00087 ; * calibration values that are to be programmed into the lookup *
00088 ; * table by the test jig running ISPPRGM. *
00089 ; * Customer would place calibration code here and make sure that *
00090 ; * calibration constants start at address STARTCALBYTE *
00091 ; ******************************************************************
0000 00092 testcode
0000 3010 00093 movlw STARTCALBYTE ; TEST -
0001 0084 00094 movwf FSR ; TEST - Init FSR with start of RAM addres
0002 00095 looptestram
0002 0804 00096 movf FSR,W ; TEST - Place address into W
0003 0080 00097 movwf INDF ; TEST - Place address into RAM data byte
0004 0A84 00098 incf FSR,F ; TEST - Move to next address
0005 0804 00099 movf FSR,W ; TEST - Place current address into W
0006 3C30 00100 sublw ENDCALBYTE+1 ; TEST - Subtract from end of RAM
0007 1D03 00101 btfss STATUS,Z ; TEST - Skip if at END of ram
0008 2802 00102 goto looptestram ; TEST - Jump back and init next RAM byte
0009 0103 00103 clrw ; TEST - Clear W
000A 200F 00104 call lookuptable ; TEST - Get first CAL value from lookup table
000B 3CFF 00105 sublw 0FFh ; TEST - Check if lookup CAL table is blank
000C 1903 00106 btfsc STATUS,Z ; TEST - Skip if table is NOT blank
000D 2830 00107 goto calsend ; TEST - Table blank - send out cal parameters
000E 00108 mainloop
000E 280E 00109 goto mainloop ; TEST - Jump back to self since CAL is done
00110
00111 ; ******************************************************************
00112 ; * lookuptable *
00113 ; * Calibration constants look-up table. This is where the CAL *
00114 ; * Constants will be stored via ISP protocol later. Note it is *
00115 ; * blank, since these values will be pogrammed by the test jig *
00116 ; * running ISPPRGM later. *
00117 ; * Input Variable: W stores index for table lookup *
00118 ; * Output Variable: W returns with the calibration constant *

 2000 Microchip Technology Inc. DS00656B-page 4-19

AN656
00119 ; * NOTE: Blank table when programmed reads “FF” for all locations *
00120 ; ******************************************************************
000F 00121 lookuptable
000F 0782 00122 addwf PCL,F ; Place the calibration constant table here!
00123
002F 00124 ORG lookuptable + CALTABLELENGTH
002F 34FF 00125 retlw 0FFh ; Return FF at last location for a blank table
00126
00127 ; ******************************************************************
00128 ; * calsend subroutine *
00129 ; * Send the calibration data stored in locations STARTCALBYTE *
00130 ; * through ENDCALBYTE in RAM to the programming jig using a serial*
00131 ; * clock and data protocol *
00132 ; * Input Variables: STARTCALBYTE through ENDCALBYTE *
00133 ; ******************************************************************
0030 00134 calsend
0030 018C 00135 clrf CSUMTOTAL ; Clear CSUMTOTAL reg for delay counter
0031 018D 00136 clrf COUNT ; Clear COUNT reg to delay counter
0032 00137 delayloop ; Delay for 100 mS to wait for prog jig wakeup
0032 0B8D 00138 decfsz COUNT,F ; Decrement COUNT and skip when zero
0033 2832 00139 goto delayloop ; Go back and delay again
0034 0B8C 00140 decfsz CSUMTOTAL,F ; Decrement CSUMTOTAL and skip when zero
0035 2832 00141 goto delayloop ; Go back and delay again
0036 0186 00142 clrf PORTB ; Place “0” into port b latch register
0037 1683 00143 bsf STATUS,RP0 ; Switch to bank 1
0038 303F 00144 movlw b’00111111’ ; RB6,7 set to outputs
Message[302]: Register in operand not in bank 0. Ensure that bank bits are correct.
0039 0086 00145 movwf TRISB ; Move to TRIS registers
003A 1283 00146 bcf STATUS,RP0 ; Switch to bank 0
003B 018C 00147 clrf CSUMTOTAL ; Clear checksum total byte
003C 3001 00148 movlw high lookuptable+1 ; place MSB of first addr of cal table into W
003D 204D 00149 call sendcalbyte ; Send the high address out
003E 3010 00150 movlw low lookuptable+1 ; place LSB of first addr of cal table into W
003F 204D 00151 call sendcalbyte ; Send low address out
0040 3010 00152 movlw STARTCALBYTE ; Place RAM start address of first cal byte
0041 0084 00153 movwf FSR ; Place this into FSR
0042 00154 loopcal
0042 0800 00155 movf INDF,W ; Place data into W
0043 204D 00156 call sendcalbyte ; Send the byte out
0044 0A84 00157 incf FSR,F ; Move to the next cal byte
0045 0804 00158 movf FSR,W ; Place byte address into W
0046 3C30 00159 sublw ENDCALBYTE+1 ; Set Z bit if we are at the end of CAL data
0047 1D03 00160 btfss STATUS,Z ; Skip if we are done
0048 2842 00161 goto loopcal ; Go back for next byte
0049 080C 00162 movf CSUMTOTAL,W ; place checksum total into W
004A 204D 00163 call sendcalbyte ; Send the checksum out
004B 0186 00164 clrf PORTB ; clear out port pins
004C 00165 calsenddone
004C 284C 00166 goto calsenddone ; We are done - go home!
00167
00168 ; ******************************************************************
00169 ; * sendcalbyte subroutine *
00170 ; * Send one byte of calibration data to the programming jig *
00171 ; * Input Variable: W contains the byte to be sent *
00172 ; ******************************************************************
004D 00173 sendcalbyte
004D 008E 00174 movwf DATAREG ; Place send byte into data register
004E 078C 00175 addwf CSUMTOTAL,F ; Update checksum total
004F 3008 00176 movlw .8 ; Place 8 into W
0050 008D 00177 movwf COUNT ; set up counter register
0051 00178 loopsendcal
0051 1706 00179 bsf PORTB,CLOCK ; Set clock line high
0052 205C 00180 call delaysend ; Wait for test jig to synch up
0053 0D8E 00181 rlf DATAREG,F ; Rotate to next bit
0054 1786 00182 bsf PORTB,DATA ; Assume data bit is high
0055 1C03 00183 btfss STATUS,C ; Skip if the data bit was high

DS00656B-page 4-20  2000 Microchip Technology Inc.

AN656
0056 1386 00184 bcf PORTB,DATA ; Set data bit to low
0057 1306 00185 bcf PORTB,CLOCK ; Clear clock bit to clock data out
0058 205C 00186 call delaysend ; Wait for test jig to synch up
0059 0B8D 00187 decfsz COUNT,F ; Skip after 8 bits
005A 2851 00188 goto loopsendcal ; Jump back and send next bit
005B 0008 00189 return ; We are done with this byte so return!
00190
00191 ; ******************************************************************
00192 ; * delaysend subroutine *
00193 ; * Delay for 50 ms to wait for the programming jig to synch up *
00194 ; ******************************************************************
005C 00195 delaysend
005C 3010 00196 movlw 10h ; Delay for 16 loops
005D 008F 00197 movwf COUNTDLY ; Use COUNTDLY as delay count variable
005E 00198 loopdelaysend
005E 0B8F 00199 decfsz COUNTDLY,F ; Decrement COUNTDLY and skip when done
005F 285E 00200 goto loopdelaysend ; Jump back for more delay
0060 0008 00201 return
00202 END

MEMORY USAGE MAP (‘X’ = Used, ‘-’ = Unused)

0000 : XXXXXXXXXXXXXXXX ---------------- ---------------X XXXXXXXXXXXXXXXX

0040 : XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX X--------------- ----------------
2000 : -------X-------- ---------------- ---------------- ----------------

All other memory blocks unused.

Program Memory Words Used: 66

Program Memory Words Free: 958

Errors : 0
Warnings : 1 reported, 0 suppressed
Messages : 1 reported, 0 suppressed

 2000 Microchip Technology Inc. DS00656B-page 4-21

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China - Beijing Microchip Technology Taiwan
Atlanta Microchip Technology, Beijing 10F-1C 207
Microchip Technology Inc. Unit 915, 6 Chaoyangmen Bei Dajie Tung Hua North Road
500 Sugar Mill Road, Suite 200B Dong Erhuan Road, Dongcheng District Taipei, Taiwan
Atlanta, GA 30350 New China Hong Kong Manhattan Building Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307 Beijing, 100027, P.R.C.
Boston Tel: 86-10-85282100 Fax: 86-10-85282104 EUROPE
Microchip Technology Inc. China - Shanghai Denmark
5 Mount Royal Avenue Microchip Technology Microchip Technology Denmark ApS
Marlborough, MA 01752 Unit B701, Far East International Plaza, Regus Business Centre
Tel: 508-480-9990 Fax: 508-480-8575 No. 317, Xianxia Road Lautrup hoj 1-3
Chicago Shanghai, 200051, P.R.C. Ballerup DK-2750 Denmark
Microchip Technology Inc. Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Tel: 45 4420 9895 Fax: 45 4420 9910
333 Pierce Road, Suite 180 Hong Kong France
Itasca, IL 60143 Microchip Asia Pacific Arizona Microchip Technology SARL
Tel: 630-285-0071 Fax: 630-285-0075 Unit 2101, Tower 2 Parc d’Activite du Moulin de Massy
Dallas Metroplaza 43 Rue du Saule Trapu
Microchip Technology Inc. 223 Hing Fong Road Batiment A - ler Etage
4570 Westgrove Drive, Suite 160 Kwai Fong, N.T., Hong Kong 91300 Massy, France
Addison, TX 75248 Tel: 852-2-401-1200 Fax: 852-2-401-3431 Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Tel: 972-818-7423 Fax: 972-818-2924 India Germany
Dayton Microchip Technology Inc. Arizona Microchip Technology GmbH
Microchip Technology Inc. India Liaison Office Gustav-Heinemann-Ring 125
Two Prestige Place, Suite 150 No. 6, Legacy, Convent Road D-81739 München, Germany
Miamisburg, OH 45342 Bangalore, 560 025, India Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Tel: 937-291-1654 Fax: 937-291-9175 Tel: 91-80-229-0061 Fax: 91-80-229-0062 Italy
Detroit Japan Arizona Microchip Technology SRL
Microchip Technology Inc. Microchip Technology Intl. Inc. Centro Direzionale Colleoni
Tri-Atria Office Building Benex S-1 6F Palazzo Taurus 1 V. Le Colleoni 1
32255 Northwestern Highway, Suite 190 3-18-20, Shinyokohama 20041 Agrate Brianza
Farmington Hills, MI 48334 Kohoku-Ku, Yokohama-shi Milan, Italy
Tel: 248-538-2250 Fax: 248-538-2260 Kanagawa, 222-0033, Japan Tel: 39-039-65791-1 Fax: 39-039-6899883
Los Angeles Tel: 81-45-471- 6166 Fax: 81-45-471-6122 United Kingdom
Microchip Technology Inc. Korea Arizona Microchip Technology Ltd.
18201 Von Karman, Suite 1090 Microchip Technology Korea 505 Eskdale Road
Irvine, CA 92612 168-1, Youngbo Bldg. 3 Floor Winnersh Triangle
Tel: 949-263-1888 Fax: 949-263-1338 Samsung-Dong, Kangnam-Ku Wokingham
New York Seoul, Korea Berkshire, England RG41 5TU
Microchip Technology Inc. Tel: 82-2-554-7200 Fax: 82-2-558-5934 Tel: 44 118 921 5858 Fax: 44-118 921-5835
150 Motor Parkway, Suite 202
03/23/00
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose Microchip received QS-9000 quality system
Microchip Technology Inc. certification for its worldwide headquarters,
2107 North First Street, Suite 590 design and wafer fabrication facilities in
San Jose, CA 95131 Chandler and Tempe, Arizona in July 1999. The
Tel: 408-436-7950 Fax: 408-436-7955 Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.

All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 5/00 Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates.
It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by
Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights
arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written
approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property
rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.

DS30277C-page 4-22  2000 Microchip Technology Inc.

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