Chapter-10 OP Circuits

Microelectronic Circuits (III)
Operational-Amplifier Circuits
Heng-Ming Hsu
National Chung-Hsing University

Department of Electrical Engineering
Outline
 The Two-Stage CMOS Op Amp
 The Cascode CMOS Op Amp
 741 Op Amp Circuit
Microelectrics (III) 許恒銘--中興大學電機系

9-1
 OPAMPs are studied in this chapter.
 OPAMP design
− bipolar OPAMPs can achieve better performance than CMOS OPAMPs.
− CMOS OPAMPs are adequate for VLSI implementation.
− BiCMOS OPAMPs combine the advantages of bipolar and CMOS
devices.

9-2
Two-Stage CMOS Op Amps
Bias 1st stage 2nd stage

generation

9-3
 Voltage gain (discussed in Sec. 7.7.1)
 Voltage gain of 1st stage: A1 = −gm1(ro2 || ro4)
 Voltage gain of 2nd stage: A2 = −gm6(ro6 || ro7)
 DC open-loop gain: Av = A1 × A2
 Input offset voltage
 Random offset: device mismatches as random in nature
 Systematic offset: due to design technique  predictable
(W / L )6 (W / L )7 If this condition is not met, a systematic offset

 =2
(W / L )4 (W / L )5 will result.
 CC is Miller-multiplied by the gain of the second stage to provide the

required dominant pole.

9-4
Input Common-Mode Range
 The lowest value of VICM has to be sufficiently large to

keep Q1 and Q2 in saturation.
VICM ≥ −VSS + Vtn + VOV3 − |Vtp|
 The highest value of VICM should ensure Q5 in saturation.

VICM ≤ VDD − |VOV5| − VSG1
 VICM ≤ VDD − |VOV5| − |Vtp| − |VOV1|
 −VSS + VOV3 + Vtn − |Vtp| ≤ VICM ≤ VDD − |Vtp| − |VOV1| − |VOV5|
Select the values of VOV as low as possible!!

9-5
Output Swing
 Output swing
The extent of the output signal is limited at the lower and by the need to
keep Q6 saturated and at the upper end by the need to keep Q7 saturated.
 −VSS + VOV6 ≤ vO ≤ VDD − |VOV7|
Select the values of VOV (of Q6 and Q7)as low as possible!!
fT ∝ VOV (in Sec. 6.2.3); the high-frequency performance of a MOSFET
improves with the overdrive voltage at which it is operated.
 There must be a substantial overlap between the allowable range of VICM
and vO for an unit-gain amp application.
9-6
Example Two-Stage CMOS Op Amp Analysis
Let IREF = 25µA, |Vt | (for all devices) = 1V, µnCox =

20 µA/V2, µpCox = 10 µA/V2, |VA | (for all devices) =
25V, VDD = VSS = 5V. For all devices evaluate ID,
|VGS |, gm, and ro. Also find A1, A2, the dc open-loop
voltage gain, the input common-mode range, and the
output voltage range. Neglect the effect of VA on bias
current.
Solution
 Dc analysis: Since Q8 and Q5 are matched, I = IREF .
Thus, Q1 – Q4 : ID1-4 = 12.5µA.
Q7 : ID7 = IREF = 25µA (Q7 is matched Q5 and Q8 ). Q6 : ID6 = 25µA.
With ID of each device known, we use I C = 12 ( µCox )(W / L )(VGS − Vt )2 to determine |VGS |.
 Small-signal analysis:
Transconduce gm = µCox (W / L )(VGS − Vt ) = 2(µCox )(W / L )I D = 2I D /(VGS − Vt )
ro is determined from VA .
ro =
ID

9-7
Summary of the dc and ac parameters:
 Determine the voltage gain:

Voltage gain of 1st stage: A1 = −gm1(ro2 || ro4) = −62.5(2 || 2) = −62.5 V/V
Voltage gain of 2nd stage: A2 = −gm6(ro6 || ro7) = −100(1 || 1) = −50 V/V
The overall dc open-loop gain: Av = A1 × A2 = (−62) × (−50) = 3125 V/V
 Operating range:
The lower limit of the input CM range: Q1 and Q2 leave the saturation region.
Since the drain of Q1 is at −5 + 1.5 = −3.5 V, then the lower limit of the input CM
range is −4.5 V.
The upper limit of the input CM range: Q5 leave the saturation region.
VIcm/max = VDD − |VGS5| + |Vt | − |VGS1| = 5 − 1.6 + 1 −1.4 = 3 V
The output range is determined from Q7 leaving the saturation region,
VOmax = VDD − |VGS7| + |Vt | = 5 − 1.6 + 1 = 4.4 V
and from Q6 leaving the saturation region,
VOmin = −VSS + |VGS6| − |Vt | = −4.5 V

9-8
Input Offset Voltage
 Random offset: device mismatches as random in nature
 Systematic offset: due to design technique  predictable
If the input stage is perfectly balanced, then VDS4 = VDS3 = VGS4.
(W / L)6 (W / L)6 I
 VGS4 = VGS6, hence
= I6 = I4
(W / L) 4 (W / L) 4 2
In order for no offset voltage to
appear at the output, then I6 = I7.
Since I 7 = (W / L)7 I
(W / L)5
(W / L )6 (W / L )7
 =2
(W / L )4 (W / L )5
If this condition is not met, a

systematic offset will result.

9-9
Voltage Gain
Simplified small-signal equivalent circuit:
 Rin =∞
2(I /2) I
Gm1 =
 Gm1 = gm1 = gm2  =
VOV 1 VOV 1
VA2 VA 4
 R1 = ro2 || ro4 =ro 2 = ro 4
I /2 I /2
 Dc gain of 1st stage
2
A1 = −gm1 (ro 2 ro 4 ) =
−Gm1R1 = −
 1 1 
VOV 1  + 
V
 A2 V A4 

9-10
A1 is increased by
 Q1 and Q2 at a low overdrive
 Choosing a longer channel length to obtain larger Early voltage, |VA|.
Both action, however, degrade the frequency response of the amplifier. (See
Sec. 6.2.3)
 G= 2I D 6
m2 g
= m6
VOV 6
VA6 VA7 VA7
 R2 = ro6 || ro7 = ro 6 ro 4 =
=
ID6 ID7 ID6
 Dc gain of 2nd stage
2
A2 =−Gm 2R2 = −gm 6 (ro 6 ro 7 ) =
−
 1 1 
VOV 6  + 
 Overall dc gain V
 A6 V A7 
Av A=
= 1A2 Gm1R1Gm=
2R 2 gm1 (r02 ro 4 ) gm 6 (r06 ro 7 )
Generally, 500 ~5000 V/V of Av,max.
 Output resistance Ro = ro6 || ro7
Ro can be large (the tens-of-kilohms range) for on-chip op amps.

9-11
Frequency Response
Small-signal equivalent circuit of the CMOS op amp:
 Transfer function: (See Sec. 7.7.1)

Vo Gm1(Gm 2 − sCC )R1R2
=
Vid 1 + s[C1R1 + C 2R2 + CC (Gm 2R1R2 + R1 + R2 )] + s 2[(C1C 2 + CC (C1C 2 + CC (C1 + C 2 )]R1R2
 C1 = Cgd2 + Cdb2 + Cgd4 + Cdb4 + Cgs6
C2 = Cdb6 + Cdb7 + Cgd7 + CL (Usually, CL is larger than transistor capacitances)
Miller capacitance CT = (1 + Gm2R2)(CC + Cgd6) ≈ Gm2R2CC
 Poles:
1 1 Gm 2CC
ωP 1 = ≈ ωP 2 ≈
R1[C1 + (1 + Gm 2R2 )CC ] Gm 2R2CC R1 C1C 2 + CC (C1 + C 2 )
 If C2, CC >> C1, then ωP2 ≈ Gm2 / C2 .
 The value of ωt is usually selected to be lower than the frequencies of
nondominant poles and zeros. Thus, A0 ωP1 = ωt .  ωt = Gm1 / CC.

9-12
 Zero: The Miller capacitance CC introduces a right-half-plane zero.
Vo = 0 ⇒ sCCVi2 = Gm2Vi2  sz = Gm2 / CC
 Since Gm2 is of the same order of magnitude as Gm1, the zero frequency
will be close to ωt .
 Since the zero is in the right half-plane, it will decrease the phase margin.
 ?? stability
 fp1 is the dominant pole formed by the interaction of Miller-multiplied CC and R1.
The unity-gain frequency:
Gm1
= ft A = v f p1
2π CC
ft must be lower than fp2 and f z, thus the design must satisfy the following two
conditions:
Gm1 Gm 2
<
CC C2
Gm1 < Gm 2

9-13
Simplified Equivalent Circuit Analysis
 The circuit applies for f » fp1.
An ideal integrator!!

9-14
Phase Margin
 Pole-splitting provides a low-frequency
dominant pole (f p1) and shifts fp2
beyond f t.
 At ft, the phase lag exceed 90o caused
by f p1 and the excess phase shift due to
fp2.
 f 
φ p 2 = − tan−1  t 
 f p2 
 ft 
φz = − tan−1  
 fz 
Phase lag at f t:
90 + tan−1( f t / f p 2 ) + tan−1( f t / f z )
φtotal =
 Phase margin:
= 180 − φtotal
90 − tan−1( f t / f p 2 ) − tan−1( f t / f z )
=
 Phase margin & stability (See 8.10.2)
 The right half-plane zero decreases the
phase margin.

9-15
Improve CMOS Op Amp with the Resistance R
Small-signal equivalent circuit of the CMOS op amp with the resistance R.
 Find zero:
Vi 2 1
= Gm 2Vi 2  sz =
R + 1/sCC CC (1/Gm 2 − R )
 R = 1/Gm2, the zero can be placed at infinite frequency.

 R > 1/Gm2, a left-half plane zero introduces adds to the phase margin.
 Discussion: The second pole is not very far from ωt . Thus the second pole
introduces appreciable phase shift at ωt , which reduces the phase margin.

9-16
Slew Rate
 When large output signal are present, slew-
rate limiting can cause nonlinear distortion.
 Slew rate: the maximum rate of change
possible at the output of a real op amp.
dvo
SR =
dt max
 A unity-gain follower with a large step input.
(the output voltage cannot change immediately.)

9-17
Slew Rate of the Two-Stage CMOS Op Amp
Model of the two-stage CMOS op amp when a large differential voltage is
applied.
I
vo (t ) = t
CC
I
⇒ SR =
CC
9-18
Relationship Between SR and ft
I
Slew rate SR =
CC
I
G=
m1 g=
m1
VGS1 − Vt
G m1
ωt =
CC
 SR = ( |VGS1| − |Vt | )ωt = VOV1ωt
 For a given ωt , the slew rate is determined by the overdrive voltage at which
the first transistor are operated.
 VOV   SR .
 For a given bias current I, a large VOV is obtained if Q1 and Q2 are p-
channel devices. (1st stage)
 It allows the 2nd stage to employ an n-channel device that has a greater
transconductance, Gm2, resulting in a higher second-pole frequency and
a corresponding higher ωt .

9-19
Ex.10.1 Two-Stage CMOS Op Amp Design
Design a dc gain of 4000 V/V in a 0.5-µm CMOS
technology.
Vtn = |Vtp | = 0.5V, k’n = 200 µA/V2, k’pCox = 80
µA/V2, V’An = |V’Ap | = 20V/µm, VDD = VSS = 1.65V,
L = 1µm for all devices. Let I = 200µA, ID6 = 0.5mA.
If C1 = 0.2pF andC1 = 0.2pF,find the required CC
and R to place the transmission zero at s = ∞ for
phase margin of 75o.
Solution
2
2(I /2) 1 V A 2I D 6 1 V A  V A 
 Av gm1(ro 2 ro 4 )gm 6 (ro 6 =
Voltage gain = ro 7 ) ⋅ ⋅ ⋅ ⋅ ⋅=
VOV 2 (I /2) VOV 2 I D 6  VOV 
400
Av = 4000 and VA = 20V  4000= 2
⇒ VOV= 0.316V
VOV
 (W/L)1 and (W/L)2:
1 ' W  2 1 W  W  25 µm  W 
I D1 =k p   vOV ⇒ 100 = ⋅ 80   ⋅ 0.3162 ⇒   = = 
2  L 1 2  L 1 L
 1 1µ m  L 2

9-20
 (W/L)3 and (W/L)4:
1 ' W  2 1 W  W  10 µm  W 
I D1 = kn   vOV ⇒ 100 = ⋅ 200   ⋅ 0.3162 ⇒   = = 
2  L 3 2  L 3 L
 3 1µm  L 4
1 ' W  2 1 W  W  50 µm
 (W/L)5: I D 5 =k p   vOV ⇒ 200 = ⋅ 80   ⋅ 0.3162 ⇒   =
2  L 5 2  L 5  L 5 1µm
 (W/L)6 and (W/L)7:

W  W  125 µm 1 W  W  50 µm
=
  =
2.5   500 = ⋅ 200   ⋅ 0.3162 ⇒   =
 L 7  L 5 1µm 2  L 6  L 6 1µm
 W 
Select IREF = 20µA, thus = W  5 µm
  =
0.1  
 L 8  L 5 1µm
 Input CM range: −1.33 V ≤ VICM ≤ 0.52 V
 Max. signal swing: −1.33 V ≤ vo ≤ 1.33 V
 Input resistance: Ri = ∞
 Output resistance: Ro = ro6 || ro7 = 20 kΩ
 Determine f p2:
2I D 6 2 × 0.5 Gm 2 3.2 × 10−3
Gm 2 =gm 6 = = =3.2mA /V  f p 2 ≈ = =637MHz
VOV 0.316 2π C 2 2π ⋅ 0.8 × 10−12

9-21
 To move the transmission zero to s = ∞, we select the value of R as
1 1
=R = = 316Ω
Gm 2 3.2 × 10−3
 For a phase margin of 75o, the phase shift due to f p2 at f = f t must be 15o, that is
ft
tan−1 = 15
f p2
 ft = 171MHz
637 × tan15 =
 Determine CC:
Gm1 2 ⋅ 100 µ A
C
=C where G=
m1 g=
m1 = 0.63mA /V
2π f t 0.316V
0.6 × 10−3
∴ CC
= = 0.6 pF
2π ⋅ 171 × 106
 Slew rate: [Eq. (9.40)]
SR =2π f tVOV =2π ⋅ 171 × 106 × 0.316 =340V / µs

9-22
Cascode CMOS Op Amp
Output resistance:
Ro = Ro 2C Ro 4C = (gm 2Cro 2Cro 2 ) (gm 4Cro 4Cro 3 )
Gain:
A1 = −gm1Ro
Composed of CS + CG.
A high-gain single-stage op amp
High output resistance: Increasing Ro
by about two orders of magnitude
increases A1 by the same factor.
But the input common-mode range is
lower than that obtained in the two-
stage amplifier.
Folded-cascode configuration have
large common-mode range.

9-23
Folded-Cascode CMOS Op Amp
Folded : replace input transistor pairs with a counterpart.
I B − I /2

9-24
More Complete Circuit for the Folded-Cascode CMOS Op Amp

9-25
 Input common-mode range:
VICMmax is limited by the requirement that Q1 and Q2 operate in saturation.
V ICM max =VDD − VOV 9 + Vtn
VICMmax should ensure Q11 in saturation.
V ICM min = −VSS + VOV 11 + VOV 1 + Vtn
 −VSS + VOV 11 + VOV 1 + Vtn ≤ V ICM ≤ VDD − VOV 9 + Vtn
VBIAS3 should be selected to provide I while operating Q11 at a low overdrive voltage.
 Output voltage swing:

Upper limit of vo is determined by the need to maintain Q10 and Q4 in saturation.
vo max =
VDD − VOV 10 − VOV 4
Select VBIAS1 so that Q10 operates at the edge of saturation:
VBIAS1 = VDD − |VOV10| − VSG4
Lowest vo is obtained when Q6 reaches the edge of saturation.
vo min =
−VSS + VOV 7 + VOV 5 + Vtn

9-26
 Voltage gain
Small-signal equivalent circuit:
 Transconductance
2(I /2) I
G
= m g=
m1 gm 2 G
= m =
VOV 1 VOV 1
 Output resistance
Ro =
R o 4 Ro 6 Ro 4 ≈ (gm 4ro 4 )(ro 2 ro10 ) Ro 6 ≈ gm 6ro 6ro 8
 Ro = gm 4ro 4 (ro 2 ro10 ) (gm 6ro 6ro 8 )
 Open-loop gain
Av G=
= m Ro gm1 {gm 4ro 4 (ro 2 ro10 ) (gm 6ro 6ro 8 )}

9-27
 Unity-gain buffer (voltage follower):
Ro R Ro 1 1
Output resistance Rof = ≈ o = = =
1 + Av Av Gm Ro Gm gm1
 It is not very small for a single-stage op amp (OTA, operational

transconductance amplifier).
 An ideal op amp has an zero output resistance!

9-28
 Frequency response:
Since the primary purpose of CMOS op amps is to feed capacitive loads, CL
is usually large, and the pole at the output becomes dominant.
 Transfer function
Vo G m Ro
=
Vid 1 + sC L Ro
 Dominant pole
1
fp =
2π C L Ro
 Unity-gain frequency
Gm
=f t A=
v fp Gm R=
ofp
2π C L
 Discussion
Single-stage op amp: CL   fp1, ft   phase margin 
Two-stage op amp: CL   f p2   phase margin 

9-29
 Slew Rate: a large differential input signal is applied. (IB > I )
IB
IB − I
I I
SR =
CL
= 2π f tVOV 1

9-30
Ex10.2 Design of a folded-cascode op amp.
I = 200µA, IB = 250µA, and |VOV| = 0.25V for all transistors. VDD = VSS = 2.5V
Kn’ = 100µA/V2, Kp’ = 40µA/V2, |VA’| = 20V/µm. L = 1µm, CL = 5pF.
 Find ID, gm, ro and W/L

for all transistors.
2I D 2I D
gm
= =
VOV 0.25
VA 20
ro
= =
ID ID
W  2I Di
  = 2
 L i k 'VOV
Note: for all transistors

gmro = 160 V /V
VGS = 1.0 V

9-31
 Find the allowable range of VICM and of the output voltage swing. (p.9-29)
−1.25V ≤ VICM ≤ 3V − 1.25V ≤ vo ≤ 2V
 Determine the values of Av, ft, f p, and SR. (p.9-30, -32, -33)
Ro 4 = 160(200 80) = 9.14M Ω Ro 6 = 21.28M Ω
Ro Ro 4 =
= Ro 6 6.4M Ω
Av = Gm Ro = 0.8 × 10−3 ⋅ 6.4 × 106 = 5120V /V
Gm 0.8 × 10−3
=ft = = 25.5MHz
2π C L 2π ⋅ 5 × 10−12
ft  1  25.5MHz
=fp =  or =  = 5kHz
Av  2π C L Ro  5120
I 200 × 10−6
SR
= = = 40V / µs
−12
CL 5 × 10
 What is the power dissipation of the op amp?
PD =×
5V 0.5mA =
2.5mW

9-32
Rail-to-Rail Input Operation (Increasing VICM)
∆i =Gm (Vid /2)
G
= m g=
m1 g=
m2 g=
m3 gm 4
∆i ∆i
∆i
∆i
A folded-cascode op amp that employs

two parallel complementary input stages
to achieve rail-to-rail input CM operation.

9-33
 Output voltage Vo = 2Gm RoVid
 Assume that both differential pairs

Vo  are operating simultaneously.
 Voltage gain A
=v = 2Gm Ro
Vid
 Operation analysis:
Over the remainder of the input CM range, only one of two differential pairs
will be operational, and the gain drops to half.

9-34
Wide-Swing Current Mirror (Increasing the Output Voltage Range)
The minimum voltage allowed at the The minimum voltage allowed at the
output is Vt + 2VOV. output is 2VOV.

9-35
Homework-1
 Problems: 3, 5, 6, 8, 11,13,15,17

9-36
741 Op-Amp
 741 op-amp uses a large number of transistors but relatively few resistors
and only one capacitor .
− R and C occupy large silicon area .
− C needs more fabrication steps .
− High-quality R&C are not easy to fabricate.
 Circuit Diagram in next page.

1.9-37
741 Op-Amp
Bias
Input
stage
2nd
gain
stage
Class AB
Output
stage
Protecting
Bias
generation

1.9-38
1.9-39
741 Op-Amp Circuit
In keeping with the IC design philosophy the circuit uses a large number of transistors, but
relatively few transistors, and only one capacitor. This philosophy is dictated by the economics
(silicon area, ease of fabrication, quality of realizable components) of the fabrication of active
and passive components in IC form.
741 op-amp consists of three stages

1)Input differential stage
2)Single-ended high-gain stage
3)Output-buffering stage

1.9-40
Bias Circuit: Q11 , Q12, Q10, R4, Q8, Q9, Q13
Bias current IREF is generated in the branch, consisting of the two
diode-connected transistors Q11 and Q12 and the resistance R5.
Using a Widlar current source formed by Q11, Q10, and R4, bias
current for the first stage is generated in the collector of Q10.
Another current mirror formed by Q8 and Q9 takes part in biasing
the first stage.
Double-collector PNP Q13:  Current mirror:
VCC VCC
IO AE (Q A )
≈
Q13A I REF AE (QB )
Q13B Q13B Q13A
AE is emitter area.
Microelectrics (III) 10-41 許恒銘--中興大學電機系

The Input Stage: Q1 ~ Q7, R1 ~ R3.
− Biased by Q8, Q9, and Q10 provide high
input impedance.
− Q3 and Q4 are lateral PNP (low β) higher
emitter-base junction breakdown than
NPNs.
 protect input transistors Q1 and Q2
when they are accidentally shorted to
supply voltages.
− Q5 ~ Q7, R1 ~ R3 provide high-resistance
load and single ended output.
− Level shifter : Q3 and Q4

The Second Stage: Q16, Q17, Q13B, R8, R9
− Q16 acts as an emitter follower, thus
giving
1. high input resistance
2. low base current if R9 is large,
hence low loading of the first stage.
− Q17 :common base configuration
active load formed by Q13B (active
load is better than resistor load).
− CC: Miller capacitor for pole-splitting
compensation 30PF area occupied is
about 13 times that of a standard
NPN transistor.

The Output Stage:
1) provide low output resistance
2) class AB
The 741 uses an efficient class AB output stage,

which consists of the complementary pair
Q14 and Q20 with biasing devices Q13A, Q18
and Q19, and an input buffer Q23. (where Q20
is a substrate pnp.)
Short-Circuit Protection Circuitry

Transistors Q15, Q21, Q24, and Q22,
and resistors R6 and R7 serve to protect the
amplifier against output short circuits and these
transistors are normally off.

1.9-44
 Device Parameters:
 The standard transistors:
npn: IS = 10−14 A, β = 200, VA = 125 V
pnp: IS = 10−14 A, β = 50, VA = 50 V
 The nonstandard transistors: Q13, Q14, and
Q20.
Q13A : ISA = 0.25×10−14 A
Q13B : ISA = 0.75×10−14 A
Q14 & Q20 : IS = 3×10−14 A (have an area
three times that of a standard device)
Output transistors usually have large areas in
order to be able to supply large load currents
and dissipate relatively large amounts of
power with only a moderate increase in the
device temperature.

1.9-45
Output Stages (in Chap. 13)
 Class A output stage: Emitter follower
Large power is dissipated in the transistor!!

1.9-46
Output Stages
 Class B output stage
There exists an range of vI centered around zero

where both transistors are cut off and vO is zero.
This dead band results in the crossover distortion!!

1.9-47
Output Stages
 Class AB output stage

1.9-48
Reference Bias Current & Input-Stage Bias
 Reference bias current
VCC − VEB12 − VBE11 − ( −VEE )

I REF = 0.73 mA
R5
 Input-stage bias
Widlar current source:
VBE11 − VBE10 = I C10R 4

I 
⇒ VT ln REF  = I C10R 4
 I C10 
⇒ I C10 = 19 µA (solved by trial and error)

1.9-49
I C1 = I C 2 ⇒ IE3 = IE4 ≈ I (High β )
2I
IC 9 = pp: 509, Eq.(6.69)
1+ 2 β
⇒ 2I ≈ I C10 (β >> 1)
For the 741, IC10 = 19 µA, thus I ≈ 9.5 µA.

We have IC1 = IC2 ≈ IC3 = IC4 = 9.5 µA

1.9-50
Neglect the base current of Q16, then
IC 6 ≈ I
Neglect the base current of Q7, then

IC 5 ≈ I
Bias current of Q7: (KCL at node-A)
node-A 2I VBE 6 + IR2
IC 7 ≈ I E 7 = +
βN R3
Determine VBE6 : (IS = 10−14 A)

I 
VBE 6 = VT ln  = 517 mV
 IS 
⇒ I C 7 = 10.5 µA

1.9-51
I B1 + I B 2
 Input bias current IB =
2
I
For the 741, IB =  Using βN = 200, yields IB = 47.5 nA.
βN
Much lower input bias currents can be obtained using an FET input stage.
 Input offset currents
Because of possible mismatches in the β mismatch, the input offset current is defined as
I OS = I B1 − I B 2
 Input offset voltage
The input offset voltage is determined primarily by mismatches between the two sides of
the input stage. In the 741 op amp, the input offset voltage is due to mismatches between
Q1 and Q2, between Q3 and Q4, between Q5 and Q6, and between R1 and R2.
 Input common-mode range
− The input common-mode range is the range of input common-mode voltages over which
the input stage remains in the linear active mode.
− In the 741, the input common-mode range is determined at the upper end by saturation
of Q1 and Q2, and at the lower end by saturation of Q3 and Q4.

Second-Stage Bias
I C13B ≈ 0.75I REF ( βP >> 1)
⇒ I C13B = 550 µA and I C17 ≈ 550 µA
I 
VBE17 = VT ln C17  = 618 mV
 IS 
I E17R8 + VBE17
I C16 ≈ I E16 = I B17 + = 16.2 µA
R9

1.9-53
Output-Stage Bias
I C13 B ≈ 0.25 I REF ≈ I E 23
I C 23 ≈ I E 23 ≈ 0.25 I REF = 180 µA
VBE18 ≈ 0.6 V ⇒ I R10 = 15 µA
I E18 = 180 − 15 = 165 µA ≈ I C18

⇒ VBE18 = 588 mV
I B18 = 165 / 200 = 0.8 µA
⇒ I C19 ≈ I E19 = 15.8 µA
I 
VBE19 = VT ln C19  = 530 mV
 IS 
VBB = VBE18 + VBE19 = 1.118 V
I  I 
VBB = VT ln C14  + VT ln C 20 
 I S 14   I S 20 
I S 14 = I S 20 = 3 × 10−14 A
⇒ I C14 = I C 20 = 154 µA

1.9-54
Summary of Dc Bias of the 741 Circuit

1.9-55
Small-Signal Analysis of the 741 Input Stage
The differential signal vi applied between

the input terminals effectively appears
across four equal emitter resistances
connected in series – those of Q1, Q2, Q3,
and Q4.
vi
ie =
4re
VT 25 mV
where re = = = 2.63 kΩ
I 9.5 µA
The input differential resistance of the op

amp is
Rid = 4( β N + 1)re
For βN = 200, we obtain Rid = 2.1 MΩ.

1.9-56
Small-Signal Analysis of the Input Stage with Load Stage
 The output node of the input stage: output current io = 2αie .

The factor of two indicates that conversion from differential to single-ended is performed without
losing half the signal.
i α
 Transconductance of the input stage: G m1 ≡ o =
vi 2re
Substituting re = 2.63 kΩ and α ≈ 1 yields Gm1 = 1/5.26 mA/V.

1.9-57
Output Resistance of the First Stage
The output resistance of the input stage:

Ro1 = Ro4 || Ro6

1.9-58
Ro 4 = ro 4 + (1 + gm 4ro 4 )R 'E Ro 6 = ro 6 + (1 + gm 6ro 6 )(R2 rπ 6 )
≈ ro 4 (1 + gm 4R 'E ) ≈ ro 6 [1 + gm 6 (R2 rπ 6 )]
where R’E = re2 || rπ and ro = VA /I .  Ro6 = 18.2 MΩ

VA = 50 V, I = 9.5 µA,
and re2 = 2.63 kΩ.
 Ro4 = 10.5 MΩ
The output resistance of the input stage: Ro1 = Ro4 || Ro6 = 6.7 MΩ

Small-Signal Equivalent Circuit for the Input Stage of the 741 Op Amp
The equivalent circuit is a simplified version of the y-parameter model of a two-

port with y12 assumed negligible.
Rid = 2.1 MΩ
Gm1 = 1/5.26 mA/V
Ro1 = 6.7 MΩ

1.9-60
Ex: 10.3 mismatch in the Input Stage
Input stage with both inputs grounded and a mismatch ∆R between R1 and R2.
VBE 5 + IR = VBE 6 + (I − ∆I )(R + ∆R )

⇒ VBE 5 − VBE 6 = I∆R − ∆I (R + ∆R )
and VBE 5 − VBE 6 = I E 5re 5 − I E 6re 6 ≈ ∆Ire

∆I ∆R
⇒ =
I R + ∆R + re
A 2% mismatch between R1 and R2 :

 Substituting R = 1 kΩ, re = 2.63 kΩ, we have ∆I = 5.5×10−3 I.
 To reduce this output current to zero, we have to apply an input voltage VOS given by
∆I 5.5 × 10 −3 I
VOS = =
G m1 G m1
I = 9.5 µA, Gm1 = 1/5.26 mA/V  VOS ≈ 0.3 mV

1.9-61
Ex: 10.4 CMRR of 741 input stage Total resistor at node - Y :
R o = Ro 9 Ro10
KCL at node - Y :
2i vicm
2i + = , if β p >> 1
β p Ro
vicm
i≅ , io = ε mi
2 Ro
io ε mi ε m
Gmcm ≡ = =
vicm vicm 2 R o
Gm1
CMRR ≡ = 2 g m1Ro / ε m
Gmcm
CMRR = 2 g m1 ( Ro 9 Ro10 ) / ε m

1.10-62
2nd stage : Input Resistance & Transconductance
 Input resistance
R i 2 = ( β16 + 1)[re16 + R9 ( β17 + 1)(re17 + R8 )]
≈ 4 MΩ
 Transconductance
αvb17
ic17 =
re17 + R8
R9 Ri17
vb17 = v i 2
(R9 Ri17 ) + re16
Ri17 = ( β17 + 1)(re17 + R8 ) Small-signal equivalent circuit model:
ic17
 Gm 2 ≡ = 6.5 mA/V
vi 2

1.9-63
Output Resistance
Output resistance Ro 2 = Ro13B Ro17

where Ro13B = ro13B = 90.9 kΩ.
Since the resistance between the base of Q17 and ground is relatively small,
the base is about grounded.
Thus, Ro17 ≈ 787 kΩ, and hence Ro2 ≈ 81 kΩ.

1.9-64
Thevenin Equivalent Circuit
Note that the stage open-circuit voltage gain is −Gm2Ro2 .

1.9-65
Analysis of the 741 Output Stage
The output stage is of the AB class, with
the network composed of Q18, Q19, and
R10 providing the bias of the output
transistors Q14 and Q20.
The emitter follower Q23 provides added
buffering, which makes the op-amp gain
almost independent of the parameters
of the output transistors.

1.9-66
Output Voltage Limits
v o max = VCC − VCEsat − VBE14

v o min = −VEE + VCEsat + VEB 23 + VEB 20
(neglecting the voltage drop across R8 )

1.9-67
Small-Signal Model of the 741 Output Stage
the second stage
 Find Ri3:
 The input resistance looking into the base of Q20, RB20 ≈ β20RL = 50×2 kΩ = 100 kΩ.
 RB20 appears in parallel with the series combination of the output resistance of Q13A
(ro13A ≈ 280 kΩ) and the resistance of the Q18−Q19 network (very small).
 The total resistance in the emitter of Q23, RE23 ≈ 100 kΩ || 280 kΩ = 74 kΩ.
 The input resistance Ri3 ≈ β20RE23 = 50×74 kΩ ≈ 3.7 MΩ.
 Open-circuit voltage voltage gain, µ : µ = v o ≈1

vo 2 R =∞
L
 With RL = ∝, the gain of the emitter-follower output transistor (Q14 or Q20) will be
nearly unity.
 With RL = ∝ the resistance in the emitter of Q23 will be very large.

1.9-68
 Find the output resistance, Ro :
 Substituting Ro2 = 81 kΩ, β23 = 50, and re23 = 25/0.18 = 139Ω yields
Ro23 = 1.73 kΩ.
 For an output current of 5mA, re20 is 5 Ω and Ro = 39 Ω with β20 = 50.

1.9-69
Output Short-Circuit Protection
 If the op-amp output terminal is short-circuited to one of the power supplies,
one of the two output transistors could conduct a large amount of current.
 resulting in sufficient heating to cause burnout of the IC.
 Mechanism
 R6 together with Q15 limits the current that would flow out of Q14 in the
event of a short circuit.
 If the current in the emitter of Q14 exceeds about 20 mA, the
voltage drop across R6 exceeds 540 mV, which turns Q15 on.
 As Q15 turns on, its collector robs some of the current supplied by
Q13A, thus reducing the base current of Q14.
 This mechanism thus limits the maximum current that op amp can
source to about 20 mA.
 The relevant circuit is composed of R7, Q21, Q24, and Q22.
The current in the inward direction is limited also to about 20 mA.

1.9-70
1.9-71
Small-Signal Gain of the 741
Cascading the small-signal equivalent circuits of the individual stages for the
evaluation of the overall voltage gain
Overall gain:
vo vi 2 vo 2 vo RL
= = −Gm (Ro1 Ri 2 )(− Gm 2Ro 2 )µ
vi vi vi 2 vo 2 R L + Ro
vo
= −476.1 × (−526.5) × 0.97 = 243,147 V/V = 107.7 dB
vi

1.9-72
Frequency Response of the 741
Miller compensation technique – to introduce a dominant low-frequency pole
 A 30-pF capacitor (CC ) is connected in the negative-feedback path of the second
stage. The effective capacitance due to CC between the base of Q16 and ground is
Ci = CC( 1+ |A2|)
where A2 = −515, and hence Ci = 15,480 pF.
 The total resistance between the base of Q16 and ground is
Rt = (Ro1 || Ri2) = (6.7 MΩ || 4 MΩ) = 2.5 MΩ
 The dominant pole:
1
fP = = 4.1 Hz
2πCi Rt
 Unit-gain bandwidth
ft = A0×f 3dB ≈ 1 MHz
 Phase margin = −90o
In practice, PM ≈ −80o due to
nondominant pole.
This phase margin is sufficient to
provide stable operation of close-
loop amplifier with any value of
feedback factor β.

1.9-73
A Simplified Model Based on Modeling the Second Stage as an Integrator
Vo (s ) Gm1 G
A(s ) ≡ = ⇒ A( jω ) = m1
Vi (s ) sCC jωCC
G
Unity-gain frequency: ωt = m1
CC
ω
Substituting Gm1 = 1/5.26 mA/V and CC = 30 pF yields f t = t ≈ 1 MHz
2π
This model is valid only at frequency f >> f3dB. A such frequencies the gain
falls of with a slope of −20dB/decade, just like that of an integrator.

1.9-74
Slew Rate of the 741
 A unity-gain follower with a large step input
Since the output voltage cannot
change immediately, a large
differential voltage appears between
the op amp input terminal.
 Model for the 741 op amp when a large differential signal is applied
Output voltage:
2I
vO (t ) = t
CC
Slew rate:
2I
SR =
CC
For the 741, I = 9.5 µA and CC = 30 pF,
resulting in SR = 0.63×106 V/s.

1.9-75
Relationship Between ft and SR
 Gm1: Gm1 = 2 1
4re
where re is the emitter resistance of each of Q1 through Q4.
Thus,
V I
re = T and Gm1 =
I 2VT
G m1 I SR
 ωt: ωt = =  ωt =
CC 2CCVT 4VT
 SR: SR = 4VT ωt
For the 741 we have SR = 4 × 25 × 103 × 2π × 106 = 0.63×106 V/s.
 A general form for the relationship between SR and ωt for an op amp with a
structure similar to that of the 741 is
 2
SR =  ωt
a 
where a is the constant of proportionality relating transconductance of the
first stage Gm1, to the first-stage bias current I, Gm1 = aI.
For a given ωt , a higher value of SR is obtained by making a smaller;
 I = constant, Gm1 .

1.9-76
Home work-2
 Problems: 20,21,22,23,24,28,35,36,40,41,48,49,52

1.10-77

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Microelectronic Circuits (III)

National Chung-Hsing University

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Bias 1st stage 2nd stage

Microelectrics (III) 許恒銘--中興大學電機系

(W / L )6 (W / L )7 If this condition is not met, a systematic offset

 CC is Miller-multiplied by the gain of the second stage to provide the

Microelectrics (III) 許恒銘--中興大學電機系

 The lowest value of VICM has to be sufficiently large to

 The highest value of VICM should ensure Q5 in saturation.

Microelectrics (III) 許恒銘--中興大學電機系

Let IREF = 25µA, |Vt | (for all devices) = 1V, µnCox =

Microelectrics (III) 許恒銘--中興大學電機系

 Determine the voltage gain:

Microelectrics (III) 許恒銘--中興大學電機系

If this condition is not met, a

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

 Transfer function: (See Sec. 7.7.1)

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

 R = 1/Gm2, the zero can be placed at infinite frequency.

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

 (W/L)6 and (W/L)7:

Microelectrics (III) 許恒銘--中興大學電機系

 Slew rate: [Eq. (9.40)]

SR =2π f tVOV =2π ⋅ 171 × 106 × 0.316 =340V / µs

Microelectrics (III) 許恒銘--中興大學電機系

Ro = Ro 2C Ro 4C = (gm 2Cro 2Cro 2 ) (gm 4Cro 4Cro 3 )

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

 −VSS + VOV 11 + VOV 1 + Vtn ≤ V ICM ≤ VDD − VOV 9 + Vtn

 Output voltage swing:

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

 It is not very small for a single-stage op amp (OTA, operational

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

 Find ID, gm, ro and W/L

Note: for all transistors

Microelectrics (III) 許恒銘--中興大學電機系

 What is the power dissipation of the op amp?

Microelectrics (III) 許恒銘--中興大學電機系

A folded-cascode op amp that employs

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系

Microelectrics (III) 許恒銘--中興大學電機系