International Journal of Electronics

ISSN: 0020-7217 (Print) 1362-3060 (Online) Journal homepage: http://www.tandfonline.com/loi/tetn20

Design and Analysis of Low Power High Speed 1-Bit

Full Adder Cells for VLSI Applications

Venkata Rao Tirumalasetty & Madhusudhan Reddy Machupalli

To cite this article: Venkata Rao Tirumalasetty & Madhusudhan Reddy Machupalli (2018): Design
and Analysis of Low Power High Speed 1-Bit Full Adder Cells for VLSI Applications, International
Journal of Electronics, DOI: 10.1080/00207217.2018.1545256

To link to this article: https://doi.org/10.1080/00207217.2018.1545256

Accepted author version posted online: 05

Nov 2018.

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Publisher: Taylor & Francis

Journal: International Journal of Electronics

DOI: 10.1080/00207217.2018.1545256
Design and Analysis of Low Power High Speed 1-Bit Full Adder Cells
for VLSI Applications

Venkata Rao TIRUMALASETTY1 , Madhusudhan Reddy MACHUPALLI2

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1
Dept. of Electronics & Communications, Malineni Lakshmaiah Women’s Engg.
College, Guntur, Andhra Pradesh, India; 2Dept. of ECE, Research Scholar, JNT

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University Kakinada, 533 003 Kakinada, India

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Email: venkatarao.srp@gmail.com, machupalliphd@gmail.com

Venkata Rao TIRUMALASETTY was born in Sriranga Puram, Guntur, (A.P) and India
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in 1988. He received the B.Tech degree in Electronics and Communication Engineering
from J.N.T.University, Kakinada in 2009 and Master of Technology (M.Tech) in VLSI
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Design from Vignan University, Vadlamudi, Guntur, India in 2012. He is currently
working as an Assistant Professor in the Department of Electronics and Communication
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Engineering, K L University, Green fields, Vaddeswaram Guntur, Andhra Pradesh,

India. He has published over 5 articles in international journals and international
conference proceedings; his main research areas are microelectronics, low power VLSI
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design.

Madhusudhan Reddy MACHUPALLI was born in Deganavandla Palli, Y.S.R

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district, Kadapa, (A.P), India in 1988. He received the B.Tech degree in electronics and
communication engineering from Sri Venkateswara University, Tirupathi in 2009 and
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Master of Technology in VLSI Design from Vignan’s University, Guntur, India in

2012. He is now pursuing Ph.D. in low-power VLSI design at Jawaharlal Nehru
Technological University Kakinada, East Godavari, India.
Design and Analysis of Low Power High Speed 1-Bit Full Adder Cells
for VLSI Applications

This paper presents a low power and high speed two hybrid 1-bit full adder cells
employing both pass transistor and transmission gate logics. These designs aim
to minimize power dissipation and reduce transistor count while at the same time
reducing the propagation delay. The proposed full adder circuits utilize 16 and 14
transistors to achieve a compact circuit design. For 1.2 V supply voltage at 0.18-

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μm CMOS technology, the power consumption is 4.266 μW was found to be

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extremely low with lower propagation delay 214.65 ps and power-delay product

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(PDP) of 0.9156 fJ by the deliberate use of CMOS inverters and strong
transmission gates. The results of the simulation illustrate the superiority of the

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newly designed 1-bit adder circuits against the reported conservative adder
structures in terms of power, delay, power delay product (PDP) and a transistor
count. The implementation of 8-bit ripple carry adder in view of proposed full
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adders are finally verified and was observed to be working efficiently with only
1.411 ns delay. The performance of the proposed circuits was examined using
Mentor Graphics Schematic Composer at 1.2 V single ended supply voltage and
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the model parameters of a TSMC 0.18-μm CMOS.

Keywords: adders; Digital circuits; Pass-transistor-logic; Transmission gate

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logic; Power-delay product;

1. Introduction
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The Adder is one of the most important components of a CPU (central processing unit),
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arithmetic logic unit (ALU), floating-point units and an address generation unit such as
cache or memory access unit. It is extensively used in many VLSI systems such as
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application-specific DSP architectures and microprocessors [1]. In addition to its main

task, that is, adding two binary numbers, has been the most important block involving
multiple operations such as subtraction, multiplication, division, calculation of
addresses, and so on. In most of these systems, the adder is a part of the Critique that
determines the overall performance of the system. Therefore, improving the
performance of the 1-bit adder cell is an important goal.
Recently, the construction of low power VLSI systems has gained momentum
due to the rapid growth of technologies in mobile communication and computing.
However, battery technology does not show faster growth like microelectronics
technology. However, there is a limited amount of energy available for mobile systems
[2]. So designers face more restrictions like high speed, high performance, small silicon
area and at the same time low power consumption. So building low-power, a high-
performing adder cell is important in today's growing VLSI Technologies.

2. State of the Art

In recent years, several variants of different logical styles have been proposed to

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implement 1-bit adder cells [3] - [18]. There are two types of adder cells in the case of

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the logical structure. One is static and the other is dynamic style. The complete static

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logics (C-CMOS, CPL, TGA, TFA and hybrid) are usually more reliable, simpler and
consume less energy than dynamic adders. Dynamic is an alternative logic style to

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design a logical function. It has some advantages over static mode such as faster
switching speeds, no leakage power consumption, no rationale logic, full oscillation
voltage levels and fewer transistors. Many researchers have combined these two
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structures and proposed complete dynamic-static complex hybrid adders.

There are standard usages for the 1-bit adder cells, which are utilized as the
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reason for comparison in this report. A portion of the standard executions is as per the
following.
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The complementary CMOS (C-CMOS) 1-bit cell depends on the general CMOS
structure, which utilizes 28 transistors [4], [9]. The benefit of the complementary
CMOS style is its toughness against voltage scaling and transistor measure, which are
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basic to give solid low voltage operation with self-assertive transistor sizes. In any case,
it has more number of transistors to actualize the 1-bit adder cell which causes an
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expansive chip range and substantial info capacitance yet couldn't give fast operation.
The Complementary Pass Transistor Logic (CPL) with swing restoration, which
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uses 32 transistors [9], [10]. CPL adder produces many transitional nodes and their
accompaniment to give the outputs. This logic style gives fast and full swing outputs,
but due to the existence of a lot of internal nodes and static inverters, there is a lot of
energy dissipation. And also, CPL suffers from leakage power consumption due to the
low swing at the output inverters. The double-pass transistor (DPL) logic [5] and the
swing restored pass-transistor logic (SRPL) [5] are related to CPL.
The full adder based on CMOS (TG-CMOS) transmission gate is a unique type
of logic [6], [12]. The main drawback of TG logic is that it requires double the number
of transistors that pass-transistor logic or requires more to realize the equal circuit. The
complete adder cell of the TG gate requires 20 transistors. Similarly, the cell of the full
adder transmission function (TFA) [10] is based on the theory of the transmission
function and has 16 transistors. It displays better speed and less power dissipation than
the regular CMOS adder cell because of the little transistor stack stature.
Another logic styles are branch-based logic and pass-transistor (BBL-PT) ([13],
[14] and [17]) based current sink full adder uses 23 transistors. It gives normal and
minimized design structures and diminishes the diffusion capacitances (since it

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facilitates diffusion sharing). The main advantage of BBL-PT based full adder having
low static power dissipation. The disadvantage of current sink based BBL-PT full adder

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[14] implementation has high power consumption and low driving capabilities.

Afterward, researchers concentrated on the mixture rationale (hybrid logic)

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approach that exploited the attributes of various logic styles keeping in mind the end
goal to enhance the overall performance. This logic (hybrid) style gives the flexibility
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to take the ideal circuits for each module for getting the ideal performance of 1-bit
adder cell. Every module is exclusively outlined such that the whole 1-bit cell circuit is
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streamlined as far as power, delay and required area.
Previously proposed techniques, new 14-transistor (14T) 1-bit adder [7] utilizes
more than one rationale style for their realization. In the same way, the hybrid pass-
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logic (HPSC) [16] full adder, new HPSC [8] full adder and hybrid –CMOS adder [11],
[15] are utilizing more than one rationale style for their realization. In such HPSC
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circuit, XOR and XNOR circuits were concurrently created by pass-transistor logic by
utilizing just six transistors, furthermore, utilized in CMOS module to deliver full-
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swing outputs of the 1-bit adder cell however at the cost of the increased transistor
count and diminished speed. These adders, for the most part, do not have the driving
abilities. Their execution as a 1-bit cell is excellent, however as the measure of chain
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expands, the execution decreases radically. In spite of the fact that the hybrid styles
offer promising execution, the majority of these hybrid logic adders experienced a poor
driving capacity issue and their execution debases definitely in the cascaded mode of
operation if the appropriately deliberate buffers are not incorporated.
In this paper, we have conveyed to give 1-bit adder cells with the hybrid style to
give a low power, high switching, low energy consumption (PDP) by use of
consolidation CMOS inverters combined with solid transmission gates.
 For the low power realization, a cell schematic must be actualized with a couple
of transistors and intra-cell nodes associations beyond what many would consider
possible. The proposed 1-bit adder circuits meet these necessities while guaranteeing
sturdiness concerning voltage and device scaling. The rest of the paper is organized as
follows. In Section 3, consists of the implementation of proposed full adder 1 with
corresponding XOR-XNOR, sum and carry circuits, Section 4 consists of the
implementation of proposed full adder 2 circuit and Section 5 explains simulation
results. The usage of an 8-bit RCA in light of the proposed 1-bit adder is depicted in

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Section 6 lastly in Section 7 ended up with a conclusion.

3. Proposed 1-Bit Full Adder Cell Implementation

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The proposed 1-bit adder circuit is represented by three modules as appeared in Fig. 1.

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Module I is an XOR-XNOR circuit which drives alternate modules. Module II and
Module III are the sum and carry circuits which utilize the output of module I and the
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third input signal (Cin) as input contribution to create the sum and carry outputs
individually.
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Cin
Module II Sum

B
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Module I
A
Module III Cout
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Figure.1. Schematic structure of proposed full adders

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The essential cell in computerized systems is the 1-bit adder cell having three 1-
bit inputs (A, B, Cin) and two 1-bit outputs (sum and carry (Cout)). The relationship
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between the inputs and the outputs is expressed as

Y = A⊕ B (1)

Y = A⊕ B (2)

Sum = Y ⊕ C in (3)

C out = A ⋅ B + C in ⋅ Y (4)
 In the hybrid logic, we obtain XOR and XNOR of the inputs A and B as the
intermediate signal at the output of the module I. These input signals and Cin are
accessible for the input of Modules II and III. So we get new sum and carry expressions
utilizing XOR output Z and XNOR output Z .
Sum = Z ⊕ C in = Z ⋅ C in + Z ⋅ C in

(5)

C out = A ⋅ Z + C in ⋅ Z (6)

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3.1 XOR-XNOR Circuit

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The circuit of Module I is an XOR-XNOR circuit. It uses a concept of pass transistor
logic. The circuit consists of CMOS current source structure (M1-M2) and output

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transistors (M3-M4) as shown in Fig. 2. The current source is a common gate design
utilizing a p-channel transistor with a gate associated with a fixed bias supply; because
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of this, the P-transistor is dependably in ON condition; while the N-transistor serves as
a pull-down network. This structure accomplishes higher voltage gain than dynamic
load structures.
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It can be seen that the output signal has a good logic level of input signals (A,
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B) = (0, 0), (0, 1), (1, 1). For the (A, B) = (0, 0) configuration, each pMOS transistor is
switched on and passes a weak logic ‘0’ (i.e. Vtp). In order to enhance the driving
capability at the output nodes, uses a CMOS inverter and provides XNOR output Z .
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M1 M3
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A M2 M4
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Figure 2. Proposed XOR-XNOR circuit

3.2 Sum Circuit

Module II represents a summing circuit as shown in Fig. 3. The expression of the sum
(5) shows that module II circuit is only an XOR circuit. For an XOR gate when input Z
will be at logic ‘0’ then output will follow the other input, it can be implemented by
using one nMOS (M2) to pass logic ‘0’ by connecting the gate terminal with Z , source
terminal with Cin and drain terminal at the output, and one pMOS (M1) to pass the logic
‘1’ by connecting the source terminal with Cin, gate terminal with Z and drain with the
output. When Z is at logic ‘0’ and Z at logic ‘1’ then both transistors (M1 & M2) are in
ON condition and output is connected to Cin. So when Cin is at logic ‘1’ output is
connected to logic ‘1’ and when it is at logic ‘0’ output is also be connected to logic ‘0’.
Both the transistors are in OFF condition for Z to be at logic ‘1’. Thus, using the
transmission gate (M1 & M2) logic there will be no voltage drop problem, whether
logic ‘1’ or logic ‘0’ is passed through it. It provides full voltage swing at the output.

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Cin

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M1
Cin

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an M2 Sum Cin

Cin
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Figure 3. Proposed full adder sum circuit

At the point when the Z and Cin inputs are in the logic '1', at that point the output
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is low; it can be realized by associating two nMOS in arrangement with its gate
terminals associated with Z and Cin. The source terminal of one of the nMOS is
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associated with the ground terminal and alternate nMOS source terminal is associated
with the output. Likewise, when Z is in logic '1' and Cin in logic '0', the output is in
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logic '1', so we utilize two pMOS in arrangement with the source terminal of one of the
pMOS in high logic (VDD), drain terminal of alternate pMOS at the output and the gate
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terminals are associated with Z and Cin correspondingly. At the point when both inputs
(Z and Cin) are in logic '1', at that point nMOS transistors are ON; due to this output is
connected to the ground i.e. output is logic ‘0’. When Z is at logic ‘1’ and Cin is at
logic ‘0’, both inputs Z and Cin is at logic ‘0’ then the pMOS transistors are in ON
condition and output is directly connected to supply voltage i.e. output is logic ‘1’.
Once the series connected nMOS/pMOS transistors are in on condition; the output sum
is directly connected to supply voltage (logic ‘1’) or ground (logic ‘0’). Because of this,
the full swing output can be achieved without any degradation of the voltage levels at
the output of the sum.

3.3 Carry Circuit

If the A = B, at that point Cout = B; If not, Cout = Cin.

Cin A
Mp2

Mp1

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Cout

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Mn1
Mn2
Cin B

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Figure 4. Proposed 1-bit adder carry circuit
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A Cin

Cin
B
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Sum Cin
A
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Cin
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Cin A
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Ac

Cout

Cin B
Figure 5.Proposed 1-bit full adder 1 circuit using pass-transistor and transmission gate logics

The circuit of Module III is a multiplexer that chooses Cin if Z is at logic ‘1’ or
chooses A or B as the output of Cout as appeared in Fig. 4. In the proposed circuit we
utilize the transmission gate with Z and Z at the gate terminals of Mn1 and Mp1
separately to pass the Cin to Cout for Z at logic ‘1’ or when additional inputs A and B are
at various logic levels. At the point when Z is in logic ‘0’ or both inputs A and B are on
the similar logic level, we need to pass any of these inputs to the output. So we utilize a
pMOS (Mp2) and a nMOS (Mn2) to pass input A through one transistor and another
input B through another transistor. By using these two inputs from two sides, improves
circuit performance. The input carry signal (Cin) propagates just through a single
transmission gate (Mn1 and Mp1), significantly reducing the overall carry propagation
path. The utilization of solid transmission gates (channel width of transistors Mn1,
Mp1, Mn2, and Mp2 becomes large) ensured a diminishment in the propagation delay

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of the carry signal.
The new 1-bit adder circuit 1 proposed as shown in Fig. 5. It can be

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implemented using XOR-XNOR, sum and carry circuits presented in Fig. 2, 3 and 4.
All the three modules can be interconnected based on the proposed schematic structure

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as shown in Fig. 1. It uses only 16 transistors, for generating the sum and carry as the
outputs.
4. Design of Proposed Full Adder 2
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For reducing the number of transistor count; full adder (FA) 2 was proposed, which
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uses 14 transistors only. It is the alternative logic for generating the sum and carry
outputs. The proposed 1-bit adder 2 sum circuit as shown in Fig. 6. And the carry
circuit is shown in Fig. 4. For both the adders XOR-XNOR and carry circuits are same;
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only sum circuit is different. The sum output of the 1-bit adder is realized by XOR-
XNOR modules and uses just 6 transistors.
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The sum output of the 1-bit adder is realized by XOR-XNOR modules and uses
just 6 transistors. The pMOS transistors and the nMOS transistors perform the second
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stage XNOR module to execute the entire sum function. The second stage XNOR
module can be realized utilizing the transmission gate logic. It provides stronger 1’s and
stronger 0’s at the output, i.e. full swing output can be achieved without any
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degradation of voltage levels in the sum output. Cin

Cin

Sum

Cin
 Figure 6. Proposed full adder 2 sum circuit

The new 1-bit adder circuit 2 as shown in Fig. 7. It can be implemented using
XOR-XNOR, carry and sum (Fig. 6) circuits presented in Fig. 2, 4 and 6. It uses only
14 transistors, for generating the sum & carry outputs. Using of series connected
nMOS/pMOS transistors and strong transmission gates in the design of proposed sum
& carry circuits; provides full voltage swing and makes our design better than the
reported adders in the paper [9], [10] and [14].
Cin

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A

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B Cin

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Sum
A
an Cin
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Cin A
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Cout
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Cin B
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Figure 7. Proposed 1-bit adder circuit 2 using pass-transistor and transmission gate logics.

5. Simulation Results
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The transient analyses of the proposed 1-bit adders are simulated using Mentor
Graphics Schematic Composer and the model parameters of a 0.18-μm CMOS
technology. The simulations were performed with the supply voltage Vdd = 1.2 V and
frequency of 100 MHz. A comparison is included with existing or already reported
designs, which demonstrates the benefit of the proposed 1-bit adders, good power-delay
product, and the results have appeared in Tab. 1. Transistors size has been optimized in
order to minimize the PDP. While optimizing the transistor sizes of 1-bit adders are
considered, it is conceivable to decrease the delay of all 1-bit adders without
significantly expanding the power utilization. All the transistor sizes (Except transistors
Mn1, Mp1, Mn2, and Mp2) for the proposed 1-bit adders are shown below and level 54
model of MOS transistors with Vtn ≅ 0.34 V and Vtp ≅ –0.39 V were used.
W = 0.5 μm and L = 0.18-µm for pMOS
W = 0.3 μm and L = 0.18-μm for nMOS
To break down the achievement of the proposed 1-bit adders amid its real use in
VLSI-applications, a practical simulation environment setup as appeared in Fig. 8. To

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provide a practical environment, buffers are added at the input and the output of the test
bench [3], [11]. The two inverters with same W/L have been used to make the input and

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output buffers. The transistor size of buffers is two for pMOS and one for nMOS.

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Buffer
Buffer
A
Full Adder Sum
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B Under
Cout
Test
Cin
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Figure 8. Proposed simulation test bench

Table 1 summarizes the pre-layout simulation results. It can be seen that the
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CPL FA demonstrates better delay and PDP in comparison to the CMOS FA.
Conversely, it shows the highest total and static power dissipations due to its higher
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transistor number. The BBL-PT and Current sink FA outperforms lowest leakage power
dissipation; since in this logic cells are designed exclusively with branches composed of
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transistors connected in series between a supply line and the gate output. Regarding
TFA & TGA FAs, demonstrates higher delay and PDP than all full adders because of
the higher number of transistors on the critical path within the sum block. The proposed
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full adders’ having minimum leakage power dissipation and outperforms the other full
adders in both delay and PDP; since a small number of transistors on the paths between
the power supply lines and the output nodes and a reduced parasitic capacitance at the
sum and carry output nodes.

Load Analysis: Output load is one of the significant parameter that affects power and
performance of the circuits. Here we changed the output loads from 2 fF to 10 fF. A
fixed value 1 fF capacitance has been added at the output of the buffer circuit.
Minimum output load for all the simulation is 2 fF. The proposed circuits have been
optimized at 1.2 V supply voltage with 2 fF output load. 16T is the best circuit in terms
of power consumption since it has the least power consuming for all values of output
load.

Table 1. Performance comparisons and pre-layout simulation results of the proposed &
alternative implementations of 1-bit full adder cell with Vdd = 1.2 V at 0.18-μm CMOS
technology.

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Leakage

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Delay Transistor
Design Power(µW) PDP (fJ) Power
(Ps) Count

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(nW)

CMOS [4], [9] 6.28 304.25 1.91069 0.9 28

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CPL [9], [10] 7.795 194.41 1.51542 1.4 32

BBL-PT [13] 7.265 290.48 2.11033 0.66 23

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Current Sink FA 7.859 231.56 1.82700 0.76 23

[14]
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TFA [10] 8.346 288.51 2.407904 1.3 16

TGA [12] 8.534 295.32 2.52203 1.2 20

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1-Bit Adder [19] 4.153 224 0.931 1.4 16

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Proposed Full 4.266 214.65 0.9156 0.95 16

Adder 1

Proposed Full 5.164 221.34 1.1429 1.1 14

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Adder 2

The proposed adder circuits can be best analyzed by performing post-layout

simulation on the extracted circuit net-list. Table 2 summarizes the post-layout
simulation results. The detailed (transistor-level) simulation performed using the
extracted net-list will provide a clear assessment of the circuit speed & power
consumption, the influence of circuit parasitics (such as parasitic capacitances and
resistances), and any glitches that may occur due to signal delay mismatches.
Table 2. Performance comparisons and post-layout simulation results of the proposed &
alternative implementations of 1-bit full adder cell with Vdd = 1.2 V at 0.18-μm CMOS
technology.
Leakage
Delay Transistor

t
Design Power(µW) PDP (fJ) Power

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(Ps) Count
(nW)

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CMOS [4], [9] 8.137 318.36 2.590 1.82 28

9.862 205.61 2.027 2.54 32

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CPL [9], [10]

BBL-PT [13] 9.423 304.88

an 2.872 1.054 23

Current Sink FA 10.153 244.35 2.480 1.85 23

[14]

TFA [10] 10.562 299.85 3.167 2.45 16

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TGA [12] 10.854 312.67 3.393 2.64 20

5.785 242.546 1.403 2.23 16

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1-Bit Adder[19]

Proposed Full 5.893 228.85 1.348 1.61 16

Adder 1
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Proposed Full 6.972 242.62 1.691 2.37 14

Adder 2
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The delay parameter is calculated from the time that the input reaches 50% of
the power supply level, to the time that the output reaches the same voltage is shown in
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Fig. 9.
Rise time and fall time of input signals in all simulations are 5% of the pulse

width. Rising and falling propagation delay are separately measured for both sum and

carry. The maximum delay of all the transitions is taken as the cell delay. The

propagation delay times τ PHL and τ PLH determine the input-to-output signal delay

during the high-to-low and low-to-high transitions of the output, respectively [18]-[21].
The τ PHL is defined as, the time required for the output voltage to fall from V OH to the

V 50% level, and τ PLH becomes the time required for the output voltage to rise from V OL to

the V 50% level.

Vin

VOH

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V50%

VOL

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VOL
t

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Vout ĩPHL
an ĩPLH

VOH
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V50%

VOL
t
ed

t0 t1

Figure 9. Propagation delay calculation

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The voltage point V 50% is defined as follows

1 1
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V 50%= V OL + (V OH − V OL) = (V OL + V OH )
2 2 (7)
Thus, the propagation delay times τ PHL and τ PLH are found in Fig. 9 as
τ PHL = t 1 − t 0
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τ PLH = t 3 − t 2

(8) The average propagation

delay τ P is given by

τ PHL + τ PLH
τp= (9)
2
The power delay product (PDP) is the product of average power consumption and
worst-case delay as indicated by the condition
PDP = Power average ∗ Delay worst − case (10)

The simulated input and output waveforms of the proposed 1-bit adders for sum and
carry are shown in Fig. 10 and Fig. 11. In simulated waveforms, the inputs (A, B & C)
applied for all possible combinations i.e. 000 to 111. The circuits are simulated at
supply voltages range from 1 to 2.4 V. The supply voltage for proposed circuits is 1.2

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V.

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Figure 10.Simulated input & output waveforms of the proposed 1-bit full Adder 1 circuit.
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Figure 11.Simulated input & output waveforms of the proposed 1-bit full adder 2 circuit
6. Performance of 8-Bit RCA

An 8-bit ripple carry adder (RCA) is executed as an augmentation of the proposed 1-bit
adders. The full adder circuits designed in this paper can now be used as the basic
building block of an 8-bit ripple carry adder as shown in Fig. 12.
A0 B0 A1 B1 A2 B2 A7 B7

C0 C1 C2 C3 C7 Cout
FA0 FA1 FA2 FA7

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S0 S1 S2 S7

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Figure 12.8-Bit RCA using proposed 1-bit full adder
The performance estimation of the 8-bit parallel adder was carried out in 0.18-
µm technology with and without utilizing intermediate buffers at suitable stages (after
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the three stages). Simulated delay results are summarized in Table 3.

Table 3. Performance comparisons of the proposed and alternative implementations of

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8-bit RCAs with Vdd = 1.2 V at 0.18-μm CMOS technology.

Design Delay(ns) Transistor Count

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CMOS [4], [9] 2.253 224

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CPL [9], [10] 1.289 256

BBL-PT [13] 2.19 184

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Current Sink Full Adder [14], [17] 1.642 184

TFA [10] 2.184 128

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TGA [12] 2.237 160

Proposed Full Adder 1 1.411 128

Proposed Full Adder 2 1.689 112

It can thus be seen that the proposed hybrid logic based 8-bit RCAs and CPL 8-
bit RCA [9] shows the best delay performance than the already existing & reported 8-
bit RCAs as shown in Table 3. Both the proposed circuits having good driving
capability are achieved through the strong transmission gates; since the input carry
signal (Cin) propagates only through a single transmission gate for 1-bit, significantly
reducing the overall carry propagation path. And also, the CPL 8-bit RCA has the good
driving capability. But, CPL based, full adder has high transistor count and it consumes
more power.

The layouts of the proposed full adder circuits have been designed using mentor
graphics IC station layout tool with TSMC 0.18-µm CMOS technology. The minimum

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channel length is utilized for all devices and the optimal channel width is precisely

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decided for every device so as to accomplish the functionality verified with low power
dissipation and lowest feasible propagation delay. The silicon area of the full adder 1

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(excluding buffers) circuit was 7.585 m × 6.840 m (≈51. 88 sq⋅ m) as shown in Fig.
13. The silicon area of the full adder 2 (excluding buffers) circuit was 6.545 m × 7.410

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m (≈48.498 sq⋅ m) as shown in Fig. 14. With respect to the implementation area
acquired from the layouts, it can be observed that the proposed 1-bit adders require the
an
smaller area. It can likewise be considered as one of the variables for the lower delay
and power utilization since it involves smaller parasitic capacitances that are driven
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within the 1-bit adder. The design area (excluding buffer) in the present design is larger
(5.34%) than that of TFA, which is additionally contained of 16 transistors [10].
However, the main concern of the proposed 1-bit adder 1 configuration was the
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minimization of Power-delay product (PDP), which turned out to be significantly

enhanced (≈63%) as for the design of TFA [10].
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 Figure 13.The layout of the proposed full adder 1 circuit in 0.18-µm technology

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Figure 14.The layout of the proposed full adder 2 circuit in 0.18-µm technology

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The performance of the proposed 1-bit adder circuits as for as propagation delay
with a change in supply voltage ranging from 1.0 to 2.4 V shown in Fig. 15. It is shown
that proposed ones, current sink based and CPL based full adders have better delay
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performance than the alternative 1-bit full adder implementations. The simulation
results show that CMOS, TFA, TGA, CPL and proposed full adders can work reliably
as supply voltage as low as 0.8 V. In spite of the fact that TFA and TGA have a lower
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transistor count, because of the absence of drivability, additional buffers are required
for each output, increasing its leakage power and switching power.
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pt
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Figure 15. Delay vs. Supply voltage comparison of proposed and alternative implementations of
1-bit full adders
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ip
cr
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Figure 16.Power vs. Supply voltage comparison of proposed and alternative
implementations of 1-bit full adders
an
M
ed
pt
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Figure 17.Power Delay Product (PDP) vs. Supply voltage comparison of proposed and
alternative implementations of 1-bit full adders.
The proposed 1-bit adder 1 has the lowest power consumption compared to the
other simulated adder circuits. The results are plotted as shown in Fig. 16. The average
power consumption of the proposed 1-bit adder circuit 1 is 4.266 µW, which was
reduced essentially by use of consolidation CMOS inverters combined with solid
transmission gates for 1.2 V supply voltage. To obtain average power consumption and
worst-case delay all possible input patterns are applied. It is shown that proposed ones
and CMOS full adders are the most power efficient cells. Proposed ones are faster than
CMOS and as a result, these are exhibits smaller power delay product and results are
enunciated in Fig. 17. The power delay product is a fundamental parameter which is
often used for measuring the quality and performance of a circuit. The average power
utilization is measured with the similar input settings and a similar input range as for
the propagation delay estimation. Among all the full adder circuits, proposed full adder
1 has a minimum PDP, which proved significantly improved 52% with respect to

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CMOS & CPL implementations, 57% with respect to branch based logic-pass transistor
implementation and 62% with respect to TFA & TGA circuits.

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7. Conclusion

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Hybrid-CMOS design style gives more freedom to the designer to select different
modules in a circuit depending upon the application. In this paper, low-power hybrid 1-
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bit full adders have been proposed and the design has been extended for the 8-bit case
also. The simulation results show that proposed hybrid full adder circuits have better
performance in terms of power, delay and PDP with a supply voltage ranging from 1.0
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V to 2.4 V than most of the standard full-adder cells owing to the novels design
modules proposed in this paper. Among all the adders, the proposed new hybrid full
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adder 1 is the best circuit in terms of power, speed and energy saved (PDP). Therefore,
it remains one of the best contenders for designing large arithmetic circuits with low
power consumption and reduced energy consumption while keeping the increase in area
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to a minimum.
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