Evaluation of Stability, Performance of

Ultra-Low Voltage TFET SRAM Cell With

Write-Assist Circuits

Kota Vinay Mishra Vishal Khairnar Nirman Dr. Sri Adibhatla Sridevi
VLSI Design VLSI Design VLSI Design Department of Micro and
VIT University, Vellore VIT University, Vellore VIT University, Vellore Nano Electronics
Kota.vinay2019@gmail.com Mishra.vishal1996@gmail.c nirmankhairnar7@gmail.co VIT University, Vellore
om m

Abstract— The down-scaling of conventional MOSFETs has

led to an impending power crisis, in which static power
consumption is becoming too high. In order to improve the
energy-efficiency of electronic circuits, small swing switches are
used to replace the MOSFETs used today. The stability and
performance of the proposed TFET 8T cell are used on TCAD
simulations based on published design rules for 20 nm technology
node. Tunnel FETs, which are gated p-i-n diodes whose on-
current arises from band-to-band tunneling, are attractive new
devices for low-power applications due to their low off-current
and their potential for a small sub threshold swing.

Keywords— Band-to-band tunneling, gated p-i-n diode, sub

threshold swing, tunnel field effect transistor (FET). TFET SRAMs, Fig:8T SRAM CELL
ultra-low voltage, write-assist circuits.
Write Operation:
INTRODUCTION During write 1 operation, Transistor M5 turns-on by enabling the
The introduction to the TFET is as follows, it includes its structure write word line signal. When the Bit Line‟ is imposed to logic1, then
and operation. A derivation of a band-to-band tunneling transmission Q node starts charging and turns on Transistor M1 which cause to flip
is carried out, and then the non-constant sub threshold swing of the Qbar node to logic 0. Now Qbar node helps enabling the Transistor
Tunnel FET is done, and some definitions are given. and then the M4 which facilitates writing good logic 1 at Q node. On the other
most important models used for the simulations in this thesis are hand, during write 0 operation, the Bit Line is imposed to logic 0 and
presented. The Small swing switches are introduced, and then in Transistor M5 turns-on by enabling write word line signal. The Q
particular, the Tunnel FET is described and its operation explained node starts discharging and turns on TransisitorM2 which in turn
and Finally, the history and state of-the-art of the Tunnel FET are flipped Qbar node to logic 1. Now Qbar node helps turning Transistor
given. Tunnel field-effect transistor (TFET) device with the band-to- M3 on, which facilitates discharging Q node properly and
band tunneling as the major current transport mechanism enables consequently logic 0 is obtained at Q node.
steeper than 60 mV/dec subthreshold swing, and is considered as a
promising device to replace MOSFET device for ultra-low Read Operation:
voltage/power operation. Read operation is performed by using MOSFETs M6, M7 and M8.
Node Qbar is connected to the gates of M7 and M8. In this case, a
SRAM current flows.
Static RAM is a memory unit, capable of storing one bit
(logic0/logic1)at a time.Two inverters are cross-coupled to form a
basic SRAM.Most of the electronics devices are manufactured with
this memory units.
READ AND WRITE OPERATION
Write access to the cell occurs through the write access transistors
and from the write bitlines, BL and BLB. Read access to the cell is
through the read access transistor and controlled by the read
wordline, RWL. The read bitline, RBL, is given to read access.
 Fig. (a). Design of 8T SRAM Circuit using MOSFET
Fig:n-type TFET and p-type TFET
READ AND WRITE WAVEFORMS:
TFET:
The read and write waveforms of 8T SRAM cell are shown in Figure The basic TFET structure is similar to a MOSFET except that the
below. During the read the output is taken from read path and word source and drain terminals of a TFET are doped of opposite type .
line remains active high during write operation the input is applied at A common TFET device structure consists of a P-I-N (p-
Bit Lines and WL is asserted. During hold the WL remains off and type, intrinsic, n-type) junction, in which the electrostatic
cell is in idle state. potential of the intrinsic region is controlled by a gate terminal.

Fig. (b).Output Waveform

SIMULATION RESULTS:

The threshold voltage of pull down transistor is reduced by .

connecting body of the transistor to the negative terminal. Threshold Fig. Basic Schematic Of TFET
voltage of only NMOS transistor is increased because increase in Vth
results in increase in delay. That is speed of the circuit reducesto a DEVICE OPERATION:
greater extent. In first proposed work the pull up PMOS transistors The device is operated by applying gate bias so that electron
are stacked and threshold voltage of pull down transistors is increased accumulation occurs in the intrinsic region. At sufficient gate bias,
by reverse biasing its body. In second circuit pull down transistor is band-to-band tunneling (BTBT) occurs when the conduction band of
reverse biased and read Bit line path NMOS and PMOS are fixed. In the intrinsic region aligns with the valence band of the P region.
third circuit both pull up transistor and read line transistors are Electrons from the valence band of the p-type region tunnel into the
stacked and pull down. conduction band of the intrinsic region and current can flow across
the device. As the gate bias is reduced, the bands becomes misaligned
DEVICE DESIGN: and current can no longer flow.
Direct BTBT: In direct band to band tunneling,electrons travel across
In this work, we consider the PNPN type TFET for its capability to valence band and conduction band without absorbing or emitting
achieve sub-threshold swing below 60 mV/dec at room temperature. phonon.This type of tunneling takes place in GaAS,InAs etc.
The device structures of the PNPN TFET, NPNP TFET are shown in
Fig. a.Double-gate (DG) InAS structures are used, with the gate InDirect BTBT: In indirect band to band tunneling,electrons
length 20 nm, silicon body thickness 5 nm, equivalent oxide undergoes a change in momentum as they travel from valence band
thickness 0.6 nm, the source/drain doping of 4*10 19 cm-3 (p+) and to conduction band due to the absorption or emission of phonon. This
6*1017cm-3(n+).The TFET circuits are analyzed using TCAD type of tunneling takes place in silicon,germanium etc.
simulations.The PNPN TFET device can be seen to have superior
current drive and sub threshold slope at very low gate bias.While at DESIGN OF TCAD:
high gate bias, the current drive of PNPN TFET device is inferior to
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Radius of Silicon core

parameters NTFET PTFET

Threshold voltage(vtn) 0.24652V
Ion 16.8607ohm
Ioff 9.16544*10-6 A
Ron 0.00002573A
Idsat 0.000108155A

CONCLUSION:

The proposed 8T SRAM cell can be very useful for ultra-low power
applications operating voltage of 0.1V with reduced delay. The con-
ventional 8T SRAM cell is modified in two ways to optimize power
and delay. First, 8T with Read assist technique and second, 8T
SRAM using two Extra pass transistors.

ACKNOWLEDGMENT:
.
REFERENCES: