Experiment No.

1
INTRODUCTION TO DIGITAL LOGIC DESIGN LAB
WORK, TRAINERS AND DSCH SIMULATOR
 Basic Measuring Instruments Included
Flexibility to Perform
Objectives:
 To introduce students with all the experiments, simulator, trainer and equipment used for
experiments.

Apparatus:

 IT-400 trainer
 DSCH Simulator.
Details/Procedure:
DSCH:
The DSCH program is a logic editor and simulator. DSCH is used to validate the
architecture of the logic circuit before the microelectronics design is started. DSCH provides a
user-friendly environment for hierarchical logic design, and fast simulation with delay analysis,
which allows the design and validation of complex logic structures.

DSCH also features the symbols, models and assembly support for 8051 and PIC16F84
controllers. Designers can create logic circuits for interfacing with these controllers and verify
software programs using DSCH.
Highlights
 User-friendly environment for rapid design of logic circuits.
  Supports hierarchical logic design.
 Added a tool on fault analysis at the gate level of digital. Faults: Stuck-at-1, stuck-at-0.
The technique allows injection of single stuck-at fault at the nodes of the circuit.
 Improved interface between DSCH and Winspice.
 Handles both conventional pattern-based logic simulation and intuitive on screen mouse-
driven simulation.
 Built-in extractor which generates a SPICE netlist from the schematic diagram
(Compatible with PSPICETM and WinSpiceTM). Generates a VERILOG description of
the schematic for layout conversion.
 Immediate access to symbol properties (Delay, fanout).
 Model and assembly support for 8051 and PIC 16F84 microcontrollers.
 Sub-micron, deep-submicron, nanoscale technology support.
 Supported by huge symbol library

IT400 Trainer:
IT-400 is a comprehensive and self-contained system suitable for anyone engaged in
Digital and Analog circuit experiments. All necessary equipment for Digital and Analog circuit
experiments such as power supply, function generator, Data Switches, LEDs, Logic Probe, 7-
Segment Displays etc. are installed on the main unit. The Bread board allows students to perform
a wide variety experiments relating to essential topics in the field of digital and analog circuit. It
is a time and cost saving device for both students and researchers interested in developing and
testing circuit prototypes.
Features:
 Bread Board Based
 Power Supplies Included
 Custom Experiments
 Output Devices like LEDs and 7-Segment Included
 Input Devices like Push Switches, Toggle Switches Included
 Standard Function Generator Included
 Passive Components Included
  Protection Circuits Included

Technical Features:
Supplies:
 Fixed DC: +5V, -5V, +12V, -12V
 Dual DC Power Supply: 0 ~ +15V and 0 ~ -15V adjustable
 FIX Supply AC: 2V-0-2V, 12V-0-12V, 15V-0-15V
Function Generator:
 Output Waveform: Sine, Square, Triangle and TTL
 Output Frequency: up to 100KHz in five steps
3 ½-Digit Digital Voltmeter:
 Volt ranges 200mV, 2V, 20V, 200V
Data Switch:
 16-bit switch with TTL Output
Push Switch
 Two independent Switches
 Each with Q, Q’ output
 De-Bounce Switch
Logic Indicator
 24 independent LEDs indicate high and low logic state
Digital Display
 3 independent 7-segment LED display with BCD to 7-segment decoder/driver input with
8-4-2-1 code
Potentiometer:
 Carbon Track 1K and 100K
Interface Connectors
 2X BNC Connectors interfaced to 2mm gold plated pins
 1X Banana Connector interfaced to 2mm gold plated pin
 DB-9 Connector with all pins interfaced to 2mm gold plated pins
 DB-25 Connector with all pins interfaced to 2mm gold plated pins
Solderless Breadboard:
 2 Terminal Strips, Tie-point 1680
 4 Distribution Strips, Tie-point 400
Audio Output
 0.5W Speaker with Audio Amplifier and Volume Control
Accessories: 2mm-1mm patch cords, Power Cord, User Manual
Safety precautions:
 Stay away from electric equipment

Conclusion:
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Remarks:
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Experiment No. 2
SIMULATION AND IMPLEMENTATION OF BASIC LOGIC GATES
(AND, OR, NOT, NAND, NOR, X-OR, ETC.)
Objectives:
 To simulate the basic logic gates on DSCH, analyses the results and verify their truth
tables.

Apparatus:
 DSCH Simulator installed on laptop/computer.

Details/Procedure:

Basic Logic Gates

AND: A multi-input circuit in which the output is 1 only if all inputs are 1. The symbolic
representation of the AND gate is shown in the table below.
OR A multi-input circuit in which the output is 1 when any input is 1. The symbolic
representation of the OR gate is shown in table below.
INVERT The output is 0 when the input is 1, and the output is 1 when the input is 0. The
symbolic representation of an inverter is shown in table below.
NAND AND followed by INVERT. The symbolic representation of the NAND gate is shown in
table below.
NOR OR followed by INVERT as shown in the table below.
EX-OR The output of the Exclusive –OR gate, is 0 when it’s two inputs are the same and its
output is 1 when its two inputs are different.
Truth Table Representation of the output logic levels of a logic circuit for every possible
combination of levels of the inputs. This is best done by means of a systematic tabulation.
Procedure:
Insert gates in simulator and observe the inputs and outputs, verify the truth tables.
Safety precautions:

Conclusion:
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Remarks:
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Experiment No. 3
DESIGN AND SIMULATION OF LOGIC CIRCUITS USING LOGIC
SIMPLIFICATION TECHNIQUES
Objectives:
 To learn design and simulation of simplified logic circuits and verification of results.

Apparatus:
 DSCH Simulator
 Digital Trainer
Details/Procedure:

Boolean Rules for Simplification:

Boolean algebra finds its most practical use in the simplification of logic circuits. If we translate
a logic circuit’s function into symbolic (Boolean) form and apply certain algebraic rules to the
resulting equation to reduce the number of terms and/or arithmetic operations, the simplified
equation may be translated back into circuit form for a logic circuit performing the same function
with fewer components. If equivalent function may be achieved with fewer components, the
result will be increased reliability and decreased cost of manufacture.
To this end, there are several rules of Boolean algebra presented in this section for use in
reducing expressions to their simplest forms. The identities and properties already reviewed in
this chapter are very useful in Boolean simplification, and for the most part bear similarity to
many identities and properties of “normal” algebra. However, the rules shown in this section are
all unique to Boolean mathematics.
This rule may be proven symbolically by factoring an “A” out of the two terms, then applying
the rules of A + 1 = 1 and 1A = A to achieve the final result:

Please note how the rule A + 1 = 1 was used to reduce the (B + 1) term to 1. When a rule like “A
+ 1 = 1” is expressed using the letter “A”, it doesn’t mean it only applies to expressions
containing “A”. What the “A” stands for in a rule like A + 1 = 1 is any Boolean variable or
collection of variables. This is perhaps the most difficult concept for new students to master in
Boolean simplification: applying standardized identities, properties, and rules to expressions not
in standard form.
For instance, the Boolean expression ABC + 1 also reduces to 1 by means of the “A + 1 = 1”
identity. In this case, we recognize that the “A” term in the identity’s standard form can represent
the entire “ABC” term in the original expression.
The next rule looks similar to the first one shown in this section, but is actually quite different
and requires a cleverer proof:
Note how the last rule (A + AB = A) is used to “un-simplify” the first “A” term in the
expression, changing the “A” into an “A + AB”. While this may seem like a backward step, it
certainly helped to reduce the expression to something simpler! Sometimes in mathematics we
must take “backward” steps to achieve the most elegant solution. Knowing when to take such a
step and when not to is part of the art-form of algebra, just as a victory in a game of chess almost
always requires calculated sacrifices.
Another rule involves the simplification of a product-of-sums expression:

And, the corresponding proof:

To summarize, here are the three new rules of Boolean simplification expounded in this section:

Circuit Simplification Examples

Let’s begin with a semiconductor gate circuit in need of simplification. The “A,” “B,” and “C”
input signals are assumed to be provided from switches, sensors, or perhaps other gate circuits.
Where these signals originate is of no concern in the task of gate reduction.

Writing a Boolean Expression to Simplify Circuits

Our first step in simplification must be to write a Boolean expression for this circuit. This task is
easily performed step by step if we start by writing sub-expressions at the output of each gate,
corresponding to the respective input signals for each gate. Remember that OR gates are
equivalent to Boolean addition, while AND gates are equivalent to Boolean multiplication. For
example, I’ll write sub-expressions at the outputs of the first three gates:

. . . then another sub-expression for the next gate:

Finally, the output (“Q”) is seen to be equal to the expression AB + BC(B + C):

Now that we have a Boolean expression to work with, we need to apply the rules of Boolean
algebra to reduce the expression to its simplest form (simplest defined as requiring the fewest
gates to implement):
The final expression, B(A + C), is much simpler than the original, yet performs the same
function. If you would like to verify this, you may generate a truth table for both expressions and
determine Q’s status (the circuits’ output) for all eight logic-state combinations of A, B, and C,
for both circuits. The two truth tables should be identical.

Generating Schematic Diagrams from Boolean Expressions

Now, we must generate a schematic diagram from this Boolean expression. To do this, evaluate
the expression, following proper mathematical order of operations (multiplication before
addition, operations inside parentheses before anything else), and draw gates for each step.
Remember again that OR gates are equivalent to Boolean addition, while AND gates are
equivalent to Boolean multiplication. In this case, we would begin with the sub-expression “A +
C”, which is an OR gate:

The next step in evaluating the expression “B(A + C)” is to multiply (AND gate) the signal B by
the output of the previous gate (A + C):
Obviously, this circuit is much simpler than the original, having only two logic gates instead of
five. Such component reduction results in higher operating speed (less delay time from input
signal transition to output signal transition), less power consumption, less cost, and greater
reliability.

Safety precautions:

Conclusion:
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Remarks:
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Experiment No. 4
DESIGN, ANALYSIS, DSCH SIMULATION AND GATE LEVEL
IMPLEMENTATION OF ADDERS AND SUBTRACTORS
Objectives:
 To design and analyze the binary adders and subtractor on DSCH and build and test their
circuits using trainer.
Apparatus:
 DSCH Simulator
 Digital Trainer
Details/Procedure:
Adders:
An adder is a digital logic circuit in electronics that implements addition of numbers. In many
computers and other types of processors, adders are used to calculate addresses, similar
operations and table indices in the ALU and also in other parts of the processors. These can be
built for many numerical representations like excess-3 or binary coded decimal. Adders are
classified into two types: half adder and full adder. The half adder circuit has two inputs: A and
B, which add two input digits and generate a carry and sum. The full adder circuit has three
inputs: A and C, which add the three input numbers and generate a carry and sum. This article
gives brief information about half adder and full adder in tabular forms and circuit diagrams.

Half Adder and Full Adder Circuit

An adder is a digital circuit that performs addition of numbers. The half adder adds two binary
digits called as augend and addend and produces two outputs as sum and carry; XOR is applied
to both inputs to produce sum and AND gate is applied to both inputs to produce carry. The full
adder adds 3 one-bit numbers, where two can be referred to as operands and one can be referred
to as bit carried in. And produces 2-bit output, and these can be referred to as output carry and
sum.
By using half adder, you can design simple addition with the help of logic gates.
Let’s see an addition of single bits.

0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10

These are the least possible single-bit combinations. But the result for 1+1 is 10, the sum result
must be re-written as a 2-bit output. Thus, the equations can be written as
0+0 = 00
0+1 = 01
1+0 = 01
1+1 = 10
The output ‘1’of ‘10’ is carry-out. ‘SUM’ is the normal output and ‘CARRY’ is the carry-out.
Half Adder Truth Table

Now it has been cleared that 1-bit adder can be easily implemented with the help of the XOR
Gate for the output ‘SUM’ and an AND Gate for the ‘Carry’. When we need to add, two 8-bit
bytes together, we can be done with the help of a full-adder logic. The half-adder is useful when
you want to add one binary digit quantities. A way to develop two-binary digit adders would be
to make a truth table and reduce it. When you want to make a three binary digit adder, do it
again. When you decide to make a four-digit adder, do it again. The circuits would be fast, but
development time is slow.

Full Adder
This adder is difficult to implement than a half-adder. The difference between a half-adder and a
full-adder is that the full-adder has three inputs and two outputs, whereas half adder has only two
inputs and two outputs. The first two inputs are A and B and the third input is an input carry as
C-IN. When a full-adder logic is designed, you string eight of them together to create a byte-
wide adder and cascade the carry bit from one adder to the next.

The output carry is designated as C-OUT and the normal output is designated as S.

Full Adder Truth Table:

With the truth-table, the full adder logic can be implemented. You can see that the output S is an
XOR between the input A and the half-adder, SUM output with B and C-IN inputs. We take C-
OUT will only be true if any of the two inputs out of the three are HIGH.
So, we can implement a full adder circuit with the help of two half adder circuits. At first, half
adder will be used to add A and B to produce a partial Sum and a second half adder logic can be
used to add C-IN to the Sum produced by the first half adder to get the final S output.

If any of the half adder logic produces a carry, there will be an output carry. So, COUT will be
an OR function of the half-adder Carry outputs. Take a look at the implementation of the full
adder circuit shown below.
The implementation of larger logic diagrams is possible with the above full adder logic a simpler
symbol is mostly used to represent the operation. Given below is a simpler schematic
representation of a one-bit full adder.
With this type of symbol, we can add two bits together, taking a carry from the next lower order
of magnitude, and sending a carry to the next higher order of magnitude. In a computer, for a
multi-bit operation, each bit must be represented by a full adder and must be added
simultaneously. Thus, to add two 8-bit numbers, you will need 8 full adders which can be formed
by cascading two of the 4-bit blocks.

Subtractor:
Half subtractor:
Half subtractor is the most essential combinational logic circuit which is used in digital
electronics. Basically, this is an electronic device or in other terms, we can say it as a logic
circuit. Half subtractor is used to perform two binary digits subtraction. In the previous article,
we have already discussed the concepts of half adder and a full adder circuit which uses the
binary numbers for the calculation. Similarly, the subtractor circuit uses binary numbers (0,1) for
the subtraction. The circuit of the half subtractor can be built with two logic gates namely NAND
and EX-OR gates. This circuit gives two elements such as the difference as well as the borrow.
This article gives half subtractor theory concept which includes theories like what is a subtractor,
half subtractor with the truth table, etc.
What is a Half Subtractor?
In binary subtraction, the process of subtraction is similar to arithmetic subtraction. In arithmetic
subtraction the base 2 number system is used whereas in binary subtraction, binary numbers are
used for subtraction. The resultant terms can be denoted with the difference and borrow.
As in binary subtraction, the major digit is 1, we can generate borrow while the subtrahend 1 is
superior to minuend 0 and due to this, borrow will need. The following example gives the binary
subtraction of two binary bits.

First Digit Second Digit Difference Borrow

0
0 0 0
1 0
0 1
1
0 1 1
0
1 1 0

In the above subtraction, the two digits can be represented with A and B. These two digits can be
subtracted and gives the resultant bits as difference and borrow.
When we observe the first two and fourth rows, the difference of these rows, then the difference
and borrow are similar because subtrahend is lesser than the minuend. Similarly, when we
observe the third row, the minuend value is subtracted from the subtrahend. So, the difference
and borrow bits are 1 because the subtrahend digit is superior to the minuend digit.
Half-Subtractor Block Diagram
The block diagram of the half subtractor is shown above. It requires two inputs as well as gives
two outputs. Here inputs are represented with A&B, and outputs are Difference and Borrow.
The above circuit can be designed with EX-OR & NAND gates. Here, NAND gate can be built
by using AND and NOT gates. So, we require three logic gates for making half subtractor circuit
namely EX-OR gate, NOT gate, and NAND gate.
Combination of AND and NOT gate produce a different combined gate named as NAND Gate.
The Ex-OR gate output will be the Diff bit and the NAND Gate output will be the Borrow bit for
the same inputs A&B.
Half Subtractor Circuit using NAND Gate
The designing of half subtractor can be done by using logic gates like NAND gate & Ex-OR
gate. In order to design this half subtractor circuit, we have to know the two concepts namely
difference and borrow.

If we monitor cautiously, it is fairly clear that the variety of operation executed by this circuit
which is accurately related to the EX-OR gate operation. Therefore, we can simply use the EX-
OR gate for making difference. In the same way, the borrow produced by half adder circuit can
be simply attained by using the blend of logic gates like AND- gate and NOT-gate.
Truth Table
The truth table of the half adder circuit is shown below. It is an essential tool for any kind of
digital circuit to know the possible combinations of inputs and outputs. For instance, if the
subtractor has two inputs then the resultant outputs will be four. The o/p of the half subtractor is
mentioned in the below table that will signify the difference bit as well as borrow bit. The half
subtractor truth table explanation can be done by using the logic gates like EX-OR logic gate and
AND gate operation followed by NOT gate.
Difference Borrow
First Bit Second Bit (EX-OR Out) (NAND Out)
 0
0 0 0
0
1 0 1
0 1
1 1
0
1 1 0
Solving the truth table using K-Map is shown below.

The Boolean expression of the half subtractor using truth table and K-map can be derived as

Difference (D) = (x’y + xy’) = x ⊕ y
Borrow (B) = x’y

Application of Half Subtractor

The applications of half subtractor include the following.
 Half subtractor is used to reduce the force of audio or radio signals
 It can be used in amplifiers to reduce the sound distortion
 Half subtractor is used in ALU of processor
 It can be used to increase and decrease operators and also calculates the addresses
 Half subtractor is used to subtract the least significant column numbers. For subtraction
of multi-digit numbers, it can be used for the LSB.

Full Subtractor:
A full subtractor is a combinational circuit that performs subtraction of two bits, one is minuend
and other is subtrahend, considering borrow of the previous adjacent lower minuend bit. This
circuit has three inputs and two outputs. The three inputs A, B and Bin, denote the minuend,
subtrahend, and previous borrow, respectively. The two outputs, D and Bout represent the
difference and output borrow, respectively.

From above table we can draw the K-Map as shown for “difference” and “borrow”.

Logical expression for difference –

D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
= Bin(A’B’ + AB) + Bin’(AB’ + A’B)
= Bin( A XNOR B) + Bin’(A XOR B)
= Bin (A XOR B)’ + Bin’(A XOR B)
= Bin XOR (A XOR B)
= (A XOR B) XOR Bin
Logical expression for borrow –
Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= A’B’Bin +A’BBin’ + A’BBin + A’BBin + A’BBin + ABBin
 = A’Bin(B + B’) + A’B(Bin + Bin’) + BBin(A + A’)
= A’Bin + A’B + BBin
OR
Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= Bin(AB + A’B’) + A’B(Bin + Bin’)
= Bin( A XNOR B) + A’B
= Bin (A XOR B)’ + A’B
Logic Circuit for Full Subtractor:

Implementation of Full Subtractor using Half Subtractors:

2 Half Subtractors and an OR gate is required to implement a Full Subtractor.

Safety precautions:

Conclusion:
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Remarks:
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Experiment No. 5
 DESIGN, ANALYSIS, DSCH SIMULATION AND GATE
IMPLEMENTATION OF DECODER AND ENCODER
Objectives:
 To design, analyze, simulate and implement
A. 3-to-8 line Decoder
B. 8-to-3 line Encoder
Apparatus:
 DSCH Simulator
 Digital Trainer
Details/Procedure:

Decoder
In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic
circuit that converts coded inputs into coded outputs, where the input and output codes are
different e.g. n-to-2n, binary-coded decimal decoders. Decoding is necessary in applications such
as data multiplexing, 7 segment display and memory address decoding.
 
The example decoder circuit would be an AND gate because the output of an AND gate is
"High" (1) only when all its inputs are "High." Such output is called as "active High output". If
instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all its
inputs are "High". Such output is called as "active low output".
 
A slightly more complex decoder would be the n-to-2n type binary decoders. These types of
decoders are combinational circuits that convert binary information from 'n' coded inputs to a
maximum of 2n unique outputs. In case the 'n' bit coded information has unused bit
combinations, the decoder may have less than 2n outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-
16 decoder are other examples.
 
The input to a decoder is parallel binary number and it is used to detect the presence of a
particular binary number at the input. The output indicates presence or absence of specific
number at the decoder input.
 
Let us suppose that a logic network has 2 inputs A and B. They will give rise to 4 states A, A’, B,
B’. The truth table for this decoder is shown below:
 
 Table 1: Truth Table of 2:4 decoder
 
 

             
 
Fig 1: Logic Diagram of 2:4 decoder
 
 
Fig 2: Representation of 2:4 decoder
 
 
For any input combination only one of the outputs is low and all others are high. The low value
at the output represents the state of the input.
 
Decoder expansion
Combine two or more small decoders with enable inputs to form a larger decoder e.g. 3-to-8-line
decoder constructed from two 2-to-4-line decoders.
Decoder with enable input can function as demultiplexer.
 
3:8 decoder
It uses all AND gates, and therefore, the outputs are active- high. For active- low outputs, NAND
gates are used. It has 3 input lines and 8 output lines. It is also called as binary to octal decoder it
takes a 3-bit binary input code and activates one of the 8(octal) outputs corresponding to that
code. The truth table is as follows:
 

 
Table 2: Truth Table of 3:8 decoder
 
 

Fig 3: Logic Diagram of 3:8 decoder

Encoder
An encoder is a device, circuit, transducer, software program, algorithm or person that converts
information from one format or code to another. The purpose of encoder is standardization,
speed, secrecy, security, or saving space by shrinking size. Encoders are combinational logic
circuits and they are exactly opposite of decoders. They accept one or more inputs and generate a
multibit output code.
Encoders perform exactly reverse operation than decoder. An encoder has M input and N output
lines. Out of M input lines only one is activated at a time and produces equivalent code on output
N lines. If a device output code has fewer bits than the input code has, the device is usually
called an encoder.

Octal to binary encoder

Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3-to-8
decoder does. At any one time, only one input line has a value of 1. The figure below shows the
truth table of an Octal-to-binary encoder.

Table 3: Truth Table of octal to binary encoder

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2 are:
Y0 = I1 + I3 + I5 + I7
Y1= I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 +I7

Fig 4: Logic Diagram of octal to binary encoder

Priority encoder
 
A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller
number of outputs. The output of a priority encoder is the binary representation of the ordinal
number starting from zero of the most significant input bit. They are often used to control
interrupt requests by acting on the highest priority request. It includes priority function. If 2 or
more inputs are equal to 1 at the same time, the input having the highest priority will take
precedence. Internal hardware will check this condition and priority is set.
 

Table 4: Truth Table of 4 bit priority encoder/p>

 

 
Fig 5: Logic Diagram of 4bit priority encoder
 
IC 74148 is an 8-input priority encoder. 74147 is 10:4 priority encoder

Safety precautions:
Conclusion:
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Remarks:
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Experiment No. 6-7:
DESIGN AND DSCH SIMULATION OF MULTIPLEXER AND
DE-MULTIPLEXER
Objectives:
 To learn design and DSCH simulation of Multiplexer and De-Multiplexer and developing
the circuit on digital trainer.

Apparatus:

 DSCH
 Digital Trainer
Details/Procedure:
Multiplexer
 
In electronics, a multiplexer or mux is a device that selects one of several analog or digital input
signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n select
lines, which are used to select which input line to send to the output. An electronic multiplexer
can be considered as a multiple-input, single-output switch i.e. digitally controlled multi-position
switch. The digital code applied at the select inputs determines which data inputs will be
switched to output.
 
A common example of multiplexing or sharing occurs when several peripheral devices share a
single transmission line or bus to communicate with computer. Each device in succession is
allocated a brief time to send and receive data. At any given time, one and only one device is
using the line. This is an example of time multiplexing since each device is given a specific time
interval to use the line.
 
In frequency multiplexing, several devices share a common line by transmitting at different
frequencies.
 

 
Table 5: Truth Table of 8:1 MUX
 
  
Fig 6: Logic Diagram of 8:1 MUX
 
 
Demultiplexer
 
A demultiplexer (or demux) is a device taking a single input signal and selecting one of many
data-output-lines, which is connected to the single input. A multiplexer is often used with a
complementary demultiplexer on the receiving end. A demultiplexer is a single-input, multiple-
output switch. Demultiplexers take one data input and a number of selection inputs, and they
have several outputs. They forward the data input to one of the outputs depending on the values
of the selection inputs.
 
Demultiplexers are sometimes convenient for designing general purpose logic, because if the
demultiplexer's input is always true, the demultiplexer acts as a decoder. This means that any
function of the selection bits can be constructed by logically OR-ing the correct set of outputs.
Demultiplexer is called as a ‘distributro’, since it transmits the same data to different
destinations.
 
 

 
Table 6: Truth Table of 1:8 DEMUX

 
Fig 7: Logic Diagram of 1:8 DEMUX
Safety precautions:

Conclusion:
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Remarks:
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 PROJECT REPORT

Project Title:
Touch Sensor with Obstacle Sensor

Apparatus:

 Battery (9v)
 Transistor (BC 547)
 Resistor (1K)
 Battery Connectors
 Connecting Wires
 LED
 Obstacle Sensor

Description:

1: Transistor:
In this project we are using a BC 547 transistor. Transistor is used as a switch. It has
3 pins emitter, base, collector . Negative terminal of the battery is connected with emitter. It is an
NPN transistor, it  is commonly used as a switch in the electronic devices only for the low
voltage applications because of its low power consumption.

2: Resistor:
1K resistor is used with touch sensor LED. It is used to resist the flow of charge.
If too much current flows through an LED it can be destroyed. So a resistor is used to limit the
flow of current.

3: Battery:
9V battery is used in this whole project.

4: Obstacle Sensor:
Obstacle sensor is used to detect any obstacle. Infrared Obstacle Sensor
Module has built-in IR transmitter and IR receiver that sends out IR energy and looks for
reflected IR energy to detect presence of any obstacle in front of the sensor module.
The module has on board potentiometer that lets user adjust detection.
(TOUCH SENSOR CIRCUIT)

(OBSTACLE MODULE)
 WORKING:

We connected positive terminal of the battery with resistor 1k and that is connected with obstacle sensor
(Vcc). Negative terminal of battery with the ground of module and then with negative side of led. Positive
side of led connected to the output pin of obstacle.
Positive terminal of battery is connected with 1k resistor and that resistor then connected to the positive
side of LED. Now a wire is connected with positive side of LED that is one terminal of touching
pad(wires). Negative terminal of battery is conncted with emitter of transistor . collector pin is connected
with negative side of LED.
Now the second terminal of touch pad is connected with base of transistor.When we will touch the
terminals of touch pad toghether circuit will be completed.
LED will glow, and when an obstacle comes in the range of obstacle module it will detect the obstacle
and will turn of its LED. While its input and obstacle LED are still ON.