26 - System Analysis-An Introduction
26 - System Analysis-An Introduction
26 - System Analysis-An Introduction
System Analysis:
An Introduction
26.1 INTRODUCTION
The growing number of packaged systems in the electrical, electronic,
and computer fields now requires that some form of system analysis
appear in the syllabus of the introductory course. Although the content
of this chapter will be a surface treatment at best, the material will
introduce a number of important terms and techniques employed in the
system analysis approach. The increasing use of packaged systems is
quite understandable when we consider the advantages associated with
such structures: reduced size, sophisticated and tested design, reduced
construction time, reduced cost compared to discrete designs, and so
forth. The use of any packaged system is limited solely to the proper
utilization of the provided terminals of the system. Entry into the inter-
nal structure is not permitted, which also eliminates the possibility of
repair to such systems.
System analysis includes the development of two-, three-, or multi-
port models of devices, systems, or structures. The emphasis in this
chapter will be on the configuration most frequently subject to model-
ing techniques: the two-port system of Fig. 26.1.
1 2
Device,
system,
structure,
etc.
1′ 2′
FIG. 26.1
Two-port system.
1150 SYSTEM ANALYSIS: AN INTRODUCTION
Note that in Fig. 26.1 there are two ports of entry or interest, each
1 Device, 2 having a pair of terminals. For some devices, the two-port network of
system, Fig. 26.1 may appear as shown in Fig. 26.2(a). The block diagram of
structure,
etc. Fig. 26.2(a) simply indicates that terminals 1′ and 2′ are in common,
which is a particular case of the general two-port network. A single-
port network and a multiport network appear in Fig. 26.2(b). The for-
mer has been analyzed throughout the text, while the characteristics of
(a) 1′,2′
the latter will be touched on in this chapter, with a more extensive cov-
erage left for a more advanced course.
1 Single- The latter part of this chapter introduces a set of equations (and,
port subsequently, networks) that will allow us to model the device or sys-
1′ configuration tem appearing within the enclosed structure of Fig. 26.1. That is, we
will be able to establish a network that will display the same terminal
characteristics as those of the original system, device, and so on. In
2 2′ Fig. 26.3, for example, a transistor appears between the four external
terminals. Through the analysis to follow, we will find a combination
1 3
of network elements that will allow us to replace the transistor with a
Multiport
1′ configuration 3′
network that will behave very much like the original device for a spe-
cific set of operating conditions. Methods such as mesh and nodal
analysis can then be applied to determine any unknown quantities. The
4 4′ models, when reduced to their simplest forms as determined by the
(b)
operating conditions, can also provide very quick estimates of network
FIG. 26.2 behavior without a lengthy mathematical derivation. In other words,
(a) Two-port system; (b) single-port system someone well-versed in the use of models can analyze the operation of
and multiport system. large, complex systems in short order. The results may be only
approximate in most cases, but this quick return for a minimum of
effort is often worthwhile.
C
1 2 The analysis of this chapter is limited to linear (fixed-value) systems
with bilateral elements. Three sets of parameters are developed for the
two-port configuration, referred to as the impedance (z), admittance
B
(y), and hybrid (h) parameters. Table 26.1 at the end of the chapter
relates the three sets of parameters.
1′ 2′
E
26.2 THE IMPEDANCE PARAMETERS Zi AND Zo
FIG. 26.3
Two-port transistor configuration. For the two-port system of Fig. 26.4, Zi is the input impedance
between terminals 1 and 1′, and Zo is the output impedance between
terminals 2 and 2′. For multiport networks an impedance level can be
defined between any two (adjacent or not) terminals of the network.
The input impedance is defined by Ohm’s law in the following
form:
Ii Io
1 2
+ +
Ei Two-port Eo
system
– –
1′ 2′
Zi Zo
FIG. 26.4
Defining Zi and Zo.
THE IMPEDANCE PARAMETERS Zi AND Zo 1151
Ei
Zi (ohms, ) (26.1)
Ii
Eo
Zo (ohms, ) (26.2)
Io Ei 0 V
VRs Ii
+
+ IRs Rs
Eg Two-port
Ei system
–
–
Zi
FIG. 26.5
Determining Zi.
(26.2). The voltage across the sensing resistor is Eg Eo, and the current
through the sensing resistor is
VR Eg Eo
IRs s
Rs Rs
Eo Eo
but Io IRs and Zo
Io IRs
Io VRs
– +
+ Rs IRs +
Two-port
Ei = 0 V
system Eo Eg
–
–
Zo
FIG. 26.6
Determining Zo.
Zi, from which the resistive and reactive components can be determined
using a few basic geometric relationships. The reactive nature (induc-
tive or capacitive) of the input impedance can be determined when the
angle between Ei and Ii is computed. For a dual-trace oscilloscope, if
Eg leads VRs (Ei leads Ii), the network is inductive; if the reverse is true,
the network is capacitive.
+ +
Red Ii
Eg Two-port
Ei system
Ii
– – Rs + –
Black
Black Red
FIG. 26.7
Determining Zi using an oscilloscope.
To determine the angle associated with Zo, the sensing resistor must
again be moved to the bottom to form a common ground with the sup-
ply Eg. Then, using the approximation Eg Eo, the magnitude and
angle of Zo can be determined.
Ei 96 mV
Zi Ri 2.4 k FIG. 26.8
Ii 40 mA Example 26.1.
Rs
+ 2 k
+
Ei = 0 V Two-port 2V
system Eo = 1.92 V Eg
–
–
Zo
FIG. 26.9
Example 26.2.
1154 SYSTEM ANALYSIS: AN INTRODUCTION
Solution:
VRs Eg Eo 2 V 1.92 V 0.08 V 80 mV
VR 80 mV
Io IRs s 40 mA
Rs 2 k
Eo 1.92 V
Zo 48 k
Io 40 mA
Eg
+ +
Zi
Channel 2
(a)
Eg: Vertical sensitivity = 10 mV/div.
VR : Vertical sensitivity = 1 mV/div.
s
(b)
FIG. 26.10
Example 26.3.
The angle of Zi: The phase angle between Eg and VRs (or IRs Ii) is
Zi 250 30°
216.51 j 125 R j XL
THE VOLTAGE GAINS AvNL, Av, AND AvT 1155
E
AvNL o (26.3)
Ei AvNL Eo
Ei
– –
The capital letter A in the notation was chosen from the term amplifi-
cation factor, with the subscript v selected to specify that voltage levels FIG. 26.11
are involved. The subscript NL reveals that the ratio was determined Defining the no-load gain AvNL.
under no-load conditions; that is, a load was not applied to the output
terminals when the gain was determined. The no-load voltage gain is
the gain typically provided with packaged systems since the applied
load is a function of the application.
The magnitude of the ratio can be determined using a DMM or an
oscilloscope. The oscilloscope, however, must be used to determine the
phase shift between the two voltages.
In Fig. 26.12 a load has been introduced to establish a loaded gain
that will be denoted simply as Av and defined by
E
Av o (26.4)
Ei with RL
Rg
+ +
+ +
Eg Ei Av Eo RL VL = Eo
–
–
– –
FIG. 26.12
Defining the loaded voltage gain Av (and AvT ).
For all two-port systems the loaded gain Av will always be less than
the no-load gain.
In other words, the application of a load will always reduce the gain
below the no-load level.
A third voltage gain can be defined using Fig. 26.12 since it has an
applied voltage source with an associated internal resistance—a situa-
tion often encountered in electronic systems. The total voltage gain of
the system is represented by AvT and is defined by
E
AvT o (26.5)
Eg
It is the voltage gain from the source Eg to the output terminals Eo. Due
to loss of signal voltage across the source resistance,
the voltage gain AvT is always less than the loaded voltage gain Av or
unloaded gain AvNL.
1156 SYSTEM ANALYSIS: AN INTRODUCTION
Eo Eo Eo Ei Eo Ei
AvT (1) ⋅
Eg Eg Eg Ei Ei Eg
Ei
then AvT Av (if loaded)
Eg
Ei
or AvT AvNL (if unloaded)
Eg
The relationship between Ei and Eg can be determined from Fig.
26.12 if we recognize that Ei is across the input impedance Zi and thus
apply the voltage divider rule as follows:
Zi (Eg)
Ei
Zi Rg
Ei Zi
or
Eg Zi Rg
Substituting into the above relationships will result in
Zi
AvT Av (if loaded) (26.6)
Zi Rg
Zi
AvT AvNL (if unloaded) (26.7)
Zi Rg
Ii Zo I2
+ Ro +
+
Ei Zi Ri AvNLEi Eo
–
– –
FIG. 26.13
Ro Equivalent model for two-port amplifier.
+
+ The input impedance is defined by Zi Ei /Ii and the voltage Eo
AvNLEi in the absence of a load, resulting in AvNL Eo /Ei as defined.
AvNLEi Eo RL
The output impedance is defined with Ei set to zero volts, resulting in
– AvNLEi 0 V, which permits the use of a short-circuit equivalent for the
– controlled source. The result is Zo Eo /Io, as defined, and the parame-
ters and structure of the equivalent model are validated.
FIG. 26.14 If a load is applied as in Fig. 26.14, an application of the voltage
Applying a load to the output of Fig. 26.13. divider rule will result in
THE VOLTAGE GAINS AvNL, Av, AND AvT 1157
RL(AvNLEi)
Eo
RL Ro
Eo RL
and Av AvNL (26.8)
Ei RL Ro
For any value of RL or Ro, the ratio RL /(RL Ro) must be less than
1, mandating that Av is always less than AvNL as stated earlier. Further,
for a fixed output impedance (Ro), the larger the load resistance (RL ),
the closer the loaded gain to the no-load level.
An experimental procedure for determining Ro can be developed if
we solve Eq. (26.8) for the output impedance Ro:
RL
Av AvNL
RL Ro
or Av(RL Ro) RLAvNL
AvRL AvRo RLAvNL
and AvRo RLAvNL AvRL
RL(AvNL Av)
with Ro
Av
AvNL
or
Ro RL
Av
1 (26.9)
Rg
+ + 1 k + +
+
Ei = 4 mV AvNL Eo = –20 V Eg Ei Av Eo RL 2.2 k VL
–
– – – –
(a) Zi = 1 k Zo = 50 k
(b)
FIG. 26.15
Example 26.4.
Solutions:
Eo 20 V
a. AvNL 5000
Ei 4 mV
RL 2.2 k
b. Av AvNL (5000)
RL Ro 2.2 k 50 k
(5000)(0.0421) 210.73
Zi 1 k
c. AvT Av (210.73)
Zi Rg 1 k 1 k
1
(210.73) 105.36
2
AvNL 5000
d. Ro RL 1 2.2 k 1
Av 210.73
2.2 k(23.727 1) 2.2 k(22.727)
50 k as specified
Ig Rg Ii Io
+ +
+
Eg Ei Av Eo RL
–
– –
Zi Zo
FIG. 26.16
Defining Ai and AiT.
Note the need for a minus sign when Io is defined, because the
defined polarity of Eo would establish the opposite direction for Io
through RL.
The loaded current gain is
Eo /RL
Io Eo Zi
Ai
Ii Ei /Zi Ei RL
THE CURRENT GAINS Ai AND AiT , AND THE POWER GAIN AG 1159
Zi
and Ai Av (26.10)
RL
The result obtained with Eq. (26.10) or (26.11) will be the same
since Ig Ii, but the option of which gain is available or which you
choose to use is now available.
Returning to Fig. 26.13 (repeated in Fig. 26.17), an equation for the
current gain can be determined in terms of the no-load voltage gain.
Ii Ro Io
+ +
+
Ei Ri AvNLEi Eo RL
–
– –
FIG. 26.17
Developing an equation for Ai in terms of AvNL.
Io Ri
so that Ai AvNL (26.12)
Ii RL Ro
Recall an earlier conclusion that the larger the value of RL, the larger
the loaded voltage gain. For current levels, Equation (26.12) reveals that
the larger the level of RL, the less the current gain of a loaded
amplifier.
In the design of an amplifier, therefore, one must balance the desired
voltage gain with the current gain and the resulting ac output power
level.
For the system of Fig. 26.17, the power delivered to the load is
determined by E2o /RL, whereas the power delivered at the input termi-
nals is E2i /Ri. The power gain is therefore defined by
E2o /RL E2o Ri
Po Eo 2 Ri
AG 2 2
Pi E i /Ri E i RL Ei RL
Ri
and AG A2v (26.13)
RL
Ri
AG (Av) Av (Av)(Ai)
RL
so AG Av Ai (26.14)
which has a format similar to that of Eq. (26.13), but now AG is given
in terms of the current gain of the system.
The last power gain to be defined is the following:
PL E2o /RL E2o /RL Eo Rg Ri
2
AGT
Pg Eg Ig E g /(Rg Ri)
2
Eg RL
Rg Ri
or AGT A2vT
RL (26.16)
Expanding:
Rg Ri
AGT AvT AvT
RL
and AGT AvT AiT (26.17)
THE CURRENT GAINS Ai AND AiT , AND THE POWER GAIN AG 1161
EXAMPLE 26.5 Given the system of Fig. 26.18 with its nameplate
data:
Ig Rg Ii Io
1 k + +
+
AvNL = –960
Eg Ei Zi = 2.7 k Eo RL = 4.7 k
Zo = 40 k
–
– –
FIG. 26.18
Example 26.5.
a. Determine Av.
b. Calculate Ai.
c. Increase RL to double its current value, and note the effect on Av and
Ai.
d. Find AiT.
e. Calculate AG.
f. Determine Ai from Eq. (26.1), and compare it to the value obtained
in part (b).
Solutions:
RL 4.7 k
a. Av AvNL (960) 100.94
RL Ro 4.7 k 40 k
Ri 2.7 k
b. Ai AvNL (960) 57.99
RL Ro 4.7 k 40 k
c. RL 2(4.7 k) 9.4 k
RL 9.4 k
Av AvNL (960)
RL Ro 9.4 k 40 k
182.67 versus 100.94, which is a significant increase
Ri 2.7 k
Ai AvNL (960)
RL Ro 40 k 9.4 k
52.47 versus 57.99
which is a drop in level but not as significant as the change in Av.
d. AiT Ai 57.99 as obtained in part (b)
Rg Ri
However, AiT AvT
RL
Ri (Rg Ri)
Av
(Ri Rg) RL
Ri 2.7 k
Av (100.94)
RL 4.7 k
57.99
as well
Ri 2.7 k
e. AG A2v (100.94)2 5853.19
RL 4.7 k
1162 SYSTEM ANALYSIS: AN INTRODUCTION
f. AG Av Ai
AG (5853.19)
or Ai
Av (100.94)
57.99 as found in part (b)
Ii1 Io3
+ +
Ei1 A v1 , A i1 Eo1 = Ei2 A v2 , A i2 Eo2 = Ei3 Av3, Ai3 Eo3 RL
– –
Zi1 Zi2 Zi3
FIG. 26.19
Cascaded system.
Too often the labeled no-load gains are employed, resulting in enor-
mous overall gains and unreasonably high expectations for the system.
In addition, bear in mind that the input impedance of stage 3 may affect
the input impedance of stage 2 and, therefore, the load on stage 1.
In general, therefore, the equations for cascaded systems initially
appear to offer a high level of simplicity to the analysis. Simply be
aware, however, that each term of the overall equations must be care-
fully evaluated before using the equation.
The total voltage gain for the system of Fig. 26.19 is
where, again, the gain of each stage is determined under loaded (con-
nected) conditions.
The current gain between any two stages can also be determined
using an equation developed earlier in the chapter. For cascaded sys-
tems, the equation has the following general format:
Zi
Ai Av (26.20)
RL
the voltage gain substituted is also from the first to third stages. The
input impedance Zi is for the first stage of interest, and RL is the load-
ing on the last stage of interest.
For example, for the three-stage amplifier of Fig. 26.19,
Zi1
AiT AvT
RL
whereas for the first two stages
Zi1
A′i A′v
Zi3
Io2 Eo2
where A′i and A′v
Ii1 Ei1
The total power gain is determined by
whereas the gain between specific stages is simply the product of the
voltage and current gains for each section. For example, for the first two
stages of Fig. 26.19,
A′G A′v2 ⋅ A′i2
where A′v2 Av1 ⋅ Av2 and A′i2 Ai1 ⋅ Ai2
EXAMPLE 26.6 For the cascaded system of Fig. 26.20, with its
nameplate no-load parameters:
Ii1 Io
+ + + +
AvNL = 1 AvNL = –600 AvNL = –1200
Ei1 Zi = 50 k Eo1 = Ei2 Zi = 1.8 k Eo2 = Ei3 Zi = 1.2 k Eo3 RL 3.3 k
Zo = 25 Zo = 40 k Zo = 50 k
– – – –
FIG. 26.20
Example 26.6.
a. Determine the load voltage and current gain for each stage, and
redraw the system of Fig. 26.20 with the loaded parameters.
b. Calculate the total voltage and current gain.
c. Find the total power gain of the system using Eq. (26.21).
d. Calculate the voltage and current gain for the first two stages using
Eqs. (26.18) and (26.19).
e. Determine the current gain for the first two stages using Eq. (26.20),
and compare your answer with the result of part (d).
f. Calculate the power gain for the first two stages using Eq. (26.21).
g. Determine the power gain for the first two stages using Eq. (26.13).
Compare this answer with the result of part (f ).
h. Calculate the incorrect voltage gain for the entire system using Eq.
(26.18) and the no-load nameplate level for each stage. Compare this
answer to the result of part (b).
1164 SYSTEM ANALYSIS: AN INTRODUCTION
Solutions:
RL Zi2 1.8 k
a. Av1 AvNL1 AvNL1 (1)
RL Ro Zi2 Ro1 1.8 k 25
0.986
Zi3 1.2 k
Av2 AvNL2 (600) 17.476
Zi3 Ro2 1.2 k 40 k
RL 3.3 k
Av3 AvNL3 (1200) 74.296
RL Ro3 3.3 k 50 k
Ri Zi1 50 k
Ai1 AvNL AvNL1 (1)
RL Ro Zi2 Ro1 1.8 k 25
27.397
Zi2 1.8 k
Ai2 AvNL2 (600) 26.214
Zi3 Ro2 1.2 k 40 k
Zi3 1.2 k
Ai3 AvNL3 (1200) 27.017
RL Ro3 3.3 k 50 k
Ii1 Io
+ +
Av1 = 0.986 Av2 = –17.476 Av3 = –74.296
Ei 1 Eo1 = Ei2 Eo2 = Ei3 Eo3 RL = 3.3 k
Ai 1 = –27.397 Ai 2 = 26.214 Ai 3 = 27.017
– –
FIG. 26.21
Solution to Example 26.6.
Eo3
b. AvT Av1 ⋅ Av2 ⋅ Av3 (0.986)(17.476)(74.296)
Ei1
1280.22
Io3
AiT Ai1 ⋅ Ai2 ⋅ Ai3 (27.397)(26.214)(27.017)
Ii1
19,403.20
c. AGT AvT ⋅ AiT (1280.22)(19,403.20) 24.84 106
d. A′v2 Av1 ⋅ Av2 (0.986)(17.476) 17.231
A′i2 Ai1 ⋅ Ai2 (27.397)(26.214) 718.185
Zi Zi1 50 k
e. A′i2 Av A′v2 (17.231)
RL Zi 3 1.2 k
717.958 versus 718.185
with the difference due to the level of accuracy carried through the
calculations.
f. A′G2 A′v2 ⋅ A′i2 (17.231)(718.185) 12,375.05
Ri Ri1 50 k
g. A′G2 A2v (A′v2)2 (17.231)2 12,371.14
RL Zi3 1.2 k
IMPEDANCE (z) PARAMETERS 1165
The impedance parameters z11, z12, and z22 are measured in ohms.
To model the system, each impedance parameter must be determined
by setting a particular variable to zero.
z11
For z11, if I2 is set to zero, as shown in Fig. 26.23, Equation (26.22a) I1 I2 = 0
becomes
+
E1 z11I1 z12(0) E1 System
–
E1
and z11 (ohms, ) (26.23)
I1 I2 0 FIG. 26.23
Determining z11.
Equation (26.23) reveals that with I2 set to zero, the impedance param-
eter is determined by the resulting ratio of E1 to I1. Since E1 and I1 are both
input quantities, with I2 set to zero, the parameter z11 is formally referred
to in the following manner:
z11 open-circuit, input-impedance parameter
z12
For z12, I1 is set to zero, and Equation (26.22a) results in
E1
z12 (ohms, ) (26.24)
I2 I2 0
For most systems where input and output quantities are to be com- I1 = 0 I2
pared, the ratio of interest is usually that of the output quantity divided
by the input quantity. In this case, the reverse is true, resulting in the + +
following: E1 System E2
– –
z12 open-circuit, reverse-transfer impedance parameter
The term transfer is included to indicate that z12 will relate an input
and output quantity (for the condition I1 0). The network configura- FIG. 26.24
tion for determining z12 is shown in Fig. 26.24. Determining z12.
1166 SYSTEM ANALYSIS: AN INTRODUCTION
For an applied source E2, the ratio E1/I2 will determine z12 with I1
set to zero.
z21
To determine z21, set I2 to zero and find the ratio E2/I1 as determined by
Eq. (26.22b). That is,
E2
z21 (ohms, ) (26.25)
I1 I2 0
In this case, input and output quantities are again the determining
variables, requiring the term transfer in the nomenclature. However, the
ratio is that of an output to an input quantity, so the descriptive term
forward is applied, and
z21 open-circuit, forward-transfer impedance parameter
I1 I2 = 0 The determining network is shown in Fig. 26.25. For an applied
+ + voltage E1, it is determined by the ratio E2/I1 with I2 set to zero.
E1 System E2
– –
z22
The remaining parameter, z22, is determined by
FIG. 26.25
Determining z21.
E2
z22 (ohms, ) (26.26)
I2 I1 0
I1 = 0 I2
+ as derived from Eq. (26.22b) with I1 set to zero. Since it is the ratio of
System E2 the output voltage to the output current with I1 set to zero, it has the ter-
– minology
z22 open-circuit, output-impedance parameter
FIG. 26.26 The required network is shown in Fig. 26.26. For an applied voltage
Determining z22. E2, it is determined by the resulting ratio E2/I2 with I1 0.
For z12, the network will appear as shown in Fig. 26.29, and
E1 I2Z3
IMPEDANCE (z) PARAMETERS 1167
I1 I2 = 0 I1 = 0 I2
1
Z1 Z2 2 1 Z1 Z2
+ 2
+
+ +
E1 Z3 E1 Z3 E1 E2
– –
–
1′ – 2′
2′ 1′
E1 I2Z3
Thus z12
I2 I1 0 I2
E2 FIG. 26.30
I2 Determining z21.
Z2 Z3
E2 I2(Z2 Z3)
Thus z22 I1 = 0 I2
I2 I1 0 I2 1 Z1 Z2
2
and z22 Z2 Z3 (26.30) +
Z3 E2
Note that for the T configuration, z12 z21. For Z1 3 0°, –
Z2 5 90°, and Z3 4 90°, we have
2′
1′
z11 Z1 Z3 3 j 4
FIG. 26.31
z12 z21 Z3 4 90° j 4 Determining z22.
z22 Z2 Z3 5 90° 4 90° 1 90° j 1
– +
1 I1 I2 2 1 I1 I2 2
z11 z22 z11 – z12 z22 – z12
+ + + +
(z21 – z12)I1
+ +
E1 z12I2 z 21I E2 E1 z12 E2
1
– –
– – – –
1′ 2′ 1′ 2′
(a) (b)
FIG. 26.32
Two possible two-port, z-parameter equivalent networks.
+ +
– –
I1 I2
2 z11 z22
1 1 2
Device, + +
network, z12I2 z21I1
system
(z) – –
1′ 2′ 1′ 2′
(a) (b)
FIG. 26.33
Substitution of the z-parameter equivalent network into a complex system.
ADMITTANCE (y) PARAMETERS 1169
EXAMPLE 26.8 Draw the equivalent circuit in the form shown in Fig.
26.32(b) using the impedance parameters determined in Example 26.7.
I1 XC XL I2
R
1 2
+ 3 1
+
4
+ +
E1 4I2 ∠–90° 4I1 ∠–90° E2
– –
– –
1′ 2′
FIG. 26.34
Example 26.8.
Note that in this case each term of each equation has the units of cur-
rent, compared to voltage for each term of Eqs. (26.22a) and (26.22b).
In addition, the unit of each coefficient is siemens, compared with the
ohm for the impedance parameters.
The impedance parameters were determined by setting a particular
current to zero through an open-circuit condition. For the admittance
(y) parameters of Eqs. (26.31a) and (26.31b), a voltage is set to zero
through a short-circuit condition.
The terminology applied to each of the admittance parameters fol-
lows directly from the descriptive terms applied to each of the
impedance parameters. The equations for each are determined
directly from Eqs. (26.31a) and (26.31b) by setting a particular volt-
age to zero.
1170 SYSTEM ANALYSIS: AN INTRODUCTION
y11
I1
y11 (siemens, S) (26.32)
E1 E2 0
I1 I2
2
+ 1
E1 System E2 = 0
–
2′
1′
FIG. 26.35
y11 determination.
y12
I1
y12 (siemens, S) (26.33)
E2 E1 0
I1 I2
1
2 +
E1 = 0 System E2
–
1′
2′
FIG. 26.36
y12 determination.
y21
I2
y21 (siemens, S) (26.34)
E1 E2 0
I1 I2
2
+ 1
E1 System E2 = 0
–
2′
1′
FIG. 26.37
y21 determination.
ADMITTANCE (y) PARAMETERS 1171
y22
I2
y22 (siemens, S) (26.35)
E2 E1 0
I1 I2
1
2 +
E1 = 0 System E2
–
1′
2′
FIG. 26.38
y22 determination.
FIG. 26.39
and y11 Y1 Y2 (26.36) p network.
I1 Short circuited
Y2 2
1
+
E1 Y1 Y3 E2 = 0
–
1′ 2′
FIG. 26.40
Determining y11.
1′
2′
FIG. 26.41
Determining y12.
The network employed for y21 appears in Fig. 26.42. In this case, Y3
is short circuited, resulting in
IY2 I2 and IY2 I2 E1Y2
I2
with y21
E1 E2 0
1′ 2′
FIG. 26.42
Determining y21.
Note that for the p configuration, y12 y21, which was expected
since the impedance parameters for the T network were such that z12
z21. A T network can be converted directly to a p network using the
Y-D transformation.
The determining network for y22 appears in Fig. 26.43, and
1′
2′
FIG. 26.43
Determining y22.
ADMITTANCE (y) PARAMETERS 1173
I2
Thus y22
E2 E1 0
Y1 0.2 mS 0°
Y2 0.02 mS 90°
Y3 0.25 mS 90°
y11 Y1 Y2
0.2 mS j 0.02 mS (L)
y12 y21 Y2 (j 0.02 mS)
j 0.02 mS (C)
y22 Y2 Y3 j 0.02 mS j 0.25 mS
j 0.23 mS (C)
Note the similarities between the results for y11 and y22 for the p net-
work compared with z11 and z22 for the T network.
Two networks satisfying the terminal relationships of Eqs. (26.31a)
and (26.31b) are shown in Fig. 26.44. Note the use of parallel branches
I1 I2 I1 I2
a b –y12
1 2 1 2
+ + + (y22 – y12)I1 +
– – – –
1′ 2′ 1′ 2′
(a) (b)
FIG. 26.44
Two possible two-port, y-parameter equivalent networks.
since each term of Eqs. (26.31a) and (26.31b) has the units of current,
and the most direct route to the equivalent circuit is an application of
Kirchhoff’s current law in reverse. That is, find the network that satis-
fies Kirchhoff’s current law relationship. For the impedance parame-
ters, each term had the units of volts, so Kirchhoff’s voltage law was
applied in reverse to determine the series combination of elements in
the equivalent circuit of Fig. 26.44(a).
Applying Kirchhoff’s current law to the network of Fig. 26.44(a), we
have
1174 SYSTEM ANALYSIS: AN INTRODUCTION
Entering Leaving
I1 0.02 mS ∠90° E1 I2
+ +
BL 0.02 mS BC 0.23 mS
E1 E2
– –
0.02 mS ∠90° E2
FIG. 26.45
Equivalent network for the results of Example 26.9.
h11
E1
h11 (ohms, ) (26.41)
I1 E2 0
FIG. 26.46
h11 determination.
HYBRID (h) PARAMETERS 1175
h12
E1
h12 (dimensionless) (26.42)
E2 I1 0
I1 = 0 I2
1
+ 2
+
E1 System E2
– –
2′
1′
FIG. 26.47
h12 determination.
h21
I2
h21 (dimensionless) (26.43)
I1 E2 0
I1 I2
2
1
+
E1 System E2 = 0
–
1′ 2′
FIG. 26.48
h21 determination.
h22
I2
h22 (siemens, S) (26.44)
E2 I1 0
I1 = 0 I2
1
+ 2
+
E1 System E2
– –
2′
1′
FIG. 26.49
h22 determination.
The hybrid equivalent circuit appears in Fig. 26.50. Since the unit of
measurement for each term of Eq. (26.40a) is the volt, Kirchhoff’s volt-
age law was applied in reverse to obtain the series input circuit indi-
cated. The unit of measurement of each term of Eq. (26.40b) has the
units of current, resulting in the parallel elements of the output circuit
as obtained by applying Kirchhoff’s current law in reverse.
I1 I2
1 h11 2
+ +
+
E1 h12E2 h21I1 h22 E2
–
– –
1′ 2′
FIG. 26.50
Two-port, hybrid-parameter equivalent network.
I1 I2
+ hi +
Rs Zi
+
1
E1 hr E2 hf I1 ho E2 ZL
+
Es –
–
– –
FIG. 26.51
Example 26.10.
Solutions:
a. Using the current divider rule, we have
(1/h o)h f I1 h f I1
I2
(1/h o) ZL 1 h oZL
I2 hf
and A i (26.45)
I1 1 hoZL
E2 h f ZL
A v (26.46)
E1 h i (1 h oZL ) h r h f ZL
For the output impedance, we will set the source voltage to zero but
preserve its internal resistance Rs as shown in Fig. 26.52.
I1 I2
1 hi +2
Rs
+ Zo
1
hr E2 hf I1 ho E2 ZL
Es = 0 –
–
1′ 2′
FIG. 26.52
Determining Zo for the hybrid equivalent network.
Since Es 0
hr E2
then I1
h i Rs
From the output circuit,
I2 h f I1 h o E 2
hr E2
or I2 h f h o E 2
h i Rs
INPUT AND OUTPUT IMPEDANCES 1179
hr h f
and
I2 h o E 2
h i Rs
Thus, E2 1 (26.48)
Zo ——
I2 hr h f
h o
h i Rs
I1 I2
z11 z22
+ +2
Rs
Zi + + Zo
E1 z12I2 z21I1 E2 ZL
+
Es – –
– –
–
2′
FIG. 26.53
Determining Zi for the z-parameter equivalent network.
z 21 I1
I2
z 22 ZL
E1 z12 I2
and I1
z11
z 21I1
or E1 z11I1 z12I2 z11I1 z12
z 22 ZL
E1 z12z 21
and Zi z11 (26.49)
I1 z 22 ZL
z12I2 E2 z 21I1
I1 and I2
Rs z11 z 22
z12I2
or E 2 z 22I2 z 21I1 z 22I2 z 21
Rs z11
z12z 21I2
and E 2 z 22I2
Rs z11
E2 z12z 21
Thus, Zo z 22 (26.50)
I2 Rs z11
h22 h12
and E1 I1 I2
Dh Dh
DhI1 h12
or E1 I2
h22 h22
which, when related to the impedance-parameter equation,
E1 z11I1 z12I2
indicates that
Dh h12
z11 and z12
h22 h22
The remaining conversions are left as an exercise. A complete table
of conversions appears in Table 26.1.
TABLE 26.1
Conversions between z, y, and h parameters.
From
→ z y h
To
→
Dz z12 1 y12
h11 h12
z22 z22 y11 y11
h
z21 1 y Dy
21
h21 h22
z22 z22 y11 y11
PSpice
hf RL
Av
hi(1 ho RL) hrhf RL
(50)(2 k)
(1 k)(1 (25 106 S)(2 k)) (4 104)(50)(2 k)
100 103 100 103
3 99.01
(1 k)(1 50 10 ) 40 1050 40
1182 SYSTEM ANALYSIS: AN INTRODUCTION
hi
I1 1 k + +
+ +
E1 = 1 V ∠0° 4× 10–4
E2
50I1 1
40 k E2 RL = 2 k VL
hrE2 hf I1 ho
– –
– –
FIG. 26.54
Hybrid equivalent model to be investigated under loaded conditions using PSpice.
E VL
and Av 2
E1 E1
FIG. 26.55
Using PSpice to analyze the network of Fig. 26.54.
COMPUTER ANALYSIS 1183
FIG. 26.56
Output file for the voltage across the load resistor of Fig. 26.55.
FIG. 26.57
Modification of the schematic of Fig. 26.55 to determine the output
impedance of the network.
1184 SYSTEM ANALYSIS: AN INTRODUCTION
has the arrow in the symbol. Everything else in the network remains the
same, so there is no need to rebuild the entire network. Simply make
the changes and run the simulation. Even the simulation does not have
to be changed since the chosen parameters will remain the same. The
current source was given a magnitude of 1 A so that the magnitude of
the VPRINT1 voltage would also be the magnitude of the output
impedance. The results of Fig. 26.58 indicate an output impedance of
200 k. The following theoretical analysis reveals that the output
impedance is indeed 200 k:
1 1
Zo —— ————
hrhf (4 104)(50)
ho 25 106 S
hi Rs 1 k 0
1 1
200 k
25 106 S 20 106 S 5 106 S
FIG. 26.58
Output file for the voltage across the 1-A current source (and output
impedance) of the network of Fig. 26.57.
PROBLEMS
SECTION 26.2 The Impedance Parameters Zi and Zo
1. Given the indicated voltage levels of Fig. 26.59, deter-
mine the magnitude of the input impedance Zi.
Rs
47 +
+
Eg 1.05 V Ei = 1 V System
–
–
Zi
FIG. 26.59
Problem 1.
PROBLEMS 1185
+ Ii1 +
Multi-port
Ei1 system Eo RL
– –
Zi = 2 k
Zi3 = 4.6 k
Ii3 = 1.5 mA
+ Ei3 –
FIG. 26.60
Problem 3.
Rs
+ 2 k
+
System Eo = 3.8 V ( p–p) Eg = 4 V ( p–p)
–
–
Zo
FIG. 26.61
Problems 4 through 6.
eg
Io
+
+
System Eo Eg vR
–
– Rs
1 k
+ VR –
Channel 1
eg : Vertical sensitivity — 0.2 V/div.
Channel 2 vRs : Vertical sensitivity — 10 mV/div.
FIG. 26.62
Problem 7.
– –
Zi = 1.8 k 0°
FIG. 26.63
Problem 8.
Ig Rg Ii Io
0.5 k + +
+
AvNL = –3200
Eg Ei Zi = 2.2 k Eo RL = 5.6 k
Zo = 40 k
– – –
FIG. 26.64
Problems 9, 12, and 13.
PROBLEMS 1187
10. For the system of Fig. 26.65(a), the no-load output volt-
age is 1440 mV, with 1.2 mV applied at the input ter-
minals. In Fig. 26.65(b), a 4.7-k load is applied to the
same system, and the output voltage drops to 192 mV,
with the same applied input signal. What is the output
impedance of the system?
+ + + +
+
Ei = 1.2 mV System Eo = –1440 mV Ei = 1.2 mV System Eo 4.7 k VL = –192 mV
–
– – –
(a) (b)
FIG. 26.65
Problem 10.
Rg Ii Io
+ 0.4 k + +
Eg Ei Av = –160 Eo RL 2 k
Zi = 0.75 k
– – –
Zi
FIG. 26.66
Problems 11 and 14.
Ii Io
+ +
+
Ei Av1 = –30 Av2 = –50 Eo RL = 8 k VL
–
– –
Zi1 = 1 k Zi2 = 2 k
FIG. 26.67
Problem 15.
Ii Io 3
1
+ +
Av 1 = –12 Av 2 = ? Av 3 = –32
Ei 1 Ai = 4 Ai = 26 Ai = ? Eo 3 RL 2.2 k
1 2 3
Zi 1 = 1 k Zi 2 = ? Zi 3 = 2 k
– –
FIG. 26.68
Problem 16.
I1 I2
Z2
+ +
E1 Z1 Z3 E2
– –
FIG. 26.69
Problems 17 and 21.
PROBLEMS 1189
I1 I2 I1 I2
Y1 Y2 Y2
+ + + +
E1 Y3 E2 E1 Y1 Y3 E2
– – – –
Y4
FIG. 26.71
Problems 19 and 23. FIG. 26.72
Problems 20 and 24.
I1 hi I2
+ 1 k +
1 Zo
Zi
+ ho
hr E2 hf I1
40 k E2 RL = 2 k
E1 4 10–4E2 50I1
–
– –
FIG. 26.73
Problems 25 and 26.
1190 SYSTEM ANALYSIS: AN INTRODUCTION
I1 (z11) (z22) I2
+ 1 k 2 k +
4 k
Rg 1 k
+ +
E1 5 10 ∠90°I2 10 103I1
3
E2 RL 1 k
+ (z12I2) (z21I1)
– –
Eg Zi Zo
– – –
FIG. 26.74
Problems 27, 32, and 34.
28. Determine the expression for the input and output imped-
ance of the y-parameter equivalent circuit.
SECTION 26.10 Conversion between Parameters
29. Determine the h parameters for the following z param-
eters:
z11 4 k
z12 2 k
z21 3 k
z22 4 k
30. a. Determine the z parameters for the following h param-
eters:
h11 1 k
h12 2 104
h21 100
h22 20 106 S
b. Determine the y parameters for the hybrid parameters
indicated in part (a).
GLOSSARY
Admittance (y) parameters A set of parameters, having the Input impedance The impedance appearing at the input ter-
units of siemens, that can be used to establish a two-port minals of a system.
equivalent network for a system. Output impedance The impedance appearing at the output
Hybrid (h) parameters A set of mixed parameters (ohms, terminals of a system with the energizing source set to zero.
siemens, some unitless) that can be used to establish a two- Single-port network A network having a single set of access
port equivalent network for a system. terminals.
Impedance (z) parameters A set of parameters, having the Two-port network A network having two pairs of access
units of ohms, that can be used to establish a two-port terminals.
equivalent network for a system.