OPA549

OPA
549 OPA
549

SBOS093E – MARCH 1999 – REVISED OCTOBER 2005

High-Voltage, High-Current
OPERATIONAL AMPLIFIER

FEATURES DESCRIPTION
● HIGH OUTPUT CURRENT: The OPA549 is a low-cost, high-voltage/high-current opera-
8A Continuous tional amplifier ideal for driving a wide variety of loads. This
10A Peak laser-trimmed monolithic integrated circuit provides excellent
● WIDE POWER-SUPPLY RANGE: low-level signal accuracy and high output voltage and current.
Single Supply: +8V to +60V The OPA549 operates from either single or dual supplies for
Dual Supply: ±4V to ±30V design flexibility. The input common-mode range extends
● WIDE OUTPUT VOLTAGE SWING below the negative supply.

● FULLY PROTECTED: The OPA549 is internally protected against over-temperature

Thermal Shutdown conditions and current overloads. In addition, the OPA549
Adjustable Current Limit provides an accurate, user-selected current limit. Unlike
other designs which use a “power” resistor in series with the
● OUTPUT DISABLE CONTROL
output current path, the OPA549 senses the load indirectly.
● THERMAL SHUTDOWN INDICATOR This allows the current limit to be adjusted from 0A to 10A
● HIGH SLEW RATE: 9V/µs with a resistor/potentiometer, or controlled digitally with a
● CONTROL REFERENCE PIN voltage-out or current-out Digital-to-Analog Converter (DAC).

● 11-LEAD POWER PACKAGE The Enable/Status (E/S) pin provides two functions. It can be
monitored to determine if the device is in thermal shutdown,
and it can be forced low to disable the output stage and
APPLICATIONS effectively disconnect the load.
● VALVE, ACTUATOR DRIVERS The OPA549 is available in an 11-lead power package. Its
● SYNCHRO, SERVO DRIVERS copper tab allows easy mounting to a heat sink for excellent
thermal performance. Operation is specified over the ex-
● POWER SUPPLIES
tended industrial temperature range, –40°C to +85°C.
● TEST EQUIPMENT
● TRANSDUCER EXCITATION V+

● AUDIO POWER AMPLIFIERS

OPA549 VO
ILIM
RCL sets the current limit
Ref
value from 0A to 10A.
RCL (Very Low Power Dissipation)

ES Pin E/S
Forced Low: Output disabled.
Indicates Low: Thermal shutdown.
V–

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 1999-2005, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

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ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
Output Current ................................................ See SOA Curve (Figure 6)
Supply Voltage, V+ to V– ................................................................... 60V DISCHARGE SENSITIVITY
Input Voltage Range ....................................... (V–) – 0.5V to (V+) + 0.5V
Input Shutdown Voltage ................................................... Ref – 0.5 to V+ This integrated circuit can be damaged by ESD. Texas Instru-
Operating Temperature .................................................. –40°C to +125°C ments recommends that all integrated circuits be handled with
Storage Temperature ..................................................... –55°C to +125°C appropriate precautions. Failure to observe proper handling
Junction Temperature ...................................................................... 150°C
Lead Temperature (soldering, 10s) ................................................. 300°C and installation procedures can cause damage.
ESD Capability (Human Body Model) ............................................. 2000V
ESD damage can range from subtle performance degradation
NOTE: (1) Stresses above these ratings may cause permanent damage. to complete device failure. Precision integrated circuits may be
Exposure to absolute maximum conditions for extended periods may de-
more susceptible to damage because very small parametric
grade device reliability.
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum at the end of this datasheet
or see the TI website at www.ti.com.

CONNECTION DIAGRAM

Tab connected to V–. Do not use to conduct current.

2 4 6 8 10
+In Ref ILIM
1 3 5 7 9 11
–In E/S

VO V– V+

Connect both pins 1 and 2 to output.

Connect both pins 5 and 7 to V–.
Connect both pins 10 and 11 to V+.

2 OPA549
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ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TCASE = +25°C, VS = ±30V, Ref = 0V, and E/S pin open, unless otherwise noted.

OPA549T, S
PARAMETER CONDITION MIN TYP MAX UNITS
OFFSET VOLTAGE VOS
Input Offset Voltage VCM = 0V, IO = 0 ±1 ±5 mV
vs Temperature dVOS/dT TCASE = –40°C to +85°C ±20 µV/°C
vs Power Supply PSRR VS = ±4V to ±30V, Ref = V– 25 100 µV/V
INPUT BIAS CURRENT(1)
Input Bias Current(2) IB VCM = 0V –100 –500 nA
vs Temperature TCASE = –40°C to +85°C ±0.5 nA/°C
Input Offset Current IOS VCM = 0V ±5 ±50 nA
NOISE
Input Voltage Noise Density en f = 1kHz 70 nV/√Hz
Current Noise Density in f = 1kHz 1 pA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range: Positive VCM Linear Operation (V+) – 3 (V+) – 2.3 V
Negative VCM Linear Operation (V–) – 0.1 (V–) – 0.2 V
Common-Mode Rejection Ratio CMRR VCM = (V–) – 0.1V to (V+) – 3V 80 95 dB
INPUT IMPEDANCE
Differential 107 || 6 Ω || pF
Common-Mode 109 || 4 Ω || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL VO = ±25V, RL = 1kΩ 100 110 dB
VO = ±25V, RL = 4Ω 100 dB
FREQUENCY RESPONSE
Gain Bandwidth Product GBW 0.9 MHz
Slew Rate SR G = 1, 50Vp-p Step, RL = 4Ω 9 V/µs
Full-Power Bandwidth See Typical Curve
Settling Time: ±0.1% G = –10, 50V Step 20 µs
Total Harmonic Distortion + Noise(3) THD+N f = 1kHz,RL = 4Ω,G = +3, Power = 25W 0.015 %
OUTPUT
Voltage Output, Positive IO = 2A (V+) – 3.2 (V+) – 2.7 V
Negative IO = –2A (V–) + 1.7 (V–) + 1.4 V
Positive IO = 8A (V+) – 4.8 (V+) – 4.3 V
Negative IO = –8A (V–) + 4.6 (V–) + 3.9 V
Negative RL = 8Ω to V– (V–) + 0.3 (V–) + 0.1 V
Maximum Continuous Current Output: dc(4) ±8 A
ac(4) Waveform Cannot Exceed 10A peak 8 A rms
Output Current Limit
Current Limit Range 0 to ±10 A
Current Limit Equation ILIM = 15800 • 4.75V/(7500Ω + RCL) A
Current Limit Tolerance(1) RCL = 7.5kΩ (ILIM = ±5A), RL = 4Ω ±200 ±500 mA
Capacitive Load Drive (Stable Operation) CLOAD See Typical Curve
Output Disabled
Leakage Current Output Disabled, VO = 0V –2000 ±200 +2000 µA
Output Capacitance Output Disabled 750 pF
OUTPUT ENABLE/STATUS (E/S) PIN
Shutdown Input Mode
VE/S High (output enabled) E/S Pin Open or Forced High (Ref) + 2.4 V
VE/S Low (output disabled) E/S Pin Forced Low (Ref) + 0.8 V
IE/S High (output enabled) E/S Pin Indicates High –50 µA
IE/S Low (output disabled) E/S Pin Indicates Low –55 µA
Output Disable Time 1 µs
Output Enable Time 3 µs
Thermal Shutdown Status Output
Normal Operation Sourcing 20µA (Ref) + 2.4 (Ref) + 3.5 V
Thermally Shutdown Sinking 5µA, TJ > 160°C (Ref) + 0.2 (Ref) + 0.8 V
Junction Temperature, Shutdown +160 °C
Reset from Shutdown +140 °C
Ref (Reference Pin for Control Signals)
Voltage Range V– (V+) – 8 V
Current(2) –3.5 mA
POWER SUPPLY
Specified Voltage VS ±30 V
Operating Voltage Range, (V+) – (V–) 8 60 V
Quiescent Current IQ ILIM Connected to Ref IO = 0 ±26 ±35 mA
Quiescent Current in Shutdown Mode ILIM Connected to Ref ±6 mA
TEMPERATURE RANGE
Specified Range –40 +85 °C
Operating Range –40 +125 °C
Storage Range –55 +125 °C
Thermal Resistance, θJC 1.4 °C/W
Thermal Resistance, θJA No Heat Sink 30 °C/W

NOTES: (1) High-speed test at TJ = +25°C. (2) Positive conventional current is defined as flowing into the terminal. (3) See “Total Harmonic Distortion + Noise vs
Frequency” in the Typical Characteristics section for additional power levels. (4) See “Safe Operating Area” (SOA) in the Typical Characteristics section.

OPA549 3
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TYPICAL CHARACTERISTICS
At TCASE = +25°C, VS = ±30V, and E/S pin open, unless otherwise noted.

OPEN-LOOP GAIN AND PHASE

vs FREQUENCY INPUT BIAS CURRENT vs TEMPERATURE
120 0 –130
–IB
100 –20 –120
+IB
–110

Input Bias Current (nA)

80 –40
–100
60 –60
Gain (dB)

Phase (°)
–90
40 –80
–80
20 –100
–70
0 –120 –60
–20 –140 –50

–40 –160 –40

1 10 100 1k 10k 100k 1M 10M –60 –40 –20 0 20 40 60 80 100 120 140
Frequency (Hz) Temperature (°C)

CURRENT LIMIT vs TEMPERATURE CURRENT LIMIT vs SUPPLY VOLTAGE

9 9
+ILIM, 8A
8 8
–ILIM, 8A
8A 7
7
Current Limit (A)

6
Current Limit (A)

6 +ILIM, 5A
5A
5 5
–ILIM, 5A
4 4

3 3
2A +ILIM, 2A
2 2
–ILIM, 2A
1 1

0 0
–75 –50 –25 0 25 50 75 100 125 0 5 10 15 20 25 30
Temperature (°C) Supply Voltage (V)

INPUT BIAS CURRENT

vs COMMON-MODE VOLTAGE QUIESCENT CURRENT vs TEMPERATURE
–200 30
–180 VS = ±30V
25
–160
Quiescent Current (mA)
Input Bias Current (nA)

–140 VS = ±5V
20
–120
–100 15
–80
10
–60 IQ Shutdown (output disabled)
–40 5
–20
–0 0
–30 –20 –10 0 10 20 30 –75 –50 –25 0 25 50 75 100 125
Common-Mode Voltage (V) Temperature (°C)

4 OPA549
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TYPICAL CHARACTERISTICS (Cont.)
At TCASE = +25°C, VS = ±30V, and E/S pin open, unless otherwise noted.

POWER-SUPPLY REJECTION RATIO

COMMON-MODE REJECTION RATIO vs FREQUENCY vs FREQUENCY
100 120

Power-Supply Rejection Ratio (dB)

Common-Mode Rejection (dB)

90 100

80 80
–PSRR
70 60
+PSRR
60 40

50 20

40 0
10 100 1k 10k 100k 10 100 1k 10k 100k 1M
Frequency (Hz) Frequency (Hz)

OPEN-LOOP GAIN, COMMON-MODE REJECTION RATIO,

AND POWER-SUPPLY REJECTION RATIO
VOLTAGE NOISE DENSITY vs FREQUENCY vs TEMPERATURE
300 120

250
AOL, CMRR, PSRR (dB)
Voltage Noise (nV/√Hz)

110
200 AOL

150 100

100 PSRR
90
50 CMRR

0 80
1 10 100 1k 10k 100k –75 –50 0 50 100 125
Frequency (Hz) Temperature (°C)

GAIN-BANDWIDTH PRODUCT AND TOTAL HARMONIC DISTORTION + NOISE

SLEW RATE vs TEMPERATURE vs FREQUENCY
1 16 1
G = +3
0.9 15
RL = 4Ω
Gain-Bandwidth Product (MHz)

GBW
0.8 14 75W

0.7 13 10W
Slew Rate (V/µs)

0.1
THD+N (%)

0.6 12
0.5 11 1W
0.1W
0.4 10
SR+
0.01
0.3 9
0.2 8
SR–
0.1 7
0 6 0.001
–75 –50 –25 0 25 50 75 100 125 20 100 1k 10k 20k
Temperature (°C) Frequency (Hz)

OPA549 5
SBOS093E www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TCASE = +25°C, VS = ±30V, and E/S pin open, unless otherwise noted.

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT OUTPUT VOLTAGE SWING vs TEMPERATURE

5 5
IO = +8A
(V+) – VO
4 4

VSUPPLY – VOUT (V)

VSUPPLY– VOUT (V)

IO = –8A
(V–) – VO
3 3
IO = +2A

2 2
IO = –2A

1 1

0 0
0 2 4 6 8 10 –75 –50 –25 0 25 50 75 100 125
Output Current (A) Temperature (°C)

MAXIMUM OUTPUT VOLTAGE SWING OUTPUT LEAKAGE CURRENT

vs FREQUENCY vs APPLIED OUTPUT VOLTAGE
30 5
Maximum output Leakage current with output disabled.
voltage without 4
25
slew rate-induced 3
Leakage Current (mA)
Output Voltage (Vp)

distortion.
20 2
1
RCL = ∞
15 0
RCL = 0
–1
10
–2

5 –3
–4
0 –5
1k 10k 100k 1M –40 –30 –20 –10 0 10 20 30 40
Frequency (Hz) Output Voltage (V)

OFFSET VOLTAGE OFFSET VOLTAGE DRIFT

PRODUCTION DISTRIBUTION PRODUCTION DISTRIBUTION
25 25

20 20
Percent of Amplifiers (%)

Percent of Amplifiers (%)

15 15

10 10

5 5

0 0
–4.7
–4.23
–3.76
–3.29
–2.82
–2.35
–1.88
–1.41
–0.94
–0.47
0
0.47
0.94
1.41
1.88
2.35
2.82
3.29
3.76
4.23
4.7

0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
64
68
72
76
80
84

Offset Voltage (µV/°C)

Offset Voltage (mV)

6 OPA549
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TYPICAL CHARACTERISTICS (Cont.)
At TCASE = +25°C, VS = ±30V, and E/S pin open, unless otherwise noted.

SMALL-SIGNAL OVERSHOOT LARGE-SIGNAL STEP RESPONSE

vs LOAD CAPACITANCE G = 3, CL = 1000pF
70

60

50
G = +1
Overshoot (%)

40

10V/div
30

20
G = –1
10

0
0 5k 10k 15k 20k 25k 30k 35k 5µs/div
Load Capacitance (pF)

SMALL-SIGNAL STEP RESPONSE SMALL-SIGNAL STEP RESPONSE

G = 1, CL = 1000pF G = 3, CL = 1000pF

100mV/div
50mV/div

2.5µs/div 2.5µs/div

OPA549 7
SBOS093E www.ti.com
APPLICATIONS INFORMATION CONTROL REFERENCE (Ref) PIN
The OPA549 features a reference (Ref) pin to which the ILIM
Figure 1 shows the OPA549 connected as a basic noninverting
and the E/S pin are referred. Ref simply provides a reference
amplifier. The OPA549 can be used in virtually any op amp
point accessible to the user that can be set to V–, ground, or
configuration.
any reference of the user’s choice. Ref cannot be set below
Power-supply terminals should be bypassed with low series the negative supply or above (V+) – 8V. If the minimum VS
impedance capacitors. The technique shown in Figure 1, using is used, Ref must be set at V–.
a ceramic and tantalum type in parallel, is recommended.
Power-supply wiring should have low series impedance.
ADJUSTABLE CURRENT LIMIT
Be sure to connect both output pins (pins 1 and 2).
The OPA549’s accurate, user-defined current limit can be set
from 0A to 10A by controlling the input to the ILIM pin. Unlike
V+
other designs, which use a power resistor in series with the
output current path, the OPA549 senses the load indirectly.
10µF
This allows the current limit to be set with a 0µA to 633µA
+
control signal. In contrast, other designs require a limiting
0.1µF(2)
resistor to handle the full output current (up to 10A in this
R1 R2
case).
10, 11 Although the design of the OPA549 allows output currents up
E/S to 10A, it is not recommended that the device be operated
9
3
1, 2
continuously at that level. The highest rated continuous
OPA549 VO current capability is 8A. Continuously running the OPA549 at
8
VIN ZL output currents greater than 8A will degrade long-term reli-
4 Ref ILIM(1)
6
R2 ability.
5, 7 G = 1+
R1 Operation of the OPA549 with current limit less than 1A
results in reduced current limit accuracy. Applications requir-
0.1µF(2) ing lower output current may be better suited to the OPA547
or OPA548.
10µF
+ Resistor-Controlled Current Limit
See Figure 2a for a simplified schematic of the internal
V– circuitry used to set the current limit. Leaving the ILIM pin open
programs the output current to zero, while connecting ILIM
NOTES: (1) ILIM connected to Ref gives the maximum
current limit, 10A (peak). (2) Connect capacitors directly to directly to Ref programs the maximum output current limit,
package power-supply pins. typically 10A.
With the OPA549, the simplest method for adjusting the
current limit uses a resistor or potentiometer connected
FIGURE 1. Basic Circuit Connections.
between the ILIM pin and Ref according to Equation 1:

POWER SUPPLIES 75kV

RCL = – 7.5kΩ (1)
ILIM
The OPA549 operates from single (+8V to +60V) or dual
(±4V to ±30V) supplies with excellent performance. Most Refer to Figure 2 for commonly used values.
behavior remains unchanged throughout the full operating Digitally-Controlled Current Limit
voltage range. Parameters that vary significantly with operat-
The low-level control signal (0µA to 633µA) also allows the
ing voltage are shown in the Typical Characteristics. Some
current limit to be digitally controlled by setting either a
applications do not require equal positive and negative out-
current (ISET) or voltage (VSET). The output current ILIM can be
put voltage swing. Power-supply voltages do not need to be
adjusted by varying ISET according to Equation 2:
equal. The OPA549 can operate with as little as 8V between
the supplies and with up to 60V between the supplies. For ISET = ILIM/15800 (2)
example, the positive supply could be set to 55V with the Figure 2b demonstrates a circuit configuration implementing
negative supply at –5V. Be sure to connect both V– pins this feature.
(pins 5 and 7) to the negative power supply, and both V+ The output current ILIM can be adjusted by varying VSET
pins (pins 10 and 11) to the positive power supply. according to Equation 3:
Package tab is internally connected to V–; however, do
VSET = (Ref) + 4.75V – (7500W)(ILIM)/15800 (3)
not use the tab to conduct current.
Figure 11 demonstrates a circuit configuration implementing
this feature.

8 OPA549
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 (a) RESISTOR METHOD (b) DAC METHOD (Current or Voltage)

Max IO = ILIM
(4.75) (15800) Max IO = ILIM
±ILIM =
7500Ω + RCL ±ILIM =15800 ISET
7500Ω 7500Ω
4.75V 4.75V
ISET

8 8
Ref Ref D/A
RCL 0.01µF
6 6
(optional, for noisy
environments)

15800 (4.75V)
RCL = – 7500Ω
ILIM ISET = ILIM/15800

75kΩ VSET = (Ref) + 4.75V – (7500Ω) (ILIM)/15800

= – 7.5kΩ
ILIM
OPA549 CURRENT LIMIT: 0A to 10A

DESIRED RESISTOR(1) CURRENT VOLTAGE

CURRENT LIMIT (RCL) (ISET) (VSET)

0A(2) ILIM Open 0µA (Ref) + 4.75V

2.5A 22.6kΩ 158µA (Ref) + 3.56V
3A 17.4kΩ 190µA (Ref) + 3.33V
4A 11.3kΩ 253µA (Ref) + 2.85V
5A 7.5kΩ 316µA (Ref) + 2.38V
6A 4.99kΩ 380µA (Ref) + 1.90V
7A 3.24kΩ 443µA (Ref) + 1.43V
8A 1.87kΩ 506µA (Ref) + 0.95V
9A 845Ω 570µA (Ref) + 0.48V
10A ILIM Connected to Ref 633µA (Ref)

NOTES: (1) Resistors are nearest standard 1% values. (2) Offset in the current limit circuitry
may introduce approximately ±0.25A variation at low current limit values.

FIGURE 2. Adjustable Current Limit.

ENABLE/STATUS (E/S) PIN

The Enable/Status Pin provides two unique functions:
1) output disable by forcing the pin low, and 2) thermal
OPA549
shutdown indication by monitoring the voltage level at the
E/S
pin. Either or both of these functions can be utilized in an Ref
application. For normal operation (output enabled), the E/S
pin can be left open or driven high (at least 2.4V above Ref).
A small value capacitor connected between the E/S pin and CMOS or TTL
CREF may be required for noisy applications. Logic
Ground
Output Disable
To disable the output, the E/S pin is pulled to a logic low (no
FIGURE 3. Output Disable.
greater than 0.8V above Ref). Typically the output is shut down
in 1µs. To return the output to an enabled state, the E/S pin
OPA549s in a switched amplifier configuration. The on/off state
should be disconnected (open) or pulled to at least 2.4V above
of the two amplifiers is controlled by the voltage on the E/S pin.
Ref. It should be noted that driving the E/S pin high (output
Under these conditions, the disabled device will behave like a
enabled) does not defeat internal thermal shutdown; however,
750pF load. Slewing faster than 3V/µs will cause leakage
it does prevent the user from monitoring the thermal shutdown
current to rapidly increase in devices that are disabled, and will
status. Figure 3 shows an example implementing this function.
contribute additional load. At high temperature (125°C), the
This function not only conserves power during idle periods slewing threshold drops to approximately 2V/µs. Input signals
(quiescent current drops to approximately 6mA) but also allows must be limited to avoid excessive slewing in multiplexed
multiplexing in multi-channel applications. See Figure 12 for two applications.

OPA549 9
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Thermal Shutdown Status
20
The OPA549 has thermal shutdown circuitry that protects the
amplifier from damage. The thermal protection circuitry dis- 10
ables the output when the junction temperature reaches
PD
approximately 160°C and allows the device to cool. When the =9
TC = 25°C
PD 0W
junction temperature cools to approximately 140°C, the output

Output Current (A)

Output current can =4
7W
circuitry is automatically re-enabled. Depending on load and be limited to less
than 8A—see text. PD
signal conditions, the thermal protection circuit may cycle on 1 =1
and off. The E/S pin can be monitored to determine if the 8W

device is in shutdown. During normal operation, the voltage on

TC = 85°C
the E/S pin is typically 3.5V above Ref. Once shutdown has
TC = 125°C
occurred, this voltage drops to approximately 200mV above Pulse Operation Only
Ref. Figure 4 shows an example implementing this function. (Limit rms current to ≤ 8A)
0.1
1 2 5 10 20 50 100
VS – VO (V)

OPA549 FIGURE 6. Safe Operating Area.

E/S
Ref
The safe output current decreases as VS – VO increases.
HCT
Output short circuits are a very demanding case for SOA. A
E/S pin can interface short circuit to ground forces the full power-supply voltage
with standard HCT logic (V+ or V–) across the conducting transistor. Increasing the
Logic inputs. Logic ground is
Ground case temperature reduces the safe output current that can be
referred to Ref.
tolerated without activating the thermal shutdown circuit of
the OPA549. For further insight on SOA, consult Application
FIGURE 4. Thermal Shutdown Status.
Report SBOA022 at the Texas Instruments web site
(www.ti.com).
External logic circuitry or an LED can be used to indicate if
the output has been thermally shutdown, see Figure 10.
POWER DISSIPATION
Output Disable and Thermal Shutdown Status
Power dissipation depends on power supply, signal, and load
As mentioned earlier, the OPA549’s output can be disabled
conditions. For dc signals, power dissipation is equal to the
and the disable status can be monitored simultaneously.
product of output current times the voltage across the con-
Figure 5 provides an example of interfacing to the E/S pin.
ducting output transistor. Power dissipation can be mini-
mized by using the lowest possible power-supply voltage
Open-drain logic output can disable necessary to assure the required output voltage swing.
the amplifier's output with a logic low.
HCT logic input monitors thermal For resistive loads, the maximum power dissipation occurs at
OPA549 shutdown status during normal a dc output voltage of one-half the power-supply voltage.
E/S operation. Dissipation with ac signals is lower. Application Bulletin
Ref SBOA022 explains how to calculate or measure power
dissipation with unusual signals and loads.
Open Drain HCT
(Output Disable) (Thermal Status
Shutdown) THERMAL PROTECTION
Power dissipated in the OPA549 will cause the junction
Logic temperature to rise. Internal thermal shutdown circuitry shuts
Ground down the output when the die temperature reaches approxi-
mately 160°C and resets when the die has cooled to 140°C.
FIGURE 5. Output Disable and Thermal Shutdown Status.
Depending on load and signal conditions, the thermal protec-
tion circuit may cycle on and off. This limits the dissipation of
SAFE OPERATING AREA
the amplifier but may have an undesirable effect on the load.
Stress on the output transistors is determined both by the
Any tendency to activate the thermal protection circuit indi-
output current and by the output voltage across the conduct-
cates excessive power dissipation or an inadequate heat
ing output transistor, VS – VO. The power dissipated by the
sink. For reliable operation, junction temperature should be
output transistor is equal to the product of the output current
limited to 125°C maximum. To estimate the margin of safety
and the voltage across the conducting transistor, VS – VO.
in a complete design (including heat sink) increase the
The Safe Operating Area (SOA curve, Figure 6) shows the
ambient temperature until the thermal protection is triggered.
permissible range of voltage and current.

10 OPA549
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Use worst-case load and signal conditions. For good reliabil- compound used (if any) also affect θCH. A typical θCH for a
ity, thermal protection should trigger more than 35°C above mounted 11-lead power ZIP package is 0.5°C/W. Now we
the maximum expected ambient condition of your applica- can solve for θHA:
tion. This produces a junction temperature of 125°C at the θHA = [(TJ – TA)/PD] – θJC – θCH
maximum expected ambient condition. θHA = [(125°C – 40°C)/10W] – 1.4°C/W – 0.5°C/W
The internal protection circuitry of the OPA549 was designed θHA = 6.6°C/W
to protect against overload conditions. It was not intended to
To maintain junction temperature below 125°C, the heat sink
replace proper heat sinking. Continuously running the OPA549
selected must have a θHA less than 6.6°C/W. In other words,
into thermal shutdown will degrade reliability.
the heat sink temperature rise above ambient must be less
than 66°C (6.6°C/W • 10W). For example, at 10W Thermalloy
AMPLIFIER MOUNTING AND HEAT SINKING model number 6396B has a heat sink temperature rise of 56°C
Most applications require a heat sink to assure that the (θHA = 56°C/10W = 5.6°C/W), which is below the required 66°C
maximum operating junction temperature (125°C) is not required in this example. Thermalloy model number 6399B has
exceeded. In addition, the junction temperature should be a sink temperature rise of 33°C (θHA = 33°C/10W = 3.3°C/W),
kept as low as possible for increased reliability. Junction which is also below the required 66°C required in this example.
temperature can be determined according to the Equations: Figure 7 shows power dissipation versus ambient temperature
for a 11-lead power ZIP package with the Thermalloy 6396B
TJ = TA + PDθJA (4)
and 6399B heat sinks.
where θJA = θJC + θCH + θHA (5)
TJ = Junction Temperature (°C)
30
TA = Ambient Temperature (°C)
PD = (TJ (max) – TA)/ θJA
PD = Power Dissipated (W) (TJ (max) – 150°C)
θJC = Junction-to-Case Thermal Resistance (°C/W)

Power Dissipation (W)

θCH = Case-to-Heat Sink Thermal Resistance (°C/W) 20 with Thermalloy 6399B
Heat Sink, θJA = 5.2°C/W
θHA = Heat Sink-to-Ambient Thermal Resistance (°C/W)
θJA = Junction-to-Air Thermal Resistance (°C/W)
with Thermalloy 6396B
Figure 7 shows maximum power dissipation versus ambient 10 Heat Sink, θJA = 7.5°C/W
temperature with and without the use of a heat sink. Using a with No Heat Sink,
θJA = 30°C/W
heat sink significantly increases the maximum power dissipa-
tion at a given ambient temperature, as shown in Figure 7.
0
The challenge in selecting the heat sink required lies in 0 25 50 75 100 125
determining the power dissipated by the OPA549. For dc Ambient Temperature (°C)
output, power dissipation is simply the load current times the
voltage developed across the conducting output transistor, Thermalloy 6399B θ HA = 5.6°C/W
PD = IL (VS – VO). Other loads are not as simple. Consult the assume θ CH = 0.5°C/W
OPA549 θ JC = 1.4°C/W
SBOA022 Application Report for further insight on calculat- θ JA = 7.5°C/W
ing power dissipation. Once power dissipation for an applica-
tion is known, the proper heat sink can be selected. Thermalloy 6396B θ HA = 3.3°C/W
assume θ CH = 0.5°C/W
Heat Sink Selection Example—An 11-lead power ZIP pack- OPA549 θ JC = 1.4°C/W
age is dissipating 10 Watts. The maximum expected ambient θ JA = 5.2°C/W

temperature is 40°C. Find the proper heat sink to keep the

FIGURE 7. Maximum Power Dissipation vs Ambient Temperature.
junction temperature below 125°C (150°C minus 25°C safety
margin).
Another variable to consider is natural convection versus
Combining Equations (4) and (5) gives: forced convection air flow. Forced-air cooling by a small fan
TJ = TA + PD ( θJC + θCH + θHA ) (6) can lower θCA (θCH + θHA) dramatically. Some heat sink
TJ, TA, and PD are given. θJC is provided in the Specifications manufacturers provide thermal data for both of these cases.
Table, 1.4°C/W (dc). θCH can be obtained from the heat sink Heat sink performance is generally specified under idealized
manufacturer. Its value depends on heat sink size, area, and conditions that may be difficult to achieve in an actual
material used. Semiconductor package type, mounting screw application. For additional information on determining heat
torque, insulating material used (if any), and thermal joint sink requirements, consult Application Report SBOA021.

OPA549 11
SBOS093E www.ti.com
As mentioned earlier, once a heat sink has been selected, avoided with clamp diodes from the output terminal to the
the complete design should be tested under worst-case load power supplies, as shown in Figure 8. Schottky rectifier
and signal conditions to ensure proper thermal protection. diodes with a 8A or greater continuous rating are recom-
Any tendency to activate the thermal protection circuitry may mended.
indicate inadequate heat sinking.
The tab of the 11-lead power ZIP package is electrically VOLTAGE SOURCE APPLICATION
connected to the negative supply, V–. It may be desirable to Figure 9 illustrates how to use the OPA549 to provide an
isolate the tab of the 11-lead power ZIP package from its accurate voltage source with only three external resistors.
mounting surface with a mica (or other film) insulator. For First, the current limit resistor, RCL, is chosen according to
lowest overall thermal resistance, it is best to isolate the the desired output current. The resulting voltage at the ILIM
entire heat sink/OPA549 structure from the mounting surface pin is constant and stable over temperature. This voltage,
rather than to use an insulator between the semiconductor VCL, is connected to the noninverting input of the op amp and
and heat sink. used as a voltage reference, thus eliminating the need for an
external reference. The feedback resistors are selected to
OUTPUT STAGE COMPENSATION gain VCL to the desired output voltage level.
The complex load impedances common in power op amp
applications can cause output stage instability. For normal
operation, output compensation circuitry is typically not re- R1 R2
quired. However, for difficult loads or if the OPA549 is in-
tended to be driven into current limit, an R/C network may be V+
required. Figure 8 shows an output R/C compensation (snub-
ber) network which generally provides excellent stability.

VO = VCL (1 + R2/R1)
4.75V
V+ 7500Ω
Ref 15800 (4.75V)
VCL IO =
7500Ω + RCL
R1 R2 R2 ILIM
G=– = –4
5kΩ 20kΩ R1
VIN
V–

D1

0.01µF RCL
OPA549
(Optional, for noisy
10Ω environments)
D2 Uses voltage developed at ILIM pin
(Carbon) Motor as a moderately accurate reference
0.01µF For Example: voltage.

V– If ILIM = 7.9A, RCL = 2kΩ

D1, D2 : Schottky Diodes 2kΩ • 4.75V
VCL = = 1V
(2kΩ + 7500Ω)
10
FIGURE 8. Motor Drive Circuit. Desired VO = 10V, G = = 10
1
R1 = 1kΩ and R2 = 9kΩ
A snubber circuit may also enhance stability when driving
large capacitive loads (> 1000pF) or inductive loads (motors,
loads separated from the amplifier by long cables). Typically, FIGURE 9. Voltage Source.
3Ω to 10Ω resistors in series with 0.01µF to 0.1µF capacitors
is adequate. Some variations in circuit values may be required PROGRAMMABLE POWER SUPPLY
with certain loads. A programmable source/sink power supply can easily be
built using the OPA549. Both the output voltage and output
OUTPUT PROTECTION current are user-controlled. See Figure 10 for a circuit using
Reactive and EMF-generating loads can return load current potentiometers to adjust the output voltage and current while
to the amplifier, causing the output voltage to exceed the Figure 11 uses DACs. An LED connected to the E/S pin
power-supply voltage. This damaging condition can be through a logic gate indicates if the OPA549 is in thermal
shutdown.

12 OPA549
www.ti.com SBOS093E
 V+ = +30V
1kΩ 9kΩ V– = 0V
9kΩ
G=1+ = 10
+5V 1kΩ

10.5kΩ 3
VO = 1V to 25V
OPA549
Output 0.12V to 2.5V IO = 0 to 10A
10kΩ 9 E/S
Adjust 4 6
ILIM 8 Ref
74HCT04 R ≥ 250Ω
499Ω

V– +5V
Thermal (LED)
0V to 4.75V Shutdown Status
1kΩ

Current
Limit
Adjust 20kΩ 0.01µF

FIGURE 10. Resistor-Controlled Programmable Power Supply.

V+ = +30V
V– = 0V
1kΩ 9kΩ
–5V
VREF OUTPUT ADJUST
G = 10
+5V
VREF A

RFB A +5V 3
1, 2
10pF OPA549 VO = 7V to 25V
9 IO = 0A to 10A
IOUT A 1/2 4 E/S
1/2 DAC7800/1/2(3) OPA2336 74HCT04
6 R ≥ 250Ω
DAC A Ref
AGND A ILIM 8

Thermal (LED)
Shutdown Status

VREF B

RFB B

10pF

IOUT B 1/2
1/2 DAC7800/1/2 OPA2336
DAC B
0.01µF
DGND AGND B

CURRENT LIMIT ADJUST

Choose DAC780X based on digital interface: DAC7800—12-bit

interface, DAC7801—8-bit interface + 4 bits, DAC7802—serial interface.

FIGURE 11. Digitally-Controlled Programmable Power Supply.

OPA549 13
SBOS093E www.ti.com
 R1 R2
VIN1

OPA549 OPA549

E/S ILIM
Ref

VO
R3 R4
VE/S VIN2 RCL1 RCL2
Close for high current
(could be open drain
output of a logic gate).
OPA549

E/S

Limit output slew rates to ≤ 3V/µs (see text).

FIGURE 12. Switched Amplifier. FIGURE 13. Multiple Current Limit Values.

R1 R2
1kΩ 4kΩ

Master
0.1Ω
OPA549
VIN
ILIM
Ref
20A Peak

VO
G=5

Slave
0.1Ω
OPA549

ILIM
Ref

FIGURE 14. Parallel Output for Increased Output Current.

14 OPA549
www.ti.com SBOS093E
 PACKAGE OPTION ADDENDUM

www.ti.com 22-Oct-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

OPA549S ACTIVE Power Package KVC 11 25 Green (RoHS CU SN N / A for Pkg Type -40 to 85 OPA549S
& no Sb/Br)
OPA549SG3 ACTIVE Power Package KVC 11 25 Green (RoHS CU SN N / A for Pkg Type -40 to 85 OPA549S
& no Sb/Br)
OPA549T ACTIVE TO-220 KV 11 25 Green (RoHS CU SN N / A for Pkg Type -40 to 85 OPA549T
& no Sb/Br)
OPA549TG3 ACTIVE TO-220 KV 11 25 Green (RoHS CU SN N / A for Pkg Type -40 to 85 OPA549T
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 22-Oct-2013

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
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