Design of High-Speed Comparator For LVDS Receiver

International Journal for Research in Technological Studies| Vol.
1, Issue 4, March 2014 | ISSN (online): 2348-1439
Design of High-Speed Comparator for LVDS Receiver

1
Jayesh S. Shetti Karwarker 2Dr. H. G. Virani
1
PG Scholar 2 Associate Professor
1, 2
Electronics & Telecommunication DepartmentGoa College of Engineering Farmagudi, Ponda, Goa
Abstract—Ever increasing demands of the processing been done by impressing the current pulse signal at the input
speeds require very high speed and power efficient of the comparator and finding whether it is positive or
interconnections between the ICs. Such connections are negative. The output voltage generated by the comparator is
governed by various standards, LVDS is one among them. In used properly to indicate the result of operation. Circuit uses
order to meet the requirements of high speed, low noise source follower input stage and a CMOS inverter as a
communication between ICs, the Low Voltage Differential positive feedback.
signalling (LVDS) protocol is used. This paper studies the II. COMPARATOR DESIGN
design of comparator stage of LVDS receiver. Due to the
differential transmission technique and the low voltage Comparator blocks are designed to meet the defined
swing, LVDS allows high transmission speeds and low specifications of LVDS receiver compliant to IEEE 1596.6
power consumption at the same time. The proposed circuitry at 1GHz. Comparator first amplifies this differential input
has been simulated properly in 180 nm CMOS process with a certain high gain around 6-10 using NMOS
technology using Cadence Spectre simulator. differential amplifier. Such a double ended output of NMOS
differential amplifier is converted to single ended full rail
Keywords: CMOS, LVDS, Comparator. output of 0-3.3V by source follower.
I. INTRODUCTION Comparator consists of two stages as NMOS
Board level chip interfaces are demanding very high speed, differential amplifier and source follower. M5 is made to
power efficient interfaces. The ever increasing processing sink a constant current hence M5 should be kept in
speed of microprocessor motherboards, optical transmission saturation. Common mode of input should be such that M1
links, intelligent hubs and routers, etc..., pushing the off- and M2 are in saturation. The gain of NMOS differential
chip data rate into the gigabits-per second range. However, amplifier is around 6-10.When the current through M1 is
unlike internal clocks, chip-to-board signaling gains little more than that of M2, VA is less than Vb. Similarly when
benefit in terms of operating frequency from the increased the current through M2 is more than that through M1, VA is
silicon integration. In the last decade, high data rates were more than Vb.
achieved by massive parallelism, with the disadvantages of
increased complexity and cost for the IC package and the
printed circuit board (PCB). For this reason, the off-chip
data rate is expected to move to the range of Gb/s-per-pin in
the near future. [2] [3]
While the reduction of the power consumption is
of great concern in battery-powered portable systems, it is
also required in other systems to reduce the costs related to
packaging and additional cooling systems. Some of today’s
biggest challenges that remain to be solved include the
ability to transfer data at fastest rate possible, low power
systems than currently available and economical solutions to
overcome the physical layer bottleneck.
Data transmission standards like RS-422, RS-485,
SCSI and others have their own limitations notably in
transferring raw data across a medium. Optical fibers are
also costly and area inefficient for long distances. Thus,
low-cost, high-speed parallel links and serial links using
copper cables are an attractive solution for such
applications. In this regard, Low-voltage Differential
Fig.1: Comparator Circuit Diagram
Signaling (LVDS) technology was developed in order to
provide a low-power and low-voltage alternative, to other Electrical specifications for comparator
high-speed I/O interfaces for point-to point All the specifications of the system are derived in
transmission.[4][5] accordance with the IEEE 1596.3 - 1996 Std. [1]
Current mode operations have been considered as Input common mode voltage =1.65 V
an alternative in analog circuit designs as CMOS VLSI
devices are scaled down in size. Comparators are used in Input differential voltage=+300m V to -300m V
data converters and other front end signal processing Output single ended voltage=3.3V
applications. Voltage comparator encounters several Dv =3.3V
difficulties including operational frequency, input offset
voltage and power consumption. Current comparison has DT=10% of frequency of operation
Copyright©IJRTS | www.ijrts.com 29
(IJRTS/Vol. 1/Issue 4/March 2014)
= 10% (1ns) =0.1nS

SR=dv/dt =3.3/0.1*10−9 =33V/nS
SR=ID/CL
ID=SR*CL=33*109*10 *10−6
=330μA
μPCOX=55
μnCO4X = 293
V DS=0.3V
VDS=V GS-VT
0.3> VGS-0.5
Fig.3: Comparator DC Schematic
0.8 > VGS
VGS < 0.8
So, VG4S = 0.7
VT =0.5V
IT=μnCOX ( W6/L6)n (VGS-VT )2
( W6/L6)p = IT/ μnOX (VGS-VT)2
=330*10−6/55*10−6*(0.2)2 = 150 μm
For better operation
(W6/L6)p=100 μm
Current divides at pm3 and pm4 Fig.4: Comparator DC Response
(W0/L0)p=50 μm
(W3/L3)p=50 μm
Again same current flows at pm2 and pm1
(W2/L2)p=100 μm
(W1/L1)p=100 μm
Inverter design
Same current flows through inverter
(W12/L12)p=100 μm
(W14/L14)p=100 μm
(W18/L18)n=20 μm
(W20/L20)n=20 μm
III. SIMULATION RESULTS
The schematic design and layout design are carried out Fig. 5: Comparator AC Schematic
using CADENCE tool for 0.18μm technology
(UMC180nm).
Fig.2: Comparator Schematic
Fig.6: Comparator AC Response
Copyright© IJRTS | www.ijrts.com 30

(IJRTS/Vol. 1/Issue 4/March 2014)
[6] Razavi. B. Design of Analog CMOS Integrated

Circuits. McGraw Hill,2001, NewYork.
[7] B.Young. A soi cmos lvds driver and receiver pair.
IEEE Symposium on VLSI Circuits, 2001.
[8] Tai-Ping Sun Chung-Yuan Chen, Jia-HongWang. A
novel mini-lvds receiver in 0.35- um cmos, 2001.
[9] Alan Hasting. The art of analog layout. Prentice Hall, 1,
2000.
[10] Douglas R Holberg Philip E Allen. CMOS Analog
Circuit Design. Oxford University press, New York.
Fig.7: Comparator Transient Schematic
Fig.8: Comparator Transient Response
Fig.9: Comparator Layout

IV. CONCLUSION
High-Speed Comparator for LVDS Receiver was designed
at 0.18um technology.
REFERENCES
[1] IEEE standard for low-voltage differential signals (lvds)
for scalable coherent interface (sci), 1596.3 sci-lvds
standard. IEEE Std.1596.3-1996, 1994.
[2] Sung-Jun Song Sung-Sik Song Wang-Joo Lee Hoi-Jun
Yo0 Jaeseo Lee, Jae-Won Lim. Design and
implementation of cmos lvds 2.5gb/s transmitter and
1.3gb/s receiver for optical interconnections, 2008.
[3] Wei Feng Hao Cui Lingyi Huang Weiwu Hu Feng
Zhang, Zongren Yang. A high speed cmos transmitter
and rail-to-rail receiver. 4TH IEEE international
symposium of electronics design, test and applications,
2008.
[4] Davide Vecchi Andrea Boni, Andrea Pierazzi. Lvds i/o
interface for gb/s-per-pin operation in .35m cmos. IEEE
J. Solid-state circuits, 36:706–711, April 2001.
[5] B.Young. A soi cmos lvds driver and receiver pair.
IEEE Symposium on VLSI Circuits, pages 153–154,
2001.
Copyright© IJRTS | www.ijrts.com 31

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International Journal for Research in Technological Studies| Vol.

1, Issue 4, March 2014 | ISSN (online): 2348-1439

Design of High-Speed Comparator for LVDS Receiver

= 10% (1ns) =0.1nS

Fig.2: Comparator Schematic

Fig.6: Comparator AC Response

Copyright© IJRTS | www.ijrts.com 30

[6] Razavi. B. Design of Analog CMOS Integrated

Fig.7: Comparator Transient Schematic

Fig.8: Comparator Transient Response

Fig.9: Comparator Layout

Copyright© IJRTS | www.ijrts.com 31

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