Adf4110bruz Adf4111bcpz Adf4111bruz Adf4112bruz Adf4113bruz Ev-Adf411xsd1z

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ADF4110BRUZ ADF4111BCPZ ADF4111BRUZ ADF4112BRUZ ADF4113BRUZ
EV-ADF411XSD1Z
EN DE FR
This Datasheet is presented by Dieses Datenblatt wird vom Cette fiche technique est
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RF PLL Frequency Synthesizers
Data Sheet ADF4110/ADF4111/ADF4112/ADF4113
FEATURES GENERAL DESCRIPTION
ADF4110: 550 MHz; ADF4111: 1.2 GHz; ADF4112: 3.0 GHz; The ADF4110 family of frequency synthesizers can be used to
ADF4113: 4.0 GHz
implement local oscillators in the upconversion and downcon-
2.7 V to 5.5 V power supply
version sections of wireless receivers and transmitters. They
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems consist of a low noise digital PFD (phase frequency detector), a
Programmable dual-modulus prescaler 8/9, 16/17, 32/33, precision charge pump, a programmable reference divider,
64/65 programmable A and B counters, and a dual-modulus prescaler
Programmable charge pump currents (P/P + 1). The A (6-bit) and B (13-bit) counters, in conjunction
Programmable antibacklash pulse width with the dual-modulus prescaler (P/P + 1), implement an N
3-wire serial interface divider (N = BP + A). In addition, the 14-bit reference counter
Analog and digital lock detect (R counter) allows selectable REFIN frequencies at the PFD
Hardware and software power-down mode input. A complete phase-locked loop (PLL) can be implemented
if the synthesizer is used with an external loop filter and voltage
APPLICATIONS
controlled oscillator (VCO).
Base stations for wireless radio (GSM, PCS, DCS, CDMA,
WCDMA) Control of all the on-chip registers is via a simple 3-wire
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) interface. The devices operate with a power supply ranging
Wireless LANS from 2.7 V to 5.5 V and can be powered down when not in use.
Communications test equipment
CATV equipment
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD VP CPGND RSET
REFERENCE
14-BIT
REFIN
R COUNTER PHASE CHARGE
FREQUENCY PUMP CP
14 DETECTOR
R COUNTER
LATCH
CLK
24-BIT FUNCTION
DATA INPUT REGISTER LATCH LOCK CURRENT CURRENT
22
LE DETECT SETTING 1 SETTING 2
A, B COUNTER
SDOUT LATCH CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
19
FROM
FUNCTION HIGH Z
LATCH
AVDD
13
MUX MUXOUT
N = BP + A
13-BIT
B COUNTER
SDOUT
RFINA PRESCALER LOAD
P/P +1 LOAD
RFINB
6-BIT
A COUNTER M3 M2 M1
ADF4110/ADF4111
03496-0-001
6
ADF4112/ADF4113
CE AGND DGND
Figure 1. Functional Block Diagram
Rev. F Document Feedback

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ADF4110/ADF4111/ADF4112/ADF4113 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Phase Frequency Detector (PFD) and Charge Pump............ 13
Applications ....................................................................................... 1 Muxout and Lock Detect ........................................................... 13
General Description ......................................................................... 1 Input Shift Register .................................................................... 13
Functional Block Diagram .............................................................. 1 Function Latch ............................................................................ 19
Revision History ............................................................................... 2 Initialization Latch ..................................................................... 20
Specifications..................................................................................... 3 Device Programming after Initial Power-Up ......................... 20
Timing Characteristics ..................................................................... 5 Resynchronizing the Prescaler Output .................................... 21
Absolute Maximum Ratings ............................................................ 6 Applications..................................................................................... 22
Transistor Count ........................................................................... 6 Local Oscillator for GSM Base Station Transmitter .............. 22
ESD Caution .................................................................................. 6 Using a D/A Converter to Drive the RSET Pin ......................... 23
Pin Configurations and Function Descriptions ........................... 7 Shutdown Circuit ....................................................................... 23
Typical Performance Characteristics ............................................. 8 Wideband PLL ............................................................................ 23
Circuit Description ......................................................................... 12 Direct Conversion Modulator .................................................. 25
Reference Input Section ............................................................. 12 Interfacing ................................................................................... 26
RF Input Stage ............................................................................. 12 PCB Design Guidelines for Chip Scale Package .................... 26
Prescaler (P/P + 1) ...................................................................... 12 Outline Dimensions ....................................................................... 27
A and B Counters ....................................................................... 12 Ordering Guide ............................................................................... 28
R Counter .................................................................................... 12
REVISION HISTORY
1/13—Rev. E to Rev. F 3/03—Data sheet changed from Rev. A to Rev. B.
Changes to Table 1 ............................................................................. 4 Edits to Specifications ....................................................................... 2
Changes to Ordering Guide ...........................................................28 Updated OUTLINE DIMENSIONS ............................................. 24
8/12—Rev. D to Rev. E 1/01—Data sheet changed from Rev. 0 to Rev. A.

Changed CP-20-1 to CP-20-6 ........................................... Universal Changes to DC Specifications in B Version, B Chips,
Updated Outline Dimensions ........................................................28 Unit, and Test Conditions/Comments Columns ..................... 2
Changes to Ordering Guide ...........................................................28 Changes to Absolute Maximum Rating ......................................... 4
Changes to FRINA Function Test ..................................................... 5
5/12—Rev. C to Rev. D Changes to Figure 8 ........................................................................... 7
Changes to Figure 2 ........................................................................... 5 New Graph Added—TPC 22 ........................................................... 9
Changes to Figure 4 and Table 4 ...................................................... 7 Change to PD Polarity Box in Table V ......................................... 15
Updated Outline Dimensions ........................................................28 Change to PD Polarity Box in Table VI ........................................ 16
Changes to Ordering Guide ...........................................................28 Change to PD Polarity Paragraph ................................................. 17
3/04—Data sheet changed from Rev. B to Rev. C. Addition of New Material
Updated Format .................................................................. Universal (PCB Design Guidelines for Chip–Scale package) ................ 23
Changes to Specifications ................................................................. 2 Replacement of CP-20 Outline with CP-20 [2] Outline ............ 24
Changes to Figure 32 .......................................................................22
Changes to the Ordering Guide.....................................................28
Rev. F | Page 2 of 28
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω;
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is as follows: B Version: −40°C to +85°C.
Table 1.
Parameter B Version B Chips 1 Unit Test Conditions/Comments
RF CHARACTERISTICS (3 V) See Figure 29 for input circuit.
RF Input Sensitivity −15/0 −15/0 dBm min/max
RF Input Frequency
ADF4110 80/550 80/550 MHz min/max For lower frequencies, ensure slew rate
(SR) > 30 V/µs.
ADF4110 50/550 50/550 MHz min/max Input level = −10 dBm.
ADF4111 0.08/1.2 0.08/1.2 GHz min/max For lower frequencies, ensure SR > 30 V/µs.
ADF4112 0.1/3.0 0.1/3.0 GHz min/max Input level = −10 dBm.
ADF4113 0.2/3.7 0.2/3.7 GHz min/max Input level = −10 dBm. For lower frequencies,
ensure SR > 130 V/µs.
Maximum Allowable Prescaler Output
Frequency 2 165 165 MHz max
RF CHARACTERISTICS (5 V)
RF Input Sensitivity −10/0 −10/0 dBm min/max
RF Input Frequency
ADF4110 80/550 80/550 MHz min/max For lower frequencies, ensure SR > 50 V/µs.
ADF4113 0.2/4.0 0.2/4.0 GHz min/max Input level = −5 dBm.
Maximum Allowable Prescaler Output
Frequency2 200 200 MHz max
REFIN CHARACTERISTICS
REFIN Input Frequency 5/104 5/104 MHz min/max For f < 5 MHz, ensure SR > 100 V/µs.
Reference Input Sensitivity 0.4/AVDD 0.4/AVDD V p-p min/max AVDD = 3.3 V, biased at AVDD/2. See Note 3.
3.0/AVDD 3.0/AVDD V p-p min/max AVDD = 5 V, biased at AVDD/2. See Note 3.
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 µA max
PHASE DETECTOR FREQUENCY 4 55 55 MHz max
CHARGE PUMP
ICP Sink/Source Programmable (see Table 9).
High Value 5 5 mA typ With RSET = 4.7 kΩ.
Low Value 625 625 µA typ
Absolute Accuracy 2.5 2.5 % typ With RSET = 4.7 kΩ.
RSET Range 2.7/10 2.7/10 kΩ typ See Table 9.
ICP 3-State Leakage Current 1 1 nA typ
Sink and Source Current Matching 2 2 % typ 0.5 V ≤ VCP ≤ VP – 0.5 V.
ICP vs. VCP 1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP – 0.5 V.
ICP vs. Temperature 2 2 % typ VCP = VP/2.
LOGIC INPUTS
VINH, Input High Voltage 0.8 × DVDD 0.8 × DVDD V min
VINL, Input Low Voltage 0.2 × DVDD 0.2 × DVDD V max
IINH/IINL, Input Current ±1 ±1 µA max
CIN, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
VOH, Output High Voltage DVDD – 0.4 DVDD – 0.4 V min IOH = 500 µA.
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA.
Parameter B Version B Chips 1 Unit Test Conditions/Comments
POWER SUPPLIES
AVDD 2.7/5.5 2.7/5.5 V min/V max
DVDD AVDD AVDD
VP AVDD/6.0 AVDD/6.0 V min/V max AVDD ≤ VP ≤ 6.0 V. See Figure 25 and Figure 26.
IDD 5 (AIDD + DIDD)
ADF4110 5.5 4.5 mA max 4.5 mA typical.
ADF4113 11 8.5 mA max 8.5 mA typical.
IP 0.5 0.5 mA max TA = 25°C.
Low Power Sleep Mode 1 1 µA typ
NOISE CHARACTERISTICS
ADF4113 Normalized Phase Noise Floor 6 −215 −215 dBc/Hz typ
Phase Noise Performance 7 @ VCO output.
ADF4110: 540 MHz Output 8 −91 −91 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency.
ADF4112: 900 MHz Output9 −90 −90 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency.
ADF4111: 836 MHz Output 10 −78 −78 dBc/Hz typ @ 300 Hz offset and 30 kHz PFD frequency.
ADF4112: 1750 MHz Output 12 −66 −66 dBc/Hz typ @ 200 Hz offset and 10 kHz PFD frequency.
ADF4113: 3100 MHz Output 14 −86 −86 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency.
Spurious Signals
ADF4110: 540 MHz Output9 −97/−106 −97/−106 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency.
ADF4113: 3100 MHz Output14 −80/−82 −82/−82 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD frequency.
1
The B chip specifications are given as typical values.
2
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3
AC coupling ensures AVDD/2 bias. See Figure 33 for a typical circuit.
4
Guaranteed by design.
5
TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logFPFD: PNSYNTH = PNTOT – 10logFPFD – 20logN.
7
The phase noise is measured with the EV-ADF411XSD1Z evaluation board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (Table 7).
8
fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop B/W = 20 kHz.
9
10
fREFIN = 10 MHz; fPFD = 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop B/W = 3 kHz.
11
fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz
12
fREFIN = 10 MHz; fPFD = 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop B/W = 1 kHz.
13
14
fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; loop B/W = 20 kHz.
TIMING CHARACTERISTICS
Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6 V;
AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments
t1 10 ns min DATA to CLOCK setup time
t2 10 ns min DATA to CLOCK hold time
t3 25 ns min CLOCK high duration
t4 25 ns min CLOCK low duration
t5 10 ns min CLOCK to LE setup time
t6 20 ns min LE pulse width
t3 t4
CLOCK
t1 t2
DB1 DB0 (LSB)

DATA DB23 (MSB) DB22 DB2 (CONTROL BIT C2) (CONTROL BIT C1)
t6
LE
t5
03496-002
LE
Figure 2. Timing Diagram
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
Table 3. rating only; functional operation of the device at these or any
Parameter Rating other conditions above those listed in the operational sections
AVDD to GND 1 −0.3 V to +7 V of this specification is not implied. Exposure to absolute
AVDD to DVDD −0.3 V to +0.3 V maximum rating conditions for extended periods may affect
VP to GND −0.3 V to +7 V device reliability.
VP to AVDD −0.3 V to +5.5 V
This device is a high performance RF integrated circuit with an
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
Analog I/O Voltage to GND −0.3 V to VP + 0.3 V
should be taken for handling and assembly.
REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V
RFINA to RFINB ±320 mV TRANSISTOR COUNT
Operating Temperature Range
6425 (CMOS) and 303 (Bipolar).
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 150.4°C/W
LFCSP θJA Thermal Impedance 122°C/W
(Paddle Soldered)
LFCSP θJA Thermal Impedance 216°C/W
(Paddle Not Soldered)
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
GND = AGND = DGND = 0 V.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
17 DVDD
16 DVDD
19 RSET
20 CP
18 VP
RSET 1 16 VP
CP 2 15 DVDD 15 MUXOUT
ADF4110 CPGND 1 ADF4110
CPGND 3 ADF4111 14 MUXOUT AGND 2 ADF4111 14 LE
ADF4112 AGND 3 ADF4112 13 DATA
AGND 4 13 LE ADF4113
ADF4113 RFINB 4 12 CLK
RFINB 5 12 DATA TOP VIEW
RFINA 5 (Not to Scale) 11 CE
RFINA 6 11 CLK
TOP VIEW
AVDD 7 (Not to Scale) 10 CE
03496-0-003
6
7
REFIN 8
9
DGND 10
REFIN 8 9 DGND
DGND
AVDD
AVDD
03496-0-004
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND.
Figure 3. TSSOP Pin Configuration Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions

TSSOP LFCSP
Pin No. Pin No. Mnemonic Function
1 19 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is
23.5
I CPmax =
R SET
So, with RSET = 4.7 kΩ, ICPmax = 5 mA.
2 20 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn
drives the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 29.
6 5 RFINA Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
7 6, 7 AVDD Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8 8 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2, and an equivalent input
resistance of 100 kΩ. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator, or
can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device depending on the status of the power-
down Bit F2.
11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13 14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
14 15 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
15 16, 17 DVDD Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
16 18 VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
VP can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. 1
EPAD Exposed Pad (LFCSP Only). The exposed paddle should be connected to AGND.
TYPICAL PERFORMANCE CHARACTERISTICS

0
FREQ PARAM DATA KEYWORD IMPEDANCE
–UNIT –TYPE –FORMAT –OHMS REFERENCE
–10 VDD = 3V, VP = 5V
GHz S MA R 50 LEVEL = –4.2dBm ICP = 5mA
FREQ MAGS11 ANGS11 FREQ MAGS11 ANGS11 –20 PFD FREQUENCY = 200kHz
0.05 0.89207 –2.0571 1.05 0.9512 –40.134 LOOP BANDWIDTH = 20kHz
0.10 0.8886 –4.4427 1.10 0.93458 –43.747
RES. BANDWIDTH = 10Hz
OUTPUT POWER (dB)

0.15 0.89022 –6.3212 1.15 0.94782 –44.393 –30
0.20 0.96323 –2.1393 1.20 0.96875 –46.937 VIDEO BANDWIDTH = 10Hz
0.25 0.90566 –12.13 1.25 0.92216 –49.6 –40 SWEEP = 1.9 s
0.30 0.90307 –13.52 1.30 0.93755 –51.884
0.35 0.89318 –15.746 1.35 0.96178 –51.21 AVERAGES = 19
0.40 0.89806 –18.056 1.40 0.94354 –53.55 –50
0.45 0.89565 –19.693 1.45 0.95189 –56.786
0.50 0.88538 –22.246 1.50 0.97647 –58.781
0.55 0.89699 –24.336 1.55 0.98619 –60.545 –60
0.60 0.89927 –25.948 1.60 0.95459 –61.43
0.65 0.87797 –28.457 1.65 0.97945 –61.241 –70 –92.5dBc/Hz
0.70 0.90765 –29.735 1.70 0.98864 –64.051
0.75 0.88526 –31.879 1.75 0.97399 –66.19
0.80 0.81267 –32.681 1.80 0.97216 –63.775 –80
0.85 0.90357 –31.522
03496-0-005
0.90 0.92954 –34.222 –90
0.95 0.92087 –36.961
1.00 0.93788 –39.343
–100
03496-0-008
–2.0kHz –1.0kHz 900MHz 1.0kHz 2.0kHz
FREQUENCY
Figure 5. S-Parameter Data for the ADF4113 RF Input (up to 1.8 GHz) Figure 8. ADF4113 Phase Noise
(900 MHz, 200kHz, 20 kHz) with DLY and SYNC Enabled
0
–40
VDD = 3V –50
–5
VP = 3V
–60
RF INPUT POWER (dBm)
–10 RMS NOISE = 0.52°

PHASE NOISE (dBc/Hz)
–70 RL = –40dBc/Hz
–15 –80
TA = +25°C
–90
–20 TA = +85°C
–100
–25 –110
–120
–30
–130
TA = –40°C
–35
03496-0-006
0 1 2 3 4 5 –140
03496-0-009
100 1k 10k 100k 1M
RF INPUT FREQUENCY (GHz)
FREQUENCY OFFSET FROM 900MHz CARRIER (Hz)
Figure 6. Input Sensitivity (ADF4113) Figure 9. ADF4113 Integrated Phase Noise

(900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 µs)
0
–40
–10 REFERENCE VDD = 3V, VP = 5V
LEVEL = –4.2dBm –50
ICP = 5mA
–20 PFD FREQUENCY = 200kHz
–60
LOOP BANDWIDTH = 20kHz
RMS NOISE = 0.62°
OUTPUT POWER (dB)
–30
–70 RL = –40dBc/Hz
VIDEO BANDWIDTH = 10Hz
–40 SWEEP = 1.9 s
–80
AVERAGES = 19
–50
–90
–60
–100
–70 –91.0dBc/Hz
–110
–80
–120
–90
–130
–100
03496-0-007
–140
03496-0-010
–2.0kHz –1.0kHz 900MHz 1.0kHz 2.0kHz

100 1k 10k 100k 1M
FREQUENCY
FREQUENCY OFFSET FROM 900MHz CARRIER (Hz)
Figure 7. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz) Figure 10. ADF4113 Integrated Phase Noise
(900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 µs)
0 –40
–10 REFERENCE VDD = 3V, VP = 5V –50

LEVEL = –4.2dBm ICP = 5mA
–20 PFD FREQUENCY = 200kHz –60
LOOP BANDWIDTH = 20kHz RMS NOISE = 1.6°

RES. BANDWIDTH = 1kHz
OUTPUT POWER (dB)
–30 –70 RL = –40dBc/Hz

VIDEO BANDWIDTH = 1kHz
–40 SWEEP = 2.5s –80
AVERAGES = 30
–50 –90
–60 –100
–70 –110
–80 –90.2dBc/Hz –120
–90 –130
–100 –140
03496-0-014
03496-0-011
–400kHz –200kHz 900MHz 200kHz 400kHz 100 1k 10k 100k 1M
FREQUENCY FREQUENCY OFFSET FROM 1750MHz CARRIER (Hz)
Figure 11. ADF4113 Reference Spurs (900 MHz, 200 kHz, 20 kHz) Figure 14. ADF4113 Integrated Phase Noise
(1750 MHz, 30 kHz, 3 kHz)
0
0
LEVEL = –4.2dBm –10 REFERENCE VDD = 3V, VP = 5V
ICP = 5mA LEVEL = –5.7dBm
–20 PFD FREQUENCY = 200kHz ICP = 5mA
LOOP BANDWIDTH = 35kHz –20 PFD FREQUENCY = 30kHz
RES. BANDWIDTH = 1kHz LOOP BANDWIDTH = 3kHz
OUTPUT POWER (dB)
–30
OUTPUT POWER (dB)
VIDEO BANDWIDTH = 1kHz –30
–40 SWEEP = 2.5s VIDEO BANDWIDTH = 3Hz
AVERAGES = 30 –40 SWEEP = 255s
–50 POSITIVE PEEK DETECT
–50 MODE
–60
–60
–70
–70 –79.6dBc/Hz
–80 –89.3dBc/Hz
–80
–90
–90
–100
03496-0-012
–400kHz –200kHz 900MHz 200kHz 400kHz –100
03496-0-015
–80kHz –40kHz 1750MHz 40kHz 80kHz
FREQUENCY
FREQUENCY
Figure 12. ADF4113 (900 MHz, 200 kHz, 35 kHz) Figure 15. ADF4113 Reference Spurs (1750 MHz, 30 kHz, 3 kHz)
0 0
–10 REFERENCE VDD = 3V, VP = 5V REFERENCE VDD = 3V, VP = 5V

–10
LEVEL = –8.0dBm ICP = 5mA LEVEL = –4.2dBm ICP = 5mA
–20 PFD FREQUENCY = 30kHz –20 PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 3kHz LOOP BANDWIDTH = 100kHz
OUTPUT POWER (dB)
–30 RES. BANDWIDTH = 10Hz

OUTPUT POWER (dB)
–30
VIDEO BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10Hz
–40 SWEEP = 477ms –40 SWEEP = 1.9s
AVERAGES = 10 AVERAGES = 45
–50 –50
–60 –60
–86.6dBc/Hz
–70 –70
–80 –75.2dBc/Hz –80
–90 –90
–100 –100
03496-0-013
03496-0-016
–400Hz –200Hz 1750MHz 200Hz 400Hz –2.0kHz –1.0kHz 3100MHz 1.0kHz 2.0kHz
FREQUENCY FREQUENCY
Figure 13. ADF4113 Phase Noise (1750 MHz, 30 kHz, 3 kHz) Figure 16. ADF4113 Phase Noise (3100 MHz, 1 MHz, 100 kHz)
–40 –60
–50 VDD = 3V
VP = 3V
–60
RMS NOISE = 1.7° –70

–70 RL = 40dBc/Hz
–80
–90 –80
–100
–110
–90
–120
–130
–140 –100
03496-0-020
03496-0-017
102 103 104 105 106 –40 –20 0 20 40 60 80 100
FREQUENCY OFFSET FROM 3100MHz CARRIER (Hz) TEMPERATURE (°C)
Figure 17. ADF4113 Integrated Phase Noise Figure 20. ADF4113 Phase Noise vs. Temperature
(3100 MHz, 1 MHz, 100 kHz) (900 MHz, 200 kHz, 20 kHz)
0 –60

LEVEL = –17.2dBm VDD = 3V
ICP = 5mA FIRST REFERENCE SPUR (dBc) VP = 5V
–20 PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz –70
OUTPUT POWER (dB)
–30
VIDEO BANDWIDTH = 1kHz
–40 SWEEP = 13s
AVERAGES = 1
–50 –80
–60
–70 –80.6dBc/Hz
–90
–80
–90
–100 –100
03496-0-021
03496-0-018
–2.0MHz –1.0MHz 3100MHz 1.0MHz 2.0MHz –40 –20 0 20 40 60 80 100
FREQUENCY TEMPERATURE (°C)
Figure 18. Reference Spurs (3100 MHz, 1 MHz, 100 kHz) Figure 21. ADF4113 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
–120 –5
VDD = 3V –15
VDD = 3V
–130 VP = 5V VP = 5V
FIRST REFERENCE SPUR (dBc)
–25
–140 –35
–45
–150 –55
–65
–160
–75
–170 –85
–95
–180
03496-0-019
–105
03496-0-022
1 10 100 1000 10000 0 1 2 3 4 5

PHASE DETECTOR FREQUENCY (kHz) TUNING VOLTAGE (V)
Figure 19. ADF4113 Phase Noise (Referred to CP Output) Figure 22. ADF4113 Reference Spurs (200 kHz) vs. VTUNE
vs. Phase Detector Frequency (900 MHz, 200 kHz, 20 kHz)
–60 3.0
VDD = 3V
VDD = 3V VP = 3V
VP = 5V 2.5
–70
2.0
DIDD (mA)
–80 1.5
1.0
–90
0.5
–100 0
03496-0-023
03496-0-026
–40 –20 0 20 40 60 80 100 0 50 100 150 200
TEMPERATURE (°C) PRESCALER OUTPUT FREQUENCY (MHz)
Figure 23. ADF4113 Phase Noise vs. Temperature Figure 26. DIDD vs. Prescaler Output Frequency
(836 MHz, 30 kHz, 3 kHz) (ADF4110, ADF4111, ADF4112, ADF4113)
–60 6
5
VDD = 3V VPP = 5V
VP = 5V 4 ICP = 5mA
FIRST REFERENCE SPUR (dBc)
–70 3
2
1
ICP (mA)
–80 0
–1
–2
–90 –3
–4
–5
–100 –6
03496-0-024
03496-0-027
–40 –20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TEMPERATURE (°C) VCP (V)
Figure 24. ADF4113 Reference Spurs vs. Temperature Figure 27. Charge Pump Output Characteristics for ADF4110 Family
(836 MHz, 30 kHz, 3 kHz)
10
8
ADF4113
7
6
AIDD (mA)
5
ADF4112
4
2
ADF4110
1 ADF4111
0
03496-0-025
0 8/9 16/17 32/33 64/65
PRESCALER VALUE
Figure 25. AIDD vs. Prescaler Value
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION A AND B COUNTERS
The reference input stage is shown in Figure 28. SW1 and SW2 The A and B CMOS counters combine with the dual-modulus
are normally closed switches. SW3 is normally open. When prescaler to allow a wide ranging division ratio in the PLL
power-down is initiated, SW3 is closed and SW1 and SW2 are feedback counter. The counters are specified to work when the
opened. This ensures that there is no loading of the REFIN pin prescaler output is 200 MHz or less. Thus, with an RF input
on power-down. frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not.
POWER-DOWN
CONTROL Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
NC 100k
prescaler, make it possible to generate output frequencies that
SW2
REFIN NC TO R COUNTER are spaced only by the reference frequency divided by R. The
BUFFER
SW1 equation for the VCO frequency is
03496-0-028
SW3
NO
fVCO = [(P × B) + A]fREFIN/R
Figure 28. Reference Input Stage
where:
RF INPUT STAGE fVCO = output frequency of external voltage controlled oscillator

The RF input stage is shown in Figure 29. It is followed by a (VCO)
two-stage limiting amplifier to generate the current mode logic P = preset modulus of dual-modulus prescaler
(CML) clock levels needed for the prescaler. B = preset divide ratio of binary 13-bit counter(3 to 8191)
A = preset divide ratio of binary 6-bit swallow counter (0 to 63)
fREFIN = output frequency of the external reference frequency
BIAS 1.6V oscillator
GENERATOR AVDD
R = preset divide ratio of binary 14-bit programmable reference
500 500 counter (1 to 16383)
RFINA R COUNTER
RFINB The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
03496-0-029
frequency detector (PFD). Division ratios from 1 to 16,383 are

AGND allowed.
Figure 29. RF Input Stage
N = BP + A
PRESCALER (P/P + 1) 13-BIT B
TO PFD
COUNTER
Along with the A and B counters, the dual-modulus prescaler FROM RF
INPUT STAGE LOAD
PRESCALER
(P/P + 1) enables the large division ratio, N, to be realized (N = P/P + 1
LOAD
BP + A). The dual-modulus prescaler, operating at CML levels,
MODULUS 6-BIT A
takes the clock from the RF input stage and divides it down to a CONTROL COUNTER
03496-0-030
manageable frequency for the CMOS A and B counters. The

prescaler is programmable; it can be set in software to 8/9,
Figure 30. A and B Counters
16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.
PHASE FREQUENCY DETECTOR (PFD) AND Lock Detect
CHARGE PUMP MUXOUT can be programmed for two types of lock detect:
The PFD takes inputs from the R counter and N counter (N = digital lock detect and analog lock detect.
BP + A) and produces an output proportional to the phase and
Digital lock detect is active high. When LDP in the R counter
frequency difference between them. Figure 31 is a simplified
latch is set to 0, digital lock detect is set high when the phase
schematic. The PFD includes a programmable delay element
error on three consecutive phase detector (PD) cycles is less
that controls the width of the antibacklash pulse. This pulse
than 15 ns. With LDP set to 1, five consecutive cycles of less
ensures that there is no dead zone in the PFD transfer function
than 15 ns are required to set the lock detect. It stays high until
and minimizes phase noise and reference spurs. Two bits in the
a phase error greater than 25 ns is detected on any subsequent
reference counter latch, ABP2 and ABP1, control the width of
PD cycle.
the pulse. See Table 7.
The N-channel open-drain analog lock detect should be
VP
CHARGE
operated with a 10 kΩ nominal external pull-up resistor. When
PUMP lock has been detected, this output is high with narrow low-
HI D1 Q1
UP
going pulses.
U1
DVDD
R DIVIDER
CLR1
PROGRAMMABLE U3 CP ANALOG LOCK DETECT

DELAY DIGITAL LOCK DETECT
R COUNTER OUTPUT MUX CONTROL MUXOUT
N COUNTER OUTPUT
ABP1 ABP2 SDOUT
CLR2
DOWN
03496-0-032
HI D2 Q2
U2 DGND
N DIVIDER Figure 32. MUXOUT Circuit

CPGND
INPUT SHIFT REGISTER

R DIVIDER
The ADF4110 family digital section includes a 24-bit input shift
N DIVIDER register, a 14-bit R counter, and a 19-bit N counter comprised of
a 6-bit A counter and a 13-bit B counter. Data is clocked into
03496-0-031
CP OUTPUT the 24-bit shift register on each rising edge of CLK MSB first.
Data is transferred from the shift register to one of four latches
Figure 31. PFD Simplified Schematic and Timing (In Lock)
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2, C1) in the shift register.
MUXOUT AND LOCK DETECT These are the two LSBs, DB1 and DB0, as shown in Figure 2.
The output multiplexer on the ADF4110 family allows the user The truth table for these bits is shown in Table 5.
to access various internal points on the chip. The state of Table 6 shows a summary of how the latches are programmed.
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Table 9 shows the full truth table. Figure 32 shows the Table 5. C2, C1 Truth Table
MUXOUT section in block diagram form. Control Bits
C2 C1 Data Latch
0 0 R Counter
0 1 N Counter (A and B)
1 0 Function Latch (Including Prescaler)
1 1 Initialization Latch
Table 6. ADF4110 Family Latch Summary
REFERENCE COUNTER LATCH

PRECISION
RESERVED
DETECT
LOCK
ANTI-
TEST BACKLASH CONTROL
DLY SYNC MODE BITS WIDTH 14-BIT REFERENCE COUNTER, R BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X DLY SYNC LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)
X = DON'T CARE
N COUNTER LATCH
CP GAIN
CONTROL
RESERVED 13-BIT B COUNTER 6-BIT A COUNTER BITS
X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)
X = DON'T CARE
FUNCTION LATCH
FASTLOCK
FASTLOCK
COUNTER
POLARITY
POWER-
POWER-
THREE-
DOWN 2
DOWN 1
ENABLE
RESET
STATE
MODE
CURRENT CURRENT
PD
CP
PRESCALER SETTING SETTING TIMER COUNTER MUXOUT CONTROL

VALUE 2 1 CONTROL CONTROL BITS
P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)
INITIALIZATION LATCH
THREE-STATE
FASTLOCK
FASTLOCK
COUNTER
POLARITY
POWER-
POWER-
DOWN 1
ENABLE
DOWN 2
RESET
MODE
CP
PD
CURRENT CURRENT
03496-0-033
Table 7. Reference Counter Latch Map
RESERVED
PRECISION
DETECT
LOCK
ANTI-
TEST BACKLASH CONTROL
DLY SYNC MODE BITS WIDTH 14-BIT REFERENCE COUNTER BITS
X DLY SYNC LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)
X = DON'T
CARE
R14 R13 R12 •••••••••• R3 R2 R1 DIVIDE RATIO

0 0 0 ••••••••• • 0 0 1 1
0 0 0 ••••••••• • 0 1 0 2
0 0 0 ••••••••• • 0 1 1 3
0 0 0 ••••••••• • 1 0 0 4
• • • ••••••••• • • • • •
• • • ••••••••• • • • • •
• • • ••••••••• • • • • •
1 1 1 ••••••••• • 1 0 0 16380
1 1 1 ••••••••• • 1 0 1 16381
1 1 1 ••••••••• • 1 1 0 16382
1 1 1 ••••••••• • 1 1 1 16383
ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
0 0 3.0ns
0 1 1.5ns
1 0 6.0ns
1 1 3.0ns
TEST MODE BITS SHOULD

BE SET TO 00 FOR NORMAL
OPERATION
LDP OPERATION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
DLY SYNC OPERATION
0 0 NORMAL OPERATION
0 1 OUTPUT OF PRESCALER IS RESYNCHRONIZED

WITH NONDELAYED VERSION OF RF INPUT
1 0 NORMAL OPERATION
03496-0-034
1 1 OUTPUT OF PRESCALER IS RESYNCHRONIZED

WITH DELAYED VERSION OF RF INPUT
Table 8. AB Counter Latch Map
CP GAIN
CONTROL
RESERVED 13-BIT B COUNTER 6-BIT A COUNTER BITS
X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)
X = DON'T CARE
A COUNTER
A6 A5 ••••••••• • A2 A1
DIVIDE RATIO
0 0 ••••••••• • 0 0 0
0 0 ••••••••• • 0 1 1
0 0 ••••••••• • 1 0 2
0 0 ••••••••• • 1 1 3
• • ••••••••• • • • •
• • ••••••••• • • • •
• • ••••••••• • • • •
1 1 ••••••••• • 0 0 60
1 1 ••••••••• • 0 1 61
1 1 ••••••••• • 1 0 62
1 1 ••••••••• • 1 1 63
B13 B12 B11 ••••••••• • B3 B2 B1 B COUNTER DIVIDE RATIO

0 0 0 ••••••••• • 0 0 0 NOT ALLOWED
0 0 0 ••••••••• • 0 0 1 NOT ALLOWED
0 0 0 ••••••••• • 0 1 0 NOT ALLOWED
0 0 0 ••••••••• • 0 1 1 3
0 0 0 ••••••••• • 1 0 0 4
• • • ••••••••• • • • • •
• • • ••••••••• • • • • •
• • • ••••••••• • • • • •
1 1 1 ••••••••• • 1 0 0 8188
1 1 1 ••••••••• • 1 0 1 8189
1 1 1 ••••••••• • 1 1 0 8190
1 1 1 ••••••••• • 1 1 1 8191
F4 (FUNCTION LATCH)
CP GAIN OPERATION
FASTLOCK ENABLE*
0 0 CHARGE PUMP CURRENT SETTING 1

IS PERMANENTLY USED.

IS PERMANENTLY USED.

IS USED.
1 1 CHARGE PUMP CURRENT IS SWITCHED

TO SETTING 2. THE TIME SPENT IN
SETTING 2 IS DEPENDENT UPON WHICH
FASTLOCK MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION. N = BP + A, P IS PRESCALER VALUE SET IN THE
FUNCTION LATCH, B MUST BE GREATER THAN OR
*SEE TABLE 9 EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES
OF (NX FREF), AT THE OUTPUT, NMIN IS (P2–P).
THESE BITS ARE NOT USED

03496-0-035
BY THE DEVICE AND ARE

DON'T CARE BITS
Table 9. Function Latch Map
THREE-STATE
FASTLOCK
FASTLOCK
COUNTER
POLARITY
POW ER-
POW ER-
DOW N 2
DOW N 1
ENABLE
RESET
MODE
CP
PD
CURRENT CURRENT
P2 P1 PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2(1) C1(0)
COUNTER
F1
OPERATION
PHASE DETECTOR 0 NORMAL

F2
POLARITY
1 R, A, B COUNTERS
0 NEGATIVE HELD IN RESET
1 POSITIVE
F3 CHARGE PUMP OUTPUT
0 NORMAL
1 THREE-STATE
F4 F5 FASTLOCK MODE
0 X FASTLOCK DISABLED
1 0 FASTLOCK MODE 1
1 1 FASTLOCK MODE 2
TIMEOUT
TC4 TC3 TC2 TC1 (PFD CYCLES)
0 0 0 0 3
0 0 0 1 7
0 0 1 0 11
0 0 1 1 15
0 1 0 0 19
0 1 0 1 23
0 1 1 0 27
0 1 1 1 31
1 0 0 0 35 M3 M2 M1 OUTPUT
1 0 0 1 39 0 0 0 THREE-STATE OUTPUT
1 0 1 0 43
0 0 1 DIGITAL LOCK DETECT
1 0 1 1 47 (ACTIVE HIGH)
1 1 0 0 51 0 1 0 N DIVIDER OUTPUT
1 1 0 1 55
0 1 1 DVDD
1 1 1 0 59
1 0 0 R DIVIDER OUTPUT
1 1 1 1 63
1 0 1 ANALOG LOCK DETECT
CPI6 CPI5 CPI4 ICP (mA) SEE FUNCTION LATCH, (N-CHANNEL OPEN-DRAIN)
TIMER COUNTER CONTROL
CPI3 CPI2 CPI1 2.7kΩ 4.7kΩ 10kΩ SECTION 1 1 0 SERIAL DATA OUTPUT
0 0 0 1.09 0.63 0.29 1 1 1 DGND
0 0 1 2.18 1.25 0.59
0 1 0 3.26 1.88 0.88
0 1 1 4.35 2.50 1.76
1 0 0 5.44 3.13 1.47
1 0 1 6.53 3.75 1.76
1 1 0 7.62 4.38 2.06
1 1 1 8.70 5.00 2.35
CE PIN PD2 PD1 MODE
0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRONOUS POWER-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN
P2 P1 PRESCALER VALUE
0 0 8/9
0 1 16/17
03496-0-036
1 0 32/33
1 1 64/65
Table 10. Initialization Latch Map
THREE-STATE
FASTLOCK
COUNTER
POLARITY
FASTLOCK
POW ER-
POW ER-
DOW N 2
DOWN 1
ENABLE
RESET
MODE
CP
PD
CURRENT CURRENT
COUNTER
F1 OPERATION
PHASE DETECTOR 0 NORMAL

F2 POLARITY
1 R, A, B COUNTERS
0 NEGATIVE HELD IN RESET
1 POSITIVE
F3 CHARGE PUMP
0 OUTPUT NORMAL
1 THREE-STATE
F4 F5 FASTLOCK MODE
0 X FASTLOCK DISABLED
1 0 FASTLOCK MODE 1
1 1 FASTLOCK MODE 2
TIMEOUT
TC4 TC3 TC2 TC1 (PFD CYCLES)
0 0 0 0 3
0 0 0 1 7
0 0 1 0 11
0 0 1 1 15
0 1 0 0 19
0 1 0 1 23
0 1 1 0 27
0 1 1 1 31
1 0 0 0 35
M3 M2 M1 OUTPUT
1 0 0 1 39
0 0 0 THREE-STATE OUTPUT
1 0 1 0 43
0 0 1 DIGITAL LOCK DETECT
1 0 1 1 47 (ACTIVE HIGH)
1 1 0 0 51
0 1 0 N DIVIDER OUTPUT
1 1 0 1 55
0 1 1 DV DD
1 1 1 0 59
1 1 1 1 63 1 0 0 R DIVIDER OUTPUT
SEE FUNCTION LATCH, 1 0 1 ANALOG LOCK DETECT

CPI6 CPI5 CPI4 ICP (mA) (N-CHANNEL OPEN-DRAIN)
TIMER COUNTER CONTROL
CPI3 CPI2 CPI1 2.7kΩ 4.7kΩ 10kΩ SECTION 1 1 0 SERIAL DATA OUTPUT
0 0 0 1.09 0.63 0.29 1 1 1 DGND
0 0 1 2.18 1.25 0.59
0 1 0 3.27 1.88 0.88
0 1 1 4.35 2.50 1.76
1 0 0 5.44 3.13 1.47
1 0 1 6.53 3.75 1.76
1 1 0 7.62 4.38 2.06
1 1 1 8.70 5.00 2.35
CE PIN PD2 PD1 MODE
0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRONOUS POWER-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN
P2 P1 PRESCALER VALUE
0 0 8/9
0 1 16/17
03496-0-037
1 0 32/33
1 1 64/65
FUNCTION LATCH
The on-chip function latch is programmed with C2, C1 set to 1. Fastlock Mode Bit
Table 9 shows the input data format for programming the DB10 of the function latch is the fastlock enable bit. When
function latch. fastlock is enabled, this bit determines which fastlock mode is
used. If the fastlock mode bit is 0, fastlock mode 1 is selected; if
Counter Reset
the fastlock mode bit is 1, fastlock mode 2 is selected.
DB2 (F1) is the counter reset bit. When DB2 is 1, the R counter
and the AB counters are reset. For normal operation, this bit Fastlock Mode 1
should be 0. Upon powering up, the F1 bit must be disabled, The charge pump current is switched to the contents of Current
and the N counter resumes counting in “close” alignment with Setting 2.
the R counter. (The maximum error is one prescaler cycle.)
The device enters fastlock by having a 1 written to the CP gain
Power-Down bit in the AB counter latch. The device exits fastlock by having a
DB3 (PD1) and DB21 (PD2) on the ADF411x provide 0 written to the CP gain bit in the AB counter latch.
program-mable power-down modes. They are enabled by the
CE pin. Fastlock Mode 2
The charge pump current is switched to the contents of Current
When the CE pin is low, the device is immediately disabled
Setting 2. The device enters fastlock by having a 1 written to the
regardless of the states of PD2, PD1.
CP gain bit in the AB counter latch. The device exits fastlock
In the programmed asynchronous power-down, the device under the control of the timer counter. After the timeout period
powers down immediately after latching a 1 into Bit PD1, determined by the value in TC4 through TC1, the CP gain bit in
provided PD2 has been loaded with a 0. the AB counter latch is automatically reset to 0 and the device
reverts to normal mode instead of fastlock. See Table 9 for the
In the programmed synchronous power-down, the device timeout periods.
power-down is gated by the charge pump to prevent unwanted
frequency jumps. Once power-down is enabled by writing a 1 Timer Counter Control
into Bit PD1 (provided a 1 has also been loaded to PD2), the The user has the option of programming two charge pump cur-
device goes into power-down on the next charge pump event. rents. Current Setting 1 is meant to be used when the RF output
is stable and the system is in a static state. Current Setting 2 is
When a power-down is activated (either synchronous or meant to be used when the system is dynamic and in a state of
asynchronous mode including CE pin activated power-down), change (i.e., when a new output frequency is programmed).
the following events occur:
The normal sequence of events is as follows:
• All active dc current paths are removed.
The user initially decides what the preferred charge pump
• The R, N, and timeout counters are forced to their load currents are going to be. For example, they may choose 2.5 mA
state conditions. as Current Setting 1 and 5 mA as Current Setting 2.
• The charge pump is forced into three-state mode. At the same time, they must also decide how long they want the
secondary current to stay active before reverting to the primary
• The digital clock detect circuitry is reset. current. This is controlled by the timer counter control bits,
• The RFIN input is debiased. DB14 through DB11 (TC4 through TC1) in the function latch.
The truth table is given in Table 10.
• The reference input buffer circuitry is disabled.
A user can program a new output frequency simply by pro-
• The input register remains active and capable of loading gramming the AB counter latch with new values for A and B. At
and latching data. the same time, the CP gain bit can be set to 1, which sets the
charge pump with the value in CPI6–CPI4 for a period deter-
MUXOUT Control mined by TC4 through TC1. When this time is up, the charge
The on-chip multiplexer is controlled by M3, M2, and M1 on pump current reverts to the value set by CPI3–CPI1. At the
the ADF4110 family. Table 9 shows the truth table. same time, the CP gain bit in the AB counter latch is reset to 0
and is ready for the next time the user wishes to change the
Fastlock Enable Bit frequency.
DB9 of the function latch is the fastlock enable bit. Fastlock is
enables only when this is 1.
Note that there is an enable feature on the timer counter. It is When the initialization latch is loaded, the following occurs:
enabled when Fastlock Mode 2 is chosen by setting the fastlock
mode bit (DB10) in the function latch to 1. 1. The function latch contents are loaded.
Charge Pump Currents 2. An internal pulse resets the R, A, B, and timeout counters
to load state conditions and three-states the charge pump.
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
Note that the prescaler band gap reference and the oscil-
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
lator input buffer are unaffected by the internal reset pulse,
charge pump. The truth table is given in Table 10.
allowing close phase alignment when counting resumes.
Prescaler Value
3. Latching the first AB counter data after the initialization
P2 and P1 in the function latch set the prescaler values. The word activates the same internal reset pulse. Successive AB
prescaler value should be chosen so that the prescaler output loads do not trigger the internal reset pulse unless there is
frequency is always less than or equal to 200 MHz. Thus, with another initialization.
an RF frequency of 2 GHz, a prescaler value of 16/17 is valid but
a value of 8/9 is not. CE Pin Method
1. Apply VDD.
PD Polarity
This bit sets the phase detector polarity bit. See Table 10. 2. Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
CP Three-State
This bit controls the CP output pin. With the bit set high, the 3. Program the function latch (10). Program the R counter
CP output is put into three-state. With the bit set low, the CP latch (00). Program the AB counter latch (01).
output is enabled.
4. Bring CE high to take the device out of power-down. The R
INITIALIZATION LATCH and AB counters now resume counting in close alignment.
When C2, C1 = 1, 1, the initialization latch is programmed. After CE goes high, a duration of 1 µs may be required for the
This is essentially the same as the function latch (programmed prescaler band gap voltage and oscillator input buffer bias to
when C2, C1 = 1, 0). reach steady state.
However, when the initialization latch is programmed, an addi- CE can be used to power the device up and down in order to
tional internal reset pulse is applied to the R and AB counters. check for channel activity. The input register does not need to
This pulse ensures that the AB counter is at load point when the be reprogrammed each time the device is disabled and enabled
AB counter data is latched, and the device begins counting in as long as it has been programmed at least once after VDD was
close phase alignment. initially applied.
If the latch is programmed for synchronous power-down (CE Counter Reset Method
pin high; PD1 bit high; PD2 bit low), the internal pulse also 1. Apply VDD.
triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse, 2. Do a function latch load (10 in 2 LSBs). As part of this,
so close phase alignment is maintained when counting resumes. load 1 to the F1 bit. This enables the counter reset.
When the first AB counter data is latched after initialization, the 3. Do an R counter load (00 in 2 LSBs). Do an AB counter
internal reset pulse is again activated. However, successive AB load (01 in 2 LSBs). Do a function latch load (10 in 2
counter loads after this will not trigger the internal reset pulse. LSBs). As part of this, load 0 to the F1 bit. This disables the
counter reset.
DEVICE PROGRAMMING AFTER INITIAL
POWER-UP This sequence provides the same close alignment as the initiali-
zation method. It offers direct control over the internal reset.
After initial power-up of the device, there are three ways to Note that counter reset holds the counters at load point and
program the device. three states the charge pump but does not trigger synchronous
Initialization Latch Method power-down. The counter reset method requires an extra
function latch load compared to the initialization latch method.
Apply VDD. Program the initialization latch (11 in 2 LSBs of
input word). Make sure the F1 bit is programmed to 0. Then, do
an R load (00 in 2 LSBs). Then do an AB load (01 in 2 LSBs).
RESYNCHRONIZING THE PRESCALER OUTPUT
Table 7 (the Reference Counter Latch Map) shows two bits, If the SYNC feature is used on the synthesizer, some care must
DB22 and DB21, which are labeled DLY and SYNC, be taken. At some point, (at certain temperatures and output
respectively. These bits affect the operation of the prescaler. frequencies), the delay through the prescaler coincides with the
active edge on RF input; this causes the SYNC feature to break
With SYNC = 1, the prescaler output is resynchronized with the down. It is important to be aware of this when using the SYNC
RF input. This has the effect of reducing jitter due to the feature. Adding a delay to the RF signal, by programming
prescaler and can lead to an overall improvement in synthesizer DLY = 1, extends the operating frequency and temperature
phase noise performance. Typically, a 1 dB to 2 dB somewhat. Using the SYNC feature also increases the value of
improvement is seen in the ADF4113. The lower bandwidth the AIDD for the device. With a 900 MHz output, the ADF4113
devices can show an even greater improvement. For example, AIDD increases by about 1.3 mA when SYNC is enabled and by
the ADF4110 phase noise is typically improved by 3 dB when an additional 0.3 mA if DLY is enabled.
SYNC is enabled.
All the typical performance plots in this data sheet, except for
With DLY = 1, the prescaler output is resynchronized with a Figure 8, apply for DLY and SYNC = 0, i.e., no resynchroniza-
delayed version of the RF input. tion or delay enabled.
APPLICATIONS
LOCAL OSCILLATOR FOR GSM BASE STATION TRANSMITTER
Figure 33 shows the ADF4111/ADF4112/ADF4113 being used All of these specifications are needed and used to come up with
with a VCO to produce the LO for a GSM base station the loop filter component values shown in Figure 33.
transmitter.
The loop filter output drives the VCO, which in turn is fed back
The reference input signal is applied to the circuit at FREFIN to the RF input of the PLL synthesizer. It also drives the RF out-
and, in this case, is terminated in 50 Ω. A typical GSM system put terminal. A T-circuit configuration provides 50 Ω matching
would have a 13 MHz TCXO driving the reference input with- between the VCO output, the RF output, and the RFIN terminal
out any 50 Ω termination. In order to have channel spacing of of the synthesizer.
200 kHz (GSM standard), the reference input must be divided
by 65, using the on-chip reference divider of the ADF4111/ In a PLL system, it is important to know when the system is in
ADF4112/ADF4113. lock. In Figure 33, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be pro-
The charge pump output of the ADF4111/ADF4112/ADF4113 grammed to monitor various internal signals in the synthesizer.
(Pin 2) drives the loop filter. In calculating the loop filter One of these is the LD or lock-detect signal.
component values, a number of items need to be considered. In
this example, the loop filter was designed so that the overall
phase margin for the system would be 45 degrees. Other PLL
system specifications are
KD = 5 mA
KV = 12 MHz/V
Loop Bandwidth = 20 kHz
FREF = 200 kHz
N = 4500
Extra Reference Spur Attenuation = 10 dB
VDD VP RFOUT
100pF
7 15 16 18Ω
B 100pF 18Ω
AVDD DVDD VP 3.3kΩ VCC P
1000pF 1000pF CP 2 C
FREFIN 8 REFIN
620pF 18Ω
51Ω1 1nF 5.6kΩ VCO190-902T
ADF4111
ADF4112
ADF4113
8.2nF
CE
MUXOUT 14 LOCK
CLK
DETECT
DATA
LE
SPI COMPATIBLE SERIAL BUS
100pF
RFINA 6
1 RSET 51Ω2
RFINB 5
CPGND
AGND
DGND
4.7kΩ
100pF
3 4 9
1TO BE USED WHEN GENERATOR SOURCE IMPEDANCE IS 50Ω.

2OPTIONAL MATCHING RESISTOR DEPENDING ON RF
OUT FREQUENCY.
03496-0-038
DECOUPLING CAPACITORS ON AVDD, DVDD, AND VP OF THE ADF411x

AND ON THE POSITIVE SUPPLY OF THE VCO190-902T HAVE BEEN
OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.
Figure 33. Local Oscillator for GSM Base Station
RFOUT
100pF
18Ω
VCO 100pF 18Ω
LOOP
CP 2
FREFIN 8 REFIN FILTER INPUT OUTPUT
18Ω
ADF4111 GND
ADF4112
ADF4113
CE
CLK
DATA LOCK
MUXOUT 14
LE DETECT
1 RSET
100pF
2.7kΩ RFINA 6
RFINB 5 51Ω
100pF
AD5320 POWER SUPPLY CONNECTIONS AND DECOUPLING

12-BIT CAPACITORS ARE OMITTED FOR CLARITY.
V-OUT DAC
03496-0-039
SPI COMPATIBLE SERIAL BUS
Figure 34. Driving the RSET Pin with a D/A Converter
USING A D/A CONVERTER TO DRIVE THE RSET PIN a tuning range as wide as an octave. For example, cable TV
tuners have a total range of about 400 MHz. Figure 36 shows an
A D/A converter can be used to drive the RSET pin of the application where the ADF4113 is used to control and program
ADF4110 family, thus increasing the level of control over the the Micronetics M3500-2235. The loop filter was designed for
charge pump current, ICP. This can be advantageous in wide- an RF output of 2900 MHz, a loop bandwidth of 40 kHz, a PFD
band applications where the sensitivity of the VCO varies over frequency of 1 MHz, ICP of 10 mA (2.5 mA synthesizer ICP
the tuning range. To compensate for this, the ICP may be varied multiplied by the gain factor of 4), VCO KD of 90 MHz/V
to maintain good phase margin and ensure loop stability. See (sensitivity of the M3500-2235 at an output of 2900 MHz), and
Figure 34. a phase margin of 45°C.
SHUTDOWN CIRCUIT In narrow-band applications, there is generally a small variation
The attached circuit in Figure 35 shows how to shut down both in output frequency (generally less than 10%) and a small
the ADF4110 family and the accompanying VCO. The ADG701 variation in VCO sensitivity over the range (typically 10% to
switch goes closed circuit when a Logic 1 is applied to the IN 15%). However, in wideband applications, both of these
input. The low cost switch is available in both SOT-23 and parameters have a much greater variation. In Figure 36, for
MSOP packages. example, there is a −25% and +17% variation in the RF output
from the nominal 2.9 GHz. The sensitivity of the VCO can vary
WIDEBAND PLL from 120 MHz/V at 2750 MHz to 75 MHz/V at 3400 MHz
Many of the wireless applications for synthesizers and VCOs in (+33%, −17%). Variations in these parameters change the loop
PLLs are narrow band in nature. These applications include the bandwidth. This in turn can affect stability and lock time. By
various wireless standards like GSM, DSC1800, CDMA, and changing the programmable ICP, it is possible to get compensa-
WCDMA. In each of these cases, the total tuning range for the tion for these varying loop conditions and ensure that the loop
local oscillator is less than 100 MHz. However, there are also is always operating close to optimal conditions.
wideband applications for which the local oscillator could have
VP
POWER-DOWN CONTROL VDD

S
ADG701 RFOUT
VDD IN
D GND 100pF
7 15 16 10 18Ω
VCC 100pF 18Ω
AVDD DVDD VP CE
LOOP
FREFIN 8 CP 2 FILTER
VCO 18Ω
REFIN
RSET 1
GND
4.7kΩ
ADF4110
ADF4111
ADF4112
ADF4113
100pF
RFINA 6
51Ω
CP GND
RFINB 5
DGND
AGND
3 4 9
100pF
03496-0-040
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE
BEEN OMITTED FROM THE DIAGRAM TO INCREASE CLARITY.
Figure 35. Local Oscillator Shutdown Circuit
20V RFOUT
12V
VDD VP
3kΩ 100pF
1kΩ
VCC 18Ω
100pF 18Ω
7 15 16 OUT
AD820 V_TUNE
AVDD DVDD VP 3.3kΩ
2 18Ω
1000pF 1000pF
CP M3500-2235
FREFIN 8 REFIN
2.8nF 19nF 130pF GND
51Ω RSET 1
4.7kΩ 680Ω
ADF4113
CE
CLK MUXOUT 14 LOCK
DATA DETECT
LE
SPI-COMPATIBLE SERIAL BUS
100pF
RFINA 6
RFINB 5 51Ω
CPGND
DGND
AGND
3 4 9 100pF
03496-0-041
DECOUPLING CAPACITORS ON AVDD, DVDD, VP OF THE ADF4113

AND ON VCC OF THE M3500-2250 HAVE BEEN OMITTED FROM
THE DIAGRAM TO AID CLARITY.
Figure 36. Wideband Phase-Locked Loop
DIRECT CONVERSION MODULATOR
In some applications, a direct conversion architecture can be Typical phase noise performance from this LO is −85 dBc/Hz at
used in base station transmitters. Figure 37 shows the combina- a 1 kHz offset.
tion available from ADI to implement this solution. The LO port of the AD8346 is driven in single-ended fashion.
The circuit diagram shows the AD9761 being used with the LOIN is ac-coupled to ground with the 100 pF capacitor; LOIP
AD8346. The use of dual integrated DACs such as the AD9761 is driven through the ac coupling capacitor from a 50 Ω source.
with specified ±0.02 dB and ±0.004 dB gain and offset matching An LO drive level of between −6 dBm and −12 dBm is required.
characteristics ensures minimum error contribution (over The circuit of Figure 37 gives a typical level of −8 dBm.
temperature) from this portion of the signal chain. The RF output is designed to drive a 50 Ω load but must be ac-
The local oscillator (LO) is implemented using the ADF4113. In coupled as shown in Figure 37. If the I and Q inputs are driven
this case, the OSC 3B1-13M0 provides the stable 13 MHz in quadrature by 2 V p-p signals, the resulting output power is
reference frequency. The system is designed for a 200 kHz around −10 dBm.
channel spacing and an output center frequency of 1960 MHz.
The target application is a WCDMA base station transmitter.
REFIO IOUTA IBBP 100pF

LOW-PASS
FILTER VOUT RFOUT
IOUTB IBBN
MODULATED AD9761
DIGITAL AD8346
DATA
TxDAC
QOUTA QBBP
LOW-PASS
FS ADJ FILTER
QOUTB QBBN
2kΩ LOIN LOIP
4.7kΩ 100pF 100pF
OSC 3B1-13M0
18Ω
RSET 3.3kΩ 100pF 18Ω
TCXO REFIN CP
910pF 3.9kΩ VCO190-1960T

ADF4113 620pF
SERIAL
DIGITAL 9.1nF
INTERFACE
RFINB RFINA 18Ω
100pF 100pF
51Ω
03496-0-042
POWER SUPPLY CONNECTIONS AND DECOUPLING CAPACITORS

ARE OMITTED FROM DIAGRAM TO INCREASE CLARITY.
Figure 37. Direct Conversion Transmitter Solution
INTERFACING
The ADF4110 family has a simple SPI® compatible serial inter- ADSP-2181 Interface
face for writing to the device. SCLK, SDATA, and LE control the Figure 39 shows the interface between the ADF4110 family and
data transfer. When latch enable (LE) goes high, the 24 bits that the ADSP-21xx digital signal processor. The ADF4110 family
have been clocked into the input register on each rising edge of needs a 24-bit serial word for each latch write. The easiest way
SCLK get transferred to the appropriate latch. See Figure 2 for to accomplish this using the ADSP-21xx family is to use the
the timing diagram and Table 5 for the latch truth table. auto buffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
The maximum allowable serial clock rate is 20 MHz. This
of serial data before an interrupt is generated.
means that the maximum update rate possible for the device is
833 kHz, or one update every 1.2 µs. This is certainly more than
SCLK SCLK
adequate for systems that have typical lock times in the
hundreds of microseconds. ADSP-21xx
DT SDATA
ADF4110
ADF4111
ADuC812 Interface TFS LE
ADF4112
ADF4113
Figure 38 shows the interface between the ADF4110 family and I/O FLAGS
CE
the ADuC812 MicroConverter®. Since the ADuC812 is based
03496-0-044
MUXOUT
(LOCK DETECT)
on an 8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master Figure 39. ADSP-21xx to ADF4110 Family Interface
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4110 family
Set up the word length for 8 bits and use three memory
needs a 24-bit word. This is accomplished by writing three 8-bit
locations for each 24-bit word. To program each 24-bit latch,
bytes from the MicroConverter to the device. When the third
store the three 8-bit bytes, enable the auto buffered mode, and
byte has been written, the LE input should be brought high to
then write to the transmit register of the DSP. This last opera-
complete the transfer.
tion initiates the autobuffer transfer.
When power is first applied to the ADF4110 family, three writes
are needed (one each to the R counter latch, N counter latch, PCB DESIGN GUIDELINES FOR CHIP SCALE
and initialization latch) for the output to become active. PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
I/O port lines on the ADuC812 are also used to control power- The printed circuit board pad for these should be 0.1 mm
down (CE input), and to detect lock (MUXOUT configured as longer than the package land length and 0.05 mm wider than
lock detect and polled by the port input). the package land width. The land should be centered on the
When the ADuC812 is operating in the mode described above, pad. This ensures that the solder joint size is maximized.
the maximum SCLOCK rate of the ADuC812 is 4 MHz. This The bottom of the chip scale package has a central thermal pad.
means that the maximum rate at which the output frequency The thermal pad on the printed circuit board should be at least
can be changed is 166 kHz. as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This ensures that
SCLOCK SCLK
shorting is avoided.
MOSI SDATA
ADuC812
ADF4110 Thermal vias may be used on the printed circuit board thermal
LE ADF4111
I/O PORTS ADF4112 pad to improve thermal performance of the package. If vias are
CE ADF4113 used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
03496-0-043
MUXOUT
(LOCK DETECT)
0.33 mm, and the via barrel should be plated with 1 oz. copper
Figure 38. ADuC812 to ADF4110 Family Interface to plug the via.
The user should connect the printed circuit board thermal pad
to AGND.
OUTLINE DIMENSIONS
4.10 0.30
4.00 SQ 0.25
PIN 1 3.90 0.18
INDICATOR PIN 1
16 20 INDICATOR
0.50
15 1
BSC
EXPOSED 2.30
PAD
2.10 SQ
2.00
11 5
10 6
0.65 0.20 MIN
TOP VIEW 0.60 BOTTOM VIEW
0.55
0.80 FOR PROPER CONNECTION OF
0.75 THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70 FUNCTION DESCRIPTIONS
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
SEATING 0.08
PLANE 0.20 REF
08-16-2010-B
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
Figure 40. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
5.10
5.00
4.90
16 9
4.50
6.40
4.40 BSC
4.30
1 8
PIN 1
1.20
MAX
0.15 0.20
0.05 0.09 0.75
0.30 8° 0.60
0.65 0.19 0° 0.45
SEATING
BSC PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 41. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option 2
ADF4110BCPZ –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADF4110BCPZ-RL –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADF4110BCPZ-RL7 –40°C to +85°C 20-Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
ADF4110BRU –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4110BRU-REEL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4110BRU-REEL7 -40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4110BRUZ –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4110BRUZ-RL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4110BRUZ-RL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4111BRUZ-RL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4111BRUZ-RL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4112BRU-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4112BRUZ-REEL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4112BRUZ-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4113BRU-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4113BRUZ-REEL –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4113BRUZ-REEL7 –40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4113BCHIPS –40°C to +85°C DIE
EVAL-ADF4113EBZ1 Evaluation Board
EVAL-ADF4113EBZ2 Evaluation Board
EV-ADF411XSD1Z Evaluation Board
1
Z = RoHS Compliant Part.
2
CP-20-6 package was formerly CP-20-1 package.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D03496-0-1/13(F)
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ADF4110BRUZ ADF4111BCPZ ADF4111BRUZ ADF4112BRUZ ADF4113BRUZ
EV-ADF411XSD1Z
EN DE FR
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the manufacturer Hersteller bereitgestellt présentée par le fabricant
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Figure 1. Functional Block Diagram

Rev. F Document Feedback

Applications ....................................................................................... 1 Muxout and Lock Detect ........................................................... 13

General Description ......................................................................... 1 Input Shift Register .................................................................... 13

Functional Block Diagram .............................................................. 1 Function Latch ............................................................................ 19

Revision History ............................................................................... 2 Initialization Latch ..................................................................... 20

Specifications..................................................................................... 3 Device Programming after Initial Power-Up ......................... 20

Timing Characteristics ..................................................................... 5 Resynchronizing the Prescaler Output .................................... 21

Absolute Maximum Ratings ............................................................ 6 Applications..................................................................................... 22

Pin Configurations and Function Descriptions ........................... 7 Shutdown Circuit ....................................................................... 23

Typical Performance Characteristics ............................................. 8 Wideband PLL ............................................................................ 23

Circuit Description ......................................................................... 12 Direct Conversion Modulator .................................................. 25

Reference Input Section ............................................................. 12 Interfacing ................................................................................... 26

Prescaler (P/P + 1) ...................................................................... 12 Outline Dimensions ....................................................................... 27

A and B Counters ....................................................................... 12 Ordering Guide ............................................................................... 28

8/12—Rev. D to Rev. E 1/01—Data sheet changed from Rev. 0 to Rev. A.

DB1 DB0 (LSB)

Figure 2. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. TSSOP Pin Configuration Figure 4. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

TYPICAL PERFORMANCE CHARACTERISTICS

OUTPUT POWER (dB)

–10 RMS NOISE = 0.52°

Figure 6. Input Sensitivity (ADF4113) Figure 9. ADF4113 Integrated Phase Noise

–2.0kHz –1.0kHz 900MHz 1.0kHz 2.0kHz

–10 REFERENCE VDD = 3V, VP = 5V –50

PHASE NOISE (dBc/Hz)

–30 –70 RL = –40dBc/Hz

–80 –90.2dBc/Hz –120

–400kHz –200kHz 900MHz 200kHz 400kHz –100

–10 REFERENCE VDD = 3V, VP = 5V REFERENCE VDD = 3V, VP = 5V

–30 RES. BANDWIDTH = 10Hz

–80 –75.2dBc/Hz –80

PHASE NOISE (dBc/Hz)

FREQUENCY OFFSET FROM 3100MHz CARRIER (Hz) TEMPERATURE (°C)

–10 REFERENCE VDD = 3V, VP = 5V

–2.0MHz –1.0MHz 3100MHz 1.0MHz 2.0MHz –40 –20 0 20 40 60 80 100

FREQUENCY TEMPERATURE (°C)

1 10 100 1000 10000 0 1 2 3 4 5

TEMPERATURE (°C) PRESCALER OUTPUT FREQUENCY (MHz)

0 8/9 16/17 32/33 64/65

Figure 25. AIDD vs. Prescaler Value

RF INPUT STAGE fVCO = output frequency of external voltage controlled oscillator

frequency detector (PFD). Division ratios from 1 to 16,383 are

manageable frequency for the CMOS A and B counters. The

PROGRAMMABLE U3 CP ANALOG LOCK DETECT

N DIVIDER Figure 32. MUXOUT Circuit

INPUT SHIFT REGISTER

REFERENCE COUNTER LATCH

X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)

PRESCALER SETTING SETTING TIMER COUNTER MUXOUT CONTROL

R14 R13 R12 •••••••••• R3 R2 R1 DIVIDE RATIO

ABP2 ABP1 ANTIBACKLASH PULSE WIDTH