Saint Louis University School of Engineering and Architecture Department of Electrical Engineering

Saint Louis University
School of Engineering and Architecture

Department of Electrical Engineering
8255 Microprocessor
Gole Cruz, Naomi Aira D
Date Submitted: May 4, 2020

Input and output devices, which are interfaced with 8085, are essential in any
microprocessor-based-system. They can be interfaced using two schemes- I/O mapped
I/O and memory mapped I/O. Both of these schemes has been designed by complex
hardware circuit and also it is dedicated for only one type of device, such as Buffer
based designed is accomplished only for I/P devices and Latch based designed is
accomplished only for O/P devices; both of these design could not be used for reverse
action. To reduce this complex hardware circuit and versatility Intel Corporation has
introduce 8255 chip, which is commonly called Programmable Peripheral Interface
[PPI]. The 8255 has 24 I/O pins divided into 3 groups of 8 pins each. The groups are
denoted by port A, port B and port C respectively. Every one of the ports can be
configured as either an input port or an output port.
Block diagram and Pin diagram of 8255:
Form the above block diagram it is noticed that any kind of I/O devices could be
connected with three ports like Port A, Port B, Port C. due to this features buffer and
latch devices are not needed for particular input or output application so, user has
flexibility to use same ports as input or output application. Another advantage of this
chip, that it can be operated in three different modes which are basically not included in
simple I/O interfacing; these different types of operation extended the data transfer
policies.
Functions of each block and pins:
Data Bus Buffer- The tri-state bidirectional 8 bit buffer is used to interface the
8255A to the microprocessor data bus (D0-D7). Data is transmitted or received by
buffer upon the execution of input or output instructions by the CPU. Control word and
status word also transferred through this data bus buffer.
Read write control logic- The function of this block is to manage all the internal and
external transfers of both data and control or status word. This block also handles user
information regarding operational mode selection, configuration of ports as an input or
output; all of this information stored in 8-bit control word register (CWR). The details of
each pin connected with this block are described below,
̅̅̅̅
𝐶𝑆(Chip Select)- A “Low” on this input pin enables the communication between the 8085
and MPU.
A0 and A1 - These are the address lines of 8255 which are directly connected to the
MPU lower address lines (A0, A1). In conjunction with chip select, control the selection
of one of the three ports or the control word register has been made. The bit
combination of these signals are shown below-
̅̅̅̅ 𝑎𝑛𝑑 𝑊𝑅
𝑅𝐷 ̅̅̅̅̅ - A “LOW” on this pin enable 8255 to send data or status information to MPU
via data bus (i.e. read operation) or enable MPU to write data and control word register
value to 8255 via data bus (i.e. write operation).
RESET -A “HIGH” on this pin clears the control word register and all ports (A,B,C) are
set to input mode.
Group A and Group B control

The functional configuration of each port is programmed by the system software.
The MPU “outputs” a control word to the 8255 to set some information such as mode,
bit-set/reset, etc. that initialize the functional configuration of 8255. Each of control
blocks (Group A and Group B) accept commands from read/write control logic, receives
“control words” from the internal data bus and issue the proper commands to its
associate ports.
Group A control- port A and Port C upper (PC4 – PC7)
Group B control – Port B and Port C lower (PC0 – PC3)
The control word register can be used for write operation and NO read operation is
allowed in this register.
Ports A, B and C
The 8255A contains three 8-bit ports (A, B and C). All can be configured in a
wide variety of functional characteristics by the system software but each has its own
special features to enhance the power and flexibility of the 8255A. The major function of
each ports has 8-bit Input or Output, buffer or latch and only Port C can be configured
as double 4-bit latch, it is used for control signal output and status signal inputs in
conjunction with ports A and B.
8255A Operational Description:

There are three basic I/O modes of operation that can be selected by the system
software after properly sets the control word register format as per the requirements.
Mode 0 – Basic Input/ Output

Mode 1 – Strobe or Handshaking Input/ Output
Mode 2 – Bi-directional Bus
In Mode 0 all ports (A, B and C) can be used as 8-bit I/O ports and configured by
the control word registers. When the RESET input goes “high” all ports will be set to
input mode and after revoked of this signal all ports remain in same mode until any
initialization established. In Mode 1 only Port A and B configured as I/O while the upper
4-bit of port C used as strobe signal for port A and lower 4-bit of port C used as strobe
signal for port B. Mode 2 is available only for port A while port B can be used as simple
I/O mode and bit’s of port C used as strobe signal. Except of these three modes of
operation 8255A offers single Bit Set/ Reset (BSR) features of port bits, which is limited
to port C only. All of these operations are maintained by a 8-bit single register called
Control Word Register (CWR). Before using this PPI chip user must be initialize all of
these 8 bit ports as input or output with proper modes of operation according to the
circuitry where it will be placed. This initialization can be done by CWR register. The
format of CWR is shown below
Mode 1 – Strobed or Handshaking Input/ Output
In Mode-0, 8255A used as a receiver & transmitter to exchange the data in
between of microprocessor & input/output devices. But in this scheme exchange data
may be lost by the both of devices due to unknown timing of data throwing in between
them so, both of the devices should be fully devoted in this throughout process to
successfully exchanging the data. This scenario may cause slow performance on
device other task execution speed except data exchanging task, it is very effective issue
for microprocessor rather than I/O devices task execution policies; where various task
are executed serially. To resolve this problem & minimize the data lost rate 8255A made
a strobe or handshaking data exchanging facilities into it.
This mode has some advantage over mode-0 respect to the task execution
priorities of microprocessor as follows:
1. During exchanging the data with slow devices, μp can perform another task
without scanning the port in a timely manner.
2. Data overwrites (during read or write operation) in a port can be resolved by a
special status signal.
Port configuration in Mode-1
• Three ports divided into two groups (Group A•& Group B); where portC split into
two parts for the following groups.
• Each group contains one 8-bit data port & one 4-bit control port
• 8-bit data port can be used as input or output. Both of the cases data are
latched.
• The 4-bit port is used for control or status of the 8-bit port.
• After selection of two groups port bits, remaining bits of portC may used as a
simple input or output.
Input control signal definition:
𝑺 𝑻 𝑩 (Strobe Input) : a “Low” on this input denotes that an input device loads data
into the input latch (portA or portB) & after completing its task this signal remain in
“High”.
IBF (Input Buffer Full) : it is an output of a flip flop (“High”) indicated to the input
devices that input latch is now full & no data cannot be received yet until μp reads
the data from latch. It will reset after read the data by CPU & thereafter input devices
can send data again.
INTR (Interrupt Request) : it is an output signal (“High”) used for interrupt the CPU to
read the received data from input latch. This signal occurred when 𝑺 𝑻 , IBF & INTE
are all in logic “High”. After getting this signal CPU finishes its current execution &
generates a 𝑅 𝐷 signal to read the corresponding data & it is reset by falling edge of
𝑅 𝐷.
NTEA & INTEB is controlled by bit set/reset of PC4 & PC2 respectively
Output control signal definition:

𝑶 𝑩 𝑭 (Output Buffer Full) : a “Low’ output of a flip flop indicates to the output
devices that output latch (portA or portB) is now filled by data & no new data cannot
be write yet by μp until output devices reads the data from latch. It will set after read
the data by output devices, when it makes an acknowledgement signal.
𝑨 𝑪 𝑲 (Acknowledge Input) : a “Low” on this input pin denotes that an output device
read the data from the output latch & after completing its read operation this signal
remain in “High”.
INTR (Interrupt Request) : it is a active “High” output signal used for interrupt the
CPU to write the new data into the latch. This signal occurred when OBF , ACK &
INTE are all in logic “High”. After getting this signal CPU finishes its current
execution & generates a 𝑊 𝑅 signal to write a new data & it is reset by falling edge
of 𝑊 .
INTEA & INTEB is controlled by bit set/reset of PC6 & PC2 respectively
Mode 2 – Strobed Bidirectional Input/ Output Bus

PortA & PortB individually defined as an input or output port with their
handshaking signal in mode-1 to support wide variety of I/O applications. But mode-
2 configuration provides a single 8-bit bus for transmitting or receiving (is called
bidirectional) data with handshaking signal to maintain the proper flow discipline in a
similar manner of mode-1. Interrupt generation and enable/disable functions are also
available in this mode.
Port configuration in Mode-2
• Only portA is used as a 8-bit bi-directional I/O bus
• Handshaking signal for communication is provided by 5-bits of portC [PC3 to
PC7].
• PC0 to PC2 is used as a simple input or output, is set by mode-0 operation
• PortB can be programmed either in mode-0 or mode-1 configuration with
PC0-PC2 used as a handshaking signal where it is applicable.
Input control signal definition:

𝑺 𝑻 𝑩 (Strobe Input) : This active LOW input signal is used to enable portA latch to
loads data into it & after completing its task this signal remain in “High”.
IBF (Input Buffer Full) : it is an output of a flip flop (“High”) indicated to the peripheral
devices that input latch is now full & no data cannot be received yet until μp reads the
data from latch. It will reset after read the data by 8085 & thereafter input devices can
send data again.
INTE1 : it is an interrupt enable flip-flop and controlled by set/reset of PC6
Output control signal definition:
𝑶 𝑩 𝑭 (Output Buffer Full) : active “Low’ output signal indicates to the peripheral devices
that output latch (portA) is now filled by data & no new data cannot be write yet by μp
until peripheral devices reads the data from latch. It will set after read the data by output
devices, when it makes an acknowledgement signal.
𝑨 𝑪 𝑲 (Acknowledge Input) : a “Low” on this input pin denotes that peripheral device
read the data from the output latch & after completing its read operation this signal
remain in “High”.
INTE2 : it is an interrupt enable flip-flop and controlled by set/reset of PC4
INTR (Interrupt Request) : it is a active “High” output signal used for interrupt the CPU
to write the new data into the latch or read the received data from the latch. Write
operation initiate when OBF , ACK & INTE are all in logic “High” and read operation
initiate when 𝑺 𝑻 𝑩 , IBF & INTE are all in logic “High”. After getting this signal CPU
finishes its current execution & generates a 𝑊 𝑅 signal to write a new data or 𝑅 𝐷 signal
to read the received data. This signal goes low after the falling edge of 𝑅 𝐷 or 𝑊 𝑅
signal.
8255A single Bit set/reset (BSR) features:

Rather than the I/O modes of operation 8255A has special bit controlling
features. In this mode of operation, any of the 8-bits of portC can be set or reset using a
single OUT instruction. This feature reduces software requirements in ON/OFF control
applications.
This mode is enabled by resetting the D7 bit of control word register (CWR) &
after choosing this bit the format of CWR is completely changed from I/O mode
structure. The format of CWR in BSR mode is shown below –
Any of the 8-bit of portC is selected by the combination of group of bits (D3, D2,
D1) as shown in fig.11 and selected portC bit is control by D0 bit of CWR to ensure set
or reset operation of the following bit.
A comparative ALP programming is depicts the simplicity of BSR modes respect
to the I/O modes of operation. Major confusing part of these two modes of operation is
accessing the address of CWR and portC which is clearly mentioned in above two
comparative statements by following “bold” text line.
Reference: http://sdprofile.weebly.com/uploads/2/8/0/1/28011053/ppi_chip-_8255.pdf

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Saint Louis University School of Engineering and Architecture Department of Electrical Engineering

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Saint Louis University

School of Engineering and Architecture

Gole Cruz, Naomi Aira D

Date Submitted: May 4, 2020

Block diagram and Pin diagram of 8255:

Group A and Group B control

8255A Operational Description:

Mode 0 – Basic Input/ Output

Port configuration in Mode-1

Output control signal definition:

Mode 2 – Strobed Bidirectional Input/ Output Bus

Input control signal definition:

8255A single Bit set/reset (BSR) features:

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