IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO.

1, JANUARY 2010 101

Constructing Online Testable Circuits

Using Reversible Logic
Sk. Noor Mahammad and Kamakoti Veezhinathan

Abstract—With the advent of nanometer technology, circuits packing of billions of transistors on very small die areas.
are more prone to transient faults that can occur during its With increasing device densities, the operating voltages and
operation. Of the different types of transient faults reported in the dimensions of the devices continue to shrink. Currently, the
literature, the single-event upset (SEU) is prominent. Traditional
techniques such as triple-modular redundancy (TMR) consume manufactured devices employ nanometer technology. These
large area and power. Reversible logic has been gaining interest devices operate by storing very less electric charges when
in the recent past due to its less heat dissipation characteristics. compared with the previous technologies. This has resulted in
This paper proposes the following: 1) a novel universal reversible these devices being highly susceptible to being affected by the
logic gate (URG) and a set of basic sequential elements that could striking of higher charged particles in the external environments
be used for building reversible sequential circuits, with 25% less
garbage than the best reported in the literature; (2) a reversible in which they are operating. The striking of externally charged
gate that can mimic the functionality of a lookup table (LUT) particles normally causes a glitch in the combinational part of
that can be used to construct a reversible field-programmable the circuit. This glitch, when it occurs closer to a clock edge,
gate array (FPGA); and (3) automatic conversion of any given may propagate and get stored in a flip-flop, thereby changing
reversible circuit into an online testable circuit that can detect the state of the circuit. This causes an error, which is called the
online any single-bit errors, including soft errors in the logic
blocks, using theoretically proved minimum garbage, which is soft error. The soft error does not damage the circuit and can
significantly lesser than the best reported in the literature. be corrected by resetting the state of the circuit. Unlike manu-
facturing defects, the soft errors cannot be detected using con-
Index Terms—Flip-flop, garbage, low power dissipation, online
testing and digital circuits, reversible logic and gates. ventional design-for-testability (DFT) techniques [1], although
there are techniques reported in the literature, for example, the
I. I NTRODUCTION built-in soft-error resilience design paradigm [2], that reuses
the existing on-chip DFT resources to reduce the soft-error

S PACE and mobile applications demand performance, low

power dissipation, and fault tolerance. The major limitation
in this type of applications is that the hardware executing the
rate. Putting all these together, in the next nanometer era, there
is certainly a need for a methodology to design power-aware
systems that can detect online errors, including soft errors.
same has to survive on battery/solar power. Hence, these sys- From the point of view of power dissipation, researchers
tems are to be extremely power aware. Traditional fault-tolerant have looked into technologies based on carbon nanotubes [3],
systems that use techniques such as triple-modular redundancy microelectromechanical system switches [4], and reversible
(TMR) consume more logic and, hence, dissipate larger power
logic [5]. Reversible logic offers a lot of promises in terms
than nonfault-tolerant versions of the same. As a result, the
of practical realization [6]. As a justification to the fore-
overall power dissipation of the chip significantly increases.
going statement, the Reversible Computing Research Group,
This, in turn, makes the system power hungry and, hence, not
Massachusetts Institute of Technology, has developed a proof-
suitable for portable applications. Another major application
of-concept reconfigurable reversible chip, which is called the
of hardware that is well reported in the literature is in the
FlatTop [7].
real-time/online safety critical system domain. For example,
This paper presents techniques for the construction of re-
the safety logic systems for nuclear reactors are essentially
versible circuits that realize the functionality of any given
hardware based and are greatly exposed to charged particles.
arbitrary digital circuit, including a two-input lookup table
Specifications of such systems demand online detection of
(LUT), and automatically converting the aforementioned re-
faults to ensure correct and safe execution.
versible circuits into online testable circuits. In essence, this
On the other hand, the semiconductor device density on
paper collectively addresses the problems of low power design
chips continues to follow the Moore’s law and currently enables
and online error detection. The rest of this paper is organized
as follows: Section II presents the related literature survey.
Manuscript received May 4, 2008; revised November 20, 2008. First pub-
lished August 18, 2009; current version published December 9, 2009. This Section III proposes efficient building blocks for the construc-
work was supported by the Reconfigurable and Intelligent Systems Engineering tion of reversible circuits. Section IV details the automatic
(RISE) Laboratory. The Associate Editor coordinating the review process was conversion of a reversible circuit into an online testable circuit.
Dr. S. Demidenko.
Sk. N. Mahammad is with the RISE Laboratory, Department of Computer Section V illustrates the proposed methodology by constructing
Science and Engineering, Indian Institute of Technology (IIT) Madras, Chennai an online testable reversible decoder circuit. This section also
600 036, India (e-mail: veezhi@gmail.com). presents SPICE-based simulation results to demonstrate the
K. Veezhinathan is with the Department of Computer Science and Engineer-
ing, IIT Madras, Chennai 600 036, India (e-mail: kama@cse.iitm.ac.in). practical feasibility and the efficiency of the proposed approach.
Digital Object Identifier 10.1109/TIM.2009.2022103 Section VI concludes this paper.

0018-9456/$26.00 © 2009 IEEE

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102 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 1, JANUARY 2010

been proposed until now, which include charge-recovery logic

(CRL) [16], split-level CRL [17], reversible energy recovery
logic (RERL) [18], [19], and NMOS RERL (nRERL) [20]. In
addition, optoelectronic and nanometer-based implementations
of reversible circuits are presented in [21] and [22]. However,
there has been relatively little progress in the synthesis of digital
designs into reversible circuits. The construction of reversible
sequential logic elements is dealt with in [23]. One of the major
issues in designing a reversible circuit is garbage minimization.
Garbage is defined as the number of outputs added to make an
n-input k-output Boolean function [(n, k) function] reversible
[24]. Realizing programmable logic using reversible gates is
an interesting area of research. Reversible programmable logic
arrays are proposed in [25].
Fig. 1. Reversible gates. (a) Feynman. (b) Toffoli. (c) Fredkin.
Very little previous research has been done on testable re-
versible circuits. Conditions for a complete test set construction
II. L ITERATURE S URVEY
were discussed, and the problem of finding a minimum test
An operation p is said to be adiabatic or physically reversible set was formulated as an integer linear program with binary
if there is neither energy to heat conversion nor change in en- variables in [26]. A new fault model, which is called the
tropy due to p. In reversible logic, the state of the computational missing gate fault model, was proposed to represent physical
device just prior to an operation is uniquely determined by its failure modes of quantum technologies [27]. An online testing
state just after the operation. In other words, no information technique for reversible logic circuits was proposed in [28]. The
about the computational state is lost. Thus, the systems realized technique involved two testable reversible logic gates R1 and
using reversible logic can be viewed as deterministic state R2, which can be used to implement various reversible digital
machines. Landauer [8] showed that, for every bit of infor- circuits. Another online testing technique for reversible logic
mation that is erased during an irreversible logic computation, circuits was given in [29] and [30]. This technique proposed
kT ln 2 joules of heat energy are generated, where k is the three reversible logic gates (R1, R2, R3). The gates R1 and
Boltzmann’s constant, and T is the temperature (in kelvins) at R2 proposed in [28]–[30] are the same. A combination of these
which the system operates. Bennett [9] showed that the kT ln 2 R1 and R2 gates was used to construct testable logic blocks.
amount of energy dissipation would not occur if a computation The R3 gate was used to construct a two-pair rail checker for
is carried out in a reversible way. Thus, a reversible operation detecting errors in any pair of blocks in the circuit.
ensures low energy dissipation [5], [10]. In the nanometer The contributions of this paper are given as follows:
era of semiconductors, the size of a basic device is rapidly 1) a novel universal reversible logic gate (URG) that can
approaching the elementary particle level. At this level, matter realize on the same outputs the following three pairs of
is governed by principles of classical and quantum mechanics. two argument operators for different values of controlling
This, in turn, states that the operations carried out by the devices signals: a) OR and AND; b) NOR and NAND; c) EXOR gate;
at the particle level are reversible [11], indicating that the future and d) fan-out gate;
computers that are to be realized using such reversible devices 2) a set of basic sequential elements that could be used
can be adiabatic/reversible [8], [10]. Hence, reversible logic is for building reversible sequential circuits, with 25% less
gaining grounds. garbage than those proposed in [23];
A reversible gate by definition is an n × n logical cell that 3) a reversible gate that can mimic the functionality of
has the same number n of inputs and outputs, with a one-to-one a LUT;
mapping between the input and output vectors. Direct fan-outs 4) automatic conversion of any given reversible circuit into
from the outputs of reversible gates or connecting an output an online testable circuit that has theoretically proved
of gate G directly to any input of G are not permitted while minimum garbage and that can detect any single-bit
constructing circuits with reversible gates [11]. errors, including soft errors in the logic blocks. The
A detailed elaborate list of reversible gates reported in the latest methodology reported in [30] consumes more
literature is presented in [12]. Some prominent among them garbage than the proposed technique and assumes that
are the Feynman gate [13] [Fig. 1(a)], the Toffoli gate [14] the complete circuit is realized in terms of a particular
[Fig. 1(b)], the Fredkin gate [11] [Fig. 1(c)], the Kerntopf gate gate R1.
[12], and the Margolus gate [15]. An n × n reversible gate
can uniquely be represented by the permutation of 2n integers,
as defined by its input–output bijection, along with the order III. B UILDING B LOCKS FOR R EVERSIBLE
of the inputs and outputs. For example, Fig. 1(d) shows the C IRCUITS AND R EVERSIBLE LUTs
input–output bijection of the Feynman gate shown in Fig. 1(a).
A. Reversible Gates
It is straightforward to see that the Feynman gate can uniquely
be represented by the tuple (((a, b) → (o1 , o2 )), (0, 1, 3, 2)). Fig. 2 illustrates the proposed URG represented by
Many techniques for implementing the reversible circuits have the tuple (((a, b, c) → (o1 , o2 , o3 )), (0, 5, 6, 3, 4, 1, 7, 2)). It is

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MAHAMMAD AND VEEZHINATHAN: CONSTRUCTING ONLINE TESTABLE CIRCUITS USING REVERSIBLE LOGIC 103

C. Reversible LUTs
A k-input LUT is a programmable logic element that can
k
be configured to realize any one of the 22 distinct k-input
Boolean functions. Typically, these are realized using 2k × 1
memory, which can store the truth table of any of the k-input
Boolean function. The 16 distinct two-input Boolean functions
Fig. 2. URG.
can uniquely be represented by the integers 0–15. For example,
the AND function f (p, q) = p&q, whose truth table is (0, 0,
0, 1), can be represented by the integer 1. Of the 16 distinct
two-input functions, the two constant functions (0, 0, 0, 0)
and (1, 1, 1, 1), which are represented by the integers 0 and
15, respectively, do not need a logic element for realization.
This section proposes a reversible gate LU T G represented
by the tuple (((a, b, c) → (O2 , O1 , O0 )), (1, 5, 3, 0, 4, 2, 7, 6)).
Fig. 3. Reversible positive-level-triggered T flip-flop. The mapping is shown in Fig. 6(a). It is interesting to note that
LU T G can be used to realize all the 14 nonconstant and distinct
two-input Boolean functions. Fig. 6(b) illustrates the procedure
to use LU T G for realizing the 14 distinct two-input Boolean
functions. For example, it is seen from the third row of Fig. 6(b)
that, by setting the inputs (a, b, c) of LU T G to (p, 0, q), the
AND function p&q represented by the integer 1 can be realized

Fig. 4. Reversible positive-edge-triggered D flip-flop.

on output O1 . Similarly, the other 13 nonconstant two-input
Boolean functions can be realized using LU T G, as described
in Fig. 6(b). It is straightforward to verify the correctness of
straightforward to see in Fig. 2 that:
Fig. 6(b) using the mapping shown in Fig. 6(a).
1) by setting input c to 0(1), the OR and AND (NOR and It is interesting to note that there are 408 such different
NAND ) of inputs a and b are realized in o1 and o3 , permutations, including the above, each representing a differ-
respectively; ent reversible gate, that can realize the same functionality of
2) by setting b to 1, the XOR of a and c is realized; LU T G, as described in the previous paragraph. The major
3) by setting a and b to ’0’ a two-fan-out circuit of c is advantage offered by these reversible gates is the memoryless
realized in o1 and o3 , respectively. realization of an LUT.
To the best of our knowledge, this is the first multifunctional
reversible gate reported in the literature that realizes all the
four basic functions, namely, AND, OR, NAND , and NOR. A IV. T ESTING R EVERSIBLE C IRCUITS
similar attempt is reported in [12], which does not realize the This section proposes a technique for automatically convert-
minimal functionally complete functions [31], namely, NAND ing any given reversible circuit into an online testable circuit.
and NOR. Unlike the technique proposed in [30], the proposed conver-
sion mechanism is independent of the type of the reversible
gates used. Every testable logic block in [30] comprises two
B. Reversible Sequential Elements
4 × 4 reversible gates R1 and R2 cascaded together, as shown
As stated in Section II, not much research has been reported in Fig. 7. The output q of R1 is q = u ⊕ v ⊕ w. Similarly, the
relating to the construction of sequential reversible circuits. The output s of R2 is s = x ⊕ y ⊕ z. Thus, q and s are the parity
construction of latches and flip-flops using reversible gates is outputs of R1 and R2, respectively. As stated in [30], if R1
described in [23] and [32]. This section presents realizations is fault free, its parity output q and the parity output s of R2
of some sequential elements that are better than those reported should be complementary; otherwise, the presence of a fault is
in [23]. Fig. 3 proposes a reversible positive-level-triggered assumed. A similar assumption is made about the faults in logic
T flip-flop. Here, a Fredkin gate is used as a 2:1 multiplexer, blocks in this paper.
and the Feynman gate is used for realizing a fan-out of 2. The conversion procedure has two steps: In the first step
The constructions of the master–slave D flip-flop and the every reversible gate G of the design is converted into a de-
T flip-flop are shown in Figs. 4 and 5, respectively. All the flip- duced reversible gate DRG(G) without modifying its original
flops shown in Figs. 3–5 follow the respective truth tables, as functionality. In the second step, DRG(G) is cascaded with a
stated in [31]. The comparison between the proposed designs deduced identity gate to realize a testable version of G, namely,
and the most recent designs reported in [23] is shown in Table I. T RG(G). The remaining of this section will explain in detail
It is evident from Table I that the proposed designs lead to a the aforementioned two steps.
25% reduction in garbage and also a reduction in the number of Step 1—Construction of DRG(R): Let the n × n reversible
3 × 3 reversible gates, as compared with the best [23] reported gate R be shown in Fig. 8(a), with the input vector I =
in the literature. [I1 , I2 , . . . , In ] and the output vector O = [O1 , O2 , . . . , On ].

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104 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 1, JANUARY 2010

Fig. 5. Reversible positive-edge-triggered T flip-flop.

TABLE I
COMPARISON OF THE PROPOSED SEQUENTIAL DESIGNS WITH THE EXISTING DESIGNS

Fig. 9. Cascade of DRGs to form the T RC.

Fig. 6. Bijection to realize all nonconstant two-input Boolean functions.

Fig. 10. (a) T RC. (b) T C.

Fig. 7. Testable block of [30].

Proof: Let [I1 , I2 , . . . , In ] map to [O1 , O2 , . . . , On ] in R.

Given that Pin = 0, it is easily seen that [I1 , I2 , . . . , In , 0]
in DRG(R) maps to [O1 , O2 , . . . , On , F ], since Pout = F
when Pin = 0. Similarly, [I1 , I2 , . . . , In , 1] in DRG(R) maps
to [O1 , O2 , . . . , On , ∼F ], since Pout = ∼F when Pin = 1.
The foregoing fact and given that R is reversible imply that
DRG(R) is also reversible. 
Fig. 8. (a) n × n reversible gate. (b) DRG. Step 2—Construction of the Testable Reversible Cell
T RC(R): Let R be an n × n reversible gate. Consider an
As the gate is reversible, we have a one-to-one mapping n × n gate X such that all the inputs to the gate X are mapped
between vector I and vector O. Let Oi = Fi (I1 , I2 , . . . , In ), to the outputs without any change. It is obvious that the gate
shortly denoted by Fi (I), 1 ≤ i ≤ n. A DRG of R, i.e., X is reversible. Let DRa = DRG(R) and DRb = DRG(X).
DRG(R), is constructed by adding an extra input bit Pin and By Lemma 1, DRa and DRb are (n + 1) × (n + 1) reversible
the corresponding output bit Pout to the gate R, as shown in gates. Cascade the gates DRa and DRb , as shown in Fig. 9,
Fig. 8(b). The bijection for DRG(R) is derived as follows: The by connecting the first n outputs of DRa to the first n inputs
outputs (O1 , O2 , . . . , On ) remain the same, as defined by the of DRb in order. The resultant gate of Fig. 9 can be viewed as
original bijection of R. The new output Pout = F ⊕ Pin , where an (n + 2) × (n + 2) gate, as shown in Fig. 10(a), which forms
F = F1 (I) ⊕ F2 (I) ⊕ · · · ⊕ Fn (I). the T RC of R, i.e., T RC(R). The input vector of T RC(R)
Lemma 1: DRG(R) is reversible. is defined as [I, Pia , Pib ], where I is the input vector of gate

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MAHAMMAD AND VEEZHINATHAN: CONSTRUCTING ONLINE TESTABLE CIRCUITS USING REVERSIBLE LOGIC 105

R, and [Pia , Pib ] are the additional input bits added to R and Proof: Three observations can easily be seen.
X while constructing the gates DRa and DRb , respectively. 1) [Poa1 , Pob1 , . . . , Poan , Pobn , 0] maps to [Poa1 , Pob1 , . . . ,
Similarly, the output vector is defined as [O, Poa , Pob ], where O Poan , Pobn , T ] and [Poa1 , Pob1 , . . . , Poan , Pobn , 1] maps
is the output vector of gate R, and [Poa , Pob ] are the additional to [Poa1 , Pob1 , . . . , Poan , Pobn , ∼ T ], where T =
output bits added to R and X while constructing the gates DRa [((Poa1 ⊕ Pob1 )+(Poa2 ⊕Pob2 )+ · · · +(Poan ⊕Pobn ))⊕
and DRb , respectively. e]. Hence, T C is reversible.
Lemma 2: T RC(R) is reversible. 2) From the step 1 of Algorithm 1, it is seen that Pia =
Proof: The fact that DRa and DRb are reversible and the Pib in the T RC. If there is a single-bit logical error
construction of T RC(R) imply the lemma.  in, e.g., the ith T RC, then by Lemma 3, its Poai will
Lemma 3: T RC(R) has two fault detection properties. be complementary to Pobi . Therefore, Poai ⊕ Pobi = 1.
1) Setting Pia = Pib , then the output of T RC(R) is erro- Hence, T = 1.
neous if the parity bits Poa and Pob are complementary. 3) The role of the function T in the T C is to test if the
2) Setting Pia = ∼Pib , then the output of T RC(R) is erro- output parity bits of any of the n T RCs differ. Thus, T is
neous if the parity bits Poa and Pob are same. a Boolean function with 2n inputs, which is realized as an
OR of n two-input EXOR functions. It is straightforward
Proof: From the construction of T RC(R), note that to see that T evaluates to 0 if and only if all the n
Poa = Pia ⊕ O1 · · · ⊕ On and Pob = Pib ⊕ O1 · · · ⊕ On . The two-input EXOR functions evaluate to 0. There are two
proof for Case 1 is as follows: Given Pia = Pib and if Poa = possible inputs that set a two-input EXOR function to
Pob , then one of the outputs of DRa or DRb is faulty. The proof 0. This implies that there are 2n possible inputs that
for Case 2 follows in similar lines.  set T to 0, and the remaining 22n − 2n inputs set T
to 1. For an n-input k-output function f , the minimum
number of garbage bits required to make it reversible is
A. Construction of an Online Testable Circuit log2 M , where M is the maximum number of times
Algorithm 1 details the proposed approach for converting any an output pattern is repeated in the truth table of f [33].
reversible circuit to an online testable reversible circuit. For the function T , M = 22n − 2n , where n is the num-
ber of T RCs in C T . Therefore, log2 M = log2 (22n −
Algorithm 1: Construction of an Online Testable Circuit. 2n ) > log2 (22n /2) = (2n − 1), for n > 1. Therefore,
Input: Reversible Circuit C log2 M ≥ 2n. Hence, the minimum garbage that must
Output: An online testable reversible circuit C T be produced in the T C that implements T is 2n. 
1 Construct C S by replacing every reversible gate R in C
by T RC(R). While constructing T RC(R) for each R,
set the parity input bits Pia = Pib . By Lemma 2, C S is B. Construction of Hierarchical Online Testing Circuitry
reversible. The complexity (number of inputs) of the T C gate linearly
2 Let n be the number of reversible gates in C. Construct increases with n. The proposed hierarchical testing methodol-
a (2n + 1) × (2n + 1) test cell (T C), as shown in ogy is to have a T C for every module (circuit of reasonably
Fig. 10(b), as follows: Let Poak and Pobk be the output small size) of the chip. This section proposes a simple reversible
parity bits of the kth T RC of C S . gate, which is called the multimodular T C (M M T C), that
• The first 2n inputs of the T C are the output parity will take as inputs the T bits of the T Cs and output an error
bits from each of the n T RCs of C S , i.e., Poai

= (set one of its outputs to 1) if any one of the input T bits

Poai and Pobi = Pobi , 1 ≤ i ≤ n. is set to 1. Assume that there are k TCs. The M M T C is a
• The last input bit of the T C, which is denoted by e, (k + 1) × (k + 1) reversible gate, which is defined in the list
is set to either logic 0 or logic 1. that follows.
• The first 2n inputs of the T C are transferred to the
Inputs: T1 , T2 , . . . , Tk and e, where e can be either 0 or 1.
output without any change, i.e., Qoai = Poai
and
  Outputs: T1 , T2 , . . . , Tk , where M M T = (T1 + T2 + · · · +
Qobi = Pobi , 1 ≤ i ≤ n [refer to Fig. 10(b)].
Tn ) ⊕ e.
• The last output bit T of the T C is defined as fol-
lows: T = [((Poa1 ⊕ Pob1 )+(Poa2 ⊕ Pob2 )+ · · ·+ Lemma 4: The cell M M T C has three properties.
(Poan ⊕ Pobn )) ⊕ e]. 1) It is reversible.
3 Cascade C S and T C, as stated in step 2, to obtain C T . 2) M M T C detects any single-bit error in C1 , C2 , . . . , Ck ,
where Ci is an online testable reversible module ∀i.
Theorem 1: The cell T C constructed in Algorithm 1 has 3) Function M M T is implemented with minimum possible
three properties. garbage.
1) It is reversible. Proof: Three observations can easily be seen.
2) If there is a single-bit error in the output of any T RC in 1) [T1 , T2 , . . . , Tk , 0] maps to [T1 , T2 , . . . , Tk , M M T ] and
C T , then T = 1, provided e = 0. [T1 , T2 , . . . , Tk , 1] maps to [T1 , T2 , . . . , Tk , ∼M M T ],
3) Function T is implemented with minimum possible where M M T = (T1 + T2 + T3 + · · · + Tk ) ⊕ e. Hence,
garbage. M M T C is reversible.

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106 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 1, JANUARY 2010

TABLE II
TRUTH TABLE FOR THE DECODER CIRCUIT

Fig. 11. Two-to-four reversible decoder C.

2) Ti bit is the test bit from the T C of module Ci . The

multimodular test (M M T ) bit is the logical OR of Ti bits
for i = 1, 2, . . . , k. Hence, if there is any error in any of
the modules Ci , then M M T will be logical 1, provided
e = 0. Hence, the error is detected.
3) As mentioned earlier, the minimum number of garbage
bits required to make the function M M T reversible is
log2 M , where M is the maximum number of times
an output pattern is repeated in the truth table of M M T
[33]. Given that the bit e is set to 0, the function M M T is
a k-input OR function, which has 2k − 1 zeros in its truth
table. Hence, M = 2k − 1, where k is the number of on- Fig. 12. Deduced Fredkin gate DRa .
line testable reversible modules attached to the M M T C.
Therefore, log M = log (2k − 1) = k. Hence, the min-
imum garbage needed for making the function M M T
reversible is k. 
To sum up, the hierarchical online testable reversible circuit
can be constructed to realize a given Boolean function, as
follows: 1) realize the Boolean function in terms of reversible
gates; 2) convert each reversible gate R in the design into
T RC(R); 3) partition the T RCs into several sets; 4) for each
Fig. 13. Deduced gate DRb .
partition of T RCs, connect their output parity bits to a T C;
5) partition the T Cs into several blocks; 6) for each partition of in Fig. 1(c) implies the truth table shown in Table II, which
T Cs, connect their T outputs to an M M T C; 6) partition the captures the functionality of the decoder.
M M T C into several sets; 7) for each partition of M M T Cs, The following steps detail the conversion of the reversible
connect their M M T outputs to another M M T C; and 8) repeat decoder, as shown in Fig. 11, to an online testable decoder.
steps 6 and 7 until the number of M M T Cs becomes 1. An error
is detected when the M M T bit of the last (root) M M T C intro- Step 1) Each 3 × 3 Fredkin gate F is replaced by a 4 × 4
duced in step 7 is set to 1. Given that T RC, T C, and M M T C DRG DRa (F ), as shown in Fig. 12.
are reversible implies that the circuit built, as aforementioned, Step 2) Each DRa (F ) is connected to the deduced iden-
is also reversible. tity gate DRG(X) to form T RC(F ). DRG(X) is
In the next section, it will be shown by an example that the shown in Fig. 13.
proposed technique for constructing online testable reversible Step 3) Fig. 14 shows the online testable version of the
circuits yields circuits with much lesser garbage than those decoder shown in Fig. 11. The gate T RCi in Fig. 14
constructed using the latest technique reported in the litera- represents T RC(Fi ), 1 ≤ i ≤ 4, Fi , as shown in
ture [30]. Fig. 11.
Step 4) As shown in Fig. 14 the parity output bits of the
T RCs are connected to the T C. The output T of
V. I LLUSTRATION OF THE P ROPOSED T ECHNIQUE the T C will be set to 1 if any one of the output of
any reversible gate in the circuit is faulty.
In this section, a reversible decoder circuit is converted to
an online testable reversible decoder circuit using the proposed
A. Simulation Results
methodology. A decoder is a combinational circuit that con-
verts binary information from n input lines to a maximum of Fig. 15 shows the two-to-four reversible decoder realized
2n unique output lines. Consider a two-to-four decoder with using the reversible gate R1, and Fig. 16 is its online testable
the enable bit, as shown in Fig. 11. The construction of the version, which is constructed as stated in [30]. The gates R2
reversible decoder circuit uses three Fredkin gates (F1 , F2 , F3 ). and the two-pair two-rail checker shown in Fig. 16 are as
In Fig. 11, A and B are the one-bit inputs to the decoder, E described in [30]. Transistor-level realizations of the reversible
is the one-bit enable, and O1 , O2 , O3 , and O4 are the output logic circuits are presented in [23] and [30]. These realizations
bits of the decoder. The functionality of the Fredkin gate shown are functionally equivalent to the gate-level descriptions and

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MAHAMMAD AND VEEZHINATHAN: CONSTRUCTING ONLINE TESTABLE CIRCUITS USING REVERSIBLE LOGIC 107

Fig. 14. Online testable reversible decoder circuit C T .

TABLE III
SIMULATION RESULTS FOR THE URG SHOWN IN FIG. 2

TABLE IV
SIMULATION RESULTS FOR THE TWO-TO-FOUR DECODER

Fig. 15. Reversible decoder construction using the R1 gate.

reversible circuits using CMOS transmission gates. The circuits

are simulated using SPICE to obtain the voltage and current
waveforms. The 180-nm transistor model from TSMC is used
for the simulation. The transistors used in the simulation are
240 nm in width and 180 nm in length. The employed power
calculation method is similar to the method described in [35].
The results of the different simulations are summarized in the
list that follows.
1) Table III summarizes the results obtained by simulating
a static CMOS implementation of the URG gate shown
Fig. 16. Online testable R1-based reversible decoder. in Fig. 2 and its reversible RERL implementation. The
reversible implementation consumes 29.23 times lesser
do not employ any reversible energy recovery principles. The power, 2.57 times more transistors, and 3.77 times more
reversible energy recovery principles such as RERL, nRERL, delay than its static CMOS counterpart.
etc., as mentioned in Section II, result in circuits that dissipate 2) Table IV summarizes the results obtained by simulating
very less dynamic power when compared with their respec- three circuits, namely, a static CMOS implementation of a
tive static CMOS implementations. In this paper, the RERL two-to-four decoder; an R1-gate-based RERL implemen-
technique described in [34] is employed for constructing the tation of the same, as shown in Fig. 15; and the proposed

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108 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 59, NO. 1, JANUARY 2010

TABLE V lead to a 25% reduction in garbage and a lesser number of

SIMULATION RESULTS FOR AN ONLINE TESTABLE
TWO-TO-FOUR DECODER 3 × 3 reversible gates when compared with the best reported
in the literature. This paper has also proposed a methodology
that automatically converts any circuit into an online testable
reversible circuit with theoretically proved minimum garbage.
The resultant testable circuit can detect online any single-
bit errors in the logic blocks. An important advantage of the
Fredkin-gate-based RERL implementation, as shown technique is that the design of a given reversible circuit need
in Fig. 11. The R1-based implementation consumes not be changed for the purpose of adding testability feature
6.23 times lesser power, 18.6 times more transistors, and to it. This paper has discussed the construction of hierarchical
4.88 times more delay than its static CMOS counterpart. multimodular online testable reversible circuits. The proposed
The proposed Fredkin-gate-based implementation con- technique was illustrated using an example that converts a
sumes 14.73 times lesser power, 9.6 times more transis- Fredkin-based decoder circuit to an online testable reversible
tors, and 3.43 times more delay than its static CMOS decoder circuit. An interesting future work would be to con-
counterpart. The proposed Fredkin-gate-based implemen- struct reversible circuits that can mimic the functionality of
tation consumes 2.36 times lesser power, 1.94 times lesser k-input LUTs, k > 2.
transistors, and 1.42 times lesser delay than the R1-based
implementation.
ACKNOWLEDGMENT
3) Table V summarizes the results obtained by simulating
the two online testable decoders shown in Figs. 14 and 16. The authors would like to thank the anonymous referees
The proposed online testable implementation consumes for their constructive feedback, which helped in significantly
1.83 times lesser power, 2.04 times lesser transistors, and improving the technical quality of this paper, and also S. Potluri
1.88 times lesser delay than the R1-based implementation and V. Ashwin, Master’s students at the RISE Laboratory, IIT
[30]. Random errors (with similar effects as single-event Madras, for their timely help with the simulations.
upsets) were induced by toggling the signal values on
the interconnects within the testable cells such that they
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