A B C D E

MODEL NAME : PAP00

PCB NO : LA-6961P ( DA********** )
BOM P/N : TBD
1 1

Schematic Document
2

Phantom(Huron River) 2

Sandy Bridge(BGA1023) + Cougar Point(SFF)

DISCRETE VGA N12P-GS(optimus)
3
2010-11-29 3

Rev: 0.4

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 1 of 54
A B C D E
 A B C D E

Compal Confidential CPU XDP

FFS Fan Control
Project Code : PAP00 Small card P.31 Conn. P.5
File Name : LA-6961P
1
HDMI HDMI Intel 1

Conn. Sandy Bridge

PEG x16 (DIS) Processor Memory Bus (DDRIII) 204pin DDRIII SO-DIMM x2
DisplayPort GPU Dual Channel BANK 0, 1, 2, 3 P.10,11
DP Conn. N12P-GS 2C 17W ULV 1.5V DDRIII 1066/1333 MHz
P.30~41

BGA 1023
P.4~9

FDI x8 DMI x4
(UMA) 100MHz
100MHz 5GB/s
2.7GT/s

LVDS LVDS Port 0

SATA3.0
2
Conn. SATA HDD-1 Conn. 2
P.20 P.26

Port 1 USB 2.0

( USB Charger ) P.24

Intel Port 3
Cougar Point Digital Camera P.20
PCI-E x1
PCH SFF Port 4
Port 3 Port 2 Port 1 Port 4 Port 6 Mini Card-1 (WLAN)
( Half ) P.23
USB2.0
Mini Card-1 Mini Card-2 LAN(GbE) Card Reader USB 3.0/2.0
Port 5 Mini Card-2 (WWAN)
WLAN (Half) WWAN (Full) AR8151-BL1A JMB380 Host Ctrl. SIM Card
BGA 1017 Balls ( Full ) P.23 P.23
P.23 P.23 P.21 P.22 Small card
Port 6
3 USB[x] USB[x] 3 in 1 USB 3.0/2.0 AlienFX/ELC P.27 3

port4 port5 RJ45 Socket Combo Conns x2 HD Audio

P.21 P.22 Small card Port 2
P12~19 BT 2.1 /BT 3.0 P.34

1394
Conn. SPI LPC Bus
RTC CKT. Audio Codec Audio Jack x3
P.12 ALC665-GR Small card ( HeadPhone x2, MIC)
Small card

Power On/Off CKT. Digital MIC Small card

P.27 SPI ROM ENE 3810 ENE KB930
P.12 P.32 P.32
DC/DC Interface CKT. AMP. APA2031RI Int. Speaker Small card
P.43 Small card

4 Power Circuit DC/DC Touch Pad Int.KBD BIOS ROM 4

P.43 P.33 P.33 P.33

Security Classification Compal Secret Data Compal Electronics,Inc.

Issued Date 2010/06/10 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 24, 2011 Sheet 2 of 54
A B C D E
 A

Board ID Table for AD channel

Vcc 3.3V +/- 5% BOARD ID Table USB PORT# DESTINATION
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision 0 None
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.2 1 JUSB1 (Ext Left Side)
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.3
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 0.4 2 Bluetooth
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4 0.5
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 3 CAMERA
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 4 JMINI1 (WLAN)
PCH
SMBUS Control Table 5 JMINI2 (WWAN)

Thermal VGA Thermal 6 ELC

SOURCE MINI1 MINI2 BATT SODIMM Sensor 1 FFS Sensor SMSC

7 None
EC_SMB_CK1
EC_SMB_DA1
KB930 V
8 None
EC_SMB_CK2 KB930
EC_SMB_DA2
9 None
PCH_SML0CLK PCH Link
PCH_SML0DATA
10 None
PCH_SML1CLK
PCH_SML1DATA
PCH V V V V V
11 None
MEM_SMBCLK
MEM_SMBDATA
PCH V V
12 None
13 None
1 1

DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION SATA DESTINATION PCI EXPRESS DESTINATION

CLKOUT_PCIE0 None CLKOUTFLEX0 None SATA0 HDD Lane 1 10/100/1G LAN

CLKOUT_PCIE1 10/100/1G LAN CLKOUTFLEX1 None SATA1 None Lane 2 MINI CARD-2 WWAN/DMC

CLKOUT_PCIE2 MINI CARD-2 WWAN CLKOUTFLEX2 None SATA2 None Lane 3 MINI CARD-1 WLAN

CLK CLKOUT_PCIE3 MINI CARD-1 WLAN CLKOUTFLEX3 None SATA3 None Lane 4 CARD READER and 1394

CLKOUT_PCIE4 CARD READER SATA4 None Lane 5 None

CLKOUT DESTINATION
CLKOUT_PCIE5 None SATA5 None Lane 6 USB 3.0
PCI0 PCH_LOOPBACK
CLKOUT_PCIE6 USB 3.0 Lane 7 None
PCI1 EC Symbol Note :
CLKOUT_PCIE7 None Lane 8 None
PCI2 None : means Digital Ground
CLKOUT_PEG_B None
PCI3 None
: means Analog Ground
PCI4 None
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 3 of 54
A
 5 4 3 2 1

+1.05VS

PEG_ICOMPI and RCOMPO signals should be shorted and routed

1
with - max length = 500 mils - typical impedance = 43 mohms UCPU1I
RC2
PEG_ICOMPO signals should be routed with - max length = 500 mils
24.9_0402_1%
- typical impedance = 14.5 mohms
BG17 M4

2
UCPU1A VSS[181] VSS[251]
BG21 VSS[182] VSS[252] M58
D G3 PEG_COMP BG24 M6 D
PEG_ICOMPI VSS[183] VSS[253]
PEG_ICOMPO G1 BG28 VSS[184] VSS[254] N1
14 DMI_CRX_PTX_N0 M2 DMI_RX#[0] PEG_RCOMPO G4 BG37 VSS[185] VSS[255] N17
14 DMI_CRX_PTX_N1 P6 DMI_RX#[1] BG41 VSS[186] VSS[256] N21
14 DMI_CRX_PTX_N2 P1 DMI_RX#[2] BG45 VSS[187] VSS[257] N25
14 DMI_CRX_PTX_N3 P10 H22 PEG_GTX_C_HRX_N0 BG49 N28
DMI_RX#[3] PEG_RX#[0] PEG_GTX_C_HRX_N0 30 VSS[188] VSS[258]
J21 PEG_GTX_C_HRX_N1 BG53 N33
PEG_RX#[1] PEG_GTX_C_HRX_N1 30 VSS[189] VSS[259]
14 DMI_CRX_PTX_P0 N3 B22 PEG_GTX_C_HRX_N2 BG9 N36
DMI_RX[0] PEG_RX#[2] PEG_GTX_C_HRX_N2 30 VSS[190] VSS[260]
14 DMI_CRX_PTX_P1 P7 D21 PEG_GTX_C_HRX_N3 C29 N40
DMI_RX[1] PEG_RX#[3] PEG_GTX_C_HRX_N3 30 VSS[191] VSS[261]

DMI
14 DMI_CRX_PTX_P2 P3 A19 PEG_GTX_C_HRX_N4 C35 N43
DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N4 30 VSS[192] VSS[262]
14 DMI_CRX_PTX_P3 P11 D17 PEG_GTX_C_HRX_N5 C40 N47
DMI_RX[3] PEG_RX#[5] PEG_GTX_C_HRX_N5 30 VSS[193] VSS[263]
B14 PEG_GTX_C_HRX_N6 D10 N48
PEG_RX#[6] PEG_GTX_C_HRX_N6 30 VSS[194] VSS[264]
K1 D13 PEG_GTX_C_HRX_N7 D14 N51
14 DMI_CTX_PRX_N0 DMI_TX#[0] PEG_RX#[7] PEG_GTX_C_HRX_N7 30 VSS[195] VSS[265]
M8 A11 PEG_GTX_C_HRX_N8 D18 N52
14 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N8 30 VSS[196] VSS[266]
N4 B10 PEG_GTX_C_HRX_N9 D22 N56
14 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] PEG_GTX_C_HRX_N9 30 VSS[197] VSS[267]
R2 G8 PEG_GTX_C_HRX_N10 D26 N61
14 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N10 30 VSS[198] VSS[268]
A8 PEG_GTX_C_HRX_N11 D29 P14
PEG_RX#[11] PEG_GTX_C_HRX_N11 30 VSS[199] VSS[269]
K3 B6 PEG_GTX_C_HRX_N12 D35 P16
14 DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N12 30 VSS[200] VSS[270]
M7 H8 PEG_GTX_C_HRX_N13 D4 P18
14 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PEG_GTX_C_HRX_N13 30 VSS[201] VSS[271]
P4 E5 PEG_GTX_C_HRX_N14 D40 P21
14 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] PEG_GTX_C_HRX_N14 30 VSS[202] VSS[272]
T3 K7 PEG_GTX_C_HRX_N15 D43 P58
14 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]

PEG_RX[0] K22 PEG_GTX_C_HRX_P0

PEG_GTX_C_HRX_N15 30

PEG_GTX_C_HRX_P0 30
D46
D50
VSS[203]
VSS[204]
VSS[205]
VSS VSS[273]
VSS[274]
VSS[275]
P59
P9
K19 PEG_GTX_C_HRX_P1 D54 R17
PEG_RX[1] PEG_GTX_C_HRX_P1 30 VSS[206] VSS[276]
C21 PEG_GTX_C_HRX_P2 D58 R20
PEG_RX[2] PEG_GTX_C_HRX_P2 30 VSS[207] VSS[277]
FDI_CTX_PRX_N0 U7 D19 PEG_GTX_C_HRX_P3 D6 R4
14 FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3] PEG_GTX_C_HRX_P3 30 VSS[208] VSS[278]
FDI_CTX_PRX_N1
W11 C19 PEG_GTX_C_HRX_P4 E25 R46
14 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] PEG_GTX_C_HRX_P4 30 VSS[209] VSS[279]
FDI_CTX_PRX_N2W1 D16 PEG_GTX_C_HRX_P5 E29 T1
14 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] PEG_GTX_C_HRX_P5 30 VSS[210] VSS[280]

PCI EXPRESS -- GRAPHICS

FDI_CTX_PRX_N3AA6 C13 PEG_GTX_C_HRX_P6 E3 T47
14 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] PEG_GTX_C_HRX_P6 30 VSS[211] VSS[281]
FDI_CTX_PRX_N4W6 D12 PEG_GTX_C_HRX_P7 E35 T50
14 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7] PEG_GTX_C_HRX_P7 30 VSS[212] VSS[282]
FDI_CTX_PRX_N5 V4 C11 PEG_GTX_C_HRX_P8 E40 T51
14 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8] PEG_GTX_C_HRX_P8 30 VSS[213] VSS[283]
FDI_CTX_PRX_N6 Y2 C9 PEG_GTX_C_HRX_P9 F13 T52
14 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] PEG_GTX_C_HRX_P9 30 VSS[214] VSS[284]
Intel(R) FDI

C FDI_CTX_PRX_N7AC9 F8 PEG_GTX_C_HRX_P10 F15 T53 C

14 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10] PEG_GTX_C_HRX_P10 30 VSS[215] VSS[285]
C8 PEG_GTX_C_HRX_P11 F19 T55
PEG_RX[11] PEG_GTX_C_HRX_P11 30 VSS[216] VSS[286]
C5 PEG_GTX_C_HRX_P12 F29 T56
PEG_RX[12] PEG_GTX_C_HRX_P12 30 VSS[217] VSS[287]
FDI_CTX_PRX_P0 U6 H6 PEG_GTX_C_HRX_P13 F35 U13
14 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13] PEG_GTX_C_HRX_P13 30 VSS[218] VSS[288]
FDI_CTX_PRX_P1W10 F6 PEG_GTX_C_HRX_P14 F40 U8
14 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P14 30 VSS[219] VSS[289]
FDI_CTX_PRX_P2 W3 K6 PEG_GTX_C_HRX_P15 F55 V20
14 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15] PEG_GTX_C_HRX_P15 30 VSS[220] VSS[290]
FDI_CTX_PRX_P3AA7 G48 V61
14 FDI_CTX_PRX_P3 FDI0_TX[3] VSS[221] VSS[291]
FDI_CTX_PRX_P4 W7 G22 PEG_HTX_GRX_N0 CC185 1 2 0.1U_0402_10V7K~D G51 W13
14 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0] PEG_HTX_C_GRX_N0 30 VSS[222] VSS[292]
FDI_CTX_PRX_P5 T4 C23 PEG_HTX_GRX_N1 CC186 1 2 0.1U_0402_10V7K~D G6 W15
14 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] PEG_HTX_C_GRX_N1 30 VSS[223] VSS[293]
FDI_CTX_PRX_P6AA3 D23 PEG_HTX_GRX_N2 CC187 1 2 0.1U_0402_10V7K~D G61 W18
14 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2] PEG_HTX_C_GRX_N2 30 VSS[224] VSS[294]
FDI_CTX_PRX_P7AC8 F21 PEG_HTX_GRX_N3 CC188 1 2 0.1U_0402_10V7K~D H10 W21
14 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] PEG_HTX_C_GRX_N3 30 VSS[225] VSS[295]
H19 PEG_HTX_GRX_N4 CC189 1 2 0.1U_0402_10V7K~D H14 W46
PEG_TX#[4] PEG_HTX_C_GRX_N4 30 VSS[226] VSS[296]
14 FDI_FSYNC0 FDI_FSYNC0 AA11 C17 PEG_HTX_GRX_N5 CC190 1 2 0.1U_0402_10V7K~D H17 W8
FDI0_FSYNC PEG_TX#[5] PEG_HTX_C_GRX_N5 30 VSS[227] VSS[297]
14 FDI_FSYNC1 FDI_FSYNC1 AC12 K15 PEG_HTX_GRX_N6 CC191 1 2 0.1U_0402_10V7K~D H21 Y4
FDI1_FSYNC PEG_TX#[6] PEG_HTX_C_GRX_N6 30 VSS[228] VSS[298]
F17 PEG_HTX_GRX_N7 CC192 1 2 0.1U_0402_10V7K~D H4 Y47
PEG_TX#[7] PEG_HTX_C_GRX_N7 30 VSS[229] VSS[299]
14 FDI_INT FDI_INT U11 F14 PEG_HTX_GRX_N8 CC193 1 2 0.1U_0402_10V7K~D H53 Y58
FDI_INT PEG_TX#[8] PEG_HTX_C_GRX_N8 30 VSS[230] VSS[300]
A15 PEG_HTX_GRX_N9 CC194 1 2 0.1U_0402_10V7K~D H58 Y59
PEG_TX#[9] PEG_HTX_C_GRX_N9 30 VSS[231] VSS[301]
14 FDI_LSYNC0 FDI_LSYNC0 AA10 J14 PEG_HTX_GRX_N10 CC195 1 2 0.1U_0402_10V7K~D J1
FDI0_LSYNC PEG_TX#[10] PEG_HTX_C_GRX_N10 30 VSS[232]
14 FDI_LSYNC1 FDI_LSYNC1 AG8 H13 PEG_HTX_GRX_N11 CC196 1 2 0.1U_0402_10V7K~D J49
FDI1_LSYNC PEG_TX#[11] PEG_HTX_C_GRX_N11 30 VSS[233]
M10 PEG_HTX_GRX_N12 CC197 1 2 0.1U_0402_10V7K~D J55
PEG_TX#[12] PEG_HTX_C_GRX_N12 30 VSS[234]
F10 PEG_HTX_GRX_N13 CC198 1 2 0.1U_0402_10V7K~D K11
+1.05VS PEG_TX#[13] PEG_HTX_C_GRX_N13 30 VSS[235]
D9 PEG_HTX_GRX_N14 CC199 1 2 0.1U_0402_10V7K~D K21
PEG_TX#[14] PEG_HTX_C_GRX_N14 30 VSS[236]
J4 PEG_HTX_GRX_N15 CC200 1 2 0.1U_0402_10V7K~D K51 A5
PEG_TX#[15] PEG_HTX_C_GRX_N15 30 VSS[237] VSS_NCTF_1
1 2 +EDP_COM AF3 K8 A57
RC36 24.9_0402_1% eDP_COMPIO PEG_HTX_GRX_P0 CC201 0.1U_0402_10V7K~D VSS[238] VSS_NCTF_2
AD2 eDP_ICOMPO PEG_TX[0] F22 1 2 PEG_HTX_C_GRX_P0 30 L16 VSS[239] VSS_NCTF_3 BC61
2 1 10K_0402_5% AG11 A23 PEG_HTX_GRX_P1 CC202 1 2 0.1U_0402_10V7K~D L20 BD3
eDP_HPD PEG_TX[1] PEG_HTX_C_GRX_P1 30 VSS[240] VSS_NCTF_4
RC126 D24 PEG_HTX_GRX_P2 CC203 1 2 0.1U_0402_10V7K~D L22 BD59
PEG_HTX_C_GRX_P2 30

NCTF
PEG_TX[2] PEG_HTX_GRX_P3 CC204 0.1U_0402_10V7K~D VSS[241] VSS_NCTF_5
PEG_TX[3] E21 1 2 PEG_HTX_C_GRX_P3 30 L26 VSS[242] VSS_NCTF_6 BE4
AG4 G19 PEG_HTX_GRX_P4 CC205 1 2 0.1U_0402_10V7K~D L30 BE58
eDP_AUX# PEG_TX[4] PEG_HTX_C_GRX_P4 30 VSS[243] VSS_NCTF_7
AF4 B18 PEG_HTX_GRX_P5 CC206 1 2 0.1U_0402_10V7K~D L34 BG5
eDP_AUX PEG_TX[5] PEG_HTX_C_GRX_P5 30 VSS[244] VSS_NCTF_8
K17 PEG_HTX_GRX_P6 CC207 1 2 0.1U_0402_10V7K~D L38 BG57
PEG_TX[6] PEG_HTX_C_GRX_P6 30 VSS[245] VSS_NCTF_9
DP

G17 PEG_HTX_GRX_P7 CC208 1 2 0.1U_0402_10V7K~D L43 C3

B PEG_TX[7] PEG_HTX_C_GRX_P7 30 VSS[246] VSS_NCTF_10 B
AC3 E14 PEG_HTX_GRX_P8 CC209 1 2 0.1U_0402_10V7K~D L48 C58
eDP_TX#[0] PEG_TX[8] PEG_HTX_C_GRX_P8 30 VSS[247] VSS_NCTF_11
AC4 C15 PEG_HTX_GRX_P9 CC210 1 2 0.1U_0402_10V7K~D L61 D59
eDP_TX#[1] PEG_TX[9] PEG_HTX_C_GRX_P9 30 VSS[248] VSS_NCTF_12
AE11 K13 PEG_HTX_GRX_P10 CC211 1 2 0.1U_0402_10V7K~D M11 E1
eDP_TX#[2] PEG_TX[10] PEG_HTX_C_GRX_P10 30 VSS[249] VSS_NCTF_13
AE7 G13 PEG_HTX_GRX_P11 CC212 1 2 0.1U_0402_10V7K~D M15 E61
eDP_TX#[3] PEG_TX[11] PEG_HTX_C_GRX_P11 30 VSS[250] VSS_NCTF_14
K10 PEG_HTX_GRX_P12 CC213 1 2 0.1U_0402_10V7K~D
PEG_TX[12] PEG_HTX_C_GRX_P12 30
AC1 G10 PEG_HTX_GRX_P13 CC214 1 2 0.1U_0402_10V7K~D
eDP_TX[0] PEG_TX[13] PEG_HTX_C_GRX_P13 30
AA4 D8 PEG_HTX_GRX_P14 CC215 1 2 0.1U_0402_10V7K~D
eDP_TX[1] PEG_TX[14] PEG_HTX_C_GRX_P14 30
AE10 K4 PEG_HTX_GRX_P15 CC216 1 2 0.1U_0402_10V7K~D
eDP_TX[2] PEG_TX[15] PEG_HTX_C_GRX_P15 30
AE6 eDP_TX[3] SANDY-BRIDGE_BGA1023~D

SANDY-BRIDGE_BGA1023~D @

@
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/6) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 4 of 54
5 4 3 2 1
 5 4 3 2 1

+3VS

1
+1.05VS +3VALW
RC6

0.1U_0402_16V4Z~D
10K_0402_5%
@ +1.5V_CPU_VDDQ
@ JXDP 1

CC65
XDP_PREQ# 1 0_0402_5%~D
1

1
XDP_PRDY# 2 14 SYSTEM_PWROK RC127 2 1
@ 2 RC8
3 3
XDP_BPM#0 RC35 0_0402_5% RC128 @ 2
2 1 4 4 14,25 PCH_PWROK 2 1 200_0402_1%
XDP_BPM#1 RC114 2 @ 1 0_0402_5% 5 +1.05VS 0_0402_5%~D UC1
5
6 1 5

2
XDP_BPM#2 RC117 2 6 B VCC
@ 1 0_0402_5% 7 7 14 PM_DRAM_PWRGD 1 2D_PWG 2 A

0.1U_0402_16V4Z~D

0.1U_0402_16V4Z~D
D XDP_BPM#3 RC115 2 @ 1 0_0402_5% 8 RC11 0_0402_5% 3 4 VDDPWRGOOD D
1K_0402_5%~D 8 RC4 GND Y
9 9 1 1 +3V_PCH 1 2
H_CPUPWRGD 1 2 RC22 H_CPUPWRGD_XDP 10 MC74VHC1G09DFT2G_SC70-5 RC8
10

CC67

CC66
14,25 PBTN_OUT# 0_0402_5%~D 1 @ 2 RC23 CFD_PWRBTN#_XDP 11 11
200_0402_1% CRB 1.1K

2
1K_0402_5%~D 1 2 RC7 CFG0_R 12 @
7 CFG0 12 2 2 CHECK LIST 0.7 --> 4.75K
14,25,54 VGATE 0_0402_5%~D 1 @ 2 RC26 SYS_PWROK_XDP 13 13
RC19
CLK_CPU_ITP 14 39_0402_1% INTEL recommand 1.1K
13 CLK_CPU_ITP 14
13 CLK_CPU_ITP# CLK_CPU_ITP# 15 PDG 0.71 rev -->200
1K_0402_5% 15
16

1
PLT_RST# 16
2 1 RC25 XDP_RST#_R 17 17
XDP_DBRESET# 18 Place near JXDP1
18
19 19

1
D
12 PCH_JTAG_TDO 0_0402_5% 2 @ 1 RC28 XDP_TDO 20 20
@
XDP_TRST# 21 9,43 RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3# 2 QC1
21
12 PCH_JTAG_TDI 0_0402_5% 2 @ 1 RC31 XDP_TDI 22 22
G 2N7002_SOT23
12 PCH_JTAG_TMS 0_0402_5% 2 @ 1 RC29 XDP_TMS 23 S

3
23
12 PCH_JTAG_TCK 0_0402_5% 1 @ 2 RC30 XDP_TCK1 24 24
25 25 G1 27
XDP_TCK 26 28
26 G2
The resistor ACES_87152-26051
+3VS
for HOOK2 should be
placed such that the +3VALW +1.05VS

0.1U_0402_16V4Z~D
stub is very small 1
on CFG0 net

1
CC68
1

@ RC32
RC27 2
75_0402_5%
1K_0402_5%~D

2
UC2
2

C 1 5 C
SYS_PWROK_XDP NC VCC RC33
15,21,22,23,24,25 PLT_RST# 2 A
3 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
GND Y 43_0402_1%
SN74LVC1G07DCKR_SC70-5~D

1
@
RC34
0_0402_5%

2
UCPU1B

J3 CLK_CPU_DMI_R RC37 1 2 0_0402_5%

PROC_DETECT (Processor Detect): pulled to BCLK CLK_CPU_DMI 13
H2 CLK_CPU_DMI#_R RC38 1 2 0_0402_5% CLK_CPU_DMI# 13

CLOCKS
BCLK#

MISC
ground on the processor package. There is no
connection to the processor silicon for this F49
signal. System board designers may use this 15 H_SNB_IVB# PROC_SELECT#
AG3 CLK_CPU_DPLL_R RC39 1 2 0_0402_5%
signal to determine if the processor is present DPLL_REF_CLK CLK_CPU_DPLL 13
AG1 CLK_CPU_DPLL#_R RC40 1 2 0_0402_5%
DPLL_REF_CLK# CLK_CPU_DPLL# 13
RC121 2 110K_0402_5% C57 PU/PD for JTAG signals
PROC_DETECT#
+1.05VS @ N59 +1.05VS
BCLK_ITP CLK_RES_ITP 13
BCLK_ITP# N58 CLK_RES_ITP# 13
PAD~D T1 @ H_CATERR# C49 CATERR# XDP_TMS 51_0402_5% 1 2 RC45
2

THERMAL
RC43 XDP_TDI_R 51_0402_5% 1 2 RC46
62_0402_5% A48 AT30 H_DRAMRST#
16,25 H_PECI PECI SM_DRAMRST# H_DRAMRST# 6
XDP_PREQ# 51_0402_5% 1 @ 2 RC47
1

RC41 BF44 SM_RCOMP0 140_0402_1%1 2 RC55 XDP_TDO 51_0402_5% 1 2 RC48

B H_PROCHOT#_R SM_RCOMP[0] SM_RCOMP1 25.5_0402_1%1 B
25,44 H_PROCHOT# 1 2 C45 PROCHOT# SM_RCOMP[1] BE43 2 RC58

DDR3
MISC
56_0402_5% BG43 SM_RCOMP2 200_0402_1%1 2 RC60
SM_RCOMP[2]
DDR3 Compensation Signals XDP_TCK 51_0402_5% 1 2 RC52
H_THERMTRIP# D45
16 H_THERMTRIP# THERMTRIP# XDP_TRST# 51_0402_5% 1 2 RC54

N53 XDP_PRDY#
PRDY# XDP_PREQ#
PREQ# N55

L56 XDP_TCK
TCK XDP_TMS
TMS L55
PWR MANAGEMENT

J58 XDP_TRST#
JTAG & BPM

RC49 TRST#

14 H_PM_SYNC 1 2 H_PM_SYNC_R C48 M60 XDP_TDI_R RC50 1 2 0_0402_5% XDP_TDI

PM_SYNC TDI XDP_TDO_R
0_0402_5%
TDO L59 RC51 1 2 0_0402_5% XDP_TDO
+3VS
RC53
16 H_CPUPWRGD 1 2 H_CPUPWRGD_R B46 RC56 XDP_DBRESET# 1K_0402_5% 1 2 RC42
UNCOREPWRGOOD
0_0402_5%
DBR# K58 XDP_DBRESET#_R 1 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# 14
RC57
VDDPWRGOOD 1 2 VDDPWRGOOD_R BE45 G58 XDP_BPM#0_R RC59 1 2 0_0402_5% XDP_BPM#0 H_CPUPWRGD_R 10K_0402_5%1 2 RC44
130_0402_1% SM_DRAMPWROK BPM#[0] XDP_BPM#1_R RC61 0_0402_5% XDP_BPM#1
BPM#[1] E55 1 2
E59 XDP_BPM#2_R RC62 1 2 0_0402_5% XDP_BPM#2
BPM#[2] XDP_BPM#3_R RC63 0_0402_5% XDP_BPM#3
BPM#[3] G55 1 2
G59 XDP_BPM#4_R RC64 1 2 0_0402_5% XDP_BPM#4
BUF_CPU_RST# BPM#[4] XDP_BPM#5_R RC65 0_0402_5% XDP_BPM#5
D44 RESET# BPM#[5] H60 1 2
J59 XDP_BPM#6_R RC66 1 2 0_0402_5% XDP_BPM#6
BPM#[6] XDP_BPM#7_R RC67 0_0402_5% XDP_BPM#7
BPM#[7] J61 1 2

XDP_BPM#4 RC68 1 2 0_0402_5%

A CFG12 7 A
XDP_BPM#5 RC69 1 2 0_0402_5%
CFG13 7
XDP_BPM#6 RC70 1 2 0_0402_5%
CFG14 7
XDP_BPM#7 RC71 1 2 0_0402_5%
CFG15 7
SANDY-BRIDGE_BGA1023~D

@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/6) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 5 of 54
5 4 3 2 1
 5 4 3 2 1

UCPU1C
10 DDR_A_D[0..63]
UCPU1D
DDR_A_D0 AG6 SA_DQ[0] 11 DDR_B_D[0..63]
DDR_A_D1 AJ6 AU36 M_CLK_DDR0
SA_DQ[1] SA_CLK[0] M_CLK_DDR0 10
DDR_A_D2 AP11 AV36 M_CLK_DDR#0 DDR_B_D0 AL4
SA_DQ[2] SA_CLK#[0] M_CLK_DDR#0 10 SB_DQ[0]
D DDR_A_D3 AL6 AY26 DDR_CKE0_DIMMA DDR_B_D1 AL1 BA34 M_CLK_DDR2 D
SA_DQ[3] SA_CKE[0] DDR_CKE0_DIMMA 10 SB_DQ[1] SB_CLK[0] M_CLK_DDR2 11
DDR_A_D4 AJ10 DDR_B_D2 AN3 AY34 M_CLK_DDR#2
SA_DQ[4] SB_DQ[2] SB_CLK#[0] M_CLK_DDR#2 11
DDR_A_D5 AJ8 DDR_B_D3 AR4 AR22 DDR_CKE2_DIMMB
SA_DQ[5] SB_DQ[3] SB_CKE[0] DDR_CKE2_DIMMB 11
DDR_A_D6 AL8 DDR_B_D4 AK4
DDR_A_D7 SA_DQ[6] DDR_B_D5 SB_DQ[4]
AL7 SA_DQ[7] AK3 SB_DQ[5]
DDR_A_D8 AR11 DDR_B_D6 AN4
DDR_A_D9 SA_DQ[8] M_CLK_DDR1 DDR_B_D7 SB_DQ[6]
AP6 SA_DQ[9] SA_CLK[1] AT40 M_CLK_DDR1 10 AR1 SB_DQ[7]
DDR_A_D10 AU6 AU40 M_CLK_DDR#1 DDR_B_D8 AU4
SA_DQ[10] SA_CLK#[1] M_CLK_DDR#1 10 SB_DQ[8]
DDR_A_D11 AV9 BB26 DDR_CKE1_DIMMA DDR_B_D9 AT2 BA36 M_CLK_DDR3
SA_DQ[11] SA_CKE[1] DDR_CKE1_DIMMA 10 SB_DQ[9] SB_CLK[1] M_CLK_DDR3 11
DDR_A_D12 AR6 DDR_B_D10 AV4 BB36 M_CLK_DDR#3
SA_DQ[12] SB_DQ[10] SB_CLK#[1] M_CLK_DDR#3 11
DDR_A_D13 AP8 DDR_B_D11 BA4 BF27 DDR_CKE3_DIMMB
SA_DQ[13] SB_DQ[11] SB_CKE[1] DDR_CKE3_DIMMB 11
DDR_A_D14 AT13 DDR_B_D12 AU3
DDR_A_D15 SA_DQ[14] DDR_B_D13 SB_DQ[12]
AU13 SA_DQ[15] AR3 SB_DQ[13]
DDR_A_D16 BC7 DDR_B_D14 AY2
DDR_A_D17 SA_DQ[16] DDR_CS0_DIMMA# DDR_B_D15 SB_DQ[14]
BB7 SA_DQ[17] SA_CS#[0] BB40 DDR_CS0_DIMMA# 10 BA3 SB_DQ[15]
DDR_A_D18 BA13 BC41 DDR_CS1_DIMMA# DDR_B_D16 BE9
SA_DQ[18] SA_CS#[1] DDR_CS1_DIMMA# 10 SB_DQ[16]
DDR_A_D19 BB11 DDR_B_D17 BD9 BE41 DDR_CS2_DIMMB#
SA_DQ[19] SB_DQ[17] SB_CS#[0] DDR_CS2_DIMMB# 11
DDR_A_D20 BA7 DDR_B_D18 BD13 BE47 DDR_CS3_DIMMB#
SA_DQ[20] SB_DQ[18] SB_CS#[1] DDR_CS3_DIMMB# 11
DDR_A_D21 BA9 DDR_B_D19 BF12
DDR_A_D22 SA_DQ[21] DDR_B_D20 SB_DQ[19]
BB9 SA_DQ[22] BF8 SB_DQ[20]
DDR_A_D23 AY13 DDR_B_D21 BD10
DDR_A_D24 SA_DQ[23] M_ODT0 DDR_B_D22 SB_DQ[21]
AV14 SA_DQ[24] SA_ODT[0] AY40 M_ODT0 10 BD14 SB_DQ[22]
DDR_A_D25 AR14 BA41 M_ODT1 DDR_B_D23 BE13
SA_DQ[25] SA_ODT[1] M_ODT1 10 SB_DQ[23]
DDR_A_D26 AY17 DDR_B_D24 BF16 AT43 M_ODT2
SA_DQ[26] SB_DQ[24] SB_ODT[0] M_ODT2 11
DDR_A_D27 AR19 DDR_B_D25 BE17 BG47 M_ODT3
SA_DQ[27] SB_DQ[25] SB_ODT[1] M_ODT3 11
DDR_A_D28 BA14 DDR_B_D26 BE18
DDR_A_D29 SA_DQ[28] DDR_B_D27 SB_DQ[26]
AU14 SA_DQ[29] BE21 SB_DQ[27]
DDR_A_D30 BB14 DDR_B_D28 BE14
SA_DQ[30] DDR_A_DQS#[0..7] 10 SB_DQ[28]
DDR_A_D31 BB17 AL11 DDR_A_DQS#0 DDR_B_D29 BG14
DDR_A_D32 SA_DQ[31] SA_DQS#[0] DDR_A_DQS#1 DDR_B_D30 SB_DQ[29]
BA45 SA_DQ[32] SA_DQS#[1] AR8 BG18 SB_DQ[30] DDR_B_DQS#[0..7] 11
DDR_A_D33 AR43 AV11 DDR_A_DQS#2 DDR_B_D31 BF19 AL3 DDR_B_DQS#0
DDR_A_D34 SA_DQ[33] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D32 SB_DQ[31] SB_DQS#[0] DDR_B_DQS#1
AW48 SA_DQ[34] SA_DQS#[3] AT17 BD50 SB_DQ[32] SB_DQS#[1] AV3
DDR_A_D35 DDR_A_DQS#4 DDR_B_D33 DDR_B_DQS#2
DDR SYSTEM MEMORY A

BC48 SA_DQ[35] SA_DQS#[4] AV45 BF48 SB_DQ[33] SB_DQS#[2] BG11

DDR_A_D36 BC45 AY51 DDR_A_DQS#5 DDR_B_D34 BD53 BD17 DDR_B_DQS#3
DDR_A_D37 SA_DQ[36] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D35 SB_DQ[34] SB_DQS#[3] DDR_B_DQS#4
AR45 AT55 BF52 BG51

DDR SYSTEM MEMORY B

C
DDR_A_D38 SA_DQ[37] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D36 SB_DQ[35] SB_DQS#[4] DDR_B_DQS#5 C
AT48 SA_DQ[38] SA_DQS#[7] AK55 BD49 SB_DQ[36] SB_DQS#[5] BA59
DDR_A_D39 AY48 DDR_B_D37 BE49 AT60 DDR_B_DQS#6
DDR_A_D40 SA_DQ[39] DDR_B_D38 SB_DQ[37] SB_DQS#[6] DDR_B_DQS#7
BA49 SA_DQ[40] BD54 SB_DQ[38] SB_DQS#[7] AK59
DDR_A_D41 AV49 DDR_B_D39 BE53
DDR_A_D42 SA_DQ[41] DDR_B_D40 SB_DQ[39]
BB51 SA_DQ[42] BF56 SB_DQ[40]
DDR_A_D43 AY53 DDR_B_D41 BE57
DDR_A_D44 SA_DQ[43] DDR_B_D42 SB_DQ[41]
BB49 SA_DQ[44] DDR_A_DQS[0..7] 10 BC59 SB_DQ[42]
DDR_A_D45 AU49 AJ11 DDR_A_DQS0 DDR_B_D43 AY60
DDR_A_D46 SA_DQ[45] SA_DQS[0] DDR_A_DQS1 DDR_B_D44 SB_DQ[43]
BA53 SA_DQ[46] SA_DQS[1] AR10 BE54 SB_DQ[44]
DDR_A_D47 BB55 AY11 DDR_A_DQS2 DDR_B_D45 BG54
SA_DQ[47] SA_DQS[2] SB_DQ[45] DDR_B_DQS[0..7] 11
DDR_A_D48 BA55 AU17 DDR_A_DQS3 DDR_B_D46 BA58 AM2 DDR_B_DQS0
DDR_A_D49 SA_DQ[48] SA_DQS[3] DDR_A_DQS4 DDR_B_D47 SB_DQ[46] SB_DQS[0] DDR_B_DQS1
AV56 SA_DQ[49] SA_DQS[4] AW45 AW59 SB_DQ[47] SB_DQS[1] AV1
DDR_A_D50 AP50 AV51 DDR_A_DQS5 DDR_B_D48 AW58 BE11 DDR_B_DQS2
DDR_A_D51 SA_DQ[50] SA_DQS[5] DDR_A_DQS6 DDR_B_D49 SB_DQ[48] SB_DQS[2] DDR_B_DQS3
AP53 SA_DQ[51] SA_DQS[6] AT56 AU58 SB_DQ[49] SB_DQS[3] BD18
DDR_A_D52 AV54 AK54 DDR_A_DQS7 DDR_B_D50 AN61 BE51 DDR_B_DQS4
DDR_A_D53 SA_DQ[52] SA_DQS[7] DDR_B_D51 SB_DQ[50] SB_DQS[4] DDR_B_DQS5
AT54 SA_DQ[53] AN59 SB_DQ[51] SB_DQS[5] BA61
DDR_A_D54 AP56 DDR_B_D52 AU59 AR59 DDR_B_DQS6
DDR_A_D55 SA_DQ[54] DDR_B_D53 SB_DQ[52] SB_DQS[6] DDR_B_DQS7
AP52 SA_DQ[55] AU61 SB_DQ[53] SB_DQS[7] AK61
DDR_A_D56 AN57 DDR_B_D54 AN58
DDR_A_D57 SA_DQ[56] DDR_B_D55 SB_DQ[54]
AN53 SA_DQ[57] AR58 SB_DQ[55]
DDR_A_D58 AG56 DDR_B_D56 AK58
DDR_A_D59 SA_DQ[58] DDR_B_D57 SB_DQ[56]
AG53 SA_DQ[59] AL58 SB_DQ[57]
DDR_A_D60 AN55 DDR_B_D58 AG58
SA_DQ[60] DDR_A_MA[0..15] 10 SB_DQ[58]
DDR_A_D61 AN52 BG35 DDR_A_MA0 DDR_B_D59 AG59
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D60 SB_DQ[59]
AG55 SA_DQ[62] SA_MA[1] BB34 AM60 SB_DQ[60] DDR_B_MA[0..15] 11
DDR_A_D63 AK56 BE35 DDR_A_MA2 DDR_B_D61 AL59 BF32 DDR_B_MA0
SA_DQ[63] SA_MA[2] DDR_A_MA3 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
SA_MA[3] BD35 AF61 SB_DQ[62] SB_MA[1] BE33
AT34 DDR_A_MA4 DDR_B_D63 AH60 BD33 DDR_B_MA2
SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[5] AU34 SB_MA[3] AU30
BB32 DDR_A_MA6 BD30 DDR_B_MA4
SA_MA[6] DDR_A_MA7 SB_MA[4] DDR_B_MA5
10 DDR_A_BS0 BD37 SA_BS[0] SA_MA[7] AT32 SB_MA[5] AV30
BF36 AY32 DDR_A_MA8 BG30 DDR_B_MA6
10 DDR_A_BS1 SA_BS[1] SA_MA[8] SB_MA[6]
BA28 AV32 DDR_A_MA9 BG39 BD29 DDR_B_MA7
10 DDR_A_BS2 SA_BS[2] SA_MA[9] 11 DDR_B_BS0 SB_BS[0] SB_MA[7]
BE37 DDR_A_MA10 BD42 BE30 DDR_B_MA8
SA_MA[10] 11 DDR_B_BS1 SB_BS[1] SB_MA[8]
B BA30 DDR_A_MA11 AT22 BE28 DDR_B_MA9 B
SA_MA[11] 11 DDR_B_BS2 SB_BS[2] SB_MA[9]
BC30 DDR_A_MA12 BD43 DDR_B_MA10
SA_MA[12] DDR_A_MA13 SB_MA[10] DDR_B_MA11
10 DDR_A_CAS# BE39 SA_CAS# SA_MA[13] AW41 SB_MA[11] AT28
BD39 AY28 DDR_A_MA14 AV28 DDR_B_MA12
10 DDR_A_RAS# SA_RAS# SA_MA[14] SB_MA[12]
AT41 AU26 DDR_A_MA15 AV43 BD46 DDR_B_MA13
10 DDR_A_WE# SA_WE# SA_MA[15] 11 DDR_B_CAS# SB_CAS# SB_MA[13]
BF40 AT26 DDR_B_MA14
11 DDR_B_RAS# SB_RAS# SB_MA[14]
BD45 AU22 DDR_B_MA15
11 DDR_B_WE# SB_WE# SB_MA[15]

SANDY-BRIDGE_BGA1023~D

@ SANDY-BRIDGE_BGA1023~D

+1.5V
1

1 @ 2 RC75
RC74 0_0402_5%~D 1K_0402_5%~D
QC2
BSS138_SOT23
2
S

5 H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# 10,11

RC76 1K_0402_5%
DG 1.0 Figure 61 RC76=1K
G
2
1

RC77 1 2 DRAMRST_CNTRL_PCH 13
4.99K_0402_1%~D RC72 0_0402_5%~D
A A
DRAMRST_CNTRL
2

1 1 @ 2 DRAMRST_CNTRL_EC 25
RC73 0_0402_5%~D
CC69
0.047U_0402_16V4Z~D
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/6) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 6 of 54
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

D D
CFG2

1
@RC78
@ RC78
UCPU1E 1K_0402_1%~D

2
5 CFG0 CFG0 B50 BE7 @ T2
@T2 PAD~D
CFG1 CFG[0] RSVD28 @T3
@ T3 PAD~D
PAD~D T51 @ C51 CFG[1] RSVD29 BG7
CFG2 B54
CFG3 CFG[2]
PAD~D T53 @ D53 CFG[3]
CFG4 A51 N42 @ T4
@T4 PAD~D
CFG5 CFG[4] RSVD30 @T5
@ T5 PAD~D
C53 CFG[5] RSVD31 L42 PEG Static Lane Reversal - CFG2 is for the 16x
CFG6 C55 L45 @T6
@ T6 PAD~D
CFG7 CFG[6] RSVD32 @T7
@ T7 PAD~D
H49 CFG[7] RSVD33 L47
CFG8
PAD~D T59 @ CFG9
A55
H51
CFG[8]
CFG2
*1:(Default) Normal Operation; Lane #
PAD~D T60 @ CFG10 CFG[9] @ T8
@T8 PAD~D definition matches socket pin map definition
PAD~D T61 @ K49 CFG[10] RSVD34 M13
CFG11 K53 M14 @T9
@ T9 PAD~D
PAD~D T62 @ CFG12 CFG[11] RSVD35 @T10
@ T10 PAD~D
5 CFG12 F53 CFG[12] RSVD36 U14 0:Lane Reversed
5 CFG13 CFG13 G53 W14 @T11
@ T11 PAD~D
CFG14 CFG[13] RSVD37 @T12
@ T12 PAD~D
5 CFG14 L51 CFG[14] RSVD38 P13
5 CFG15 CFG15 F51 CFG4
+VCC_CORE CFG16 CFG[15]
PAD~D T64 @ D52 CFG[16]

1
CFG17 L53 AT49 @ T13
@T13 PAD~D
PAD~D T63 @ CFG[17] RSVD39 @T14
@ T14 PAD~D @RC81
@ RC81
RSVD40 K24
RC80 @ 1K_0402_1%~D

RESERVED
2 1 50_0402_1% VCC_VAL_SENSE H43
+VCC_GFXCORE_AXG VSS_VAL_SENSE VCC_VAL_SENSE @ T15
@T15 PAD~D
1 2 K43 AH2

2
RC91 @ 50_0402_1% VSS_VAL_SENSE RSVD41 @T16
@ T16 PAD~D
RSVD42 AG13
RC79 @ AM14 @T17
@ T17 PAD~D
VCC_AXG_VAL_SENSE RSVD43
2 1 50_0402_1% @ H45 VAXG_VAL_SENSE RSVD44 AM15 @T204
@ T204 PAD~D
C
1 2VSS_AXG_VAL_SENSE K45 VSSAXG_VAL_SENSE C
RC90 50_0402_1%
N50 @T20
@ T20 PAD~D
+V_DDR_REFA PAD~D T19 @ RSVD45
F48 VCC_DIE_SENSE Display Port Presence Strap
+V_DDR_REFB

RC82 @ 2 0_0402_5%~D +V_DDR_REFA_R

RC83
1
1 @ 2 0_0402_5%~D +V_DDR_REFB_R
H48
K48
RSVD6
CFG4
* 1 : Disabled; No Physical Display Port
RSVD7
A4 @T21
@ T21 PAD~D attached to Embedded Display Port
DC_TEST_A4
DC_TEST_C4 C4
PAD~D T25 @ BA19 D3 0 : Enabled; An external Display Port device is
RSVD8 DC_TEST_D3
1

PAD~D T26 @ AV19 D1 @T22

@ T22 PAD~D
AT21
RSVD9 DC_TEST_D1
A58 connected to the Embedded Display Port
RC84 RC85 PAD~D T28 @ RSVD10 DC_TEST_A58
BB21 RSVD11 DC_TEST_A59 A59
1K_0402_1% 1K_0402_1% PAD~D T30 @ BB19 C59
RSVD12 DC_TEST_C59
AY21 A61
2

PAD~D T33 @ RSVD13 DC_TEST_A61 CFG6

BA22 RSVD14 DC_TEST_C61 C61
PAD~D T34 @ AY22 D61 @ T24
@T24 PAD~D
PAD~D T35 @ RSVD15 DC_TEST_D61 @T29
@ T29 PAD~D CFG5
AU19 RSVD16 DC_TEST_BD61 BD61
INTEL 12/28 recommand AU21 RSVD17 DC_TEST_BE61 BE61

1
PAD~D T38 @ BD21 BE59
to add 1k pull down PAD~D T39 @ BD22
RSVD18 DC_TEST_BE59
BG61 @RC87
@ RC87 @RC86
@ RC86
PAD~D T40 @ RSVD19 DC_TEST_BG61 1K_0402_1%~D 1K_0402_1%~D
BD25 RSVD20 DC_TEST_BG59 BG59
PAD~D T41 @ BD26 BG58 @ T31
@T31 PAD~D
PAD~D T42 @ RSVD21 DC_TEST_BG58 @T36
@ T36 PAD~D
BG22 BG4

2
PAD~D T43 @ RSVD22 DC_TEST_BG4
BE22 RSVD23 DC_TEST_BG3 BG3
PAD~D T44 @ BG26 BE3
PAD~D T45 @ RSVD24 DC_TEST_BE3
BE26 RSVD25 DC_TEST_BG1 BG1
PAD~D T46 @ BF23 BE1
PAD~D T47 @ RSVD26 DC_TEST_BE1 @T48
@ T48 PAD~D
BE24 RSVD27 DC_TEST_BD1 BD1

PCIE Port Bifurcation Straps

SANDY-BRIDGE_BGA1023~D
B B
@ *11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

1
@RC89
@ RC89
1K_0402_1%~D

2
PEG DEFER TRAINING

CFG7
*1: (Default) PEG Train immediately
following xxRESETB de assertion

A 0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/6) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 7 of 54
5 4 3 2 1
 5 4 3 2 1

UCPU1F
+1.05VS

8.5A
+VCC_CORE AF46
VCCIO[1]

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VCCIO[3] AG48 1 1 1 1 1 1 1 1 1 1
VCCIO[4] AG50

CC235

CC236

CC217

CC237

CC218

CC219

CC220

CC221

CC222

CC223
D
DC=33A A26
A29
VCC[1] VCCIO[5] AG51
AJ17 D
VCC[2] VCCIO[6] 2 2 2 2 2 2 2 2 2 2
A31 VCC[3] VCCIO[7] AJ21
A34 VCC[4] VCCIO[8] AJ25
A35 VCC[5] VCCIO[9] AJ43
A38 VCC[6] VCCIO[10] AJ47
A39 VCC[7] VCCIO[11] AK50
A42 VCC[8] VCCIO[12] AK51
+VCC_CORE

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
C26 VCC[9] VCCIO[13] AL14 1 1 1 1 1 1 1 1 1
C27 VCC[10] VCCIO[14] AL15

CC238

CC224

CC239

CC225

CC226

CC240

CC227

CC228

CC229
C32 VCC[11] VCCIO[15] AL16
C34 VCC[12] VCCIO[16] AL20
2 2 2 2 2 2 2 2 2
C37 VCC[13] VCCIO[17] AL22
1 1 1 1 1 1 1 C39 VCC[14] VCCIO[18] AL26
22U_0805_6.3V6M
CC241

22U_0805_6.3V6M
CC230

22U_0805_6.3V6M
CC231

22U_0805_6.3V6M
CC232

22U_0805_6.3V6M
CC242

22U_0805_6.3V6M
CC233

22U_0805_6.3V6M
CC234
C42 VCC[15] VCCIO[19] AL45
D27 VCC[16] VCCIO[20] AL48
D32 VCC[17] VCCIO[21] AM16
2 2 2 2 2 2 2
D34 VCC[18] VCCIO[22] AM17
D37 VCC[19] VCCIO[23] AM21

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
D39 VCC[20] VCCIO[24] AM43 1 1 1 1 1 1 1 1 1
D42 VCC[21] VCCIO[25] AM47

CC243

CC244

CC245

CC246

CC247

CC248

CC249

CC250

CC251
E26 VCC[22] VCCIO[26] AN20
E28 VCC[23] VCCIO[27] AN42
2 2 2 2 2 2 2 2 2
E32 VCC[24] VCCIO[28] AN45
1 1 1 1 1 E34 VCC[25] VCCIO[29] AN48
22U_0805_6.3V6M
CC252

22U_0805_6.3V6M
CC253

22U_0805_6.3V6M
CC254

22U_0805_6.3V6M
CC255

22U_0805_6.3V6M
CC256

C106

C107

C108
470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M
1 1 1 E37 VCC[26]
E38 VCC[27]

CORE SUPPLY
+ + + F25
2 2 2 2 2 VCC[28]

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
F26

PEG AND DDR

VCC[29] 1 1 1 1 1 1 1 1
F28 VCC[30]
2 3 2 3 2 3

CC257

CC258

CC259

CC260

CC261

CC262

CC263

CC264
F32 VCC[31]
F34 VCC[32] 2 2 2 2 2 2 2 2 placed internal
F37 VCC[33] VCCIO[30] AA14
F38 VCC[34] VCCIO[31] AA15
F42 VCC[35] VCCIO[32] AB17
C
G42 VCC[36] VCCIO[33] AB20 C
H25 VCC[37] VCCIO[34] AC13
H26 VCC[38] VCCIO[35] AD16
+VCC_CORE

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D

330U_D2_2VM_R6M~D
H28 VCC[39] VCCIO[36] AD18 1 1 1
H29 VCC[40] VCCIO[37] AD21

CC110

CC111

CC112
H32 AE14 @ + + +
,ŝŐŚͲ&ƌĞƋƵĞŶĐLJĞĐŽƵƉůŝŶŐ H34
VCC[41]
VCC[42]
VCCIO[38]
VCCIO[39] AE15
H35 VCC[43] VCCIO[40] AF16
2 2 2
2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

H37 VCC[44] VCCIO[41] AF18

1 1 1 1 1 1 1 1 1 1 H38 VCC[45] VCCIO[42] AF20
CC265

CC266

CC267

CC268

CC269

CC270

CC271

CC272

CC273

CC274

H40 VCC[46] VCCIO[43] AG15

J25 VCC[47] VCCIO[44] AG16
J26 VCC[48] VCCIO[45] AG17
2 2 2 2 2 2 2 2 2 2
J28 VCC[49] VCCIO[46] AG20
J29 VCC[50] VCCIO[47] AG21
J32 VCC[51] VCCIO[48] AJ14

POWER
J34 VCC[52] VCCIO[49] AJ15
J35 VCC[53] +1.05VS
J37 VCC[54]
J38 VCC[55] +1.05VS
J40 VCC[56]
J42 VCC[57] RC122
K26 VCC[58] VCCIO50 W16
2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

2.2U_0402_6.3V6K

K27 VCC[59] VCCIO51 W17 1 2

1
1 1 1 1 1 1 K29 VCC[60]
CC275

CC276

CC277

CC278

CC279

CC280

K32 RC113
VCC[61] 0_0805_5%
K34 VCC[62] 75_0402_5%
K35 VCC[63]
2 2 2 2 2 2 Need PWR add new circuit on 1.05V(refer CRB)
K37

2
VCC[64]
K39 VCC[66]
K42 BC22 H_VCCP_SEL 2 1
placed internal VCC[67] VCCIO_SEL VCCP_PWRCTRL 50
L25 0_0402_5%~D RC88
VCC[68]
L28 VCC[69]
L33 VCC[70] +VCCP_VCCPQ +1.05VS +1.05VS
L36 VCC[71]
B L40 B

QUIET RAILS
VCC[72] RC123
N26 VCC[73]
N30 VCC[74] VCCPQE[1] AM25 1 2
N34 AN22 0_0805_5%
VCC[75] VCCPQE[2]
N38 VCC[76]

1
1 2

1
CC281 RC93 Place the PU
1U_0402_6.3V6K RC95 75_0402_5%
resistors close to CPU
130_0402_1%~D

2
2
A44 H_CPU_SVIDALRT# RC94 1 2 43_0402_1%
VIDALERT# VR_SVID_ALRT# 54
B43 H_CPU_SVIDCLK RC92 1 2 0_0402_5%~D
SVID

VIDSCLK VR_SVID_CLK 54
C44 H_CPU_SVIDDAT RC96 1 2 0_0402_5%~D
VIDSOUT VR_SVID_DAT 54
+VCC_CORE

1
Place the PU
RC97
100_0402_1%~D
resistors close to CPU

2
F43 VCCSENSE_R RC98 1 2 0_0402_5%~D
SENSE LINES

VCC_SENSE VCCSENSE 54
VSS_SENSE G43 VSSSENSE_R RC99 1 2 0_0402_5%~D VSSSENSE 54
@

1
RC124 1 2 +1.05VS
10_0402_1% RC100 Place the PU
AN16 VCCIO_SENSE 50 100_0402_1%~D
VCCIO_SENSE
AN17 resistors close to VR
VSS_SENSE_VCCIO VSSIO_SENSE 50

2
1

RC125
A A
10_0402_1%
SANDY-BRIDGE_BGA1023~D @
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/6) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 8 of 54
5 4 3 2 1
 5 4 3 2 1

+1.5V_CPU_VDDQ Source
+1.5V QC3 +1.5V_CPU_VDDQ
+3VALW B+_BIAS AO4728L_SO8~D
8 1
7 2

20K_0402_5%~D
6 3 1

10U_0805_10V4Z~D
5

CC138

RC103
RC101
RC102 100K_0402_5%~D UCPU1H

4
100K_0402_5%~D 2

2
RUN_ON_CPU1.5VS3

0.1U_0603_50V_X7R
A13 VSS[1] VSS[91] AM38

330K_0402_1%
QC5B 1 A17 AM4
RUN_ON_CPU1.5VS3# VSS[2] VSS[92]
D 5 A21 VSS[3] VSS[93] AM42 D

CC139
RC105
A25 VSS[4] VSS[94] AM45
2N7002DW-7-F_SOT363-6~D A28 AM48

4
2 VSS[5] VSS[95]
A33 AM58

2
VSS[6] VSS[96]

6
A37 VSS[7] VSS[97] AN1
QC5A A40 AN21
@RC104
@ RC104 2N7002DW-7-F_SOT363-6~D VSS[8] VSS[98]
A45 VSS[9] VSS[99] AN25
17,25,43,48,49,50,51 SUSP# 1 2 2 A49 VSS[10] VSS[100] AN28
0_0402_5%~D A53 AN33
RC107 VSS[11] VSS[101]
A9 AN36

1
VSS[12] VSS[102]
25 CPU1.5V_S3_GATE 1 2 RUN_ON_CPU1.5VS3# 5,43 AA1 VSS[13] VSS[103] AN40
0_0402_5%~D AA13 AN43
+VCC_GFXCORE_AXG VSS[14] VSS[104]
AA50 VSS[15] VSS[105] AN47
AA51 VSS[16] VSS[106] AN50
AA52 VSS[17] VSS[107] AN54
AA53 VSS[18] VSS[108] AP10
470U_D2_2VM_R4.5M

470U_D2_2VM_R4.5M

1 1 AA55 VSS[19] VSS[109] AP51

AA56 VSS[20] VSS[110] AP55
CC294

CC295

+ + AA8 AP7
+1.5V_CPU_VDDQ VSS[21] VSS[111]
AB16 VSS[22] VSS[112] AR13
AB18 VSS[23] VSS[113] AR17
2 2 UCPU1G AB21 VSS[24] VSS[114] AR21
AB48 VSS[25] VSS[115] AR41

1
AB61 VSS[26] VSS[116] AR48
1 2 RC112 AC10 AR61
@RC106
@ RC106 0_0402_5% 100_0402_1% VSS[27] VSS[117]
18A +V_SM_VREF should AC14 VSS[28] VSS[118] AR7
AA46 VAXG[1] have 10 mil trace width AC46 VSS[29] VSS[119] AT14
AB47 AC6 AT19

2
VAXG[2] VSS[30] VSS[120]
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

1 1 1 1 1 1 AB50 VAXG[3] AD17 VSS[31] VSS[121] AT36

CC282

CC286

CC287

CC283

CC288

CC289

AB51 AY43 +V_SM_VREF_CNT 3 1 +V_SM_VREF AD20 AT4

VAXG[4] SM_VREF VSS[32] VSS[122]
AB52 AD4 AT45
VAXG[5] VSS[33]
VSS VSS[123]

1
AB53 1 QC4 AD61 AT52
2 2 2 2 2 2 VAXG[6] CC284 NTR4503NT1G 1N_SOT23-3~D RC116 VSS[34] VSS[124]
AB55 VAXG[7] AE13 VSS[35] VSS[125] AT58
AB56 100_0402_1%
AB58
VAXG[8] 5A 2
AE8
AF1
VSS[36] VSS[126] AU1
AU11
VAXG[9] 0.1U_0402_16V4Z~D 2 VSS[37] VSS[127]
AB59 AJ28 AF17 AU28

2
VAXG[10] VDDQ[1] RUN_ON_CPU1.5VS3 VSS[38] VSS[128]
AC61 VAXG[11] VDDQ[2] AJ33 AF21 VSS[39] VSS[129] AU32
AD47 VAXG[12] VDDQ[3] AJ36 AF47 VSS[40] VSS[130] AU51
AD48 VAXG[13] VDDQ[4] AJ40 AF48 VSS[41] VSS[131] AU7
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

AD50 AL30 AF50 AV17

- 1.5V RAILS
VAXG[14] VDDQ[5] VSS[42] VSS[132]
1 1 1 1 1 AD51 VAXG[15] VDDQ[6] AL34 AF51 VSS[43] VSS[133] AV21
CC327

CC325

CC324

CC326

CC328

C AD52 AL38 AF52 AV22 C

VAXG[16] VDDQ[7] VSS[44] VSS[134]
AD53 VAXG[17] VDDQ[8] AL42 AF53 VSS[45] VSS[135] AV34
AD55 VAXG[18] VDDQ[9] AM33 AF55 VSS[46] VSS[136] AV40
2 2 2 2 2
AD56 VAXG[19] VDDQ[10] AM36 AF56 VSS[47] VSS[137] AV48
AD58 VAXG[20] VDDQ[11] AM40 AF58 VSS[48] VSS[138] AV55
AD59 VAXG[21] VDDQ[12] AN30 AF59 VSS[49] VSS[139] AW13
AE46 VAXG[22] VDDQ[13] AN34 AG10 VSS[50] VSS[140] AW43
+1.5V_CPU_VDDQ
POWER
N45 VAXG[23] VDDQ[14] AN38 AG14 VSS[51] VSS[141] AW61
P47 AR26 @J8
@ J8 AG18 AW7
VAXG[24] VDDQ[15] VSS[52] VSS[142]
P48 VAXG[25] VDDQ[16] AR28 1 2 +1.5V AG47 VSS[53] VSS[143] AY14
P50 VAXG[26] VDDQ[17] AR30 AG52 VSS[54] VSS[144] AY19
P51 AR32 PAD-OPEN 4x4m AG61 AY30
VAXG[27] VDDQ[18] VSS[55] VSS[145]
10U_0603_6.3V6M

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D
1 P52 AR34 1 1 1 1 1 1 1 1 1 AG7 AY36
DDR3

VAXG[28] VDDQ[19] VSS[56] VSS[146]

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1 1 1 1 1 P53 VAXG[29] VDDQ[20] AR36 PJP30 OPEN AH4 VSS[57] VSS[147] AY4
CC323

CC160

CC161

CC162

CC163

CC164

CC165

CC177

CC178
P55 AR40 + CC166 AH58 AY41
VAXG[30] VDDQ[21] VSS[58] VSS[148]
CC322

CC321

CC320

CC319

CC318

P56 AV41 330U_D2_2VM_R6M AJ13 AY45

2 VAXG[31] VDDQ[22] 2 2 2 2 2 2 2 2 VSS[59] VSS[149]
P61 VAXG[32] VDDQ[23] AW26 AJ16 VSS[60] VSS[150] AY49
2 2 2 2 2 2
T48 VAXG[33] VDDQ[24] BA40 AJ20 VSS[61] VSS[151] AY55
GRAPHICS

T58 VAXG[34] VDDQ[25] BB28 AJ22 VSS[62] VSS[152] AY58

T59 VAXG[35] VDDQ[26] BG33 AJ26 VSS[63] VSS[153] AY9
T61 VAXG[36] AJ30 VSS[64] VSS[154] BA1
U46 VAXG[37] AJ34 VSS[65] VSS[155] BA11
V47 VAXG[38] AJ38 VSS[66] VSS[156] BA17
V48 VAXG[39] AJ42 VSS[67] VSS[157] BA21
placed internal V50 AJ45 BA26
VAXG[40] VSS[68] VSS[158]

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
V51 VAXG[41] AJ48 VSS[69] VSS[159] BA32
V52 VAXG[42] 1 1 1 1 1 1 1 1 1 1 AJ7 VSS[70] VSS[160] BA48
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

CC302

CC303

CC304

CC305

CC306

CC307

CC308

CC309

CC310

CC311
V53 VAXG[43] AK1 VSS[71] VSS[161] BA51
1 1 1 1 1 1 V55 VAXG[44] AK52 VSS[72] VSS[162] BB53
CC296

CC297

CC298

CC299

CC300

CC301

V56 VAXG[45] AL10 VSS[73] VSS[163] BC13

2 2 2 2 2 2 2 2 2 2
V58 VAXG[46] AL13 VSS[74] VSS[164] BC5
V59 VAXG[47] AL17 VSS[75] VSS[165] BC57
2 2 2 2 2 2
W50 VAXG[48] AL21 VSS[76] VSS[166] BD12
W51 placed internal AL25 BD16
VAXG[49] VSS[77] VSS[167]
W52 VAXG[50] AL28 VSS[78] VSS[168] BD19
W53 VAXG[51] AL33 VSS[79] VSS[169] BD23
W55 VAXG[52] AL36 VSS[80] VSS[170] BD27
W56 VAXG[53] AL40 VSS[81] VSS[171] BD32
W61 VAXG[54] AL43 VSS[82] VSS[172] BD36
Y48 VAXG[55] AL47 VSS[83] VSS[173] BD40
Y61 VAXG[56] AL61 VSS[84] VSS[174] BD44
B B
AM13 VSS[85] VSS[175] BD48
AM20 VSS[86] VSS[176] BD52
+1.5V_CPU_VDDQ
AM22 VSS[87] VSS[177] BD56
AM26 VSS[88] VSS[178] BD8
+1.5V_CPU_VDDQ +1.5V AM30 BE5
QUIET RAILS

VSS[89] VSS[179]
TBD VCCDQ[1] AM28 AM34 VSS[90] VSS[180] BG13
LINES
SENSE

VCC_AXG_SENSE F45 AN26

54 VCC_AXG_SENSE VAXG_SENSE VCCDQ[2]
VSS_AXG_SENSE G45 1U_0402_6.3V6K CC182 2 1 0.1U_0402_10V7K~D
54 VSS_AXG_SENSE VSSAXG_SENSE
+1.8VS 1 2
CC184 2 1 0.1U_0402_10V7K~D
SANDY-BRIDGE_BGA1023~D
1.8V RAIL

CC312
CC181 2 1 0.1U_0402_10V7K~D
RC1091 2 0_0805_5% +1.8VS_VCCPLL BB3 VCCPLL[1]
1U_0402_6.3V6K~D

1 1 BC1 VCCPLL[2]
330U_D2_5VM_R6M~D

10U_0805_4VAM~D

1U_0402_6.3V6K~D

1 1 BC4 CC183 2 1 0.1U_0402_10V7K~D

VCCPLL[3]
CC176

CC175

+
CC172

CC174

2
2 2 2
VDDQ_SENSE BC43
BA43 add CC181 , CC182, 4 caps are all pop.
SENSE LINES

VSS_SENSE_VDDQ
6A L17 follow checklist 1.0 5/24
placed internal VCCSA[1]
L21 VCCSA[2]
N16 VCCSA[3]
+VCCSA N20 VCCSA[4]
SA RAIL

N22 VCCSA[5]
P17 VCCSA[6]
10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0805_4VAM~D

10U_0603_6.3V6M~D

1 1 1 1 1 1 P20 VCCSA[7] VCCSA_SENSE U10 VCCSA_SENSE 52

CC171 R16 VCCSA[8]
CC173

CC167

CC168

CC169

CC170

+ R18 VCCSA[9]
R21 VCCSA[10]
330U_D2_2VM_R6M~D 2 2 2 2 2
U15 VCCSA[11]
2
V16 VCCSA[12]
V17 D48 VCCSA_VID0
VCCSA[13] VCCSA_VID[0]
1

V18 VCCSA[14] VCCSA_VID[1] D49 VCCSA_SEL 52

2 1 RC120 V21 @ RC110 VID[0] VID[1] 2011 2012
52 VSSSA_SENSE VCCSA[15]
1

0_0402_5%~D W20 0_0402_5%~D 0 0 0.90 V Yes Yes

VCCSA[16] RC111 0 1 0.80 V Yes Yes
10K_0402_5% 1 0 0.725 V No Yes
2

A 1 1 0.675 V No Yes A
2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 SANDY-BRIDGE_BGA1023~D
CC313

CC314

CC315

CC316

CC317

@
2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

placed internal 2010/07/06 2011/07/06 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/6) PWR,VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 9 of 54
5 4 3 2 1
 5 4 3 2 1

+1.5V

1
RD2 0_0402_5%~D +1.5V +1.5V
6 DDR_A_DQS#[0..7]
RD1 +V_DDR_REFA 1 2 JDIMM1
1K_0402_1% +DIMM0_VREF 1 2
6 DDR_A_DQS[0..7] VREF_DQ VSS
3 4 DDR_A_D4
+V_DDR_REFA VSS DQ4

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
DDR_A_D0 5 6 DDR_A_D5
6 DDR_A_D[0..63]

2
DDR_A_D1 DQ0 DQ5
7 DQ1 VSS 8
1 1 9 10 DDR_A_DQS#0
6 DDR_A_MA[0..15] VSS DQS0#
11 12 DDR_A_DQS0
DM0 DQS0

CD1

CD2
13 VSS VSS 14
RD3 DDR_A_D2 15 16 DDR_A_D6
2 2 DDR_A_D3 DQ2 DQ6 DDR_A_D7
1K_0402_1% 17 DQ3 DQ7 18
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12

2
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 DQ9 DQ13 24
25 VSS VSS 26
DDR_A_DQS#1 27 28
D
DDR_A_DQS1 DQS1# DM1 DDR3_DRAMRST# D
29 DQS1 RESET# 30 DDR3_DRAMRST# 6,11
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
Layout Note: All VREF traces should 35 DQ11 DQ15 36
have 10 mil trace width 37 38
Place near JDIMM1 DDR_A_D16 39
VSS VSS
40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_A_DQS#2 45 46
DDR_A_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_A_D22
+1.5V DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS DDR_A_D28
55 VSS DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DQ24 DQ29
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

DDR_A_D25 59 60
DQ25 VSS DDR_A_DQS#3
1 1 1 1 61 VSS DQS3# 62
CD3

CD4

CD5

CD6

63 64 DDR_A_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_A_D26 67 68 DDR_A_D30
2 2 2 2 DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS VSS 72

6 DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA DDR_CKE1_DIMMA 6

CKE0 CKE1
75 VDD VDD 76
77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
6 DDR_A_BS2 79 BA2 A14 80
81 VDD VDD 82
+1.5V DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD VDD 88
DDR_A_MA8 89 90 DDR_A_MA6
A8 A6
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 VDD VDD 94
330U_SX_2VY~D

@ 1 DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
1 1 1 1 1 1 1 97 A1 A0 98
CD7

CD8

CD9

CD10

CD11

CD12

CD13

CD14

+ 99 100
M_CLK_DDR0 VDD VDD M_CLK_DDR1
6 M_CLK_DDR0 101 CK0 CK1 102 M_CLK_DDR1 6
C 6 M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1 M_CLK_DDR#1 6 C
2 2 2 2 2 2 2 2 CK0# CK1# +1.5V
105 VDD VDD 106
DDR_A_MA10 107 108 DDR_A_BS1 DDR_A_BS1 6
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
6 DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# 6
111 VDD VDD 112

1
6 DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA# DDR_CS0_DIMMA# 6
DDR_A_CAS# WE# S0# M_ODT0 RD4
6 DDR_A_CAS# 115 CAS# ODT0 116 M_ODT0 6
117 118 1K_0402_1%
DDR_A_MA13 VDD VDD M_ODT1
119 A13 ODT1 120 M_ODT1 6
6 DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122

2
S1# NC
123 VDD VDD 124
Layout Note: 125 126 +VREF_CA
TEST VREF_CA
127 128
Place near JDIMM1.203,204 VSS VSS

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
DDR_A_D33 131 132 DDR_A_D37
DQ33 DQ37 RD5
133 VSS VSS 134 1 1
DDR_A_DQS#4 135 136 1K_0402_1%
DQS4# DM4

CD15

CD16
DDR_A_DQS4 137 138
DQS4 VSS DDR_A_D38
139 140

2
DDR_A_D34 VSS DQ38 DDR_A_D39 2 2
141 DQ34 DQ39 142
DDR_A_D35 143 144
+0.75VS DQ35 VSS DDR_A_D44
145 VSS DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_A_DQS#5
VSS DQS5#
1U_0402_6.3V6K~D

153 154 DDR_A_DQS5

DM5 DQS5
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1 155 VSS VSS 156

1 1 1 DDR_A_D42 157 158 DDR_A_D46
DQ42 DQ46
CD17

DDR_A_D43 159 160 DDR_A_D47

DQ43 DQ47
CD18

CD19

CD20

161 VSS VSS 162

2 DDR_A_D48 DDR_A_D52
163 DQ48 DQ52 164
2 2 2 DDR_A_D49 DDR_A_D53
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_A_DQS#6 169 170
DDR_A_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_A_D54
DDR_A_D50 VSS DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS DDR_A_D60
179 VSS DQ60 180
DDR_A_D56 181 182 DDR_A_D61
B
DDR_A_D57 DQ56 DQ61 B
183 DQ57 VSS 184
185 186 DDR_A_DQS#7
VSS DQS7# DDR_A_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
195 VSS VSS 196
1 2 197 SA0 EVENT# 198
+3VS RD6 10K_0402_5%~D199 200 PCH_SMBDATA
VDDSPD SDA PCH_SMBDATA 11,13,24
1 2 201 202 PCH_SMBCLK
SA1 SCL PCH_SMBCLK 11,13,24
0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

1 1 RD7 10K_0402_5%~D203 204 +0.75VS

VTT VTT
CD21

CD22

+0.75VS
205 GND1 GND2 206
2 2
FOX AS0A626-U2RN-7F 204P DDR3
CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 10 of 54
5 4 3 2 1
 5 4 3 2 1

+1.5V

RD14 0_0402_5%~D

1
1 2 +1.5V +1.5V
+V_DDR_REFB
RD15 JDIMM2
1K_0402_1% +DIMM1_VREF 1 2
VREF_DQ VSS DDR_B_D4
3 VSS DQ4 4
+V_DDR_REFB

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
DDR_B_D0 5 6 DDR_B_D5

2
DDR_B_D1 DQ0 DQ5
7 DQ1 VSS 8
1 1 9 10 DDR_B_DQS#0
6 DDR_B_DQS#[0..7] VSS DQS0#
11 12 DDR_B_DQS0
DM0 DQS0

CD27

CD26
6 DDR_B_DQS[0..7] 13 VSS VSS 14

1
DDR_B_D2 15 16 DDR_B_D6
RD16 2 2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
6 DDR_B_D[0..63] 17 DQ3 DQ7 18
D
1K_0402_1% 19 VSS VSS 20 D
DDR_B_D8 21 22 DDR_B_D12
6 DDR_B_MA[0..15] DQ8 DQ12
DDR_B_D9 23 24 DDR_B_D13

2
DQ9 DQ13
25 VSS VSS 26
DDR_B_DQS#1 27 28
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# 6,10
Note: 31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
Check voltage tolerance of DDR_B_D11 35
DQ10 DQ14
36 DDR_B_D15
DQ11 DQ15
VREF_DQ at the DIMM socket 37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS DDR_B_D28
Layout Note: All VREF traces should 55 VSS DQ28 56
have 10 mil trace width DDR_B_D24 57 58 DDR_B_D29
Place near JDIMMB DDR_B_D25 59
DQ24 DQ29
60
DQ25 VSS DDR_B_DQS#3
61 VSS DQS3# 62
63 64 DDR_B_DQS3
DM3 DQS3
65 VSS VSS 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS VSS 72
+1.5V
6 DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB DDR_CKE3_DIMMB 6
CKE0 CKE1
75 VDD VDD 76
77 78 DDR_B_MA15
NC A15
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

6 DDR_B_BS2 DDR_B_BS2 79 80 DDR_B_MA14

BA2 A14
1 1 1 1 81 VDD VDD 82
CD28

CD29

CD30

CD31

DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD VDD 88
2 2 2 2 DDR_B_MA8 DDR_B_MA6
89 A8 A6 90
DDR_B_MA5 91 92 DDR_B_MA4
A5 A4
93 VDD VDD 94
C DDR_B_MA3 95 96 DDR_B_MA2 C
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
6 M_CLK_DDR2 M_CLK_DDR2 101 102 M_CLK_DDR3 M_CLK_DDR3 6
M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3
6 M_CLK_DDR#2 103 CK0# CK1# 104 M_CLK_DDR#3 6
+1.5V +1.5V
105 VDD VDD 106
DDR_B_MA10 107 108 DDR_B_BS1 DDR_B_BS1 6
DDR_B_BS0 A10/AP BA1 DDR_B_RAS#
6 DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# 6
111 VDD VDD 112

1
10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

6 DDR_B_WE# DDR_B_WE# 113 114 DDR_CS2_DIMMB# DDR_CS2_DIMMB# 6

DDR_B_CAS# WE# S0# M_ODT2 RD17
6 DDR_B_CAS# 115 CAS# ODT0 116 M_ODT2 6
330U_SX_2VY~D

@ 1 117 118 1K_0402_1%

DDR_B_MA13 VDD VDD M_ODT3
1 1 1 1 1 1 1 119 A13 ODT1 120 M_ODT3 6
CD32

CD33

CD34

CD35

CD36

CD37

CD38

CD39

+ DDR_CS3_DIMMB# 121 122

6 DDR_CS3_DIMMB#

2
S1# NC
123 VDD VDD 124
125 126 +VREF_CB
2 2 2 2 2 2 2 2 TEST VREF_CA
127 VSS VSS 128

2.2U_0603_6.3V6K~D

0.1U_0402_16V4Z~D
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36

1
DDR_B_D33 131 132 DDR_B_D37
DQ33 DQ37 RD18
133 VSS VSS 134 1 1
DDR_B_DQS#4 135 136 1K_0402_1%
DQS4# DM4

CD40

CD41
DDR_B_DQS4 137 138
DQS4 VSS DDR_B_D38
139 140

2
DDR_B_D34 VSS DQ38 DDR_B_D39 2 2
141 DQ34 DQ39 142
DDR_B_D35 143 144
DQ35 VSS DDR_B_D44
145 VSS DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
Layout Note: 149 DQ41 VSS 150
151 152 DDR_B_DQS#5
Place near JDIMMB.203,204 153
VSS DQS5#
154 DDR_B_DQS5
DM5 DQS5
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS VSS 168
+0.75VS DDR_B_DQS#6 169 170
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
B
DDR_B_D50 VSS DQ54 DDR_B_D55 B
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

179 180 DDR_B_D60

DDR_B_D56 VSS DQ60 DDR_B_D61
1 1 1 1 181 DQ56 DQ61 182
DDR_B_D57 183 184
DQ57 VSS
CD42

CD43

CD44

CD45

185 186 DDR_B_DQS#7

VSS DQS7# DDR_B_DQS7
187 DM7 DQS7 188
2 2 2 2
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
195 VSS VSS 196
+3VS 197 198
SA0 EVENT# PCH_SMBDATA
+3VS 199 VDDSPD SDA 200 PCH_SMBDATA 10,13,24
2 1 201 202 PCH_SMBCLK
SA1 SCL PCH_SMBCLK 10,13,24
+0.75VS 203 VTT VTT 204 +0.75VS
1

0.1U_0402_16V4Z~D

2.2U_0603_6.3V6K~D

RD19
10K_0402_5%~D

10K_0402_5%~D
RD20

1 1 205 GND1 GND2 206

CD46

CD47

FOX AS0A626-UARN-7F 204P DDR3

2

CONN@
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII DIMMB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 11 of 54
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

1 2 PCH_RTCX2
RH2 10M_0402_5%

32.768KHZ_12.5PF_Q13MC14610002
1

4
18P_0402_50V8J

1 1
OSC

OSC

CH2 CH3
18P_0402_50V8J
2 YH1 2
NC

NC

D D
2

UH1A
far away hot spot
+RTCVCC PCH_RTCX1 A19 A37 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 23,25

1
CMOS A39 LPC_AD1
FWH1 / LAD1 LPC_AD1 23,25
CH4 CLRP1 PCH_RTCX2 C19 C39 LPC_AD2
RTCX2 FWH2 / LAD2 LPC_AD2 23,25
1U_0603_10V4Z SHORT PADS C37 LPC_AD3
LPC_AD3 23,25

2
2 PCH_RTCRST# FWH3 / LAD3
1 2 F19 RTCRST#
RH25 20K_0402_5% K40 LPC_FRAME#
FWH4 / LFRAME# LPC_FRAME# 23,25
1 2 PCH_SRTCRST# A23
RH23 20K_0402_5% SRTCRST#
1 H40

LPC
RTC
LDRQ0#

1
SM_INTRUDER# K22 F37
CH5 CLRP2 INTRUDER# LDRQ1# / GPIO23
1U_0603_10V4Z SHORT PADS PCH_INTVRMEN C21 Y4 SERIRQ SERIRQ 25

2
HDA_BIT_CLK 2 ME CMOS INTVRMEN SERIRQ
24 HDA_BITCLK_AUDIO 1 2
RH27 33_0402_5% CLP1 & CLP2 place near DIMM
SATA0RXN AN3 SATA_PRX_DTX_N0 26
2 1 HDA_BIT_CLK H35 AN1 SATA_PRX_DTX_P0 26
HDA_BCLK SATA0RXP
10P_0402_50V8J @ C1077
SATA0TXN AU3 SATA_PTX_DRX_N0 CH91 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N0_C 26 HDD1
+5VS HDA_SYNC H37 AU1 SATA_PTX_DRX_P0 CH90 1 2 0.01U_0402_16V7K

SATA3
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0_C 26
1 2 HDA_RST#
24 HDA_RST_AUDIO#
RH28 33_0402_5% HDA_SPKR N1 AN6
24 HDA_SPKR SPKR SATA1RXN
2
G

SATA1RXP AN8
HDA_RST# F35 AR3
HDA_SYNC HDA_RST# SATA1TXN
24 HDA_SYNC_AUDIO 1 2 3 1 SATA1TXP AR1
RH33 33_0402_5% +RTCVCC
S

24 HDA_SDIN0 HDA_SDIN0 D36 AD4

QH1 BSS138_SOT23 HDA_SDIN0 SATA2RXN RH11 1 SM_INTRUDER#
SATA2RXP AD2 2
1 2 1 @ 2 B36 AL3 1M_0402_5%
RH275 1M_0402_5%~D RH36 0_0402_5%~D HDA_SDIN1 SATA2TXN
SATA2TXP AL1
C35

IHDA
HDA_SDIN2
C SATA3RXN AD8 C
A35 HDA_SDIN3 SATA3RXP AD6
SATA3TXN AG3
AG1 +RTCVCC
HDA_SDOUT HDA_SDOUT SATA3TXP
25 HDA_SDO 1 2 K37

SATA
RH24 0_0402_5%~D HDA_SDO
SATA4RXN AE3
@ AE1 PCH_INTVRMEN RH31 2 1 330K_0402_5%
HDA_SDOUT HDA_DOCK_EN# SATA4RXP
24 HDA_SDOUT_AUDIO 1 2 K35 HDA_DOCK_EN# / GPIO33 SATA4TXN AH8
RH30 33_0402_5% AH6 PCH_INTVRMEN RH34 2 @ 1 330K_0402_5%
SATA4TXP
29 PCH_DP_HPD M35 HDA_DOCK_RST# / GPIO13
SATA5RXN AC3
SATA5RXP AC1 INTVRMEN
+3V_PCH +3V_PCH +3V_PCH PCH_JTAG_TCK M17
SATA5TXN AJ3
AJ1
* H烉Integrated VRM enable
L烉Integrated VRM disable
5 PCH_JTAG_TCK JTAG_TCK SATA5TXP
PCH_JTAG_TMS M15 AB10 +1.05VS_VCC_SATA

JTAG
5 PCH_JTAG_TMS JTAG_TMS SATAICOMPO
1

@ RH38
@RH38 @ RH39
@RH39 @ RH40
@RH40 PCH_JTAG_TDI U12 AB12 SATA_COMP 1 2 +3VS
5 PCH_JTAG_TDI JTAG_TDI SATAICOMPI
200_0402_5% 200_0402_5% 200_0402_5% RH41 37.4_0402_1% @
PCH_JTAG_TDO M12 BBS_BIT0_R RH49 2 1 10K_0402_5%
5 PCH_JTAG_TDO JTAG_TDO +1.05VS_SATA3
AF10
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI SATA3RCOMPO SERIRQ RH29 2 1 10K_0402_5%

AF12 SATA3_COMP 1 2
SATA3COMPI
1

RH43 49.9_0402_1% PCH_GPIO21 RH32 2 1 10K_0402_5%

RH44 RH45 RH46
100_0402_1% 100_0402_1% 100_0402_1% PCH_SPI_CLK AD12 AH4 RBIAS_SATA3 1 2 PCH_SATALED#RH35 2 1 10K_0402_5%
SPI_CLK SATA3RBIAS RH48 750_0402_1%
PCH_SPI_CS# AB8
2

SPI_CS0#
AB6 +3VS
SPI

SPI_CS1# PCH_SATALED#
SATALED# W10 PCH_SATALED# 27
PCH_SPI_SI W8 M2 PCH_GPIO21 HDA_SPKR RH37 2 @ 1 1K_0402_5%
SPI_MOSI SATA0GP / GPIO21
PCH_SPI_SO Y2 R1 BBS_BIT0_R LOW=Default
SPI_MISO SATA1GP / GPIO19
*HIGH=No Reboot
B COUGAR-POINT-SFF_BGA1017~D B

HDA_SDO +3V_PCH
SPI ROM FOR ME ( 4MByte ) ME debug mode , this signal has a weak internal PD
L=>security measures defined in the Flash HDA_SDOUT RH42 2 @ 1 1K_0402_5%
+3V_PCH Descriptor will be in effect (default)
*Low = Disabled

SPI ROM FOR ME

High = Enabled
H=>Flash Descriptor Security will be overridden
2

( 4MByte )
@ RH57
3.3K_0402_5%
+3V_PCH
1

U48
PCH_SPI_CS# 1 2 PCH_SPI_CS#_R 1 8 HDA_SYNC
RH58 0_0402_5% /CS VCC
PCH_SPI_SO 1 2
RH60 0_0402_5%
PCH_SPI_SO_R 2 DO /HOLD 7 PCH_SPI_HOLD# 2
3.3K_0402_5%
1
RH56
1
CH6
0.1U_0402_16V4Z
RTC Battery This signal has a weak internal pull-down
On Die PLL VR is supplied by
+3V_PCH 1 2 PCH_SPI_WP# 3 6 PCH_SPI_CLK_R 2 1 PCH_SPI_CLK 1.5V when smapled high
RH54 3.3K_0402_5% /WP CLK RH255 0_0402_5% 2 +RTCBATT
PCH_SPI_SI_R +3VLP 1.8V when sampled low
4 GND DIO 5 1 2 PCH_SPI_SI
RH63 0_0402_5% Needs to be pulled High for Huron River platfrom

2
2 1 PCH_JTAG_TCK RH259
51_0402_5% RH53 W25X32VSSIG_SO8~D +3V_PCH
1K_0402_5% 20mils
SPI BIOS Pinout
20mils HDA_SYNC RH52 2 1 1K_0402_5%

2 1

3
(1)CS# (5)DIO
(2)DO (6)CLK DH4
(3)WP# (7)HOLD# BAT54CW_SOT323-3
2 1 HDA_SDOUT
10P_0402_50V8J @ C1083 (4)GND (8)VCC RH55
A 20mils A
@ @ +RTCVCC 1 HDA_DOCK_EN# 2 @ 1 1K_0402_5%
CH94 RH256 W25X32 1
2 1 1 2PCH_SPI_CLK CH95 PCH_GPIO21 RH47 2 1 10K_0402_5%
33_0402_5% 1U_0603_10V4Z @
22P_0402_50V8J Place CH95 close to PCH.
Reserve for EMI please close to UH1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/8) SATA,HDA,SPI, LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 12 of 54
5 4 3 2 1
 5 4 3 2 1

1 2 EC_LID_OUT# SMBCLK 1 2 +3V_PCH

EC_LID_OUT# 25
0_0402_5% RH68 RH67 2.2K_0402_5%
UH1B SMBDATA 1 2
RH69 2.2K_0402_5%
21 PCIE_PRX_GLANTX_N1 PCIE_PRX_GLANTX_N1 BJ33 SML0CLK 1 2
PCIE_PRX_GLANTX_P1 PERN1
21 PCIE_PRX_GLANTX_P1 BL33 PERP1 SMBALERT# / GPIO11 H12 PCH_LID_SW_IN# 1 @ 2 LID_SW_IN# 24,25,27
RH70 2.2K_0402_5%
10/100/1G LAN ---> CH9 1 2 0.1U_0402_10V7K~D PCIE_PTX_GLANRX_N1_C BB30 0_0402_5% RH71 SML0DATA 1 2
21 PCIE_PTX_GLANRX_N1 PETN1
CH14 1 2 0.1U_0402_10V7K~D PCIE_PTX_GLANRX_P1_C AY30 F17 SMBCLK RH72 2.2K_0402_5%
21 PCIE_PTX_GLANRX_P1 PETP1 SMBCLK
MEMORY SML1CLK 1 2
23 PCIE_PRX_WWANTX_N2 PCIE_PRX_WWANTX_N2 BJ35 F10 SMBDATA RH73 2.2K_0402_5%
PCIE_PRX_WWANTX_P2 PERN2 SMBDATA SML1DATA
23 PCIE_PRX_WWANTX_P2 BL35 PERP2 1 2
MiniWWAN ---> CH10 1 2 0.1U_0402_10V7K~D PCIE_PTX_WWANRX_N2_C BB33 RH74 2.2K_0402_5%
23 PCIE_PTX_WWANRX_N2 PETN2
CH15 1 2 0.1U_0402_10V7K~D PCIE_PTX_WWANRX_P2_C AY33 DRAMRST_CNTRL_PCH 1 2

SMBUS
D 23 PCIE_PTX_WWANRX_P2 PETP2 D
SML0ALERT# / GPIO60 H22 DRAMRST_CNTRL_PCH DRAMRST_CNTRL_PCH 6
RH75 1K_0402_5%
PCIE_PRX_WLANTX_N3
23 PCIE_PRX_WLANTX_N3
PCIE_PRX_WLANTX_P3
BH36
BK36
PERN3
K12 SML0CLK PCH_GPIO74
5/24 change
1 2
to 10K
23 PCIE_PRX_WLANTX_P3 PERP3 SML0CLK
MiniWLAN (Mini Card 2)---> CH11 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_N3_C BF33 RH87 10K_0402_5%
23 PCIE_PTX_WLANRX_N3 PETN3
CH16 1 2 0.1U_0402_10V7K~D PCIE_PTX_WLANRX_P3_C BD33 A9 SML0DATA
23 PCIE_PTX_WLANRX_P3 PETP3 SML0DATA LID_SW_IN# RH85 1 2 +3VALW
22 PCIE_PRX_CARDTX_N4 PCIE_PRX_CARDTX_N4 BJ37 47K_0402_5%~D
PCIE_PRX_CARDTX_P4 PERN4
22 PCIE_PRX_CARDTX_P4 BL37 PERP4
1394/Card Reader ---> CH12 1 2 0.1U_0402_10V7K~D PCIE_PTX_CARDRX_N4_C BD35 C9 PCH_GPIO74
22 PCIE_PTX_CARDRX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74
CH13 1 2 0.1U_0402_10V7K~D PCIE_PTX_CARDRX_P4_C BF35 CLKIN_DMI2# RH76 1 2 10K_0402_5%
22 PCIE_PTX_CARDRX_P4 PETP4
D12 SML1CLK CLKIN_DMI2 RH77 1 2 10K_0402_5%

PCI-E*
SML1CLK / GPIO58 CLKIN_DMI# RH78 10K_0402_5%
BJ39 PERN5 1 2
BL39 PERP5 SML1DATA / GPIO75 C11 SML1DATA CLKIN_DMI RH79 1 2 10K_0402_5%
EXPRESS_CARD ---> AY35 CLKIN_DOT96# RH80 1 2 10K_0402_5%
PETN5 CLKIN_DOT96 RH81 10K_0402_5%
BB35 PETP5 Total device 20090512
CLKIN_SATA# RH82
1 2
10K_0402_5%
1 2
PCIE_PRX_USB3TX_N6 BH40 add double mosfet prevent CLKIN_SATA RH83 1 2 10K_0402_5%
24 PCIE_PRX_USB3TX_N6 PERN6
PCIE_PRX_USB3TX_P6 BK40 ATI M92 electric leakage CLK_PCH_14M RH84 1 2 10K_0402_5%

Controller
24 PCIE_PRX_USB3TX_P6 PERP6
USB 3.0 ---> CH19 1 2 0.1U_0402_10V7K~D PCIE_PTX_USB3RX_N6_C BD37 L3
24 PCIE_PTX_USB3RX_N6 PETN6 CL_CLK1
CH20 1 2 0.1U_0402_10V7K~D PCIE_PTX_USB3RX_P6_C BF37
24 PCIE_PTX_USB3RX_P6 PETP6 If use extenal CLK gen, please place close to CLK gen

Link
BJ41 J1 else, please place close to PCH
PERN7 CL_DATA1
@ @
BL41
AY37
PERP7
PETN7
PRGLILHG
RH86 CH21 BB37 M8
CLK_PCH_14M 2 PETP7 CL_RST1# +3VS
1 1 2
33_0402_5% 22P_0402_50V8J BJ43 PERN8
BL43 PERP8
Reserve for EMI please close to UH1 AY40 +3V_PCH PCH_GPIO64 1 2
PETN8 RH166 10K_0402_5%
BB40 PETP8 RH141 PCH_GPIO65 1 2
R8 PEG_A_CLKRQ# 1 2 10K_0402_5%~D RH108 10K_0402_5%
C @ @ PAD~D T81 @ PEG_A_CLKRQ# / GPIO47 CAM_DET# C
AD48 CLKOUT_PCIE0N CLK_REQ_VGA# 30 1 2
RH89 CH22 PAD~D T82 @ AD50 RH179 10K_0402_5%
CLK_PCI_LPBACK2 CLKOUT_PCIE0P
1 1 2 AF44 CLK_PEG_VGA# CLK_PEG_VGA# 30 BT_DET# 1 2

CLOCKS
33_0402_5% 22P_0402_50V8J RH91 1 CLKOUT_PEG_A_N +3VS +3VS
+3V_PCH 2 10K_0402_5%~D PCIECLKREQ0# M4 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AF46 CLK_PEG_VGA CLK_PEG_VGA 30 RH109 10K_0402_5%
Reserve for EMI please close to
UH1
RH93 1 2 0_0402_5%~D PCIE_LAN# AE49 BB24 CLK_CPU_DMI#
21 CLK_PCIE_LAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5
10/100/1G LAN ---> RH94 1 2 0_0402_5%~D PCIE_LAN AE51 AY24 CLK_CPU_DMI
21 CLK_PCIE_LAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
+3VS RH95 2 1 10K_0402_5%~D
21 LANCLK_REQ# LANCLK_REQ# U8 PCIECLKRQ1# / GPIO18
@ CLKOUT_DP_N AN10 CLK_CPU_DPLL# CLK_CPU_DPLL# 5

2
CLKOUT_DP_P AN12 CLK_CPU_DPLL CLK_CPU_DPLL 5
RH96 2 1 0_0402_5%~D PCIE_MINI2# AD40 RH98 RH99
23 CLK_PCIE_WWAN# CLKOUT_PCIE2N
RH97 2 1 0_0402_5%~D PCIE_MINI2 AD42 2.2K_0402_5% 2.2K_0402_5%
23 CLK_PCIE_WWAN CLKOUT_PCIE2P
MiniWWAN (Mini Card 1)---> +3VS RH1002 1 10K_0402_5%~D BD17 CLKIN_DMI#
CLKIN_DMI_N

2
23 CLKREQ_WWAN# MINI2CLK_REQ# T4 BF17 CLKIN_DMI

1
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P
SMBCLK 6 1 PCH_SMBCLK 10,11,24
RH1012 1 0_0402_5%~D PCIE_MINI1# AA49 BB26 CLKIN_DMI2#
23 CLK_PCIE_WLAN# CLKOUT_PCIE3N CLKIN_GND1_N
RH1022 1 0_0402_5%~D PCIE_MINI1 AA51 AY26 CLKIN_DMI2 2N7002DW-T/R7_SOT363-6
23 CLK_PCIE_WLAN CLKOUT_PCIE3P CLKIN_GND1_P
MiniWLAN (Mini Card 2)---> +3V_PCH RH1032 1 10K_0402_5%~D QH3A
23 CLKREQ_WLAN# MINI1CLK_REQ# B8 RH105
PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N M24 CLKIN_DOT96# 1 @ 2

5
CLKIN_DOT_96P K24 CLKIN_DOT96 0_0402_5%
RH104 2 1 0_0402_5%~D PCIE_CD# Y48
22 CLK_PCIE_CD# CLKOUT_PCIE4N
RH106 2 1 0_0402_5%~D PCIE_CD Y50 SMBDATA 3 4
22 CLK_PCIE_CD CLKOUT_PCIE4P PCH_SMBDATA 10,11,24
1394/Card Reader ---> CLKIN_SATA_N AK8 CLKIN_SATA#
RH107 2 1 10K_0402_5%~D CDCLK_REQ# M19 AK6 CLKIN_SATA 2N7002DW-T/R7_SOT363-6
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P
QH3B
RH111
AB40 J49 CLK_PCH_14M 1 @ 2
CLKOUT_PCIE5N REFCLK14IN 0_0402_5%
AB42 CLKOUT_PCIE5P
B B
EXPRESS_CARD --->
+3V_PCH RH1101 2 10K_0402_5%~D K8 E51 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK 15

AF40 CLKOUT_PEG_B_N XTAL25_IN W49 XTAL25_IN

AF42 CLKOUT_PEG_B_P XTAL25_OUT W51 XTAL25_OUT
+3VS
+3V_PCH RH1121 2 10K_0402_5%~D PEG_B_CLKREQ# C4 PEG_B_CLKRQ# / GPIO56
AC49 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN
RH114 XCLK_RCOMP
24 CLK_PCIE_USB30# 2 1 0_0402_5%~D PCIE_USB30# AB44 CLKOUT_PCIE6N
RH113 90.9_0402_1%

2
USB 3.0 ---> RH115 2 1 0_0402_5%~D PCIE_USB30 AB46 QH4A
24 CLK_PCIE_USB30 CLKOUT_PCIE6P
+3V_PCH RH116 1 2 10K_0402_5%~D
24 USB30_CLKREQ# USB30_CLKREQ# J3 SML1CLK 6 1 PCH_SMLCLK 23,25,26,31,46
PCIECLKRQ6# / GPIO45
XTAL25_IN W44 H50 PCH_GPIO64 2N7002DW-T/R7_SOT363-6
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64
W46
2 1 XTAL25_OUT CLKOUT_PCIE7P
FLEX CLOCKS CLKOUTFLEX1 / GPIO65 D48 PCH_GPIO65

5
1M_0402_5% RH117 +3V_PCH RH1181 2 10K_0402_5%~D GPIO46 H4 QH4B
YH2 PCIECLKRQ7# / GPIO46
CLKOUTFLEX2 / GPIO66 G49 BT_DET# BT_DET# 23
25MHZ_18PF_1Y725000CE1A~D CLK_CPU_ITP# RH119 2 1 0_0402_5%~D CLK_BCLK_ITP# AR12 SML1DATA 3 4 PCH_SMLDATA 23,25,26,31,46
5 CLK_CPU_ITP# CLKOUT_ITPXDP_N
1 2 CLK_CPU_ITP RH120 2 1 0_0402_5%~D CLK_BCLK_ITP AR10 J51 CAM_DET#
5 CLK_CPU_ITP CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 CAM_DET# 20
2N7002DW-T/R7_SOT363-6

1 1 RH121 2 @ 1 0_0402_5%~D COUGAR-POINT-SFF_BGA1017~D

5 CLK_RES_ITP#
CH23 CH24 RH122 2 @ 1 0_0402_5%~D
5 CLK_RES_ITP
27P_0402_50V8J 27P_0402_50V8J
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/8) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 13 of 54
5 4 3 2 1
 5 4 3 2 1

UH1C

4 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BL21 BL13 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 4

DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1
4 DMI_CTX_PRX_N1 BL23 DMI1RXN FDI_RXN1 BJ15 FDI_CTX_PRX_N1 4
4 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BJ19 BD12 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 4
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3 UH1D
4 DMI_CTX_PRX_N3 BL17 DMI3RXN FDI_RXN3 BJ11 FDI_CTX_PRX_N3 4
AY15 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 4 ENBKL M44 AU40
FDI_RXN4 25 ENBKL L_BKLTEN SDVO_TVCLKINN
4 DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 BJ21 AY12 FDI_CTX_PRX_N5 FDI_CTX_PRX_N5 4 M42 AU42
DMI0RXP FDI_RXN5 20,25 VGA_LVDDEN L_VDD_EN SDVO_TVCLKINP
4 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BJ23 BJ9 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 4
DMI_CTX_PRX_P2 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N7
4 DMI_CTX_PRX_P2 BL19 DMI2RXP FDI_RXN7 BF10 FDI_CTX_PRX_N7 4 20 PCH_VGA_PWM L49 L_BKLTCTL SDVO_STALLN AR51
4 DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 BJ17 AR49
DMI3RXP FDI_CTX_PRX_P0 LVDS_DDC_CLK SDVO_STALLP
FDI_RXP0 BJ13 FDI_CTX_PRX_P0 4 20 LVDS_DDC_CLK L51 L_DDC_CLK
DMI_CRX_PTX_N0 BD22 BL15 FDI_CTX_PRX_P1 FDI_CTX_PRX_P1 4 20 LVDS_DDC_DATA LVDS_DDC_DATA K46 AT50
4 DMI_CRX_PTX_N0 DMI0TXN FDI_RXP1 L_DDC_DATA SDVO_INTN
DMI_CRX_PTX_N1 BB22 BF12 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 4 AT48
D 4 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 SDVO_INTP D
DMI_CRX_PTX_N2 BB19 BL11 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 4 CTRL_CLK R42
4 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 L_CTRL_CLK
DMI_CRX_PTX_N3 BB17 BB15 FDI_CTX_PRX_P4 CTRL_DATA M40

DMI
FDI
4 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4 FDI_CTX_PRX_P4 4 L_CTRL_DATA
BB12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 4
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6 LVDS_IBG
4 DMI_CRX_PTX_P0 BF22 DMI0TXP FDI_RXP6 BL9 FDI_CTX_PRX_P6 4 AH42 LVD_IBG SDVO_CTRLCLK W42
DMI_CRX_PTX_P1 AY22 BD10 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 4 PAD~D T203 AH40 R44
4 DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 LVD_VBG SDVO_CTRLDATA
DMI_CRX_PTX_P2 AY19
4 DMI_CRX_PTX_P2 DMI2TXP
DMI_CRX_PTX_P3 AY17 AG51
4 DMI_CRX_PTX_P3 DMI3TXP LVD_VREFH
BB10 FDI_INT AG49 AW51
FDI_INT FDI_INT 4 LVD_VREFL DDPB_AUXN
DDPB_AUXP AW49
+1.05VS BF19 BH12 FDI_FSYNC0 AY42 RH142 1 2 100K_0402_5%
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4 DDPB_HPD
LVDS_ACLK- AK44

LVDS
20 LVDS_ACLK- LVDSA_CLK#
1 2 DMI_IRCOMP BD19 BK8 FDI_FSYNC1 LVDS_ACLK+ AK46 AY48
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 4 20 LVDS_ACLK+ LVDSA_CLK DDPB_0N
RH124 49.9_0402_1% AY50
RBIAS_CPY FDI_LSYNC0 LVDS_A0- DDPB_0P
1 2 BK20 DMI2RBIAS FDI_LSYNC0 BK12 FDI_LSYNC0 4 20 LVDS_A0- AR46 LVDSA_DATA#0 HDMI DDPB_1N AY44

Digital Display Interface

RH125 750_0402_1%~D LVDS_A1- AN49 AY46
20 LVDS_A1- LVDSA_DATA#1 DDPB_1P
4mil width and place BH8 FDI_LSYNC1 LVDS_A2- AN44 BB44
FDI_LSYNC1 FDI_LSYNC1 4 20 LVDS_A2- LVDSA_DATA#2 DDPB_2N
AK40 BB46
within 500mil of the PCH LVDSA_DATA#3 DDPB_2P
BA49
LVDS_A0+ DDPB_3N
20 LVDS_A0+ AR44 LVDSA_DATA0 DDPB_3P BA51
F22 DSWODVREN LVDS_A1+ AN51
DSWVRMEN 20 LVDS_A1+ LVDSA_DATA1
@ LVDS_A2+ AN46

System Power Management

20 LVDS_A2+ LVDSA_DATA2
1 RH126 2 0_0402_5%~D PCH_RSMRST#_R AK42 LVDSA_DATA3 DDPC_CTRLCLK T50
25 SUSACK# 1 2 SUSACK#_R F15 SUSACK# DPWROK A21 PCH_DPWROK PCH_DPWROK 25 DDPC_CTRLDATA U44
RH127 0_0402_5%~D
AH46 LVDSB_CLK#
5 XDP_DBRESET# XDP_DBRESET# L1 D8 WAKE# 1 2 PCIE_WAKE# 21,23,24,25 AH44 AU51
SYS_RESET# WAKE# RH128 0_0402_5%~D LVDSB_CLK DDPC_AUXN
DDPC_AUXP AU49
@ AM50 BE46 RH149 1 2 100K_0402_5%
SYSTEM_PWROK M10 PM_CLKRUN# LVDSB_DATA#0 DDPC_HPD
1 2 SYS_PWROK CLKRUN# / GPIO32 T2 AL49 LVDSB_DATA#1
RH273 0_0402_5% AJ51 BC49
LVDSB_DATA#2 DDPC_0N
AH50 LVDSB_DATA#3 DDPC_0P BC51
PCH_PWROK 1 2 PM_PWROK_R M22 G6 SUS_STAT# T76 PAD~D BD48
C RH130 0_0402_5% PWROK SUS_STAT# / GPIO61 DDPC_1N C
AM48 LVDSB_DATA0 DDPC_1P BD50

1 2 G3 D3 SUSCLK 2 @ 1
AL51
AJ49
LVDSB_DATA1 mDP DDPC_2N BF46
BF45
25 PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK_R 25 LVDSB_DATA2 DDPC_2P
RH131 0_0402_5% RH132 0_0402_5% AH48 BE49
LVDSB_DATA3 DDPC_3N
DDPC_3P BE51
PM_DRAM_PWRGD B12 F6 PM_SLP_S5#
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 25,27
M46 CRT_BLUE DDPD_CTRLCLK M48
25 PCH_RSMRST# 1 2PCH_RSMRST#_R B20 RSMRST# SLP_S4# K10 PM_SLP_S4#
PM_SLP_S4# 25 R46 CRT_GREEN DDPD_CTRLDATA U42
RH133 0_0402_5%~D U46 CRT_RED
1 2 SUSWARN#_R C13 D4 PM_SLP_S3# AU46

CRT
25 SUSWARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 25,27 DDPD_AUXN
RH134 0_0402_5%~D R49 AU44
CRT_DDC_CLK DDPD_AUXP RH152
N49 CRT_DDC_DATA DDPD_HPD BK44 1 2 100K_0402_5%
5,25 PBTN_OUT# 1 2 PBTN_OUT#_R K19 PWRBTN# SLP_A# C7
RH135 0_0402_5%~D BG51
DDPD_0N
M50 CRT_HSYNC DDPD_0P BG49
25 AC_PRESENT 1 2 AC_PRESENT_R H19 ACPRESENT / GPIO31 SLP_SUS# A15 PM_SLP_SUS#
PM_SLP_SUS# 25 N51 CRT_VSYNC DMC DDPD_1N BF42
RH137 0_0402_5%~D BD42
DDPD_1P
DDPD_2N BJ47
GPIO72 H10 BB8 H_PM_SYNC CRT_IREF R51 BL47
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5 DAC_IREF DDPD_2P
T48 CRT_IRTN DDPD_3N BL45
Can be left NC when IAMT is DDPD_3P BJ45

1
SUSWARN# 1 2 SUSACK#_R RI# F12 A7 PCH_GPIO29 not support on the platfrom
RH139 0_0402_5%~D RI# SLP_LAN# / GPIO29 COUGAR-POINT-SFF_BGA1017~D
If not using integrated
LAN,signal may be left as NC. RH140
COUGAR-POINT-SFF_BGA1017~D 1K_0402_0.5%~D
+3V_PCH Check EC for S3 S4 LED

2
PCH_GPIO29 RH1481 @ 2 10K_0402_5%
B GPIO72 RH1431 2 10K_0402_5% +3VS B
+RTCVCC
RI# RH1451 2 10K_0402_5% RH264 1 2 2.2K_0402_5% LVDS_DDC_CLK

WAKE# RH1461 2 1K_0402_5% DSWODVREN RH147 2 1 330K_0402_5% RH265 1 2 2.2K_0402_5% LVDS_DDC_DATA

AC_PRESENT RH1501 @ 2 10K_0402_5% DSWODVREN RH151 2 @ 1 330K_0402_5% RH248 1 2 PM_CLKRUN#

@ 8.2K_0402_5%
SUSWARN# RH1541 2 10K_0402_5% 1 2 CTRL_CLK
DSWODVREN - On Die DSW VR Enable RH155 2.2K_0402_5%~D

PCH_RSMRST# RH1591 2 10K_0402_5%

* H烉Enable
L烉Disable
1
RH157
2
2.2K_0402_5%~D
CTRL_DATA

SYSTEM_PWROK RH2721 2 10K_0402_5% RH167 1 2 PM_CLKRUN#

8.2K_0402_5%
1 2 LVDS_IBG
RH144 2.37K_0402_1%~D
1 2 VGA_LVDDEN
RH158 100K_0402_5%~D
1 2 ENBKL
RH123 100K_0402_5%
+3VS 2 1 SUSCLK
10P_0402_50V8J @ C1082

1
CH96
0.1U_0402_16V4Z
2
5

UH7
VCC

A PCH_PWROK 1 A
5,25 PCH_PWROK IN1
4 SYSTEM_PWROK
OUT SYSTEM_PWROK 5
2
GND

5,25,54 VGATE IN2

MC74VHC1G08DFT2G_SC70-5
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/8) DMI,FDI,PM,GFX,DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 14 of 54
5 4 3 2 1

Compal Electronics, Inc

 5 4 3 2 1

UH1E
RSVD1 BE3
RSVD2 BE1
BH24 TP1 RSVD3 AU8
BK24 TP2 RSVD4 BJ7
BH20 TP3
BK16 TP4 RSVD5 BA3
BH16 TP5 RSVD6 BH3
AN42 TP6
AN40 TP7 RSVD7 AU6
AR40 TP8 RSVD8 AW3
AR42 TP9 RSVD9 AW1
D20 TP10 RSVD10 AY6 DMI Termination Voltage
M30 TP11 RSVD11 AY2
E3 TP12 RSVD12 AY4 Set to Vcc when HIGH
D AM4 BC3 NV_CLE D
TP13 RSVD13
AT4 BC1 Set to Vss when LOW

RSVD
TP14 RSVD14
AT2 TP15 RSVD15 BG1
AD10 TP16 RSVD16 BG3
B24 TP17 RSVD17 BE6
D24 TP18 RSVD18 BH4
AD44 TP19 RSVD19 BF7
AD46 BJ4 +1.8VS

RSVD
TP20 RSVD20
RSVD21 BJ5
RSVD22 BK6 Weak internal

1
BJ48 TP21 PU,Do not pull low
BL7 AY8 NV_ALE RH161
TP22 RSVD23 NV_CLE
W40 TP23 DF_TVS BC7 2.2K_0402_5%
K30 TP24
BH49 BL5 1K_0402_5%

2
TP41 RSVD24 NV_CLE
BB42 TP42 2 1RH162 H_SNB_IVB# 5
RSVD25 BB6

BJ25 TP25 RSVD26 BD2

BJ27 TP26 RSVD27 BD4
BJ31 TP27
BJ29 TP28 RSVD28 BA1
BL25 TP29 RSVD29 BF6 CLOSE TO THE BRANCHING POINT
BL27 TP30
BL31 TP31
BL29 TP32 USBP0N F24
BF26 TP33 USBP0P H24
BB28 C25 USB20_N1
TP34 USBP1N USB20_N1 24
BF28 A25 USB20_P1 USB/Left
TP35 USBP1P USB20_P1 24
BF30 C27 USB20_N2 Intel Anti-Theft Techonlogy
TP36 USBP2N USB20_N2 23
BD26 A27 USB20_P2 Bluetooth
TP37 USBP2P USB20_P2 23
AY28 H28 USB20_N3 High=Endabled
C TP38 USBP3N USB20_N3 20 C
BD28 F28 USB20_P3 Camera NV_ALE
TP39 USBP3P USB20_P3 20
BD30 M26 USB20_N4 Low=Disable(floating)
TP40 USBP4N
USBP4P K26 USB20_P4
USB20_N4
USB20_P4
23
23 Mini Card(WLAN) *
D28 USB20_N5
USBP5N USB20_N5 23 +1.8VS
B28 USB20_P5 Mini Card(WWAN)
USBP5P USB20_P5 23
H26 USB20_N6
USBP6N USB20_N6 27
F26 USB20_P6 ELC LED NV_ALE @RH160
@ RH1601 2 1K_0402_5%
USBP6P USB20_P6 27
PCI_PIRQA# D49 D32
PCI_PIRQB# PIRQA# USBP7N
C48 B32

PCI
PCI_PIRQC# PIRQB# USBP7P
C47 PIRQC# USBP8N M28
PCI_PIRQD# C45 K28
PIRQD# USBP8P
USBP9N C29
DGPU_HOLD_RST# G46 A29

USB
DGPU_SELECT# REQ1# / GPIO50 USBP9P
K44 REQ2# / GPIO52 USBP10N C31
DGPU_PWR_EN F46 A31
30,33,43,53 DGPU_PWR_EN REQ3# / GPIO54 USBP10P
USBP11N H33
23 WWAN_RADIO_OFF# WWAN_RADIO_OFF# F42 F33
WLAN_BT_RADIO_OFF# GNT1# / GPIO51 USBP11P +3V_PCH
23 WLAN_BT_RADIO_OFF# H42 GNT2# / GPIO53 USBP12N H30
WL_OFF# D44 F30
23 WL_OFF# GNT3# / GPIO55 USBP12P
M33 RPH1
USBP13N USB_OC0#
USBP13P K33 4 5
FFS_INT1 A47 USB_OC1# 3 6
24 FFS_INT1 PIRQE# / GPIO2
GPIO3 C41 Within 500 mils USB_OC2# 2 7
DP_CBL_DET PIRQF# / GPIO3 USBRBIAS USB_OC5#
F45 PIRQG# / GPIO4 USBRBIAS# C33 1 2 1 8
CR_CPPEN F40 RH163 22.6_0402_1%
22 CR_CPPEN PIRQH# / GPIO5 10K_1206_8P4R_5%~D
A33 RPH2
PAD~D T123 @ USBRBIAS 1.5VDDR_VID0
H2 PME# 4 5
1.5VDDR_VID1 3 6
PCH_PLTRST# F7 C17 USB_OC0# USB30_SMI# 2 7
PLTRST# OC0# / GPIO59 USB_OC0# 24
A17 USB_OC1# USB_OC6# 1 8
OC1# / GPIO40 1.5VDDR_VID0
OC2# / GPIO41 A13 1.5VDDR_VID0 48
B CLK_PCI_LPBACK RH164 2 1 22_0402_5% CLK_PCI0 G51 D16 1.5VDDR_VID1 10K_1206_8P4R_5%~D B
13 CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42 1.5VDDR_VID1 48
CLK_PCI_LPC RH165 1 2 22_0402_5% CLK_PCI1 E49 A11 USB_OC2#
25 CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43 (For USB Port 9)
PAD~D T170 @ CLK_PCI2 H48 B16 USB_OC5#
PAD~D T166 @ CLK_PCI3 CLKOUT_PCI2 OC5# / GPIO9 USB_OC6#
J43 CLKOUT_PCI3 OC6# / GPIO10 C23
PAD~D T168 @ CLK_PCI4 G45 H15 USB3_SMI# USB30_SMI# 24
CLKOUT_PCI4 OC7# / GPIO14
2 1 CLK_PCI1
10P_0402_50V8J @ C1078 COUGAR-POINT-SFF_BGA1017~D
1 2
+3VS @RH254
@ RH254 0_0402_5%
+3VS 1 @ 2
RPH3 RH168 0_0402_5%
WL_OFF# 1 8
2

PCI_PIRQB# 2 7 @ +3VS +3VS

PCI_PIRQD# 3 6 RH169
PCI_PIRQC# 4 5 10K_0402_5%

5
UH6
5

8.2K_0804_8P4R_5% UH5 2 1 2 DGPU_PWROK

P
DGPU_PWROK 16,30,53
1

PCH_PLTRST# B
1 2 1 RH170 4 @RH267
@ RH267 0_0402_5%
P

IN1 30 PLTRST_VGA# Y
RPH4 4 100_0402_5% 1 DGPU_HOLD_RST# 1 2 PCH_PLTRST#
5,21,22,23,24,25 PLT_RST# O A

G
1
WWAN_RADIO_OFF# 1 8 2 RH266 0_0402_5%
IN2
G

DGPU_SELECT# 2 7 RH172 NC7SZ08P5X_NL_SC70-5

3
1

DGPU_PWR_EN 3 6 SN74AHC1G08DCKR_SC70-5 100K_0402_5%

3

FFS_INT1 4 5
RH171 10K_0402_5%

2
8.2K_0804_8P4R_5% 100K_0402_5% RH192
@ 1/24 SPECTER RESERVE
2

RPH5
CR_CPPEN 1 8
PCI_PIRQA# 2 7
DP_CBL_DET 3 6
GPIO3 4 5
A 8.2K_0804_8P4R_5% A
RH184
WLAN_BT_RADIO_OFF# 1 2 8.2K_0402_5%
RH173
DGPU_HOLD_RST# @1 2 8.2K_0402_5%

RH185
DGPU_HOLD_RST# 1 2 8.2K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/8) PCI, USB, NVRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Tuesday, January 25, 2011 Sheet 15 of 54
5 4 3 2 1
 5 4 3 2 1

UH1F

GPIO0 W1 K42 GPIO68

BMBUSY# / GPIO0 TACH4 / GPIO68
DGPU_EDIDSEL# B40 A43 GPIO69 @T126
@ T126 PAD~D
TACH1 / GPIO1 TACH5 / GPIO69
GPIO6 C43 D40 LVDS_CAB_DET# +3VS
TACH2 / GPIO6 TACH6 / GPIO70
25 EC_SCI# EC_SCI# A45 A41
TACH3 / GPIO7 TACH7 / GPIO71

2
D D

25 EC_SMI# EC_SMI# H17 RH174

GPIO8
10K_0402_5%
23 BT_RADIO_OFF# BT_RADIO_OFF# C5 LAN_PHY_PWR_CTRL / GPIO12

1
28 PCH_HDMI_HPD# PCH_HDMI_HPD# K6 U3
GPIO15 A20GATE GATEA20 25
AU12 PCH_PECI_R 1 @ 2

CPU/MISC
PECI H_PECI 5,25
PCH_GPIO16 AA3 0_0402_5% RH175
SATA4GP / GPIO16 KB_RST#
RCIN# U6 KB_RST# 25

GPIO
GPIO28 DGPU_PWROK B44 AU10
15,30,53 DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD 5
On-Die PLL Voltage Regulator
This signal has a weak internal pull up PCH_GPIO22 W3 BC9 H_THERMTRIP#_C 1 2 H_THERMTRIP# H_THERMTRIP# 5
SCLOCK / GPIO22 THRMTRIP# 390_0402_5% RH176
H烉On-Die voltage regulator enable K15 R6 INIT3_3V#
* L烉On-Die PLL Voltage Regulator disable GPIO24 / MEM_LED INIT3_3V#
PCH_GPIO27 C15
PCH_GPIO28 GPIO27
1 2

1
PCH_GPIO28 G1 @
@RH177
@ RH177 1K_0402_5%~D GPIO28 RH178
TS_VSS1 AK10
BT_ON# R3 10K_0402_5%
23 BT_ON# STP_PCI# / GPIO34
TS_VSS2 AH12
W12

2
GPIO35
TS_VSS3 AK12 INIT3_3V
GPIO36 W6 SATA2GP / GPIO36
TS_VSS4 AH10 This signal has weak internal
PCH_GPIO37 M6 SATA3GP / GPIO37 PU, can't pull low
NC_1 U40
PCH_GPIO37 PCH_GPIO38 N3 SLOAD / GPIO38
FDI TERMINATION VOLTAGE OVERRIDE
PCH_GPIO39 U10
C SDATAOUT0 / GPIO39 C
LOW - Tx, Rx terminated
* to same voltage 24,26 FFS_INT2
FFS_INT2 U1 SDATAOUT1 / GPIO48 VSS_NCTF_15 BL48
(DC Coupling Mode) GPIO49 AA1 SATA5GP / GPIO49 VSS_NCTF_16 BL49
+3VS HDD_DETECT# K17 BL51
26 HDD_DETECT# GPIO57 VSS_NCTF_17

VSS_NCTF_18 C3
RH181 2 @ 1 1K_0402_5% PCH_GPIO37
A4 VSS_NCTF_1 VSS_NCTF_19 C49

RH182 2 1 PCH_GPIO37 A48 C51

VSS_NCTF_2 VSS_NCTF_20 +3V_PCH

100K_0402_5% A49 VSS_NCTF_3 VSS_NCTF_21 D1

NCTF
A5 VSS_NCTF_4 VSS_NCTF_22 D51
BT_RADIO_OFF# 1 @ 2 10K_0402_5%
A51 E1 RH191
VSS_NCTF_5 VSS_NCTF_23 GPIO68
GPIO27 1 2 10K_0402_5%
BH1 RH187
VSS_NCTF_6 HDD_DETECT# <BOM 2Structure>
10K_0402_5%
PCH_GPIO27 (Have internal Pull-High) 1
BH51 RH188
*High: VCCVRM VR Enable VSS_NCTF_7
RH189
Low: VCCVRM VR Disable BJ1 VSS_NCTF_8 PCH_HDMI_HPD# 1 2 1K_0402_5%
1 2 PCH_GPIO27 BJ3
@RH186
@ RH186 10K_0402_5% VSS_NCTF_9 EC_SMI# <BOM 2Structure>
10K_0402_5%
1
BJ49 RH190
VSS_NCTF_10
BJ51 VSS_NCTF_11
BL1 VSS_NCTF_12
B B
BL3 +3VS
VSS_NCTF_13
BL4 VSS_NCTF_14 PCH_GPIO16 1 RH183 2 10K_0402_5%

COUGAR-POINT-SFF_BGA1017~D DGPU_EDIDSEL# 1 RH180 2 10K_0402_5%

GPIO6 2 1 8.2K_0402_5%
RH252
GPIO0 1 2 10K_0402_5%
RH198
GPIO36 1 2 200K_0402_5%
RH193
BT_ON# 1 2 10K_0402_5%
RH195
KB_RST# 1 2 10K_0402_5%
RH196
PCH_GPIO28 needs to be connected to XDP_FN8 remove PCH_GPIO48 pull high
PCH_GPIO35 needs to be connected to XDP_FN9 PCH_GPIO22 1 2 10K_0402_5%
PCH_GPIO15 needs to be connected to XDP_FN16 RH197

PCH_GPIO38 1 <BOM 2Structure>

10K_0402_5%
Please refer to Huron River Debug Board DG 0.5 RH262
PCH_GPIO39 1 <BOM 2Structure>
10K_0402_5%
RH263
add RH185,RH229,RH251 FFS_INT2 1 2 10K_0402_5%
RH229
5/25 @
GPIO49 1 <BOM 2Structure>
10K_0402_5%
RH258
A A
LVDS_CAB_DET# 1 2 10K_0402_5%
RH251
DGPU_PWROK 1 2 10K_0402_5%
RH253
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/8) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 16 of 54
5 4 3 2 1
 5 4 3 2 1

+1.05VS PCH Power Rail Table

S0 Iccmax
J10
UH1G POWER +3VS Voltage Rail Voltage Current (A)
1300mA
2 1 +1.05VS_VCCCORE AB21 LH1
VCCCORE[1] 1mA

0.01U_0402_16V7K

0.1U_0402_10V7K
AB23 U51 +VCCADAC 2 1 V_PROC_IO 1.05 0.001
VCCCORE[2] VCCADAC

10U_0805_4VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
AC21 BLM18PG181SN1_0603~D
PAD-OPEN 4x4m 1 1 1 1 VCCCORE[3] 1 1 1
AC23

CRT
@ VCCCORE[4]

CH27

CH28

CH25

CH26

CH29

CH30
AE21 V50 CH31 V5REF 5 0.001
VCCCORE[5] VSSADAC 10U_0805_4VAM~D
AE23 VCCCORE[6]
D 2 2 2 2 2 2 2 D
AF21 VCCCORE[7]
AF23 @ +3VS V5REF_Sus 5 0.001
VCCCORE[8]

VCC CORE
AG21 VCCCORE[9] 1mA
AG23 VCCCORE[10] VCCALVDS[1] AF33 +VCCA_LVDS RH199 1 2 0.022_0805_1%
AG25 VCCCORE[11] VCCALVDS[2] AG33 Vcc3_3 3.3 0.266
placed internal AG27 VCCCORE[12]
AJ21 VCCCORE[13]
AJ23 VCCCORE[14] VSSALVDS[1] AC33 VccADAC 3.3 0.001
AJ25 AE33 +1.8VS
VCCCORE[15] VSSALVDS[2]
AJ27 VCCCORE[16]
AJ29 Near AP43 LH2 VccADPLLA 1.05 0.08

LVDS
VCCCORE[17] +VCCTX_LVDS
AJ31 VCCCORE[18] 60mA VCCTX_LVDS[1] AF37 2 1

0.01U_0402_16V7K

0.01U_0402_16V7K
AK29 1 0.1UH_MLF1608DR10KT_10%_1608
VCCCORE[19] CH32 1
AK31 VCCCORE[20] VCCTX_LVDS[2] AG37 1 CH34 0.1uH inductor, 200mA VccADPLLB 1.05 0.08
+1.05VS AK33 CH33
VCCCORE[21]
AM33 VCCCORE[22] VCCTX_LVDS[3] AG39
2

22U_0805_6.3V6M
AM35 VCCCORE[23]
VccCore 1.05 1.3
2 2
VCCTX_LVDS[4] AJ37

+1.05VS RH200 2 1 0_0603_5%~D +1.05VS_VCCDPLLEXP AM21 VCCIO[28]

VccDMI 1.05 0.042
placed internal
@ LH3
2 @ 1+VCCAPLLEXP_R 1 2 +VCCAPLLEXP AP19 VCCAPLLEXP
RH202 VccIO 1.05 2.925
RH201 0_0603_5%~D 1UH_LB2012T1R0M_20%~D T39 +3VS_VCC3_3_6 1 2

HVCMOS
VCC3_3[6] +3VS

10U_0805_4VAM~D
1 0_0805_5%
Place CH35 Near AP19 pin AR15 VCCIO[15] 1 VccASW 1.05 1.01
CH35
@
AT13 U37 CH36
2 @ VCCIO[16] VCC3_3[7]
0.1U_0402_10V7K~D VccSPI 3.3 0.02
2925mA 2
+1.05VS AR23 VCCIO[17]
VccDSW 3.3 0.003
C AR25 C
RH203 VCCIO[18]
AU21 +VCCAFDI_VRM
+1.05VS_VCC_EXP VCCVRM[3] +VCCP_VCCDMI
1 2 AR27 VCCIO[19] VCCVRM[4] AW21 VccpNAND 1.8 0.19
+1.05VS
RH204
10U_0805_4VAM~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0_0805_5% 1 1 1 1 1 AR29 VCCIO[20]

20mA VCCDMI[1] AM23 +VCCP_VCCDMI 1 2 VccRTC 3.3 6 uA
@
CH37

CH38

CH39

CH40

CH41

AU23 1

DMI
VCCIO[21] 0_0805_5%

VCCIO
2 2 2 2 2 LH9 CH42 VccSus3_3 3.3 0.119
AU25 VCCIO[22] +1.05VS
+3VS @
2 1U_0402_6.3V6K~D
AU27 VCCIO[23] VCCCLKDMI AP39 +1.05VS_VCC_DMI_CCI 1 2
1 10UH_LBR2012T100M_20%~D VccSusHDA 3.3 / 1.5 0.01
AU29 VCCIO[24]
placed internal placed internal CH43
1U_0402_6.3V6K~D placed internal VccVRM 1.8 / 1.5 0.16
1

2
AU35 VCCIO[25] 190mA
RH206 AJ13
VccDFTERM[1]
0_0805_5% AW34 VCCIO[26]
VccCLKDMI 1.05 0.02
+VCCPNAND

NAND / SPI
@
AJ15 1 2 +1.8VS
2

+3VS_VCCA3GBG VccDFTERM[2] RH207 0_0805_5%~D

BK28 VCC3_3[3]
VccSSC 1.05 0.095

0.1U_0402_10V7K~D
1
CH44 AK15 1
+1.05VS VccDFTERM[3]
VccDIFFCLKN 1.05 0.055

CH45
0.1U_0402_10V7K +VCCAFDI_VRM AU19
2 VCCVRM[5]
AW18 VCCVRM[6] VccDFTERM[4] AL13
2 VccALVDS 3.3 0.001
Place CH53 Near AP13,AP15 pin 20mA
AP13 VCCAFDPLL[1]
2 @ 1 +1.05VS_VCCAPLL_FDI AP15 VccTX_LVDS 1.8 0.06
VCCAFDPLL[2]
1U_0402_6.3V6K~D

RH208 0_0603_5%~D 1 RH209 RH210

FDI

+1.05VS 1 2+1.05VS_VCCDPLL_FDI AK21 VCCIO[27] VCCSPI Y19 +3V_VCCPSPI 1 2 +3V_PCH

CH46

B 0_0805_5% 0_0805_5% B

2 @ 1
+VCCP_VCCDMI AU15 VCCDMI[2]
@ AW16 @
CH47
VCCDMI[3] 1U_0402_6.3V6K~D
2
COUGAR-POINT-SFF_BGA1017~D placed internal

VCCVRM = 160mA detal waiting for newest spec

+3VALW +1.5VS +VCCAFDI_VRM

RH211
2 1 +VCCAFDI_VRM
1
0_0603_5%~D
C432
1U_0402_6.3V6K~D U623
2
1 VIN VOUT 5 2 1
4 RH212
SUSP# NC 0_0603_5%~D
9,25,43,48,49,50,51 SUSP# 3 EN GND 2
@
RT9013-15GB_SOT23-5

5/18 modified
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 17 of 54
5 4 3 2 1
 5 4 3 2 1

+1.05VS
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
2 @ 1 +VCCACLK
+3V_PCH RH213 0_0603_5%
UH1J POWER QH7
1 2
+3V_DSW RH214 0_0603_5%~D +1.05VS_VCCUSBCORE +5VALW RH215 AO3413_SOT23 +5V_PCH
1 AC51 VCCACLK VCCIO[29] R23 2 1 +1.05VS
0_0603_5%~D 0_0603_5%~D

D
CH48 R25 1 RH220 2 1 3 1
0.1U_0402_10V7K~D VCCIO[30]

0.1U_0402_10V7K~D
1 2 +VCCPDSW R12
2 VCCDSW3_3 3mA

20K_0402_5%~D
D RH221 @ 0_0603_5%~D U23 CH50 D
VCCIO[31]

1
1U_0402_6.3V6K~D

G
1

2
2

R22
+PCH_VCCDSW R10 U25
+1.05VS DCPSUSBYP VCCIO[32]

C8
@ LH4
@LH4 1 placed internal
@ RH216 10UH_LBR2012T100M_20%~D
43 PCH_PWR_EN# 2
1 2 +VCCAPLL_CPY 1 2 @CH51
@ CH51 +3VS_VCC_CLKF33 V37

2
0.1U_0402_10V7K~D VCC3_3[5]
V39 VCC3_3[6]
2

10U_0805_10V4Z~D
0_0805_5%~D @ 1 R27 +3V_VCCPUSB 2 1 +3V_PCH
119mA VCCSUS3_3[7]

0.1U_0402_10V7K~D
RH217 0_0603_5%~D
+1.05VS

CH49
+VCCAPLL_CPY_PCH AW31 R29 1 +3V_VCCAUBG 2 1 +3V_PCH
VCCAPLLDMI2 VCCSUS3_3[8] +5V_PCH +3V_PCH

0.1U_0402_10V7K~D
RH218 0_0603_5%~D
2

CH52
1 2 +VCCDPLL_CPY AP27 U27 1

USB
RH219 0_0603_5%~D VCCIO[14] VCCSUS3_3[9]

2
2

CH53
U29 +VCCA_USBSUS
VCCSUS3_3[10]

1U_0402_6.3V6K~D
+1.05VM_VCCSUS V13 RH222 DH2
+VCCSUS1 DCPSUS[1] 2 100_0402_5%~D
QH6 1 VCCSUS3_3[6] N27 1 RB751S40T1_SOD523-2~D
+3VALW +3V_DSW CH54 @ AR33
1 DCPSUS[2]
AO3413_SOT23

CH55
@ AU33

1
DCPSUS[3]

@
1U_0402_6.3V6K~D CH76 N18 +1.05VS_VCCAUPLL 2 1 +1.05VS +PCH_V5REF_SUS
2 VCCIO[34] 2
S

3 1 1U_0402_6.3V6K~D 1010mA RH223 0_0603_5%~D 1

2
AB27 VCCASW[1]
M37 +PCH_V5REF_SUS CH56
+1.05VM_VCCASW
1mA V5REF_SUS 0.1U_0603_25V7K
G

AB29 2 1 +3V_PCH
2

VCCASW[2] 2

Clock and Miscellaneous

22U_0805_6.3V6M~D

22U_0805_6.3V6M~D

0.1U_0402_10V7K~D
1 1 RH224 0_0603_5%~D
AB31 AU31 +VCCA_USBSUS 1
VCCASW[3] DCPSUS[4]

CH57

CH58

CH59
AC27 AM27 +3V_VCCPSUS_1
2 2 VCCASW[4] VCCSUS3_3[1]
2
25 PCH_VREG_EN# AC29 VCCASW[5]
+1.05VS +5VS +3VS
AC31 VCCASW[6]
N36 +PCH_V5REF_RUN
1mA V5REF

2
C 1 2 AE27 RH226 C
VCCASW[7]
1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D
RH225 0_0805_5%~D 1 1 1 0_0603_5%~D RH227 DH3
AE29 R33 +3V_VCCPSUS 2 1 100_0402_5%~D RB751S40T1_SOD523-2~D

PCI/GPIO/LPC
VCCASW[8] VCCSUS3_3[2] +3V_PCH
CH60

CH61

CH62
1
AE31 R35

1
2 2 2 VCCASW[9] VCCSUS3_3[3] CH63 +PCH_V5REF_RUN
1U_0402_6.3V +3VS
U21 VCCASW[10] VCCSUS3_3[4] U33 1
2
+3VS +3VS_VCCPCORE CH64
V21 VCCASW[11] VCCSUS3_3[5] U35 2 1
RH228 0_0805_5%~D 1U_0603_10V6K~D
5/18 delete RH229 placed internal V23
1 2
VCCASW[12] CH65
VCC3_3[1] AB19
LH5 V25 0.1U_0402_10V7K~D
10UH_LBR2012T100M_20%~D VCCASW[13] 2 +3VS
VCC3_3[8] AC19
1 2+3VS_VCC_CLKF33_R 1 2 +3VS_VCC_CLKF33 Y21 VCCASW[14]
10U_0805_10V4Z~D

1U_0402_6.3V6K~D

0_0805_5%~D RH230 1 1 R40 +3VS_VCCPPCI 2 1

VCC3_3[4] RH231 0_0603_5%
Y23 VCCASW[15] 1
CH66

CH67

Y25 CH68
2 2 VCCASW[16] +3VS 0.1U_0402_10V7K~D
RH232 2
Y27 VCCASW[17]
AF6 +VCC3_3_2 2 1
VCC3_3[2] +1.05VS_SATA3
Y29 VCCASW[18] 1
placed internal 0_0603_5%~D RH233
Y31 AA13 CH69 2 1 +1.05VS
VCCASW[19] VCCIO[5] 0.1U_0402_10V7K~D
2 1
+1.05VS 0_0805_5%~D
+VCCRTCEXT R15 AG13 CH70
@ +1.05VM_VCCSUS DCPRTC[1] VCCIO[12] 1U_0402_6.3V6K~D
2 1 1 U15 DCPRTC[2]
RH234 0_0603_5% +1.05VS_SATA3 2
VCCIO[13] AG15
CH71
0.1U_0402_10V7K~D +VCCAFDI_VRM AC39 placed internal
B +1.05VS 2 VCCVRM[4] @LH6
@ LH6 @ B
VCCIO[6] AF15
10UH_LBR2012T100M_20%~D RH236

SATA
2 1 +VCCDIFFCLK 80mA AM2 +VCCSATAPLL 1 2 +VCCSATAPLL_R 2 1
VCCAPLLSATA +1.05VS
RH235 0_0603_5% +1.05VS_VCCA_A_DPL BF40 +VCCAFDI_VRM
VCCADPLLA 80mA 0_0805_5%~D
1 1
CH72 +1.05VS_VCCA_B_DPL BD40 AE19 +VCCAFDI_VRM @ CH73
@CH73
VCCADPLLB VCCVRM[1] 10U_0805_10V4Z~D
VCCVRM[2] AF17
+1.05VS placed internal 1U_0402_6.3V6K~D +1.05VS_VCCDIFFCLKN +1.05VS_VCC_SATA Place CH80 Near AK1 pin
2 55mA RH238 2
AJ17 VCCIO[7]
2 1 +1.05VS_VCCDIFFCLKN AC37 AB15 +1.05VS_VCC_SATA 2 1 +1.05VS
VCCDIFFCLKN[1] VCCIO[2]

1U_0402_6.3V6K~D
RH237 0_0603_5% 1 AE37 VCCDIFFCLKN[2] 0_0805_5%~D
AE39 VCCDIFFCLKN[3] VCCIO[3] AC13 1
CH74
95mA

CH75
1U_0402_6.3V6K~D AC15
+1.05VS placed internal 2 +1.05VS_SSCVCC VCCIO[4]
AC35 VCCSSC 2
2 1 placed internal +1.05VS
RH239 0_0603_5% 1 1 +VCCSST U17
CH78 DCPSST +VCCME_22 RH240
VCCASW[22] U19 2 1 0_0603_5%~D
CH77 0.1U_0402_10V7K~D
FUSE

1U_0402_6.3V6K~D
+1.05VS 2 2 +VCCME_23 RH241
VCCASW[23] R19 2 1 0_0603_5%~D
CPU
0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1 2 +V_CPU_IO AM17
RH242 0_0603_5%~D V_PROC_IO 1mA +VCCME_21 RH243
1 1 1 VCCASW[21] V19 2 1 0_0603_5%~D
+RTCVCC
CH80

CH81

CH79
4.7U_0603_6.3V6K~D
2 2 2
RTC

N16 V31 +VCCSUSHDA 2 1

HDA

VCCRTC 10mA VCCSUSHDA +3V_PCH

0.1U_0402_10V7K~D

0.1U_0402_10V7K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

RH244 0_0603_5%~D
1U_0402_6.3V6K~D

1 1 1 1 1 1 2 +3V_PCH

150_0402_1%
LH7 COUGAR-POINT-SFF_BGA1017~D @RH245
@ RH245 180_0402_1% If it support 3.3V audio signals

1
CH82

CH83

CH84

CH92

CH85

A 10UH_LBR2012T100M_20%~D POP:RH228 A
1 2 +1.05VS_VCCA_A_DPL Depop RH233/RH234
+1.05VS 2 2 2 2 2
RH246
@
If it support 1.5V audio signals
220U_B2_2.5VM_R35M~D

1 2 +VCCA_DPLL_L 1 2 +1.05VS_VCCA_B_DPL POP:RH233/RH234

2
220U_B2_2.5VM_R35M~D

RH247 LH8 Depop R228

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

10UH_LBR2012T100M_20%~D 1 1 placed internal

0_0805_5%~D
+
1
+
1 Security Classification Compal Secret Data Compal Electronics, Inc.
CH86

CH88
CH87

CH89

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/8) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
placed internal
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 18 of 54
5 4 3 2 1
 5 4 3 2 1

UH1I

BA25 VSS[159] VSS[264] J18

BA27 VSS[160] VSS[265] J21
BA29 VSS[161] VSS[266] J23
BA31 VSS[162] VSS[267] J25
BA34 VSS[163] VSS[268] J27
BA36 VSS[164] VSS[269] J29
BA39 VSS[165] VSS[270] J31
BA41 VSS[166] VSS[271] J34
D UH1H BA43 J36 D
VSS[167] VSS[272]
G7 VSS[0] BA45 VSS[168] VSS[273] L25
BA7 VSS[169] VSS[274] J41
AA11 VSS[1] VSS[80] AL41 BA9 VSS[170] VSS[275] J45
AA39 VSS[2] VSS[81] AL43 BB4 VSS[171] VSS[276] J7
AA41 VSS[3] VSS[82] AL45 F2 VSS[172] VSS[277] J9
AA43 VSS[4] VSS[83] AL7 BB48 VSS[173] VSS[278] K2
AA45 VSS[5] VSS[84] AL9 BB50 VSS[174] VSS[279] K4
AA7 VSS[6] VSS[85] AM15 BC11 VSS[175] VSS[280] K48
AA9 VSS[7] VSS[86] AM19 BC13 VSS[176] VSS[281] K50
AB17 VSS[8] VSS[87] AM25 BC16 VSS[177] VSS[282] L11
AB2 VSS[9] VSS[88] AM29 BC18 VSS[178] VSS[283] L13
AB25 VSS[10] VSS[89] AM31 BC21 VSS[179] VSS[284] L16
AB33 VSS[11] VSS[90] AM37 BC23 VSS[180] VSS[285] L18
AB35 VSS[12] VSS[91] AP11 BC25 VSS[181] VSS[286] L29
AB37 VSS[13] VSS[92] AP17 BC27 VSS[182] VSS[287] L21
AB4 VSS[14] VSS[93] AP2 BC29 VSS[183] VSS[288] L23
AB48 VSS[15] VSS[94] AP21 BC31 VSS[184] VSS[289] L27
AB50 VSS[16] VSS[95] AP23 BC34 VSS[185] VSS[290] L9
AC11 VSS[17] VSS[96] AP25 BC36 VSS[186] VSS[291] L31
AC17 VSS[18] VSS[97] AP29 BC39 VSS[187] VSS[292] L34
AC25 VSS[19] VSS[98] AP31 BC41 VSS[188] VSS[293] L36
AC41 VSS[20] VSS[99] AP33 BC43 VSS[189] VSS[294] L39
AC43 VSS[21] VSS[100] AP35 BC45 VSS[190] VSS[295] L41
AC45 VSS[22] VSS[101] AP37 BE11 VSS[191] VSS[296] L43
AC7 VSS[23] VSS[102] AP4 BE13 VSS[192] VSS[297] L45
AE13 VSS[24] VSS[103] AP41 BE16 VSS[193] VSS[298] L7
AE15 VSS[25] VSS[104] AP43 BE21 VSS[194] VSS[299] N13
AE17 VSS[26] VSS[105] AP45 BE23 VSS[195] VSS[300] N21
AE25 VSS[27] VSS[106] AP48 BE27 VSS[196] VSS[301] R37
AE35 VSS[28] VSS[107] AP50 BE29 VSS[197] VSS[302] N23
AE41 VSS[29] VSS[108] AP7 BE31 VSS[198] VSS[303] N29
C AE43 AP9 BE34 N31 C
VSS[30] VSS[109] VSS[199] VSS[304]
AE45 VSS[31] VSS[110] AR19 BE36 VSS[200] VSS[305] N34
AE7 VSS[32] VSS[111] AR21 BE39 VSS[201] VSS[306] N39
AE9 VSS[33] VSS[112] AR31 BE41 VSS[202] VSS[307] N41
AF19 VSS[34] VSS[113] AR35 BE43 VSS[203] VSS[308] N43
AF2 VSS[35] VSS[114] AR37 BE45 VSS[204] VSS[309] N45
AF25 VSS[36] VSS[115] AT11 BE7 VSS[205] VSS[310] N7
AF27 VSS[37] VSS[116] AT39 BE9 VSS[206] VSS[311] N9
AF29 VSS[38] VSS[117] AT41 BE18 VSS[207] VSS[312] P2
AF31 VSS[39] VSS[118] AT43 BF2 VSS[208] VSS[313] P4
AF4 VSS[40] VSS[119] AT45 BF4 VSS[209] VSS[314] P48
AF48 VSS[41] VSS[120] AT7 BF48 VSS[210] VSS[315] P50
AF50 VSS[42] VSS[121] AT9 BF50 VSS[211] VSS[316] R17
AG11 VSS[43] VSS[122] AU17 BH10 VSS[212] VSS[317] R21
AG17 VSS[44] VSS[123] AU37 BH14 VSS[213] VSS[318] R31
AC9 VSS[45] VSS[124] AV2 BH26 VSS[214] VSS[319] T11
AE11 VSS[46] VSS[125] AV4 BH32 VSS[215] VSS[320] T13
AG19 VSS[47] VSS[126] AV48 BH34 VSS[216] VSS[321] T41
AG29 VSS[48] VSS[127] AV50 BH38 VSS[217] VSS[322] T43
AG31 VSS[49] VSS[128] AW11 BH42 VSS[218] VSS[323] T45
AG35 VSS[50] VSS[129] AW13 BH44 VSS[219] VSS[324] T7
AG41 VSS[51] VSS[130] AW23 BH46 VSS[220] VSS[325] T9
AG43 VSS[52] VSS[131] AW25 G21 VSS[221] VSS[328] BH28
AG45 VSS[53] VSS[132] AW27 BH48 VSS[222] VSS[329] N25
AG7 VSS[54] VSS[133] AW29 BH6 VSS[223] VSS[330] AF8
AG9 VSS[55] VSS[134] AW36 BK10 VSS[224] VSS[331] AF35
AH2 VSS[56] VSS[135] AW39 BK14 VSS[225] VSS[333] BB2
AJ11 VSS[57] VSS[136] AW43 BK18 VSS[226] VSS[334] BE25
AJ19 VSS[58] VSS[137] AW45 BK22 VSS[227] VSS[335] BH30
AJ33 VSS[59] VSS[138] AW7 BK26 VSS[228] VSS[337] F4
AJ35 VSS[60] VSS[139] AW9 D14 VSS[229] VSS[338] G25
AJ39 VSS[61] VSS[140] AY10 BK32 VSS[230] VSS[340] N11
B AJ41 B10 BK34 BH18 B
VSS[62] VSS[141] VSS[231] VSS[342]
AJ43 VSS[63] VSS[142] B14 BK38 VSS[232] VSS[343] BH22
AJ45 VSS[64] VSS[143] B18 BK42 VSS[233] VSS[344] BK30
AJ7 VSS[65] VSS[144] B22 BK46 VSS[234] VSS[345] AR17
AJ9 VSS[66] VSS[145] B26 D10 VSS[235] VSS[346] J39
AK17 VSS[67] VSS[146] B30 D18 VSS[236] VSS[353] U31
AK19 VSS[68] VSS[147] B34 D22 VSS[237] VSS[354] U49
AK2 VSS[69] VSS[148] B38 D26 VSS[238] VSS[355] V11
AK23 VSS[70] VSS[149] B42 D30 VSS[239] VSS[356] V15
AK25 VSS[71] VSS[150] B46 D34 VSS[240] VSS[357] V17
AK27 VSS[72] VSS[151] B6 D38 VSS[241] VSS[358] V2
AK35 VSS[73] VSS[152] BA11 D42 VSS[242] VSS[359] V27
AK37 VSS[74] VSS[153] BA13 D46 VSS[243] VSS[360] V29
AK4 VSS[75] VSS[154] BA16 F48 VSS[244] VSS[361] V33
AK48 VSS[76] VSS[155] AW41 F50 VSS[245] VSS[362] V35
AK50 VSS[77] VSS[156] BA18 G11 VSS[246] VSS[363] V4
AL11 VSS[78] VSS[157] BA21 G13 VSS[247] VSS[364] V41
AL39 VSS[79] VSS[158] BA23 G16 VSS[248] VSS[365] V43
G18 VSS[249] VSS[366] V45
COUGAR-POINT-SFF_BGA1017~D G23 V48
VSS[250] VSS[367]
G27 VSS[251] VSS[368] V7
G29 VSS[252] VSS[369] V9
G31 VSS[253] VSS[370] Y15
G34 VSS[254] VSS[371] Y17
G36 VSS[255] VSS[372] Y33
G39 VSS[256] VSS[373] Y35
G41 VSS[257] VSS[374] Y37
D6 VSS[258] VSS[347] AR8
G43 VSS[259] VSS[348] AR6
G9 VSS[260] VSS[349] BF15
J11 VSS[261] VSS[350] BD15
J13 VSS[262] VSS[351] BF24
A J16 BD24 A
VSS[263] VSS[352]

COUGAR-POINT-SFF_BGA1017~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/8) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Monday, January 24, 2011 Sheet 19 of 54
5 4 3 2 1
 5 4 3 2 1

+3VS
1/12 add for ENE EC protect

2
D13 1/24
@ R442
W=60mils
2 1
RB751V_SOD323 +LCDVDD +LCDVDD +3VS
4.7K_0402_5% Q22
D5 SI2301BDS_SOT23

1
1 2 DISPLAYOFF# 1 2 220P_0402_50V7K
25 BKOFF#
C586 R439

S
1 3

D
1
CH751H-40PT_SOD323-2 @ 110_0402_5%~D
D
@ +5VALW D
R395 1 1 1

G
2

2
10K_0402_5%~D C580 C581

2
C579 4.7U_0603_6.3V6K

1+LCDVDD_R
2
1/12 add for ENE EC protect R440 0.1U_0402_16V4Z 4.7U_0805_10V4Z
+3VS 2 2 2
100K_0402_5%

1
1
+3VS
R441
Q23 D
@ R394
@R394 2 2 1
10K_0402_5%~D 2N7002_SOT23 G
SN74AHC1G08DCKR_SC70-5 S 100K_0402_5% 2

3
5
U54 C582
1 1U_0402_6.3V4Z

P
14 PCH_VGA_PWM IN1 1
4 INVT_PWM_L L5 1 2INVT_PWM
O
25 EC_INV_PWM 2 IN2

G
1 D37
FMBA_L10_BLM18BB221SN1D CU63 VGA_LVDDEN 2
14,25 VGA_LVDDEN

1
D
@
1 2 Q24
2 G 2N7002_SOT23

1
@ R1838
@R1838 100P_0402_50V7K~D 25 EC_ENVDD EC_ENVDD 3 S

3
0_0402_5%~D
2 1 BAT54C-7-F_SOT23~D R449
100K_0402_5%
@ R1837
@R1837

2
0_0402_5%~D
2 1
W=20mils

B+ SI3457BDV-T1-E3_TSOP6~D
INVPWR_B+
C Q25 40mil C
40mil

D
+5VALW
6

S
INVPWR_B+
1

@ 4 5
R2013 2 +LCDVDD
1

+3VS +3VS_LCD +3VS

1000P_0402_50V7K~D
820_0805_1% 1

G
R2014 1 R451

1
2N7002DW-7-F_SOT363-6

100K_0402_5% 1 1 2
3 2

3
@ R452 C588 0_0603_5% 1 1 1 1 1 1

C587
@ 100K_0402_5%~D 0.1U_0603_50V4Z~D C574 C576 C577 C578
2

Q305B 2 C590 C575

2

10U_0805_10V4Z

0.1U_0402_16V4Z

390P_0402_50V7K
0.1U_0402_16V4Z~D
2N7002DW-7-F_SOT363-6

0.1U_0402_16V4Z

2
2 2 2 2 2 2

1800P_0402_50V7K
5
PWR_SRC_ON
6

@
4

Q305A +3VS

1
+LCDVDD_E 2 R453
100K_0402_5%~D
@
1

R263 1 2 10K_0402_5% CE_ENABLE_R

LVDS and USB CAM connector

2
R264 1 2 10K_0402_5% DBC_ENABLE_R
@

1
0_0402_5%~D D
Discharg Circuit 25 EN_INVPWR R459 1 2 +LCDVDD_E 2 Q26 68P_0402_50V8J
G 2N7002W-7-F_SOT323-3~D CE_ENABLE_R R254 1 2 10K_0402_5% 2 1 C589
@ 0_0402_5%~D S DBC_ENABLE_R R255 1 2 10K_0402_5% 1/24 Add D14
3
+LCDVDD R460 1 2 0.1U_0603_25V7K
@ 2 1 C591
R457 1 2 0_0402_5%~D JLVDS1
INVPWR_B+ 1 1
D14
W=40mils 2 2
3 3
2 1 DBC_ENABLE_R 4
25 DBC_ENABLE 4
RB751V_SOD323 5 5
W=60mils +LCDVDD 6 6
7 7
+3VS_LCD 8 8
B
9 9 B
+3VS INVT_PWM
W=20mils DISPLAYOFF#
10 10
11 11
Q27 +3VS_CAM 12
25 LCD_TEST 12
SI2301BDS_SOT23 13
LVDS_DDC_CLK 13
W=20mils 14 LVDS_DDC_CLK 14 14
S

LVDS_DDC_DATA
D

3 1 14 LVDS_DDC_DATA 15 15
16 16
1

100K_0402_5%~D
0.1U_0402_10V6K~D

1 1/20 C594, C595 change 5P to 2.5P LVDS_A0+ 17

14 LVDS_A0+ 17
LVDS_A0-
G

1 14 LVDS_A0- 18
2

18
R455

C593 19 19
C592

0.1U_0402_16V4Z LVDS_ACLK+ LVDS_A1+ 20

2 14 LVDS_A1+ 20
LVDS_A1- 21
14 LVDS_A1-
2

2 LVDS_ACLK- 21
22 22
1 1 LVDS_A2+ 23
14 LVDS_A2+ 23
C594 C595 LVDS_A2- 24
14 LVDS_A2- 24
R456 25 25
1 2CAM_ON/OFF 1.5P_0402_50V 1.5P_0402_50V
14 LVDS_ACLK+
LVDS_ACLK+ 26 26
2 2 LVDS_ACLK-
14 LVDS_ACLK- 27 27
1K_0402_5%~D Reserve for EMI 28 28
1

D
29
25 EN_CAM 2 Q28 (Place close to JLVDS1) 30
29
41
G 2N7002_SOT23-3 D6 @ 30 G1
31 31 G2 42
S 2 USB20_P3 32 43
3

USB20_N3 USB20_N3 32 G3
15 USB20_N3 1 33 33 G4 44
USB20_P3 3 34 45
15 USB20_P3 13 CAM_DET# 34 G5
1K_0402_5%~D 35 46
25 CE_ENABLE 35 G6
PJDLC05C_SOT23-3 R458 1 2 CE_ENABLE_R 36 36 G7 47
DMIC_DATA R1839 1 2 0_0603_5% 37 48
24 DMIC_DATA 37 G8
DMIC_CLK R1840 1 2 0_0603_5% 38 49
24 DMIC_CLK 38 G9
39 39 G10 50
+3VS_CAM 40 40 G11 51

100P_0402_50V8J~D

100P_0402_50V8J~D
D7 @
W=20mils I-PEX_20439-040E-01_40P
PJDLC05C_SOT23-3 1 1 CONN@

C596

C597
2 DMIC_DATA
1
DMIC_CLK 2 2
A 3 A

Close to CONN

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/06 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS /camera conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Tuesday, January 25, 2011 Sheet 20 of 54
5 4 3 2 1
 5 4 3 2 1

UL1
Atheros +LAN_IO
13 PCIE_PRX_GLANTX_P1 2 1 PCIE_PRX_GLANTX_P1_C 30 11 LAN_MDIP0 RL2 2 1 49.9_0402_1% +LAN0 CL3 1 2 1000P_0402_50V7K~D
CL2 0.1U_0402_16V7K~D TX_P AR8151 AL1A TRXP0 LAN_MDIN0 RL1 49.9_0402_1% CL4 0.1U_0402_16V7K~D
TRXN0 12 2 1 1 2
13 PCIE_PRX_GLANTX_N1 2 1 PCIE_PRX_GLANTX_N1_C 29 14 LAN_MDIP1 RL3 2 1 49.9_0402_1% +LAN1 CL5 1 2 1000P_0402_50V7K~D
TX_N TRXP1

1
0_0402_5%~D
CL1 0.1U_0402_16V7K~D 15 LAN_MDIN1 RL4 2 1 49.9_0402_1% CL6 1 2 0.1U_0402_16V7K~D
PCIE_PTX_GLANRX_P1 TRXN1 LAN_MDIP2 RL5 49.9_0402_1% +LAN2 CL7 1000P_0402_50V7K~D
13 PCIE_PTX_GLANRX_P1 35 RX_P TRXP2 17 2 1 1 2
18 LAN_MDIN2 RL7 2 1 49.9_0402_1% CL8 1 2 0.1U_0402_16V7K~D RL6
PCIE_PTX_GLANRX_N1 TRXN2 LAN_MDIP3 RL8 49.9_0402_1% +LAN3 CL9 1000P_0402_50V7K~D
13 PCIE_PTX_GLANRX_N1 36 RX_N TRXP3 20 2 1 1 2
21 LAN_MDIN3 RL9 2 1 49.9_0402_1% CL10 1 2 0.1U_0402_16V7K~D

2
CLK_PCIE_LAN TRXN3
13 CLK_PCIE_LAN 33 REFCLK_P
close to Lan chip 1000p reserved for EMI PLT_RST# 1 @ 2 4.7K_0402_5%~D
CLK_PCIE_LAN# 32 RL10
13 CLK_PCIE_LAN# REFCLK_N
13 +AVDDL PCIE_WAKE# 1 @ 2 4.7K_0402_5%~D
CLKREQ_LAN#_R AVDDL RL11
13 LANCLK_REQ# 2 1 4 CLKREQ# AVDDL 19
RL12 0_0402_5%~D +LAN_IO
PLT_RST# AVDDL 31 W=20mils
D 5,15,22,23,24,25 PLT_RST# 2 PERST# AVDDL 34 D
6 CLKREQ_LAN#_R 1 2 4.7K_0402_5%~D
PCIE_WAKE# AVDDL_REG RL13
14,23,24,25 PCIE_WAKE# 3 WAKE# LL1
16 +AVDDH 4.7UH_1008HC-472EJFS-A_5%_1008 W=40mils
AVDDH
25 SMCLK AVDDH 22 W=20mils
26 SMDATA AVDDH_REG 9 W=20mils
CONNECT TO POWER 28 +LX 1 2 +VDDCT +DVDDL
TEST_RST

1000P_0402_50V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
27 24 +DVDDL
TESTMODE DVDDL

1U_0603_10V6K~D
41 GND DVDDL_REG 37 W=20mils

4.7U_0603_6.3V6K~D
LAN_X1
W=40mils 1
CL12
1 1 1 1 1 1
7 XTLO
LAN_X2_R 8 1 +LAN_IO CL11 CL13 CL14 CL15 CL16 CL17
XTLI VDD33
W=40mils 2 2 2 2 2 2 2
05/19 modified 40 +LX
RL15 LX
LAN_ACTIVITY VDDCT 5 +VDDCT W=40mils close to Lan pin40
38 LED_0
2

LAN_LINK#_R 39 10 +RBIAS 1 RL14 2

LAN_LED2#_R LED_1 RBIAS
23 LED_2 close to Lan pin5
2

2.37K_0402_1%~D close to Lan pin37 close to Lan pin24

0_0402_5%~D RL16 W=20mils
25MHz_12P_X5H025000FC1H-H 5.1K_0402_1%~D AR8151-BL1A
1

YL1
Version A will be fail on 802.3a
1

1 2 LAN_X2
1 1
CL18 CL19
need to update to Version B
2 2
15P_0402_50V8J~D
15P_0402_50V8J~D

W=40mils
W=40mils
C +3VALW C
QL1 W=20mils W=20mils
+LAN_IO close to Lan pin19
D

6 1A
S

1 5 4 close to Lan pin9 close to Lan pin16 close to Lan pin6 close to Lan pin31

1000P_0402_50V7K~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
0.1U_0402_16V7K~D
CL20 2

1U_0603_10V6K~D
1U_0402_6.3V6K~D 1 +AVDDH +AVDDL

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D
SI3456BDV-T1-E3 1N TSOP6
G

1U_0603_10V6K~D

1U_0603_10V6K~D
1 1 1 1 1
3

B+_BIAS 1 1 1 1 1 1 1 1 1 1
CL31 CL32 CL33 CL34 CL35
CL21 CL22 CL23 CL24 CL25 CL26 CL27 CL28 CL29 CL30
2

2 2 2 2 2
RL18 2 2 2 2 2 2 2 2 2 2
470K_0402_5%~D
1

EN_WOL close to Pin 1

0.1U_0402_25V6
1

D
1.5M_0402_5%~D

QL2 CL36
1 close to Lan pin22
25 EN_WOL# 2
SSM3K7002FU_SC70-3 RL19
close to Lan pin34 close to Lan pin13
G
S
3

2
1

W=20mils TS1
LL2 RL21
+VDDCT 2 1 +VDDCT_L 1 24 RJ45_CT0 1 2
MURATA_BLM18AG601SN1D_0603 LAN_MDIN3 TCT1 MCT1 RJ45_MDI3- 75_0402_1%~D
2 TD1+ MX1+ 23
LAN_MDIP3 3 22 RJ45_MDI3+ JLAN1
TD1- MX1- RL22
4 21 RJ45_CT1 1 2 13
B
LAN_MDIN2 TCT2 MCT2 RJ45_MDI2- 75_0402_1%~D Yellow LED- B
5 TD2+ MX2+ 20
LAN_MDIP2 6 19 RJ45_MDI2+ LAN_ACTIVITY 1 2 LAN_ACTIVITY_R 12
TD2- MX2- RL23 511_0402_1%~D RL25 Yellow LED+
7 18 RJ45_CT2 1 2 RJ45_MDI3- 8
LAN_MDIN1 TCT3 MCT3 RJ45_MDI1- 75_0402_1%~D TX3-
8 TD3+ MX3+ 17
LAN_MDIP1 9 16 RJ45_MDI1+ RJ45_MDI3+ 7
TD3- MX3- RL24 TX3+
10 15 RJ45_CT3 1 2 RJ45_MDI1- 6
LAN_MDIN0 TCT4 MCT4 RJ45_MDI0- 75_0402_1%~D TX1-
11 TD4+ MX4+ 14
LAN_MDIP0 12 13 RJ45_MDI0+ RL26 RJ45_MDI2- 5
TD4- MX4- LAN_LED2#_R TX2-
2 1LAN_LED2#
200_0402_1%~D RJ45_MDI2+ 4
CL38 TX2+
2
350UH_GST5009-CLF CL39 470P_0402_50V7K 1 2 RJ45_MDI1+ 3
1000P_1808_3KV7K~D TX1+
TIMAG: S X'FORM_ IH-160 LAN , SP050006F00
BOTHHAND: S X'FORM_ GST5009-D LF LAN,SP050006B00 RJ45_MDI0- 2
1 RL27 TX0-
LAN_LINK#_R 2 1 LAN_LINK# RJ45_MDI0+ 1 TX0+
1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D

1000P_0402_50V7K~D
1U_0603_10V6K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

0.1U_0402_16V7K~D

GND 15
130_0402_1%~D LAN_LED2# 11 14
Orange LED- GND
CL40

CL41

CL42

CL43

CL44

CL45

CL46

CL47

CL48

1 2 1 2 1 2 1 2 1 470P_0402_50V7K CL49
2 1 LAN_LINK# 9 Green LED-
close to LL2 @ @ @ @ +LAN_IO 1 2 LAN_LED_VCC1 10 Green-Orange LED+
2 1 2 1 2 1 2 1 2 0_0402_5%~D RL20
W=20mils TYCO_2041633-1
CONN@

close to TS1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GLAN AR8151 AL1A/ RJ45
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Tuesday, January 25, 2011 Sheet 21 of 54
5 4 3 2 1
 5 4 3 2 1

3 in 1 Card Reader CONN

+3V_MCVCC

JCARD1
+3VS +1.8VS_APVDD XDWP_SDWP
Neer to pin19,20 40mil Neer to pin37
XD_SD_MS_D1
1 SD-WP-SW
40mil XD_SD_MS_D0
2 SD-DAT1
3 SD-DAT0
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4 SD-GND

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 1 1 1 C1159 1 1 1 5
C1153 C1157 C1158 C1154 C1160 C1163 SDCMD_MSBS_XDWE# MS-GND
6 MS-BS

10U_0805_10V4Z
D XDCE_SDCLK_MSCLK 7 D
XD_SD_MS_D1 SD-CLK
8 MS-DAT1
2 2 2 2 2 2 2 XD_SD_MS_D0 9 MS-DAT0
10 SD-VCC
+1.8VS_APVDD XD_SD_MS_D2 11 MS-DAT2
12 SD-GND
XDCD1#_MSCD# 13
XD_SD_MS_D3 MS-INS
Neer to pin44 14 MS-DAT3

1000P_0402_50V7K

0.1U_0402_16V4Z
1 1 1 SDCMD_MSBS_XDWE# 15
C1161 C1156 C1162 XDCE_SDCLK_MSCLK SD-CMD
Neer to pin18 16 MS-SCLK
17 MS-VCC

10U_0805_10V4Z
XD_SD_MS_D3 18
2 2 2 SD-DAT3
19 MS-GND
XD_SD_MS_D2 20 22
XDCD0#_SDCD# SD-DAT2 GND1
21 SD-CD-SWGND2 23
U33
Trace 20mils TAITW_R009-121-LK_RV
13 CLK_PCIE_CD# 3 5 SP07000KT00
APCLKN APVDD CONN@
13 CLK_PCIE_CD 4 APCLKP APV18 10 1 2

13 PCIE_PTX_CARDRX_N4 9 C1155
APRXN 0.1U_0402_16V4Z
13 PCIE_PTX_CARDRX_P4 8 APRXP DV33 19 +3VS
DV33 20
C1165 22P_0402_50V8J C1168 1 2 0.1U_0402_16V7K PCIE_IRX_CRTX_N5_C 11 44
13 PCIE_PRX_CARDTX_N4 APTXN DV33
2 1 XIN C1166 1 2 0.1U_0402_16V7K PCIE_IRX_CRTX_P5_C 12 18 +1.8VS_APVDD
13 PCIE_PRX_CARDTX_P4 APTXP DV18
R979 12K_0402_1% 37
APREXT DV18 +3V_MCVCC
1 2 7 APREXT
1

APREXT 12 mil 48 XD_SD_MS_D0

Y4 MDIO0 XD_SD_MS_D1 SDCMD_MSBS_XDWE# 1
MDIO1 47 2
24.576MHZ_16P_X8A024576FG1H XIN 38 46 XD_SD_MS_D2 R981 10K_0402_5%
XOUT TXIN MDIO2 XD_SD_MS_D3 XDWP_SDWP
39 45 1 2
JMB380
2

+3VS TXOUT MDIO3 SDCMD_MSBS_XDWE# R982 1K_0402_5%

MDIO4 43
C 2 1 XOUT 42 MDIO5 R983 2 1 22_0402_5%~D XDCE_SDCLK_MSCLK C
C1170 1 MDIO5 XDWP_SDWP
2 30 TAV33 MDIO6 41
C1169 22P_0402_50V8J 0.1U_0402_16V7K 40 MDIO7 1
MDIO7 C1167
MDIO8 29
1 28 +3VS
5,15,21,23,24,25 PLT_RST# XRSTN MDIO9
2 27 22P_0402_50V8J
+3VS XTEST MDIO10 2 MDIO7
MDIO11 26 1 2
@ @ R985 0_0402_5% 25 MDIO12 R984 10K_0402_5%
R990 4.7K_0402_1% MDIO12 MDIO13 MDIO13
15 CR_CPPEN 1 2 13 SEEDAT MDIO13 23 1 2
1 2 XDCD1#_MSCD# 14 22 MDIO14 R986 1K_0402_1%
T18 PAD SEECLK MDIO14
@
XDCD0#_SDCD# IEEE1394_TPAP0
1
R992
2
4.7K_0402_1%
GPIO PIN XDCD1#_MSCD# 15
TPA1P 34
35 IEEE1394_TPBIAS0 R987 12K_0402_1% MDIO12 R988 1 2200K_0402_1%
XDCD0#_SDCD# CR1_CD1N TPBIAS_1 TREXT
@ 16 CR1_CD0N TREXT 36 1 2
TREXT 12 mil MDIO14 1 2
@ 6 R989 200K_0402_1%
+3V_MCVCC APGND
17 CR1_PCTLN
C1177 1 2 XDCD1#_MSCD# 24
0.1U_0402_16V7K TCPS IEEE1394_TPBN0
TPB1N 31
C1178 1 2 XDCD0#_SDCD# 21 32 IEEE1394_TPBP0
0.1U_0402_16V7K CR1_LEDN TPB1P IEEE1394_TPAN0
TPA1N 33
@ R993 0_0402_5%~D
49 1 2 IEEE1394_TPBN0_R
TPAD R9940_0402_5%~D
JMB380C-QGAZ0B_QFN48_7X7 1 2 IEEE1394_TPBP0_R
Layout Note:
Add GND shield for 1394. DLW21SN121SQ2L_4P~D
+3V_MCVCC
+3V_MCVCC
IEEE1394_TPBN0 @ 4
4 3 3
1394 CONN
GND J3
IEEE1394_TPBP0 1 2 1 8
B 1 L60 2 TPB- GND B
40mil GND DLW21SN121SQ2L_4P~D
2 TPB+ GND 7
1 3 TPA- GND 6
C1176 IEEE1394_TPAN0 @ 4
10U_0805_6.3V6M C1171 1 C1172 1 C1173 1 4 3 3 4 TPA+ GND 5

2
GND FOX_UV31413-WS23P-7F~D
IEEE1394_TPAP0 1 2 DC235000G00
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1 L61 2 CONN@
Near to JCARD1 2 2 2

56.2_0402_1%~D220P_0402_50V X7R

56.2_0402_1%~D 4.99K_0402_1%
0.1U_0402_16V4Z

1
56.2_0402_1%~D
R998

56.2_0402_1%~D
R999
1 2 IEEE1394_TPAN0_R

R996

R997
R995 0_0402_5%~D
1 2 IEEE1394_TPAP0_R
R1000 0_0402_5%~D

2
IEEE1394_TPBIAS0

1
1

0.33U_0402_10V6K
C1174

R1002
1 Layout Note: Shield GND for
2 IEEE1394_TPA and TPB

C1175
2
2 Minimize this distance between
IC and terminating resistor.

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/25 Deciphered Date 2010/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CARD READER/1394
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6961P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 24, 2011 Sheet 22 of 54
5 4 3 2 1
 5 4 3 2 1

+1.5VS +1.5VS_WWAN SIM Card

0.047U_0402_16V4Z~D
U31 @
2 1

47P_0402_50V8J~D
0.01U_0402_25V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z
1 1 1 1 1

C1092

C1093

C1095

C1096

C1094
R956 UIM_RESET 1 6 UIM_VPP
0_1206_5% @
WWAN PCIE MiniCard 2 2 2 2 2
+3VS
2 5 +UIM_PWR
+1.5VS_WWAN +3VS_WWAN
R961 2 1 0_1206_5% UIM_CLK 3 4 UIM_DATA
JWWAN1

0.047U_0402_16V4Z~D

33P_0402_50V8J~D

33P_0402_50V8J~D

33P_0402_50V8J~D

33P_0402_50V8J~D
14,21,24,25 PCIE_WAKE# PCIE_WAKE# 1 2 R960 2 1
1 2

47P_0402_50V8J~D

0.01U_0402_25V7K
D 3 4 0_1206_5% D
3 4 1 1 1 1 1

C1102

C1103

C1104

C1105
330U_D2E_6.3VM_R25M
4.7U_0805_10V4Z

0.1U_0402_16V4Z
5 6 1 1 1 1 SRV05-4.TCT_SOT23-6~D
5 6

C1189
7 8 +
13 CLKREQ_WWAN# 7 8 +UIM_PWR

C1097

C1098

C1099

C1100

C1101
9 10 UIM_DATA @ @ @ @ @
9 10 UIM_CLK 2 2 2 2
11 12
13 CLK_PCIE_WWAN#
13 CLK_PCIE_WWAN 13
15
11
13
15
12
14
16
14
16
UIM_RESET
UIM_VPP
2 2 2 2 2
110 mils
17 17 18 18
19 20 WWAN_RADIO_OFF#
19 20 WWAN_RADIO_OFF# 15 +UIM_PWR
0.1U_0402_16V7K 21 22 PLT_RST#
21 22
13 PCIE_PRX_WWANTX_N2
C648 2 1PCIE_PRX_WWANTX_C_N2 23 23 24 24

1U_0603_10V4Z~D
13 PCIE_PRX_WWANTX_P2
C649 2 1PCIE_PRX_WWANTX_C_P2 25 25 26 26
27 27 28 28 1

C1106
0.1U_0402_16V7K 29 30 WWAN_SMB_CK_R R940 1 2 0_0402_5%
29 30 PCH_SMLCLK 13,25,26,31,46
13 PCIE_PTX_WWANRX_N2 31 32 WWAN_SMB_DA_R R941 1 2 0_0402_5%
31 32 PCH_SMLDATA 13,25,26,31,46
33 34
13 PCIE_PTX_WWANRX_P2
35
33
35
34
36 36 USB20_N5
USB20_N5 15
40 mils 2
37 38 USB20_P5
37 38 USB20_P5 15
+3VS_WWAN 39 39 40 40
41 42 JSIM1
41 42
43 43 44 44 5 GND VCC 1
45 46 UIM_VPP 6 2 UIM_RESET
0_0402_5% 45 46 UIM_DATA VPP RST UIM_CLK
47 47 48 48 For EC debug card 7 I/O CLK 3
25 EC_TX R943 1 2 EC_DET 49 50 8 4
R944 1 0_0402_5% 49 50 EC_DET R1108 100K_0402_1% GND NC
25 EC_RX 2 51 51 52 52 1 2 9 GND
53 GND1 GND2 54
HB_5680629-SICR11

LOTES_AAA-PCI-041-K01 CONN@

C
CONN@ C

Primary Power Aux Power

PWR Voltage
Rail Tolerance Peak Normal Normal +3VS +3VS

+3.3V +-9% 1000 750 @

Bluetooth CU11
0.1U_0402_16V4Z
1
CU12
250 (Wake enable)
+3.3Vaux +-9% 330 250 5 (Not wake enable) 1U_0603_10V4Z

3
S
2
G
BT_ON# 1 2 2
16 BT_ON# QU1
+1.5V +-5% 500 375 NA RU6
10_0402_5% D AO3413_SOT23-3

1
0.1U_0402_16V4Z
CU15 W=40mils
40 mils WLAN/WIMAX PCIE Mini Card +3VS_BT

1
4.7U_0805_10V4Z
1
+3V_WLAN +1.5VS_WLAN CU17 RU8

+3VS 2 1
20 mils +1.5VS

2
CU16 300_0603_5%
47P_0402_50V8J~D
0.01U_0402_25V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z
0.047U_0402_16V4Z~D

1 1 1 1 1 2 1

2
C1107

C1108

C1109

C1110

C1111

47P_0402_50V8J~D
0.01U_0402_25V7K

0.1U_0402_16V4Z

4.7U_0805_10V4Z

R946

0.047U_0402_16V4Z~D
1 1 1 1 1
C1112

C1113

C1114

C1115

C1116
0_1206_5% @ R950 0.1U_0402_16V4Z
0_1206_5% @

1
2 2 2 2 2 D
2 2 2 2 2 QU2
2
G 2N7002_SOT23
+3V_WLAN S

3
+1.5VS_WLAN
B B
JWLAN1 +3VS_BT
PCIE_WAKE# 1 2 C1703
14,21,24,25 PCIE_WAKE#
BT_ACTIVE R947 1 2 0_0402_5%3
1
3
2
4 4 For Compal LPC debug card 2 1 JBT1
COEX2_WLAN_ACTIVE R948 1 2 0_0402_5%5 6
CLKREQ_WLAN# 5 6 R951 0_0402_5% LPC_LFRAME# 0.1U_0402_16V4Z~D
13 CLKREQ_WLAN# 7 7 8 8 1 2 LPC_FRAME# 12,25
9 10 R952 1 2 0_0402_5% LPC_AD3 14
9 10 LPC_AD3 12,25 GND
13 CLK_PCIE_WLAN# 11 12 R953 1 2 0_0402_5% LPC_AD2 13
11 12 LPC_AD2 12,25 GND
13 CLK_PCIE_WLAN 13 14 R954 1 2 0_0402_5% LPC_AD1
13 14 LPC_AD1 12,25
R949 0_0402_5% 15 16 R955 1 2 0_0402_5% LPC_AD0 12
15 16 LPC_AD0 12,25 12
PLT_RST# 1 2 17 18 13 BT_DET# 11
17 18 WL_OFF# COEX2_WLAN_ACTIVE 11
15 WLAN_BT_RADIO_OFF# 1 2 19 19 20 20 WL_OFF# 15 10 10
R957 0_0402_5% 21 22 PLT_RST# 9
21 22 PLT_RST# 5,15,21,22,24,25 9
13 PCIE_PRX_WLANTX_N3
C660 2 1 PCIE_PRX_WLANTX_C_N3 23 23 24 24 8 8
13 PCIE_PRX_WLANTX_P3
C661 2 1 PCIE_PRX_WLANTX_C_P3 25 25 26 26 7 7
0.1U_0402_16V7K 27 28 BT_RADIO_OFF# 6
27 28 16 BT_RADIO_OFF# 6
0.1U_0402_16V7K 29 30 WLAN_SMB_CLK_R R958 1 2 0_0402_5% BT_ACTIVE 5
29 30 PCH_SMLCLK 13,25,26,31,46 5
13 PCIE_PTX_WLANRX_N3 PCIE_PTX_WLANRX_N3 31 32 WLAN_SMB_DAT_R R959 1 2 0_0402_5% 4
31 32 PCH_SMLDATA 13,25,26,31,46 4
13 PCIE_PTX_WLANRX_P3 PCIE_PTX_WLANRX_P3 33 34 3
33 34 USB20_N4 3
35 35 36 36 USB20_N4 15 15 USB20_N2 2 2
37 38 USB20_P4 1
37 38 USB20_P4 15 15 USB20_P2 1
+3V_WLAN 39 39 40 40
41 42 CONN@
41 42 MOLEX 48227-1211 12P
43 43 44 44
45 45 46 46
47 47 48 48

100P_0402_50V8J~D
R962 49 50
49 50

33P_0402_50V8J~D

10K_0402_5%~D
1 2 51 52
51 52 CIS link OK

@C1342
@
0_0402_5% 1 1

C1704

R1407

C1342
53 GND1 GND2 54
@
A LOTES_AAA-PCI-041-K01 2 2 A

2
CONN@

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/25 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN/WWAN/SIM/BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6961P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 24, 2011 Sheet 23 of 54
5 4 3 2 1
 5 4 3 2 1

IO Board CONN
JBTB1

51 51 52 52
13 PCIE_PRX_USB3TX_N6 49 49 50 50 PCIE_PTX_USB3RX_N6 13
13 PCIE_PRX_USB3TX_P6 47 47 48 48 PCIE_PTX_USB3RX_P6 13
45 45 46 46
D 43 44 D
13 CLK_PCIE_USB30# 43 44 PCIE_WAKE# 14,21,23,25
13 CLK_PCIE_USB30 41 41 42 42 PLT_RST# 5,15,21,22,23,25
39 39 40 40 LID_SW_IN# 13,25,27
12 HDA_BITCLK_AUDIO 37 37 38 38 EC_EAPD 25
35 35 36 36 BEEP# 25
20 DMIC_DATA 33 33 34 34 PCH_SMBCLK 10,11,13
20 DMIC_CLK 31 31 32 32 PCH_SMBDATA 10,11,13
27 IO_BOARD_CONN 29 29 30 30
12 HDA_RST_AUDIO# 27 27 28 28
12 HDA_SDIN0 25 25 26 26
12 HDA_SDOUT_AUDIO 23 23 24 24
12 HDA_SYNC_AUDIO 21 21 22 22
25 SPK_MUTE# 19 19 20 20
16,26 FFS_INT2 17 17 18 18 HDA_SPKR 12
15 USB30_SMI# 15 15 16 16 FFS_INT1 15 +1.5V 1 2 +1.5V_USB30
25 USB_PWR_ON 13 14 USB30_CLKREQ# 13 R1962 0_0603_5%~D
13 14
11 11 12 12 +1.5VS 1 2
9 10 R1963 0_0603_5%~D
9 10
+5VALW 7 7 8 8 +5VALW @
5 5 6 6
+5VS 3 3 4 4 +1.5V_USB30
+3VS 1 1 2 2 +3VALW
E-T_1001-F50C-02R

CONN@

+5V_CHGUSB
OE#
C
Function 2.0A C
U36 L
PWRSHARE_EN# PWRSHARE_OE# Dect charger
1 CEN CB 8 PWRSHARE_OE# 25

0.1U_0402_16V4Z
USBP2_D-_C 2 7 H D=1D 1
DM TDM USB20_N1 15

150U_B2_6.3V-M~D
USBP2_D+_C 3 6 1
DP TDP USB20_P1 15 +
4 5 +5VALW R1011
GND VCC C1179 C1181
9 GND
1 100K_0402_5%~D @
MAX14566EETA+_TDFN-EP8_2X2~D 2 2

2
C1180 R1010 1 2 0_0402_5%
0.1U_0402_16V4Z~D
2 JUSB1
WCM2012F2S-900T04_0805 1
USBP2_D-_C USBP2_D- VCC
Powershare 4 4 3 3
USBP2_D+
2
3
USB_N
USB_P
4 GND
USBP2_D+_C 1 2 5
1 2 GND
6
2.0A L62
D16 7
GND
GND
8 GND
2 1 +5VALW +5V_CHGUSB 3
25 PWRSHARE_EC_EN# 2 1 U37 1 FOX_UB111SC-R1BHC-7H
D71 1 8 R1014 1 2 0_0402_5% 2 CONN@
GND OC1# USB_OC0# 15
1SS355TE-17_SOD323-2 2 7
R215 IN OUT1
3 EN1# OUT2 6 @ PJDLC05C_SOT23-3
PWRSHARE_EN# 1 2 10K_0402_5%~D 4 5
EN2# OC2#
TPS2062ADR_SO8~D
0.1U_0402_16V4Z

1 1
1

10U_1206_16V4Z

C1182 C1183
R1239
10K_0402_5%~D
B 2 2 B
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/07/25 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB/LID SW/IO CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6961P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 24, 2011 Sheet 24 of 54
5 4 3 2 1
 5 4 3 2 1

+3VALW L43
FBMA-L11-160808-800LMT_0603 KSI[0..7]
KSI[0..7] 42
@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VALW_EC 2 +EC_VCCA
R216
1 2
1 1 1 1 2 2
1
KSO[0..16]
KSO[0..16] 42
Board ID
+3VS 0_0805_5% C277 C276 C278 C279 C280 C281 +3VALW
1

1 2 BKOFF# 1000P_0402_50V7K C282

2
R217 10K_0402_5% 2 2 2 2 1 1
2
2 EC_SCI# 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z R219

ECAGND
1
R218 10K_0402_5% Ra 100K_0402_5%
D
1 @ 2 PWRSHARE_EC_EN# D
R220 10K_0402_5%

0.1U_0402_16V4Z
AD_BID0

111
125
22
33
96

67
U622

2
1
R225 C283

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
Rb 56K_0402_1%
2

1
GATEA20 1 21 DBC_ENABLE
16 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F DBC_ENABLE 20
KB_RST# 2 23 BEEP# change netname
16 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# 24
SERIRQ 3 26 SYSTEM_FAN_PWM
12 SERIRQ SERIRQ# FANPWM1/GPIO12 SYSTEM_FAN_PWM 26from BEEP to BEEP#
LPC_FRAME# 4 27 ACOFF Analog Board ID definition,
12,23 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 44,46
C284 LPC_AD3 5 2 1 ECAGND
12,23 LPC_AD3 LAD3 Please see page 3.
@ 22P_0402_50V8J LPC_AD2 7 PWM Output C286 100P_0402_50V8J
12,23 LPC_AD2 LAD2
2 1 R226 2 1 @ 33_0402_5% LPC_AD1 8 63 BATT_TEMP
12,23 LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 45
LPC_AD0 PM_SLP_SUS# +5VS
12,23 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
PM_SLP_SUS# 14
ADP_I/AD2/GPIO3A 65 ADP_I 44,46
12 AD Input 66 AD_BID0
15 CLK_PCI_LPC PCICLK AD3/GPIO3B
13 75 TP_CLK 2 1
5,15,21,22,23,24 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
+3VALW R221 2 1 47K_0402_5% EC_RST# 37 76 4.7K_0402_5% R223
ECRST# SELIO2#/AD5/GPIO43 IMON 54
EC_SCI# 20 R262 1 2 0_0402_5% TP_DATA 2 1
16 EC_SCI# SCI#/GPIO0E
C285 2 1 0.1U_0402_16V4Z 20 EN_CAM EN_CAM 38 4.7K_0402_5% R224
CLKRUN#/GPIO1D
DAC_BRIG/DA0/GPIO3C 68
70 AC_SEL difference with HW6 CKT
EN_DFAN1/DA1/GPIO3D AC_SEL 44
DA Output 71 IREF
IREF/DA2/GPIO3E IREF 46
KSI0 55 72 CHGVADJ SPK_MUTE# EC_CRY1 EC_CRY2
KSI0/GPIO30 DA3/GPIO3F CHGVADJ 46 SPK_MUTE# 24
KSI1 56 KSI1/GPIO31

1
KSI2 D
57 KSI2/GPIO32 2N7002_SOT23 1 1
KSI3 58 83 EC_MUTE_R R228 2 1 0_0402_5% EC_MUTE 2 C287 C288
KSI3/GPIO33 PSCLK1/GPIO4A

4
Q21 @

10K_0402_5%
KSI4 59 84 G
KSI4/GPIO34 PSDAT1/GPIO4B USB_PWR_ON 24

2
KSI5 60 85 AC_PRESENT S 27P_0402_50V8J 27P_0402_50V8J

OSC

OSC
AC_PRESENT 14

3
+3VALW KSI6 KSI5/GPIO35 PSCLK2/GPIO4C H_PROCHOT#_EC 2 2 @
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86

R1803
KSI7 62 87 TP_CLK @
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 42
1 2 EC_SMB_CK1 KSO0 39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA
TP_DATA 42
R229 2.2K_0402_5% KSO1

NC

NC
40

1
KSO1/GPIO21
1 2 EC_SMB_DA1 KSO2 41 KSO2/GPIO22
R230 2.2K_0402_5% KSO3 42 97 VGATE +3V_PCH
VGATE 5,14,54

3
KSO4 KSO3/GPIO23 SDICS#/GPXOA00 EN_WOL# @
C 43 KSO4/GPIO24 SDICLK/GPXOA01 98 EN_WOL# 21 C
1 2 KSO1 KSO5 44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99 HDA_SDO
HDA_SDO 12
X1

2
R231 47K_0402_5% KSO6 45 109 LID_SW_IN# R1790 32.768KHZ_12.5PF_Q13MC14610002
KSO6/GPIO26 Matrix SDIDI/GPXID0 LID_SW_IN# 13,24,27
1 2 KSO2 KSO7 46 KSO7/GPIO27 SPI Device Interface
R232 47K_0402_5% KSO8 47 4/26 added 47K_0402_5%~D
KSO9 KSO8/GPIO28 FRD#
10/1 ENE Recommand 48 KSO9/GPIO29 SPIDI/RD# 119
KSO10 49 120 R234 1 2 33_0402_5% FWR# EC_MUTE 1 R233 2 10K_0402_5%

1
PCIE_WAKE#_R KSO11 KSO10/GPIO2A SPIDO/WR# EC_SPI_CLK R236 1 SPI_CLK LID_SW_IN# EC_SPI_CLK C1079 1
1 2 10K_0402_5% C289 1 2 0.1U_0402_16V4Z 50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 2 33_0402_5% 2 @ 10P_0402_50V8J
R235 KSO12 51 128 R237 1 2 33_0402_5% FSEL#
KSO12/GPIO2C SPICS#
1 @ 2 EC_MUTE @ KSO13 52 KSO13/GPIO2D
@
R238 10K_0402_5% KSO14 53 KSO14/GPIO2E
1 @ 2 EC_SMI# KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 PCH_VREG_EN#
PCH_VREG_EN# 18
R239 1K_0402_1% KSO16 81 74 EC_PECI 1 2 Reserve for EMI please close to U622
KSO16/GPIO48 CIR_RLC_TX/GPIO41 H_PECI 5,16
1 @ 2 SPK_MUTE# 14 PCH_DPWROK
PCH_DPWROK 82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89 FSTCHG
FSTCHG 46
R240 43_0402_1%
R241 10K_0402_5% 90 CHRG_STATE# @ @
BATT_CHGI_LED#/GPIO52 CHRG_STATE# 27 Please place R240 close
1 2 EC_ESB_CLK CAPS_LED#/GPIO53 91 CAPS_LED#
CAPS_LED# 27
R251 C291
R242 4.7K_0402_5% EC_SMB_CK1 77 GPIO 92 BATT_LOW_LED# to EC with in 750mil EC_ESB_CLK 2 1 1 2
45 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_LOW_LED 27 +3VALW
1 2 EC_ESB_DAT 45 EC_SMB_DA1
EC_SMB_DA1 78 SDA1/GPIO45 SUSP_LED#/GPIO55 93 EC_ALERT# 46
33_0402_5% 22P_0402_50V8J
R243 4.7K_0402_5% EC_SMB_CK2 79 SM Bus 95 SYSON
SCL2/GPIO46 SYSON/GPIO56 SYSON 43,48
1@
@R245
R245 2 0_0402_5% EC_SMB_DA2 80 121 VR_ON
13,23,26,31,46 PCH_SMLCLK SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 54
1@
@R246
R246 2 0_0402_5% 127 ACIN
13,23,26,31,46 PCH_SMLDATA AC_IN/GPIO59 ACIN 27,30,46

1
2 1
C550 100P_0402_50V8J R248
1@
@R249
R249 2 0_0402_5% PM_SLP_S3#_R 6 100 PCH_RSMRST# 47K_0402_5%
14,27 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 PCH_RSMRST# 14
1@
@R250
R250 2 0_0402_5% PM_SLP_S5#_R 14 101 EC_LID_OUT#
14,27 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 13
EC_SMI# 15 102 EC_ON
16 EC_SMI# EC_ON 42,47

2
PS_ID EC_SMI#/GPIO08 EC_ON/GPXO05 3S/4S# RST#
44 PS_ID 16 LID_SW#/GPIO0A EC test PSID EC_SWI#/GPXO06 103 3S/4S#
EC_ESB_CLK R252 1@ 2 EC_ESB_CLK_R 17 104 PCH_PWROK 2
SUSP#/GPIO0B ICH_PWROK/GPXO06 PCH_PWROK 5,14
0_0402_5% EC_ESB_DAT 18 GPO 105 BKOFF#
PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 20
SUSWARN# 19 GPIO 106 CPU1.5V_S3_GATE C292
14 SUSWARN# EC_PME#/GPIO0D WL_OFF#/GPXO09 CPU1.5V_S3_GATE 9
25 107 PCH_APWROK 0.1U_0402_16V4Z
20 EC_INV_PWM EC_THERM#/GPIO11 GPXO10 PCH_APWROK 14 1
SYSTEM_FAN_FB SA_PGOOD
PCH_PWR_EN 26 SYSTEM_FAN_FB PCH_PWR_EN
28
29
FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 SA_PGOOD 52
+3VS 43 PCH_PWR_EN FANFB2/GPIO15
H_PROCHOT#_EC 23 EC_TX
EC_TX
EC_RX
30 EC_TX/GPIO16 PM_SLP_S4#
23 EC_RX 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# 14
need add 42 ON/OFF#
ON/OFF# 32 ON_OFF/GPIO18 ENBKL/GPXID2 112 ENBKL
ENBKL 14
SUSACK# 34 114 EC_EAPD
14 SUSACK# PWR_LED#/GPIO19 GPXID3 EC_EAPD 24
CE_ENABLE 36 GPI 115 PWRSHARE_EC_EN#
B 20 CE_ENABLE NUMLED#/GPIO1A GPXID4 PWRSHARE_EC_EN# 24 B
116 SUSP#
GPXID5 SUSP# 9,17,43,48,49,50,51
1 2 EC_SMB_CK2 GPXID6 117 PBTN_OUT#
PBTN_OUT# 5,14
R244 2.2K_0402_5% 0_0402_5% 118 PCIE_WAKE#_R 2 1
GPXID7 PCIE_WAKE# 14,21,23,24
1 2 EC_SMB_DA2 EC_CRY1 122 XCLK1
0_0402_5% R227
R247 2.2K_0402_5% 1 2 EC_CRY2 123 124 +V18R
14 SUSCLK_R XCLK0 V18R
R253 1
AGND

C293
GND
GND
GND
GND
GND
1

20P_0402_50V8J~D

1
C1947 4.7U_0805_10V4Z
2
100K_0402_5%

KB930QF A1 LQFP 128P

11
24
35
94
113

69

R1095 20mil
2 L44 U620
2

ECAGND 2 1 EC_ESB_CLK 1 13
FBMA-L11-160808-800LMT_0603 ESB_CLK TEST_EN#

20 EN_INVPWR 2 GPIO00 GPIO08/CAS_DAT 14 EC_ENVDD 20

RST# 3 15
RST# GPIO09
5,44 H_PROCHOT# H_PROCHOT# 1@ 2 VR_HOT# EC_ESB_DAT 4 16
VR_HOT# 54 ESB_DAT GPIO0A
R256 0_0402_5%
5 GPIO01 GPIO0B 17 PWRSHARE_OE# 24
1

D
2 H_PROCHOT#_EC 6 GPIO02 GPIO0C/PWM0 18 WLAN_BT_LED# 27
G
S Q285 7 19
3

2N7002_SOT23 GPIO03 GPIO0D/PWM1

44 Dyn_Turbo_Sel 8 GPIO04 GPIO0E/PWM2 20

6 DRAMRST_CNTRL_EC 9 GPIO05 GPIO0F/PWM3 21

10 GPIO06 GPIO10/ESB_RUN# 22 LCD_TEST 20

SP07000F500 S SOCKET WIESON G6179-100000
SPI ROM 128KB
11 23
8P SPIFLASH 14,20 VGA_LVDDEN GPIO07/CAS_CLK GPIO11/BaseAddOpt 3V_F347_ON 27
60 mil
WIESO_G6179-100000_8P 12 24

GND
+3VALW GND VCC +3VALW

0.1U_0402_16V4Z
U624 1
A 20mils 8 4 KC3810_QFN24_4X4 C294 A

25
VCC VSS @ @
1
C297 3 R257 C296
0.1U_0402_16V4Z W SPI_CLK_R 2
2 1 1 2
7 33_0402_5%
2 HOLD 22P_0402_50V8J
FSEL# 1 2 SPI_FSEL# 1 Reserve for EMI please close to U36
R258 0_0402_5% S
SPI_CLK 1 2 SPI_CLK_R 6
R259 0_0402_5% C
FWR# 1 2 SPI_FWR# 5 2 SPI_SO 1 2 FRD#
R260 0_0402_5% D Q R261 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
MX25L1005AMC-12G SOP 8P 2010/07/12 2011/07/06 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB930/ ENE3810
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-6961P
Date: Tuesday, January 25, 2011 Sheet 25 of 54
5 4 3 2 1
 5 4 3 2 1

+3VS

Skin Thermal Sensor +5VS

0.1U_0402_10V7K~D
1

C1816
C1923
2 +3VS
1 2.2U_0603_6.3V6K~D

2
10K_0402_5%

10K_0402_5%
SENSOR_DIODE_P1 R1796 1 2 0_0402_5%~D REMOTE_P1
U616

2
D R1802 D
1

1
1 C C1815 1 8 PCH_SMLCLK 10K_0402_5%
VDD SMCLK PCH_SMLCLK 13,23,25,31,46

R1800

R1801
2
@ C1814
@C1814 B 470P_0402_50V7K 2 7 PCH_SMLDATA
PCH_SMLDATA 13,23,25,31,46

1
100P_0402_50V8J~D E Q283 2 DP SMDATA JFAN1

1
2 MMBT3904WT1G_SC70-3~D SENSOR_DIODE_N1 R1797 REMOTE_N1
1 2 0_0402_5%~D 3 DN ALERT 6 1 1
25 SYSTEM_FAN_PWM SYSTEM_FAN_PWM 2
R1798 1 SYSTEM_FAN_FB 2
+3VS 2 4.7K_0402_5% 4 THERM#/ADDR GND 5 25 SYSTEM_FAN_FB 2 1 3 3 G5 5
D65 4 6
CH751H-40PT_SOD323-2~D 4 G6
EMC1412-A-ACZL-TR_MSOP8
ACES_85205-04001
CONN@

C C

HDD Connector
JHDD1 Near CONN side.
GND 1
SATA_PTX_DRX_P0_C
HTX+ 2
3 SATA_PTX_DRX_N0_C
SATA_PTX_DRX_P0_C 12
+5VS Pleace near HDD CONN (JHDD1)
HTX- SATA_PTX_DRX_N0_C 12
4 C1085 0.01U_0402_16V7K
GND SATA_PRX_DTX_N0_C 1
HRX- 5 2 SATA_PRX_DTX_N0 SATA_PRX_DTX_N0 12

1000P_0402_25V8J
6 SATA_PRX_DTX_P0_C 1 2 SATA_PRX_DTX_P0
HRX+ SATA_PRX_DTX_P0 12

10U_0805_10V4Z
GND 7 1 1 1 1
C1086 0.01U_0402_16V7K C1087 C1088 C1089
C1090

0.1U_0402_16V4Z

0.1U_0402_16V4Z
2 2 2 2
VCC3.3 8 +3VS
VCC3.3 9
VCC3.3 10
GND 11
12 HDD_DETECT#
GND HDD_DETECT# 16
GND 13
+5VS
VCC5 14
15
40 mils
VCC5
VCC5 16
17 +3VS
GND FFS_INT2_Q
RESERVED 18
19 +5VS
B GND +3VS B
23 GND1 VCC12 20
24 GND2 VCC12 21
VCC12 22
1

10U_0805_10V4Z
1 1
C1195 C1196
LD2822F-SARL6 @ R938
@R938

0.1U_0402_16V4Z
CONN@ 100K_0402_5%~D
2

2 2
G

16,24 FFS_INT2 FFS_INT2 3 1 1 2 FFS_INT2_Q

S

D12
Q83 SDM10U45-7_SOD523-2~D
SSM3K7002FU_SC70-3~D

A A

DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, FAN & Thermal Sensor
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.4
LA-6961P
Date: Tuesday, January 25, 2011 Sheet 26 of 54
5 4 3 2 1
 5 4 3 2 1

+3.3V_F347
+3.3V_F347 +3.3V_F347
R1166 22P_0402_50V8J
1 2
0_0603_5%~D 1 1
C1261
1 1 K/B Backlight

1
C1225 C1226 C13

1
R1051 R1052
1U_0805_10V7 0.1U_0402_16V4Z 2 2 4.7K_0402_1% 4.7K_0402_1% R1053 R1054
AD2 AD1 AD0 +3.3V_F347
2 2 4.7K_0402_1% 4.7K_0402_1%
0.1U_0402_16V4Z
0 0 1

2
+5VALW U41

2
6 2 SPI_MOCLK U42
D +5VS R1185 @ VDD P0.0 SPI_MOSO INT#_1 D
P0.1 1 22 INT#/O16 V+ 21
1 2 0_0603_5%~D USB20_P6 4 32 SPI_MOSI
15 USB20_P6 D+ P0.2
USB20_N6 5 31 SPI_MOCS# I2C_CLK 19 1
15 USB20_N6 D- P0.3 SCL P0 KB_LED_R_DRV# 42
30 I2C_DAT +3.3V_F347 I2C_DAT 20 2
P0.4 SDA P1 KB_LED_G_DRV# 42
W=40mils +3.3V_F347 7 29 I2C_CLK R1055 3
REGIN P0.5 P2 KB_LED_B_DRV# 42
R1186 1 2 0_0603_5%~D 8 28 ELC_NC1 1K_0402_5% AD1_0 18 4
VBUS P0.6 AD1_1 AD0 P3
P0.7 27 1 2 23 AD1 P4 5
+3.3V_F347 R1056 1 2 1K_0402_1% 9 AD1_2 24 6
RST#/C2CK SLP_S3 AD2 P5
1 1 10 P3.0/C2D P1.0 26 P6 7

1
C1227 C1228 +3.3V_F347 25 CHRG_STATE 14 8
P1.1 ACIN# R1057 R1058 P12 P7
18 P2.0 P1.2 24 15 P13 P8 10
1U_0805_10V7 0.1U_0402_16V4Z JP1 17 23 LID_SW_IN# 4.7K_0402_1% 4.7K_0402_1% 16 11
2 2 P2.1 P1.3 LID_SW_IN# 13,24,25 P14 P9
1 1 16 P2.2 P1.4 22 BATT_LOW_LED 25 17 P15 P10 12
2 15 21 SLP_S5 13

2
2 P2.3 P1.5 ELC_NC2 P11
5 G1 3 3 14 P2.4 P1.6 20 9 GND GND 25
6 G2 4 4 13 P2.5 P1.7 19
12 MAX7313ATG+T_TQFN24_4X4
MOLEX_53398-0471~D P2.6
11 P2.7 GND 3
@
C8051F347-GQ_LQFP32_7X7
@ C1200
ELC_NC1 1 2 47P_0402_50V8J~D

@ C1201
ELC_NC2 1 2 47P_0402_50V8J~D

+3.3V_F347
Status Board CONN
1

CONN@
R1059 FCI_10089708-016010LF~D
100K_0402_1% +3.3V_F347 16 18
C 16 GND C
+5VALW 15 15 GND 17
+5VS 14
2

SLP_S3 +3.3V_F347 +3.3V_F347 +3.3V_F347 14

12 PCH_SATALED# 13 13
LID_SW_IN# 12 12
1

D I2C_DAT 11 11

1
2 Q86 1 I2C_CLK 10
14,25 PM_SLP_S3# 10
G 2N7002_SOT23 R1060 C1229 25 CAPS_LED# 9 9
1

2
S 10K_0402_5% 8
3

R1061 R1062 0.1U_0402_16V4Z D17 8

25 WLAN_BT_LED# 7 7
10K_0402_5% 10K_0402_5% 2
PJDLC05C_SOT23-3 42 ON/OFFBTN# 6

2
U43 6
@ 5 5
SPI_MOCS# 1 8 4
2

CE# VDD R1063 1 15_0402_5% SPI_MOCLK 4

3 WP# SCK 6 2 3 3
7 5 R1064 1 2 15_0402_5% SPI_MOSI 2
HOLD# SI R1065 1 15_0402_5% SPI_MOSO 2
4 VSS SO 2 2 24 IO_BOARD_CONN 1 1
+3.3V_F347 1

1
MX25L8005M2C-15G SOP 8P JP2
C1230
1

22P_0402_50V8J~D
2

3
R1066
100K_0402_1% D18
PJSOT24C_SOT23-3
2

SLP_S5
Close to CONN
1

D
Q87
14,25 PM_SLP_S5# 2
G 2N7002_SOT23 +3VALW
60MILS +3.3V_F347
+3.3V_F347 behavior
S @
3

1
J4
2 1
STATE
2 1
B JUMP_43X118 B
S0 S3 S4 S5 DEVICE SMBUS ADDRESS
Q88
+3.3V_F347 SI3456BDV-T1-E3 1N TSOP6
MAXIM - LED 0100 000b
AC IN ON ON ON ON
MAXIM - GPIO 0100 001b
D

6
S
1

5
2
4 BAT only ON ON OFF OFF I2C EEPROM 1010 000b
R1067 1 1

1
100K_0402_1% C1231
G

1 4.7U_0603_6.3V R1068
2

ACIN# C1232 100K_0402_1%

2
1

D 0.1U_0402_16V4Z
Reference AD2 AD1 AD0 MAX7313
2
Q89 +3VALW B+ 2
25,30,46 ACIN 2
G 2N7002_SOT23 R1069
S 100K_0402_1%
3

1 2 DB 0 1 0 L/R Headlight , Logo

R1070 C1233
1

D
0.1U_0402_25V6

100K_0402_1% Q90 RH129

1M_0402_5%

2 1 CAP , Wireless
2

G @
+3.3V_F347
DB 0 1 1
S Power Button , Eyes/Rim
3
1

D
2N7002_SOT23

Q91 2
25 3V_F347_ON 2
1

G 2N7002_SOT23
1

S U6 0 0 1 K/B Backlight
3

R1071 R1072
100K_0402_1% 100K_0402_1%
2

CHRG_STATE
2

A A
1

D
2 Q92
25 CHRG_STATE#
G 2N7002_SOT23
S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/07/25 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ELC/STATUS CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6961P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 25, 2011 Sheet 27 of 54
5 4 3 2 1
 5 4 3 2 1

+HDMI_5V_OUT +HDMI_5V_OUT

F1 D8

2
G
BSS138_SOT23~D 2 1 1 2 +5VS
1
VGA_HDMI_HPD 3 1 1.1A_6VDC_FUSE SS1040_SOD123
30 VGA_HDMI_HPD
C1054

D
Q76 0.1U_0402_16V4Z
W=40mils

1
2
R925
20K_0402_1%
D D

Vgs <=1.5 V

2
31 VGA_HDMI_TX2- VGA_HDMI_TX2- C1059 2 1 0.1U_0402_16V7K HDMI_C_TX2-
31 VGA_HDMI_TX2+ VGA_HDMI_TX2+ C1060 2 1 0.1U_0402_16V7K HDMI_C_TX2+ R903 L51
MBK1608221YZF_2P
31 VGA_HDMI_TX1- VGA_HDMI_TX1- C1061 2 1 0.1U_0402_16V7K HDMI_C_TX1- 1 2 1 2 HP_DETECT
31 VGA_HDMI_TX1+ VGA_HDMI_TX1+ C1062 2 1 0.1U_0402_16V7K HDMI_C_TX1+
10K_0402_5% 1

1
31 VGA_HDMI_TX0- VGA_HDMI_TX0- C1063 2 1 0.1U_0402_16V7K HDMI_C_TX0-

1
VGA_HDMI_TX0+ C1064 2 1 0.1U_0402_16V7K HDMI_C_TX0+ D9 C1058
31 VGA_HDMI_TX0+
R904 BAV99-7-F_SOT23-3 220P_0402_50V7K
VGA_HDMI_CLK- C1065 2
31 VGA_HDMI_CLK- 2 1 0.1U_0402_16V7K HDMI_C_CLK- 100K_0402_5% @
31 VGA_HDMI_CLK+ VGA_HDMI_CLK+ C1066 2 1 0.1U_0402_16V7K HDMI_C_CLK+
PCH_HDMI_HPD#
16 PCH_HDMI_HPD#

3
1

1
R908
499_0402_1%

R909
499_0402_1%

R910
499_0402_1%

R911
499_0402_1%

R912
499_0402_1%

R913
499_0402_1%

R914
499_0402_1%

R916
499_0402_1%

1
D Q77
2
G
S +3VS

3
2N7002_SOT23

0_0402_5%
HDMI Connector

1
D @
+3VS_DGPU 1 2 2
R919 G HDMI_C_TX2- 1 2 C_DVI_R_TXD2- HDMI_C_TX0+ 1 2 C_DVI_R_TXD0+

1
Q78 S R905 0_0402_5% R906 0_0402_5%

3
R920 2N7002_SOT23 @ +HDMI_5V_OUT
100K_0402_5% L53 WCM-2012-900T_4P
3 3 4 4 2 2 1 1
C JHDMI1 C

2
HP_DETECT 19 HP_DET
2 2 1 1 3 3 4 4 18 +5V
17 DDC/CEC_GND
WCM-2012-900T_4P L52 DVI_SDATA 16
DVI_SCLK SDA
15 SCL
HDMI_C_TX2+ 1 2 C_DVI_R_TXD2+ HDMI_C_TX0- 1 2 C_DVI_R_TXD0- 14
R907 0_0402_5% R915 0_0402_5% Reserved
13 CEC
@ @ C_DVI_R_TXC- 12 20
CK- GND
11 CK_shield GND 21
C_DVI_R_TXC+ 10 22
@ C_DVI_R_TXD0- CK+ GND
9 D0- GND 23
+HDMI_5V_OUT HDMI_C_TX1+ 1 2 C_DVI_R_TXD1+ HDMI_C_CLK+ 1 2 C_DVI_R_TXC+ 8
R917 0_0402_5% R918 0_0402_5% C_DVI_R_TXD0+ D0_shield
7 D0+
@ C_DVI_R_TXD1- 6
+3VS_DGPU WCM-2012-900T_4P WCM-2012-900T_4P D1-
5 D1_shield
1

3 4 3 4 C_DVI_R_TXD1+ 4
R924 D15 3 4 3 4 C_DVI_R_TXD2- D1+
3 D2-
0_0402_5% CH751H-40PT_SOD323-2 2
@ C_DVI_R_TXD2+ D2_shield
2 2 1 1 2 2 1 1 1 D2+
2

R463 R465 L54 L55 LOTES_ABA-HDM-029-P01

5V Level
4.7K_0402_5%
4.7K_0402_5% HDMI_C_TX1- 1 2 C_DVI_R_TXD1- HDMI_C_CLK- 1 2 C_DVI_R_TXC- CONN@
+3VS_DGPU
2.2K_0402_5%

2.2K_0402_5%

R921 0_0402_5% R922 0_0402_5%

1

R901 @ @
R900
5

FCM2012CF-800T06_2P
31 VGA_HDMI_DATA 4 3DVI_SDATA_L 1 2 DVI_SDATA
B L49 B
Q284B
2N7002DW-T/R7_SOT363-6
2

FCM2012CF-800T06_2P
1 6 DVI_SCLK_L 1 2 DVI_SCLK
31 VGA_HDMI_CLK
L50
10P_0402_50V8J

10P_0402_50V8J

Q284A 1 1
2N7002DW-T/R7_SOT363-6 C1056 C1057
Place closed to JHDMI1
2 2

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/25 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6961P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 24, 2011 Sheet 28 of 54
5 4 3 2 1
 5 4 3 2 1

+3VS Co-lay +3VS_DP

GPU DDC Dongle SW for DP +3VS_DGPU DP_DDC_DATA_C R469 2 1 100K_0402_5%~D +3VS_DGPU 1

F2
2 +3VS_DP_L +3VS_DP
DP_DDC_CLK_C R470 2 1 100K_0402_5%~D 1

0.1U_0402_16V4Z~D
C1068
2 1 1.5A_6V_1206L150PR~D 1 1

22U_0805_6.3V6M~D

C110

10U_0805_10V4Z~D
C1067
C370 R923 2 @ 1 0_1206_5%~D
0.1U_0402_16V4Z~D 2
U82 2 2
CAB_DET# 1 14
Near to NV
DP_DDC_CLK BE0 VCC CAB_DET
31 DP_DDC_CLK 2 A0 BE3 13 R1236
0.1U_0402_10V7K~D 31 DISP_A0N_VGA C1069 2 1 0.1U_0402_10V6K~D DISP_C_A0N
DPB_GPU_AUX/DDC 3 12 DP_DDC_CLK_C 2 1 C414 DP_DDC_CLK 1 2 100K_0402_5%~D 31 DISP_A0P_VGA C1070 2 1 0.1U_0402_10V6K~D DISP_C_A0P
B0 A3
CAB_DET# 4 11 31 DISP_A1N_VGA C1071 2 1 0.1U_0402_10V6K~D DISP_C_A1N JDP1
DP_DDC_DATA BE1 B3 CAB_DET C1073 2 0.1U_0402_10V6K~D DISP_C_A1P
31 DP_DDC_DATA 5 A1 BE2 10 R1237 31 DISP_A1P_VGA 1
D 0.1U_0402_10V7K~D D
DPB_GPU_AUX#/DDC 6 9 DP_DDC_DATA_C 2 1 C598 DP_DDC_DATA1 2 100K_0402_5%~D 31 DISP_A2N_VGA C1072 2 1 0.1U_0402_10V6K~D DISP_C_A2N
B1 A2 C1074 2 0.1U_0402_10V6K~D DISP_C_A2P
31 DISP_A2P_VGA 1
7 8 DISP_C_A0P 1 LANE0_P
GND B2 C1075 2 0.1U_0402_10V6K~D DISP_C_A3N
31 DISP_A3N_VGA 1 2 GND
PI3C3125LEX_TSSOP14~D 31 DISP_A3P_VGA C1076 2 1 0.1U_0402_10V6K~D DISP_C_A3P DISP_C_A0N 3 LANE0_N
DISP_C_A1P 4 LANE1_P
5

Dongle Normal DISP_C_A1N

DISP_C_A2P
6
7 LANE2_P
GND
LANE1_N

8 GND
DISP_C_A2N 9 LANE2_N
DISP_C_A3P 10 LANE3_P
11 GND
ZZZ DISP_C_A3N 12 LANE3_N
CAB_DET
Place close JDP1 DISP_CEC
13
14 CONFIG1
CONFIG2
@ D10 DPB_GPU_AUX/DDC 15 AUXCH_P
DISP_C_A0P 1 10 DISP_C_A0P +5VS 16 GND
DPB_GPU_AUX#/DDC 17 AUXCH_N
DISP_C_A0N 2 9 DISP_C_A0N 2 1 PCB-MB +3VS DISP_HD 18
12 PCH_DP_HPD HPD
Vgs <=1.5 V 19

2
RETURN

G
DISP_C_A3P 4 7 DISP_C_A3P R1238 10K_0402_5% PCBA@ 20 DP_PWR

1
DISP_C_A3N 5 6 DISP_C_A3N 2 1 3 1 DISP_HD R931 21
30 VGA_DP_HPD
R936

D
22

R932

R933

C1081

C1080
R1234 10K_0402_5% 100K_0402_1%~D

GROUND
3 23

1
Q110 24
8 R1235 BSS138_SOT23~D 1M_0402_5%~D

1
100K_0402_5%~D 1 1
RCLAMP0524P.TCT~D CAB_DET# MOLEX_105088-0001
Close connect CONN@

2
2 2

2
5.1M_0402_5%

1M_0402_5%~D

22U_0805_6.3V6M~D

0.1U_0402_10V6K~D
@ D11

1
DISP_C_A1P D
C 1 10 DISP_C_A1P Q81
C
2
DISP_C_A1N 2 9 DISP_C_A1N Follow Intel HPD design rev 1.6 G
S

3
DISP_C_A2P 4 7 DISP_C_A2P 2N7002_SOT23

1
DISP_C_A2N 5 6 DISP_C_A2N R937

3
1M_0402_5%~D

2
8

RCLAMP0524P.TCT~D @

B B

A A

DELL CONFIDENTIAL/PROPRIETARY
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/07/25 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DP/FAN/HDD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6961P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 24, 2011 Sheet 29 of 54

5 4 3 2 1
 5 4 3 2 1

UV1A
PEG_GTX_C_HRX_P[0..15]
4 PEG_GTX_C_HRX_P[0..15]
PEG_HTX_C_GRX_P0 AP17 Part 1 of 7 K1
PEG_HTX_C_GRX_N0 PEX_RX0 GPIO0 dGPU_DP_HPD
AN17 PEX_RX0_N GPIO1 K2
PEG_HTX_C_GRX_P1 AN19 K3 PEG_GTX_C_HRX_N[0..15]
PEX_RX1 GPIO2 4 PEG_GTX_C_HRX_N[0..15]
PEG_HTX_C_GRX_N1 AP19 H3
PEG_HTX_C_GRX_P2 PEX_RX1_N GPIO3
AR19 PEX_RX2 GPIO4 H2
PEG_HTX_C_GRX_N2 AR20 H1 GPU_VID0 PEG_HTX_C_GRX_P[0..15]
PEX_RX2_N GPIO5 GPU_VID0 53 4 PEG_HTX_C_GRX_P[0..15]
PEG_HTX_C_GRX_P3 AP20 H4 GPU_VID1
PEX_RX3 GPIO6 GPU_VID1 53
PEG_HTX_C_GRX_N3 AN20 H5
PEG_HTX_C_GRX_P4 PEX_RX3_N GPIO7 GPIO8 PEG_HTX_C_GRX_N[0..15]
AN22 PEX_RX4 GPIO8 H6 4 PEG_HTX_C_GRX_N[0..15]
PEG_HTX_C_GRX_N4 AP22 J7 THERM#_VGA
PEX_RX4_N GPIO9 THERM#_VGA 31
PEG_HTX_C_GRX_P5 AR22 K4
PEG_HTX_C_GRX_N5 PEX_RX5 GPIO10 D25 @
AR23 PEX_RX5_N GPIO11 K5
PEG_HTX_C_GRX_P6 GPIO12

GPIO
AP23 PEX_RX6 GPIO12 H7 2 1 ACIN 25,27,46
D PEG_HTX_C_GRX_N6 AN23 J4 D
PEX_RX6_N GPIO13 TV6
PEG_HTX_C_GRX_P7 AN25 J6 CH751H-40PT_SOD323-2
PEG_HTX_C_GRX_N7 PEX_RX7 GPIO14 dGPU_HDMI_HPD
AP25 PEX_RX7_N GPIO15 L1
PEG_HTX_C_GRX_P8 AR25 L2 +3VS_DGPU
PEG_HTX_C_GRX_N8 PEX_RX8 GPIO16 CV117
Under GPU(Place near balls) AR26 PEX_RX8_N GPIO17 L4
150mA PEG_HTX_C_GRX_P9 AP26 M4 1 2
BLM18PG330SN1D_0603 PEG_HTX_C_GRX_N9 PEX_RX9 GPIO18
AN26 PEX_RX9_N GPIO19 L7

5
+1.05VS_DGPU 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M +PLLVDD PEG_HTX_C_GRX_P10 AN28 L5 UV13 0.1U_0402_16V4Z
LV1 PEG_HTX_C_GRX_N10 PEX_RX10 GPIO20
AP28 K6 2

P
PEX_RX10_N GPIO21 B DGPU_PWROK 15,16,53
1 1 1 1 2 PEG_HTX_C_GRX_P11 AR28 L6 4
CV86 CV85 CV11 CV12 CV99 PEG_HTX_C_GRX_N11 PEX_RX11 GPIO22 Y
AR29 PEX_RX11_N GPIO23 M6 A 1 VGA_HDMI_HPD 28

G
PEG_HTX_C_GRX_P12 AP29 M7
PEG_HTX_C_GRX_N12 PEX_RX12 GPIO24
AN29

3
2 2 2 2 1 PEG_HTX_C_GRX_P13 PEX_RX12_N NC7SZ08P5X_NL_SC70-5
AN31 PEX_RX13 MIOA_D0_NC N1
PEG_HTX_C_GRX_N13 AP31 P4
0.1U_0402_16V4Z 0.1U_0402_16V4Z PEG_HTX_C_GRX_P14 PEX_RX13_N MIOA_D1_NC
AR31 PEX_RX14 MIOA_D2_NC P1
PEG_HTX_C_GRX_N14 AR32 P2
PEG_HTX_C_GRX_P15 PEX_RX14_N MIOA_D3_NC
AR34 PEX_RX15 MIOA_D4_NC P3
PEG_HTX_C_GRX_N15 AP34 T3
PEX_RX15_N MIOA_D5_NC
MIOA_D6_NC T2
MIOA_D7_NC T1
PEG_GTX_C_HRX_P0 CV13 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_P0 AL17 U4 +3VS_DGPU
PEX_TX0 MIOA_D8_NC

PCI EXPRESS
PEG_GTX_C_HRX_N0 CV14 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N0 AM17 U1 CV118
PEG_GTX_C_HRX_P1 CV15 0.1U_0402_10V7K~D PEG_GTX_CRX_P1 PEX_TX0_N MIOA_D9_NC
1 2 AM18 PEX_TX1 MIOA_D10_NC U2 1 2
PEG_GTX_C_HRX_N1 CV16 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N1 AM19 U3
PEX_TX1_N MIOA_D11_NC

5
PEG_GTX_C_HRX_P2 CV17 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_P2 AL19 R6 UV14 0.1U_0402_16V4Z
PEG_GTX_C_HRX_N2 CV18 0.1U_0402_10V7K~D PEG_GTX_CRX_N2 PEX_TX2 MIOA_D12_NC
1 2 AK19 T6 2

DVO

P
PEX_TX2_N MIOA_D13_NC B DGPU_PWROK 15,16,53
PEG_GTX_C_HRX_P3 CV19 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_P3 AL20 N6 dGPU_DP_HPD 4
PEG_GTX_C_HRX_N3 CV20 0.1U_0402_10V7K~D PEG_GTX_CRX_N3 PEX_TX3 MIOA_D14_NC Y
1 2 AM20 PEX_TX3_N A 1 VGA_DP_HPD 29

G
PEG_GTX_C_HRX_P4 CV21 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_P4 AM21 Y1
PEG_GTX_C_HRX_N4 CV22 0.1U_0402_10V7K~D PEG_GTX_CRX_N4 PEX_TX4 MIOB_D0_NC
1 2 AM22 Y2

3
PEG_GTX_C_HRX_P5 CV23 0.1U_0402_10V7K~D PEG_GTX_CRX_P5 PEX_TX4_N MIOB_D1_NC NC7SZ08P5X_NL_SC70-5
1 2 AL22 PEX_TX5 MIOB_D2_NC Y3
C PEG_GTX_C_HRX_N5 CV24 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N5 AK22 AB3 C
PEG_GTX_C_HRX_P6 CV25 0.1U_0402_10V7K~D PEG_GTX_CRX_P6 PEX_TX5_N MIOB_D3_NC
1 2 AL23 PEX_TX6 MIOB_D4_NC AB2
PEG_GTX_C_HRX_N6 CV26 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N6 AM23 AB1
PEG_GTX_C_HRX_P7 CV27 0.1U_0402_10V7K~D PEG_GTX_CRX_P7 PEX_TX6_N MIOB_D5_NC
1 2 AM24 PEX_TX7 MIOB_D6_NC AC4
PEG_GTX_C_HRX_N7 CV28 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N7 AM25 AC1
PEG_GTX_C_HRX_P8 CV29 0.1U_0402_10V7K~D PEG_GTX_CRX_P8 PEX_TX7_N MIOB_D7_NC
1 2 AL25 PEX_TX8 MIOB_D8_NC AC2
PEG_GTX_C_HRX_N8 CV30 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N8 AK25 AC3
PEG_GTX_C_HRX_P9 CV31 0.1U_0402_10V7K~D PEG_GTX_CRX_P9 PEX_TX8_N MIOB_D9_NC
1 2 AL26 PEX_TX9 MIOBD_10_NC AE3
PEG_GTX_C_HRX_N9 CV32 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N9 AM26 AE2
PEG_GTX_C_HRX_P10 CV33 0.1U_0402_10V7K~D PEG_GTX_CRX_P10 PEX_TX9_N MIOB_D11_NC
1 2 AM27 PEX_TX10 MIOB_D12_NC U6
PEG_GTX_C_HRX_N10 CV34 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N10 AM28 W6
PEG_GTX_C_HRX_P11 CV35 0.1U_0402_10V7K~D PEG_GTX_CRX_P11 PEX_TX10_N MIOB_D13_NC
1 2 AL28 PEX_TX11 MIOB_D14_NC Y6
PEG_GTX_C_HRX_N11 CV36 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N11 AK28
PEG_GTX_C_HRX_P12 CV37 0.1U_0402_10V7K~D PEG_GTX_CRX_P12 PEX_TX11_N
1 2 AK29 PEX_TX12 MIOA_HSYNC_NC N3
PEG_GTX_C_HRX_N12 CV38 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N12 AL29 L3
PEG_GTX_C_HRX_P13 CV39 0.1U_0402_10V7K~D PEG_GTX_CRX_P13 PEX_TX12_N MIOA_VSYNC_NC
1 2 AM29 PEX_TX13
PEG_GTX_C_HRX_N13 CV40 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N13 AM30 W1
PEG_GTX_C_HRX_P14 CV41 0.1U_0402_10V7K~D PEG_GTX_CRX_P14 PEX_TX13_N MIOB_HSYNC_NC
1 2 AM31 PEX_TX14 MIOB_VSYNC_NC W2
PEG_GTX_C_HRX_N14 CV42 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N14 AM32
PEG_GTX_C_HRX_P15 CV43 0.1U_0402_10V7K~D PEG_GTX_CRX_P15 PEX_TX14_N
1 2 AN32 PEX_TX15 MIOA_DE_NC N2
PEG_GTX_C_HRX_N15 CV44 1 2 0.1U_0402_10V7K~D PEG_GTX_CRX_N15 AP32 P5
PEX_TX15_N MIOA_CTL3_NC
MIOA_VREF_NC N5
+3VS_DGPU

MIOB_DE_NC Y5
13 CLK_PEG_VGA CLK_PEG_VGA AR16 W3
CLK_PEG_VGA# PEX_REFCLK MIOB_CTL3_NC
13 CLK_PEG_VGA# AR17 PEX_REFCLK_N MIOB_VREF_NC AF1
CLK_REQ_GPU# AR13 GPIO8 1 2
PEX_CLKREQ_N RV4 10K_0402_5%
MIOA_CLKIN_NC N4 1 2
@ PEX_TSTCLK_OUT RV15 10K_0402_5%
Differential signal 1
RV16
2
200_0402_1% PEX_TSTCLK_OUT#
AJ17
AJ18
PEX_TSTCLK_OUT MIOA_CLKOUT_NC R4
GPIO12 1 2
PEX_TSTCLK_OUT_N RV5 10K_0402_5%
MIOB_CLKIN_NC AE1 1 2
V4 RV17 10K_0402_5% I2CC_SCL 1 2
B PLTRST_VGA_R# MIOB_CLKOUT_NC RV6 2.2K_0402_5% B
15 PLTRST_VGA# 1 2 AM16 PEX_RST_N
RV18 0_0402_5% AG21 T4 I2CC_SDA 1 2
PEX_TERMP MIOA_CLKOUT_NC_N RV7 2.2K_0402_5%
1 2 MIOB_CLKOUT_NC_N W4
RV19 2.49K_0402_1%
1 2 60mA U5 SMB_CLK_GPU 1 2
RV28 10M_0402_5% +PLLVDD MIOACAL_PD_VDDQ_NC RV8 2.2K_0402_5%
AE9 PLLVDD MIOACAL_PU_GND_NC T5
45mA SMB_DATA_GPU 1 2
YV1 AF9 AA7 RV9 2.2K_0402_5%
SP_PLLVDD MIOBCAL_PD_VDDQ_NC THERM#_VGA
XTALIN XTAL_OUT
45mA MIOBCAL_PU_GND_NC AA6 1
RV10
2
@ 100K_0402_5%
1 2 AD9 VID_PLLVDD HDCP_SCL
CLK

1 2
27MHZ_16PF_X5H027000FG1H XTALIN B1 RV11 2.2K_0402_5%
XTAL_OUT XTAL_IN HDCP_SDA
1 1 B2 XTAL_OUT DACA_RED AM15 1 2
CV45 CV46 AM14 RV12 2.2K_0402_5%
18P_0402_50V8J 18P_0402_50V8J XTALOUT DACA_GREEN I2CA_SCL
D1 XTAL_OUTBUFF DACA_BLUE AL14 1 2
2 1 XTALSSIN D2 XTAL_SSIN
RV13 2.2K_0402_5%
1

2 2 RV25 10K_0402_5% I2CA_SDA

DACA_HSYNC AM13 1 2
RV26 AL13 RV14 2.2K_0402_5%
10K_0402_5% DACA_VSYNC I2CB_SCL
Internal Thermal Sensor 1 2
31 SMB_CLK_GPU SMB_CLK_GPU E2 AJ12 RV121 2.2K_0402_5%
SMB_DATA_GPU E1 I2CS_SCL DACA_VDD I2CB_SDA
31 SMB_DATA_GPU AK12 1 2
2

I2CS_SDA DACA_VREF RV122 2.2K_0402_5%

DACA_RSET AK13

1
I2CC_SCL E3 I2CC_SCL
DACs

I2CC_SDA E4 AK4 RV27

I2CC_SDA DACB_RED 10K_0402_5%
DACB_GREEN AL4
+3VS_DGPU I2CB_SCL G3 AJ4
15,33,43,53 DGPU_PWR_EN I2CB_SCL DACB_BLUE
I2CB_SDA
I2C

G2

2
I2CB_SDA
DACB_HSYNC AM1
2

I2CA_SCL G1 AM2
RV126 @ I2CA_SDA I2CA_SCL DACB_VSYNC
G4 I2CA_SDA
2

10K_0402_5% AG7
RV118 HDCP_SCL DACB_VDD
F6 I2CH_SCL DACB_VREF AK6

1
A 10K_0402_5% HDCP_SDA G6 AH7 A
2 1

I2CH_SDA DACB_RSET RV31

10K_0402_5%
G

QV2 @
13 CLK_REQ_VGA# 1 3 1 2 CLK_REQ_GPU# N12P-GV1-A1_BGA_973P
2

RV20 0_0402_5%
D

2N7002_SOT23-3
RV123
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title
VGA(1/12)-PCIE/DAC/GPIO
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 30 of 54
5 4 3 2 1
 5 4 3 2 1

UV1D

Part 4 of 7
AM11 IFPA_TXC NC_0 A2
AM12 IFPA_TXC_N NC_1 A7 Internal Thermal Sensor
AM8 B7
AL8
IFPA_TXD0
IFPA_TXD0_N
NC_2
NC_3 C5 External VGA Thermal Sensor SMB_CLK_GPU 30
AM10 IFPA_TXD1 NC_4 C7 SMB_DATA_GPU 30
AM9 IFPA_TXD1_N NC_5 D5
AK10 IFPA_TXD2 NC_6 D6

1
AL10 IFPA_TXD2_N NC_7 D7
AK11 E5 RV33 RV34
IFPA_TXD3 NC_8
D
AL11 IFPA_TXD3_N NC_9 E7 0_0402_5% 0_0402_5% D
NC_10 F4
G5

2
NC_11 +3VS_DGPU
AP13
AN13
IFPB_TXC NC_12 H32
J25 UV2
Address: 0x9A H
IFPB_TXC_N NC_13 VGA_SMB_CK2
AN8 IFPB_TXD4 NC_14 J26 2 1 1 VDD SCLK 8
AP8 P6 CV53 0.1U_0402_16V4Z
IFPB_TXD4_N NC_15 THERM_D+ VGA_SMB_DA2
AP10 IFPB_TXD5 NC_16 U7 2 D+ SDATA 7
AN10 V6 CV54
IFPB_TXD5_N NC_17 THERM#_VGA
AR11 IFPB_TXD6 NC_18 Y4 1 2 3 D- ALERT# 6 THERM#_VGA 30
AR10 IFPB_TXD6_N NC_19 AA4
AN11 AB4 THERM_D- 2200P_0402_50V7K 4 5
IFPB_TXD7 NC_20 THERM# GND
AP11 IFPB_TXD7_N NC_21 AB7 1 2 +3VS_DGPU
AC5 RV54 10K_0402_5%
NC_22

NC
AD6 ADM1032ARMZ-2REEL_MSOP8
NC_23
29 DISP_A0P_VGA AM7 IFPC_L0 NC_24 AF6
29 DISP_A0N_VGA AM6 IFPC_L0_N NC_25 AG6
29 DISP_A1P_VGA AL5 IFPC_L1 NC_26 AG20
29 DISP_A1N_VGA AM5 IFPC_L1_N NC_27 AJ5
AM3 AK15
DP 29 DISP_A2P_VGA
29 DISP_A2N_VGA AM4
IFPC_L2
IFPC_L2_N
NC_28
NC_29 AL7
29 DISP_A3P_VGA AP1 IFPC_L3
AR2 +3VS_DGPU
29 DISP_A3N_VGA IFPC_L3_N
+3VS_DGPU
AR8 IFPD_L0

2
AR7 IFPD_L0_N
AP7 RV22 RV24
IFPD_L1 2.2K_0402_5% 2.2K_0402_5%
AN7 IFPD_L1_N
AN5 IFPD_L2

2
LVDS/TMDS
C AP5 C

1
IFPD_L2_N
AR5 IFPD_L3
AR4 VGA_SMB_CK2 1 6
IFPD_L3_N PCH_SMLCLK 13,23,25,26,46

5
QV1A
28 VGA_HDMI_TX2+ VGA_HDMI_TX2+ AH6 2N7002DW-T/R7_SOT363-6
VGA_HDMI_TX2- IFPE_L0 VGA_SMB_DA2
28 VGA_HDMI_TX2- AH5 IFPE_L0_N 4 3 PCH_SMLDATA 13,23,25,26,46
28 VGA_HDMI_TX1+ VGA_HDMI_TX1+ AH4
VGA_HDMI_TX1- IFPE_L1 QV1B
AG4
HDMI 28 VGA_HDMI_TX1-
28 VGA_HDMI_TX0+ VGA_HDMI_TX0+ AF4
IFPE_L1_N
IFPE_L2
2N7002DW-T/R7_SOT363-6 PU AT EC SIDE, +3VS AND 4.7K
28 VGA_HDMI_TX0- VGA_HDMI_TX0- AF5
VGA_HDMI_CLK+ IFPE_L2_N
28 VGA_HDMI_CLK+ AE6 IFPE_L3
28 VGA_HDMI_CLK- VGA_HDMI_CLK- AE5 IFPE_L3_N

VDD_SENSE_0 D35 +VGASENSE_1 1 2 +VGASENSE 53

AL2 P7 RV21 0_0402_5%
IFPF_L0 VDD_SENSE_1
AL3 IFPF_L0_N VDD_SENSE_2 AD20 @
AJ3 IFPF_L1
AJ2 IFPF_L1_N
AJ1 IFPF_L2
AH1 IFPF_L2_N GND_SENSE_0 AD19
AH2 IFPF_L3 GND_SENSE_1 E35
AH3 IFPF_L3_N GND_SENSE_2 R7
+3VS_DGPU

DP_DDC_CLK AP2 1 2 VGA_HDMI_CLK

29 DP_DDC_CLK IFPC_AUX_I2CW_SCL
DP_DDC_DATA RV119 4.7K_0402_5%
DP 29 DP_DDC_DATA AN3 IFPC_AUX_I2CW_SDA_N TEST RV47 @
1 2 VGA_HDMI_DATA
B B
AP4 AP35 TESTMODE 1 2 RV120 4.7K_0402_5%
IFPD_AUX_I2CX_SCL TESTMODE
AN4 IFPD_AUX_I2CX_SDA_N JTAG_TCK AP14 TV2 @
JTAG_TDI AN14 TV3 10K_0402_5%
JTAG_TDO AN16 TV4
VGA_HDMI_CLK
HDMI 28 VGA_HDMI_CLK
VGA_HDMI_DATA
AE4
AD4
IFPE_AUX_I2CY_SCL JTAG_TMS AR14
AP16 1 2
TV5
28 VGA_HDMI_DATA IFPE_AUX_I2CY_SDA_N JTAG_TRST_N RV41 10K_0402_5%

AF3 IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N SERIAL ROM_SCLK
ROM_CS_N C3
D3 ROM_SI ROM_SI 41
+3VS_DGPU ROM_SI ROM_SO
ROM_SO C4 ROM_SO 41
D4 ROM_SCLK ROM_SCLK 41 1
ROM_SCLK
2

C599
RV113
10K_0402_5%
GENERAL A5 1 2
2
68P_0402_50V8J
NC/SPDIF_NC RV49 36K_0402_5%
A4 BUFRST_N
N9 1 2
1

MULTI_STRAP_REF0_GND RV48 40.2K_0402_1%

AB5 CEC
MULTI_STRAP_REF1_GND M9 1 2
41 STRAP0 STRAP0 W5 RV50 40.2K_0402_1%
STRAP1 STRAP0 THERM_D+
41 STRAP1 W7 STRAP1 THERMDP B5
41 STRAP2 STRAP2 V7 B4 THERM_D-
STRAP2 THERMDN

A A
N12P-GV1-A1_BGA_973P

Security Classification Compal Secret Data X76 Compal Electronics, Inc.

Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(2/12)-LVDS/HDMI/DP/THM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Tuesday, January 25, 2011 Sheet 31 of 54
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE C1184 1 2 0.1U_0402_10V7K~D +1.05VS +VCC_CORE C1186 1 2 0.1U_0402_10V7K~D +1.05VS

+VCC_GFXCORE_AXG C1185 1 2 0.1U_0402_10V7K~D +VCC_CORE +VCC_CORE C1190 1 2 0.1U_0402_10V7K~D +1.05VS Near GPU
+VGA_CORE
+VCC_GFXCORE_AXG C1187 1 2 0.1U_0402_10V7K~D +VCC_CORE
47U_0805_4V6 10U_0603_6.3V6M 4.7U_0603_6.3V6K
1
+VCC_GFXCORE_AXG C1188 1 2 0.1U_0402_10V7K~D +VCC_CORE 1 1 1 1 1
CV57 + CV912 CV64 CV66 CV213
D D
CV318
30.5A 470U_D2_2V-M~D 2 3 2 2 2 2 2

+VGA_CORE +VGA_CORE 22U_0805_6.3V6M 10U_0603_6.3V6M

UV1G

AB11 VDD_0 VDD_56 P21

AB13 Part 7 of 7 P23
VDD_1 VDD_57
AB15 VDD_2 VDD_58 P25
AB17 VDD_3 VDD_59 R11
AB19 VDD_4 VDD_60 R12
AB21 VDD_5 VDD_61 R13
AB23 VDD_6 VDD_62 R14
AB25 VDD_7 VDD_63 R15
AC11 VDD_8 VDD_64 R16
AC12 VDD_9 VDD_65 R17
AC13 VDD_10 VDD_66 R18
AC14 VDD_11 VDD_67 R19
AC15 R20
AC16
VDD_12
VDD_13
VDD_68
VDD_69 R21 Under GPU
AC17 VDD_14 VDD_70 R22
AC18 R23 +VGA_CORE
VDD_15 VDD_71
AC19 VDD_16 VDD_72 R24
AC20 VDD_17 VDD_73 R25
AC21 T12 0.1U_0402_16V4Z 0.047U_0402_25V6K
VDD_18 VDD_74
C AC22 VDD_19 VDD_75 T14 C
AC23 VDD_20 VDD_76 T16 1 1 1 1 1
AC24 T18 CV295 CV296 CV73 CV74 CV75
VDD_21 VDD_77
AC25 VDD_22 VDD_78 T20
AD12 VDD_23 VDD_79 T22
2 2 2 2 2
AD14 VDD_24 VDD_80 T24
AD16 VDD_25 VDD_81 V11
AD18 VDD_26 VDD_82 V13
AD22 VDD_27 VDD_83 V15
AD24 V17 0.1U_0402_16V4Z 0.047U_0402_25V6K 0.047U_0402_25V6K
VDD_28 VDD_84
L11 VDD_29 VDD_85 V19
L12 VDD_30 VDD_86 V21
L13 VDD_31 VDD_87 V23
L14 VDD_32 VDD_88 V25
L15 W11 +VGA_CORE +VGA_CORE
VDD_33 VDD_89
L16 VDD_34 VDD_90 W12
L17 VDD_35 VDD_91 W13
L18 VDD_36 VDD_92 W14
L19 VDD_37 VDD_93 W15
L20 W16 0.022U_0402_25V7K 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K
VDD_38 VDD_94
L21 VDD_39 VDD_95 W17
L22 W18 CV80 1 CV81 1 CV119 1 1
VDD_40 VDD_96

1
L23 W19 CV72 CV913 CV914 CV915
VDD_41 VDD_97
L24 VDD_42 VDD_98 W20
L25 W21

2
VDD_43 VDD_99 2 2 2 2
M12 VDD_44 VDD_100 W22
M14 VDD_45 VDD_101 W23
B M16 W24 0.022U_0402_25V7K B
VDD_46 VDD_102 0.022U_0402_25V7K 1U_0402_6.3V4Z 0.22U_0402_6.3V6K
M18 VDD_47 VDD_103 W25
M20 VDD_48 VDD_104 Y12
M22 VDD_49 VDD_105 Y14
M24 VDD_50 VDD_106 Y16
P11 VDD_51 VDD_107 Y18
P13 VDD_52 VDD_108 Y20
P15 VDD_53 VDD_109 Y22
P17 VDD_54 VDD_110 Y24
P19 VDD_55
+VGA_CORE

0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K

N12P-GV1-A1_BGA_973P 1 1 1 1 1 1 1 1
CV105 CV115 CV116 CV120 CV121 CV127 CV128 CV130

2 2 2 2 2 2 2 2

0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K 0.01U_0402_25V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(3/12)-VGA CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 32 of 54
5 4 3 2 1
 5 4 3 2 1

UV1E
3.5A Part 5 of 7 2500mA Place near balls Place near GPU
+VRAM_1.5VS 4.7U_0603_6.3V6K 1U_0402_6.3V6K J23 AG11 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M +1.05VS_DGPU
FBVDDQ_0 PEX_IOVDDQ_0
J24 FBVDDQ_1 PEX_IOVDDQ_1 AG12
1 1 1 1 J29 FBVDDQ_2 PEX_IOVDDQ_2 AG13 1 1 1 1 1 1 1
CV82 CV83 CV197 CV214 AA27 AG15 CV3
FBVDDQ_3 PEX_IOVDDQ_3 CV87 CV88 CV89 CV90 CV91 CV92
AA29 FBVDDQ_4 PEX_IOVDDQ_4 AG16
4.7U_0603_6.3V6K AA31 AG17 22U_0805_6.3V6M
2 2 2 2 FBVDDQ_5 PEX_IOVDDQ_5 2 2 2 2 2 2 2
AB27 FBVDDQ_6 PEX_IOVDDQ_6 AG18
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22
1U_0402_6.3V6K AC27 AG23 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
FBVDDQ_8 PEX_IOVDDQ_8
D
AD27 FBVDDQ_9 PEX_IOVDDQ_9 AG24 D
Under GPU(below 150mils) AE27 FBVDDQ_10 PEX_IOVDDQ_10 AG25
AJ28 FBVDDQ_11 PEX_IOVDDQ_11 AG26
B18 FBVDDQ_12 PEX_IOVDDQ_12 AJ14
+VRAM_1.5VS0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z E21 FBVDDQ_13 PEX_IOVDDQ_13 AJ15 0.1U_0402_16V4Z 1U_0402_6.3V4Z 10U_0603_6.3V6M +1.05VS_DGPU
G17 FBVDDQ_14 PEX_IOVDDQ_14 AJ19
1 1 1 1 1 1 1 1 G18 FBVDDQ_15 PEX_IOVDDQ_15 AJ21 1 1 1 1 1 1 1
G22 AJ22 CV220 CV111 CV4
CV124 CV136 CV123 CV126 CV104 CV125 CV102 CV103 FBVDDQ_16 PEX_IOVDDQ_16 CV95 CV96 CV97 CV98
G8 FBVDDQ_17 PEX_IOVDDQ_17 AJ24
G9 AJ25 22U_0805_6.3V6M
2 2 2 2 2 2 2 2 FBVDDQ_18 PEX_IOVDDQ_18 2 2 2 2 2 2 2
H29 FBVDDQ_19 PEX_IOVDDQ_19 AJ27
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z J15 AK20 0.1U_0402_16V4Z 1U_0402_6.3V4Z 4.7U_0603_6.3V6K
FBVDDQ_21 PEX_IOVDDQ_21
J16 FBVDDQ_22 PEX_IOVDDQ_22 AK23
J17 FBVDDQ_23 PEX_IOVDDQ_23 AK26
J20 FBVDDQ_24 PEX_IOVDDQ_24 AL16
J21 FBVDDQ_25 Under GPU(below 150mils) Place near GPU
J22 FBVDDQ_26
N27 LV4
FBVDDQ_27 1U_0402_6.3V4Z
P27 FBVDDQ_28 PEX_IOVDD_0 AK16 2 1 +1.05VS_DGPU
R27 FBVDDQ_29 PEX_IOVDD_1 AK17
T27 AK21 1 1 1 BLM18PG121SN1D_0603 1
FBVDDQ_30 PEX_IOVDD_2 CV109
U27 FBVDDQ_31 PEX_IOVDD_3 AK24
U29 AK27 CV106 CV107 CV108
FBVDDQ_32 PEX_IOVDD_4 4.7U_0603_6.3V6K
V27 FBVDDQ_33 120mA 2 2 2 4.7U_0603_6.3V6K 2
V29 FBVDDQ_34
V34 FBVDDQ_35
W27 AG14 +PEX_PLLVDD 0.1U_0402_16V4Z
FBVDDQ_36 PEX_PLLVDD
Y27 FBVDDQ_37 +3VS_DGPU
C
1 2 +IFPAB_PLLVDD AK9 AG19
240mA (120mA each) 0.1U_0402_16V4Z 1U_0402_6.3V6K
C

RV101 10K_0402_5% IFPAB_PLLVDD PEX_SVDD_3V3

AJ11 IFPAB_RSET PEX_SVDD_3V3_NC F7
+3VS_DGPU
1 1 1 1

1 2 +IFPAB_IOVDD AG9
120mA(12~16mils) CV110 CV218 CV261 CV219
RV107 10K_0402_5% IFPA_IOVDD 0.1U_0402_16V4Z 1U_0402_6.3V6K
AG10 IFPB_IOVDD VDD33_0 J10
2 2 2 2
VDD33_1 J11
220mA VDD33_2 J12 1 1 1 1 1
+IFPC_PLLVDD AJ9 J13 CV114 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
IFPC_PLLVDD VDD33_3 CV217 CV216 CV112 C912
1 2 AK7 IFPC_RSET VDD33_4 J9
RV109 1K_0402_5%~D 285mA 4.7U_0603_6.3V6K
+IFPC_IOVDD 2 2 2 2 2
AJ8 IFPC_IOVDD Place near GPU
P9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+IFPD_PLLVDD MIOA_VDDQ_NC_0
1 2 AC6 IFPD_PLLVDD MIOA_VDDQ_NC_1 R9

2
RV110 10K_0402_5% Under GPU(Place near balls)
AB6 IFPD_RSET MIOA_VDDQ_NC_2 T9
U9
Place near GPU
+IFPD_IOVDD MIOA_VDDQ_NC_3 RV124
1 2 AK8 IFPD_IOVDD
RV114 10K_0402_5%
220mA AA9 10K_0402_5% +3VS_DGPU

1
+IFPEF_PLLVDD MIOB_VDDQ_NC_0 +3VS +3VS_DGPU
AJ6 IFPEF_PLLVDD MIOB_VDDQ_NC_1 AB9
1 2 AL1 IFPEF_RSET MIOB_VDDQ_NC_2 W9
RV116 1K_0402_5%~D 285mA Y9
+IFPE_IOVDD MIOB_VDDQ_NC_3
AE7 IFPE_IOVDD

2
AD7 IFPF_IOVDD QV5
RV125
10K_0402_5% SI7121DN-T1-GE3_POWERPAK8-5

+3VALW
1 60mil(1.4A)
2

1
B B
N12P-GV1-A1_BGA_973P 3 5

470_0603_5%
Under GPU(below 150mils)

2
220mA

2
LV13 +1.05VS_DGPU RQ1
285mA

3VS_Dgate
+3VS_DGPU 2 1 +IFPC_PLLVDD LV5 RQ2
BLM18PG181SN1D_0603 2 1 +IFPC_IOVDD 100K_0402_5%
BLM18PG181SN1D_0603 RQ3

1
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1K_0402_5%

1
1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 2 1
CV442

CV443

CV444

CV908

CV436

CV437

CV446

CV445

CV909

1
RQ4 D

1
D QV4 2 3VS_Dgate
2 2 2 2 2 2 2 2 2 QV3 SSM3K7002FU_SC70-3 G
15,30,43,53 DGPU_PWR_EN 1 2 2
10K_0402_5% G 1 S

3
1 S SSM3K7002FU_SC70-3 QC7

3
QC6 0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D 2
+1.05VS_DGPU 2
LV6 285mA
2 1 +IFPE_IOVDD
BLM18PG181SN1D_0603
4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

220mA
1U_0402_6.3V6K

LV14 1 1 1 1
CV439

CV451

CV450

CV911

+3VS_DGPU 2 1 +IFPEF_PLLVDD
BLM18PG181SN1D_0603
2 2 2 2
4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V6K

A 1 1 1 1 1 A
CV438

CV449

CV448

CV447

CV910

2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(4/12)-POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 33 of 54
5 4 3 2 1
 5 4 3 2 1

UV1F

B3 Part 6 of 7
GND_0
B6 GND_1 GND_97 V18
B9 GND_2 GND_98 V20
B12 GND_3 GND_99 V22
B15 GND_4 GND_100 V24
B21 GND_5 GND_101 V31
B24 GND_6 GND_102 Y11
B27 GND_7 GND_103 Y13
B30 GND_8 GND_104 Y15
B33 GND_9 GND_105 Y17
D
C2 GND_10 GND_106 Y19 D
C34 GND_11 GND_107 Y21
E6 GND_12 GND_108 Y23
E9 GND_13 GND_109 Y25
E12 GND_14 GND_110 AA2
E15 GND_15 GND_111 AA5
E18 GND_16 GND_112 AA11
E24 GND_17 GND_113 AA12
E27 GND_18 GND_114 AA13
E30 GND_19 GND_115 AA14
F2 GND_20 GND_116 AA15
F31 GND_21 GND_117 AA16
F34 GND_22 GND_118 AA17
F5 GND_23 GND_119 AA18
J2 GND_24 GND_120 AA19
J5 GND_25 GND_121 AA20
J31 GND_26 GND_122 AA21
J34 GND_27 GND_123 AA22
K9 GND_28 GND_124 AA23
L9 GND_29 GND_125 AA24
M2 GND_30 GND_126 AA25
M5 GND_31 GND_127 AA34
M11 GND_32 GND_128 AB12
M13 GND_33 GND_129 AB14
M15 GND_34 GND_130 AB16
M17 GND_35 GND_131 AB18
M19 GND_36 GND_132 AB20
M21 GND_37 GND_133 AB22
M23 GND_38 GND_134 AB24
M25 GND_39 GND_135 AC9
C M31 GND_40 GND_136 AD2 C
M34 GND_41 GND_137 AD5
N11 GND_42 GND_138 AD11
N12 GND_43 GND_139 AD13
N13 GND_44 GND_140 AD15
N14 GND_45 GND_141 AD17
N15 GND_46 GND_142 AD21
N16 GND_47 GND_143 AD23
N17 GND_48 GND_144 AD25
N18 GND_49 GND_145 AD31
N19 GND_50 GND_146 AD34
N20 GND_51 GND_147 AE11
N21 GND_52 GND_148 AE12
N22 GND_53 GND_149 AE13
N23 GND_54 GND_150 AE14
N24 GND_55 GND_151 AE15
N25 GND_56 GND_152 AE16
P12 GND_57 GND_153 AE17
P14 GND_58 GND_154 AE18
P16 GND_59 GND_155 AE19
P18 GND_60 GND_156 AE20
P20 GND_61 GND_157 AE21
P22 GND_62 GND_158 AE22
P24 GND_63 GND_159 AE23
R2 GND_64 GND_160 AE24
R5 GND_65 GND_161 AE25
R31 GND_66 GND_162 AG2
R34 GND_67 GND_163 AG5
T11 GND_68 GND_164 AG31
B
T13 GND_69 GND_165 AG34 B
T15 GND_70 GND_166 AK2
T17 GND_71 GND_167 AK5
T19 GND_72 GND_168 AK14
T21 GND_73 GND_169 AK31
T23 GND_74 GND_170 AK34
T25 GND_75 GND_171 AL6
U11 GND_76 GND_172 AL9
U12 GND_77 GND_173 AL12
U13 GND_78 GND_174 AL15
U14 GND_79 GND_175 AL18
U15 GND_80 GND_176 AL21
U16 GND_81 GND_177 AL24
U17 GND_82 GND_178 AL27
U18 GND_83 GND_179 AL30
U19 GND_84 GND_180 AN2
U20 GND_85 GND_181 AN34
U21 GND_86 GND_182 AP3
U22 GND_87 GND_183 AP6
U23 GND_88 GND_184 AP9
U24 GND_89 GND_185 AP12
U25 GND_90 GND_186 AP15
V2 GND_91 GND_187 AP18
V5 GND_92 GND_188 AP21
V9 GND_93 GND_189 AP24
V12 GND_94 GND_190 AP27
V14 GND_95 GND_191 AP30
V16 GND_96 GND_192 AP33

A A

N12P-GV1-A1_BGA_973P

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(5/12)-GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 34 of 54
5 4 3 2 1
 5 4 3 2 1

UV1B

D Part 2 of 7 U30 CMDA0 D

MDA[0..63] FBA_CMD0 CMDA0 37
MDA0 L32 V30
37,38 MDA[0..63] FBA_D0 FBA_CMD1
MDA1 N33 U31 CMDA2
MDA2 L33
FBA_D1
FBA_D2
FBA_CMD2
FBA_CMD3 V32 CMDA3
CMDA2
CMDA3
37
37
Mode E - Mirror Mode Mapping
MDA3 N34 T35 CMDA4
FBA_D3 FBA_CMD4 CMDA4 37,38
MDA4 N35 U33 CMDA5 DATA Bus
FBA_D4 FBA_CMD5 CMDA5 37,38
MDA5 P35 W32 CMDA6
FBA_D5 FBA_CMD6 CMDA6 37,38
MDA6 P33 W33 CMDA7 Address 0..31 32..63
FBA_D6 FBA_CMD7 CMDA7 37,38
MDA7 P34 W31 CMDA8
FBA_D7 FBA_CMD8 CMDA8 37,38
MDA8 K35 W34 CMDA9 CMD3 CKE_L
FBA_D8 FBA_CMD9 CMDA9 37,38
MDA9 K33 U34 CMDA10
FBA_D9 FBA_CMD10 CMDA10 37,38
MDA10 K34 U35 CMDA11 CMD8 A8 A8
FBA_D10 FBA_CMD11 CMDA11 37,38
MDA11 H33 U32 CMDA12
FBA_D11 FBA_CMD12 CMDA12 37,38
MDA12 G34 T34 CMDA13 CMD2 CS0#_L
FBA_D12 FBA_CMD13 CMDA13 37,38
MDA13 G33 T33 CMDA14
FBA_D13 FBA_CMD14 CMDA14 37,38
MDA14 E34 W30 CMDA15 CMD21 A7 A6
FBA_D14 FBA_CMD15 CMDA15 37,38
MDA15 E33 AB30 CMDA16
FBA_D15 FBA_CMD16 CMDA16 38
MDA16 G31 AA30 CMD24 A2 A1
MDA17 FBA_D16 FBA_CMD17 CMDA18
F30 FBA_D17 FBA_CMD18 AB31 CMDA18 38
MDA18 G30 AA32 CMDA19 CMD23 A11 A9
FBA_D18 FBA_CMD19 CMDA19 38
MDA19 G32 AB33 CMDA20
FBA_D19 FBA_CMD20 CMDA20 37,38
MDA20 K30 Y32 CMDA21 CMD26 A5 A4
FBA_D20 FBA_CMD21 CMDA21 37,38
MDA21 K32 Y33 CMDA22
FBA_D21 FBA_CMD22 CMDA22 37,38
MDA22 H30 AB34 CMDA23 CMD7 A0 A12
FBA_D22 FBA_CMD23 CMDA23 37,38
MDA23 K31 AB35 CMDA24
FBA_D23 FBA_CMD24 CMDA24 37,38
MDA24 L31 Y35 CMDA25 CMD15 CAS# CAS#
FBA_D24 FBA_CMD25 CMDA25 37,38
MDA25 L30 W35 CMDA26
FBA_D25 FBA_CMD26 CMDA26 37,38

MEMORY INTERFACE
C MDA26 M32 Y34 CMDA27 CMD13 BA1 A3 C
FBA_D26 FBA_CMD27 CMDA27 37,38
MDA27 N30 Y31 CMDA28
FBA_D27 FBA_CMD28 CMDA28 37,38
MDA28 M30 Y30 CMDA29 CMD4 A9 A11
FBA_D28 FBA_CMD29 CMDA29 37,38
MDA29 P31 W29 CMDA30
FBA_D29 FBA_CMD30 CMDA30 37,38
MDA30 R32 Y29 CMD18 CS0#_H
MDA31 FBA_D30 FBA_CMD31
R30 FBA_D31
MDA32 AG30 P32 DQMA0 CMD29 BA0 BA0
MDA33 FBA_D32 FBA_DQM0 DQMA1
AG32 FBA_D33 FBA_DQM1 H34 DQMA[7..0] 37,38
MDA34 AH31 J30 DQMA2 CMD27 BA2 A15
MDA35 FBA_D34 FBA_DQM2 DQMA3
AF31 FBA_D35 FBA_DQM3 P30
MDA36 AF30 AF32 DQMA4 CMD6 A3 BA1
MDA37 FBA_D36 FBA_DQM4 DQMA5
AE30 FBA_D37 FBA_DQM5 AL32
MDA38 AC32 AL34 DQMA6 CMD17 CS1#_H
MDA39 FBA_D38 FBA_DQM6 DQMA7
AD30 FBA_D39 FBA_DQM7 AF35
+VRAM_1.5VS MDA40 AN33 FBA_D40 CMD19 ODT_H
MDA41 AL31 L35 DQSA#0
FBA_D41 FBA_DQS_RN0

A
MDA42 AM33 G35 DQSA#1 CMD22 A4 A5
FBA_D42 FBA_DQS_RN1
1

MDA43 AL33 H31 DQSA#2

RV55 MDA44 FBA_D43 FBA_DQS_RN2 DQSA#3
AK30 FBA_D44 FBA_DQS_RN3 N32 DQSA#[7..0] 37,38 CMD12 A13 A14
1.1K_0402_1% MDA45 AK32 AD32 DQSA#4
@ MDA46 FBA_D45 FBA_DQS_RN4 DQSA#5
AJ30 FBA_D46 FBA_DQS_RN5 AJ31 CMD28 WE# A10
12mil MDA47 AH30 AJ35 DQSA#6
2

+FB_VREF MDA48 FBA_D47 FBA_DQS_RN6 DQSA#7

AH33 FBA_D48 FBA_DQS_RN7 AC34 CMD10 A1 A2
MDA49 AH35 FBA_D49
1

1 MDA50 AH34 L34 DQSA0 CMD25 A10 WE#

RV56 CV146 MDA51 FBA_D50 FBA_DQS_WP0 DQSA1
AH32 FBA_D51 FBA_DQS_WP1 H35
1.1K_0402_1% 0.01U_0402_25V7K MDA52 AJ33 J32 DQSA2 CMD9 A12 A0
@ @ MDA53 FBA_D52 FBA_DQS_WP2 DQSA3
B AL35 FBA_D53 FBA_DQS_WP3 N31 B
2 MDA54 DQSA4
AM34 AE31 CMD1 CS1#_L
2

MDA55 FBA_D54 FBA_DQS_WP4 DQSA5

AM35 FBA_D55 FBA_DQS_WP5 AJ32 DQSA[7..0] 37,38
MDA56 AF33 AJ34 DQSA6 CMD11 RAS# RAS#
MDA57 FBA_D56 FBA_DQS_WP6 DQSA7
AE32 FBA_D57 FBA_DQS_WP7 AC33
MDA58 AF34 CMD0 ODT_L
MDA59 FBA_D58
AE35 FBA_D59 FBA_WCK0 P29
Under GPU(below 150mils) MDA60 AE34 R29 CMD5 A6 A7
MDA61 FBA_D60 FBA_WCK0_N
AE33 FBA_D61 FBA_WCK1 L29
+1.05VS_DGPU MDA62 AB32 FBA_D62 FBA_WCK1_N M29 CMD16 CKE_H
MDA63 AC35 AG29
BLM18PG330SN1D_0603 FBA_D63 FBA_WCK2
100mA 10U_0603_6.3V6M +FB_AVDD0 FBA_WCK2_N AH29 CMD20 RST RST
1 2 AG27 FB_DLLAVDD_0 FBA_WCK3 AD29
LV11 AF27 AE29 CMD14 A14 A13
FB_PLLAVDD_0 FBA_WCK3_N
1 1 2
CV65 +FB_AVDD1 J19 CMD30 A15 BA2
CV139 CV84 FB_DLLAVDD_1 CLKA0
J18 FB_PLLAVDD_1 FBA_CLK0 T32 CLKA0 37
+VRAM_1.5VS T31 CLKA0#
FBA_CLK0_N CLKA0# 37
1U_0402_6.3V6K2 2 1 +FB_VREF J27 FB_VREF_NC CLKA1
2RV57 60.4_0402_1%
1 T30 FBA_DEBUG0 FBA_CLK1 AC31 CLKA1 38
0.1U_0402_16V4Z 2 1 T29 AC30 CLKA1#
FBA_DEBUG1 FBA_CLK1_N CLKA1# 38
RV29 10K_0402_5%

N12P-GV1-A1_BGA_973P
+1.05VS_DGPU

A BLM18PG330SN1D_0603 100mA A
1 2 0.1U_0402_16V4Z +FB_AVDD1
LV12
1 1 2
CV101 CV150 CV100
2 2 1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

1U_0402_6.3V6K 10U_0603_6.3V6M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(6/12)-MEM Interface A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 35 of 54
5 4 3 2 1
 5 4 3 2 1

UV1C

Part 3 of 7 F18 CMDB0

MDB[0..63] FBC_CMD0 CMDB0 39
MDB0 B13 E19
39,40 MDB[0..63] FBC_D0 FBC_CMD1
MDB1 D13 D18 CMDB2
FBC_D1 FBC_CMD2 CMDB2 39
MDB2 A13 C17 CMDB3
MDB3 A14
FBC_D2
FBC_D3
FBC_CMD3
FBC_CMD4 F19 CMDB4
CMDB3
CMDB4
39
39,40
Mode E - Mirror Mode Mapping
MDB4 C16 C19 CMDB5
FBC_D4 FBC_CMD5 CMDB5 39,40
D MDB5 B16 B17 CMDB6 D
FBC_D5 FBC_CMD6 CMDB6 39,40
MDB6 A17 E20 CMDB7 DATA Bus
FBC_D6 FBC_CMD7 CMDB7 39,40
MDB7 D16 B19 CMDB8
FBC_D7 FBC_CMD8 CMDB8 39,40
MDB8 C13 D20 CMDB9 Address 0..31 32..63
FBC_D8 FBC_CMD9 CMDB9 39,40
MDB9 B11 A19 CMDB10
FBC_D9 FBC_CMD10 CMDB10 39,40
MDB10 C11 D19 CMDB11 CMD3 CKE_L
FBC_D10 FBC_CMD11 CMDB11 39,40
MDB11 A11 C20 CMDB12
FBC_D11 FBC_CMD12 CMDB12 39,40
MDB12 C10 F20 CMDB13 CMD8 A8 A8
FBC_D12 FBC_CMD13 CMDB13 39,40
MDB13 C8 B20 CMDB14
FBC_D13 FBC_CMD14 CMDB14 39,40
MDB14 B8 G21 CMDB15 CMD2 CS0#_L
FBC_D14 FBC_CMD15 CMDB15 39,40
MDB15 A8 F22 CMDB16
FBC_D15 FBC_CMD16 CMDB16 40
MDB16 E8 F24 CMD21 A7 A6
MDB17 FBC_D16 FBC_CMD17 CMDB18
F8 FBC_D17 FBC_CMD18 F23 CMDB18 40
MDB18 F10 C25 CMDB19 CMD24 A2 A1
FBC_D18 FBC_CMD19 CMDB19 40
MDB19 F9 C23 CMDB20
FBC_D19 FBC_CMD20 CMDB20 39,40
MDB20 F12 F21 CMDB21 CMD23 A11 A9
FBC_D20 FBC_CMD21 CMDB21 39,40
MDB21 D8 E22 CMDB22
FBC_D21 FBC_CMD22 CMDB22 39,40
MDB22 D11 D21 CMDB23 CMD26 A5 A4
FBC_D22 FBC_CMD23 CMDB23 39,40
MDB23 E11 A23 CMDB24
FBC_D23 FBC_CMD24 CMDB24 39,40
MDB24 D12 D22 CMDB25 CMD7 A0 A12
FBC_D24 FBC_CMD25 CMDB25 39,40
MDB25 E13 B23 CMDB26
FBC_D25 FBC_CMD26 CMDB26 39,40

MEMORY INTERFACE C
MDB26 F13 C22 CMDB27 CMD15 CAS# CAS#
FBC_D26 FBC_CMD27 CMDB27 39,40
MDB27 F14 B22 CMDB28
FBC_D27 FBC_CMD28 CMDB28 39,40
MDB28 F15 A22 CMDB29 CMD13 BA1 A3
FBC_D28 FBC_CMD29 CMDB29 39,40
MDB29 E16 A20 CMDB30
FBC_D29 FBC_CMD30 CMDB30 39,40
MDB30 F16 G20 CMD4 A9 A11
MDB31 FBC_D30 FBC_CMD31
F17 FBC_D31
C MDB32 D29 A16 DQMB0 CMD18 CS0#_H C
MDB33 FBC_D32 FBC_DQM0 DQMB1
F27 FBC_D33 FBC_DQM1 D10
MDB34 F28 F11 DQMB2 CMD29 BA0 BA0
FBC_D34 FBC_DQM2 DQMB[7..0] 39,40
MDB35 E28 D15 DQMB3
MDB36 FBC_D35 FBC_DQM3 DQMB4
D26 FBC_D36 FBC_DQM4 D27 CMD27 BA2 A15
MDB37 F25 D34 DQMB5
MDB38 FBC_D37 FBC_DQM5 DQMB6
D24 FBC_D38 FBC_DQM6 A34 CMD6 A3 BA1
MDB39 E25 D28 DQMB7
MDB40 FBC_D39 FBC_DQM7
E32 FBC_D40 CMD17 CS1#_H
MDB41 F32 B14 DQSB#0
MDB42 FBC_D41 FBC_DQS_RN0 DQSB#1
D33 FBC_D42 FBC_DQS_RN1 B10 CMD19 ODT_H
MDB43 E31 D9 DQSB#2
MDB44 FBC_D43 FBC_DQS_RN2 DQSB#3
C33 FBC_D44 FBC_DQS_RN3 E14 DQSB#[7..0] 39,40 CMD22 A4 A5
MDB45 F29 F26 DQSB#4
MDB46 FBC_D45 FBC_DQS_RN4 DQSB#5
D30 FBC_D46 FBC_DQS_RN5 D31 CMD12 A13 A14
MDB47 E29 A31 DQSB#6
MDB48 FBC_D47 FBC_DQS_RN6 DQSB#7
B29 FBC_D48 FBC_DQS_RN7 A26 CMD28 WE# A10
MDB49 C31
MDB50 FBC_D49 DQSB0
C29 FBC_D50 FBC_DQS_WP0 C14 CMD10 A1 A2
MDB51 B31 A10 DQSB1
MDB52 FBC_D51 FBC_DQS_WP1 DQSB2
C32 FBC_D52 FBC_DQS_WP2 E10 CMD25 A10 WE#
MDB53 B32 D14 DQSB3
MDB54 FBC_D53 FBC_DQS_WP3 DQSB4
B35 FBC_D54 FBC_DQS_WP4 E26 CMD9 A12 A0
MDB55 B34 D32 DQSB5
FBC_D55 FBC_DQS_WP5 DQSB[7..0] 39,40
MDB56 A29 A32 DQSB6 CMD1 CS1#_L
MDB57 FBC_D56 FBC_DQS_WP6 DQSB7
B28 FBC_D57 FBC_DQS_WP7 B26
MDB58 A28 CMD11 RAS# RAS#
MDB59 FBC_D58
B C28 FBC_D59 FBC_WCK0 G14 B
MDB60 C26 G15 CMD0 ODT_L
MDB61 FBC_D60 FBC_WCK0_N
D25 FBC_D61 FBC_WCK1 G11
MDB62 B25 G12 CMD5 A6 A7
MDB63 FBC_D62 FBC_WCK1_N
A25 FBC_D63 FBC_WCK2 G27
FBC_WCK2_N G28 CMD16 CKE_H
FBC_WCK3 G24
+VRAM_1.5VS 1 2 K27 FBCAL_PD_VDDQ FBC_WCK3_N G25 CMD20 RST RST
RV58 40.2_0402_1%
1 2 L27 FBCAL_PU_GND CMD14 A14 A13
RV59 40.2_0402_1% E17 CLKB0
FBC_CLK0 CLKB0 39
1 2 M27 D17 CLKB0# CMD30 A15 BA2
FBCAL_TERM_GND FBC_CLK0_N CLKB0# 39
RV60 60.4_0402_1%
+VRAM_1.5VS 60.4_0402_1% 2 1 RV61 G19 D23 CLKB1
FBC_DEBUG0 FBC_CLK1 CLKB1 40
2 1 G16 E23 CLKB1#
FBB_DEBUG1 FBC_CLK1_N CLKB1# 40
RV30 10K_0402_5%

N12P-GV1-A1_BGA_973P

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(7/12)-MEM Interface C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 36 of 54
5 4 3 2 1
 5 4 3 2 1

MDA[0..63] 35,38
Memory Partition A - Lower 32 bits CMDA[30..0] 35,38

DQMA[7..0] 35,38
UV5 UV6
DQSA[7..0] 35,38
+VRAM_1.5VS +FBA_VREF0 M8 E3 MDA3 +FBA_VREF0 M8 E3 MDA19
VREFCA DQL0 VREFCA DQL0 DQSA#[7..0] 35,38
H1 F7 MDA6 H1 F7 MDA17
VREFDQ DQL1 MDA1 VREFDQ DQL1 MDA18
DQL2 F2 DQL2 F2
1

D CMDA7 N3 F8 MDA4 Group0 CMDA7 N3 F8 MDA16 Group2 D

RV62 CMDA10 A0 DQL3 MDA2 CMDA10 A0 DQL3 MDA20
P7 A1 DQL4 H3 P7 A1 DQL4 H3
CMDA24 P3 H8 MDA7 CMDA24 P3 H8 MDA22
1.1K_0402_1% CMDA6 A2 DQL5 MDA0 CMDA6 A2 DQL5 MDA21
N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDA22 P8 H7 MDA5 CMDA22 P8 H7 MDA23
Mode E - Mirror
2

+FBA_VREF0 CMDA26 A4 DQL7 CMDA26 A4 DQL7

P2 A5 P2 A5
CMDA5 R8 CMDA5 R8
A6 A6
Mode Mapping
1

1 CMDA21 R2 D7 MDA29 CMDA21 R2 D7 MDA14

RV63 CV151 CMDA8 A7 DQU0 MDA26 CMDA8 A7 DQU0 MDA8
T8 A8 DQU1 C3 T8 A8 DQU1 C3
0.01U_0402_25V7K CMDA4 R3 C8 MDA30 CMDA4 R3 C8 MDA12 DATA Bus
1.1K_0402_1% CMDA25 A9 DQU2 MDA24 CMDA25 A9 DQU2 MDA10
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
2 CMDA23 MDA27 CMDA23 MDA13 Address
R7 A7 Group3 R7 A7 Group1 0..31 32..63
2

CMDA9 A11 DQU4 MDA25 CMDA9 A11 DQU4 MDA11

N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDA12 T3 B8 MDA31 CMDA12 T3 B8 MDA15 CMD3 CKE_L
CMDA14 A13 DQU6 MDA28 CMDA14 A13 DQU6 MDA9
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDA30 M7 CMDA30 M7 CMD8 A8 A8
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD2 CS0#_L
CMDA29 M2 B2 CMDA29 M2 B2
CMDA13 BA0 VDD CMDA13 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD21 A7 A6
CLKA0 CMDA27 M3 G7 CMDA27 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD24 A2 A1
VDD K8 VDD K8
2

VDD N1 VDD N1 CMD23 A11 A9

RV64 CLKA0 J7 N9 CLKA0 J7 N9
35 CLKA0 CK VDD CK VDD
160_0402_1% CLKA0# K7 R1 CLKA0# K7 R1 CMD26 A5 A4
35 CLKA0# CK VDD CK VDD
CMDA3 K9 R9 CMDA3 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
C CMD7 A0 A12 C
1

CLKA0# CMDA0 K1 A1 CMDA0 K1 A1 CMD15 CAS# CAS#

CMDA2 ODT/ODT0 VDDQ CMDA2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDA11 J3 C1 CMDA11 J3 C1 CMD13 BA1 A3
CMDA15 RAS VDDQ CMDA15 RAS VDDQ CMDA0
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDA28 L3 D2 CMDA28 L3 D2 CMD4 A9 A11
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
F1 F1 CMDA3 CMD18 CS0#_H
DQSA0 VDDQ DQSA2 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
DQSA3 C7 H9 DQSA1 C7 H9 CMD29 BA0 BA0
DQSU VDDQ DQSU VDDQ

2
RV98 RV102 CMD27 BA2 A15
DQMA0 E7 A9 DQMA2 E7 A9 10K_0402_5% 10K_0402_5%
DQMA3 DML VSS DQMA1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD6 A3 BA1
E1 E1

1
VSS VSS
VSS G8 VSS G8 CMD17 CS1#_H
DQSA#0 G3 J2 DQSA#2 G3 J2
DQSA#3 DQSL VSS DQSA#1 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD19 ODT_H
VSS M1 VSS M1
VSS M9 VSS M9 CMD22 A4 A5
VSS P1 VSS P1
CMDA20 T2 P9 CMDA20 T2 P9 CMD12 A13 A14
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD28 WE# A10
CMD10 A1 A2
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 B
1

RV65 RV66 L1 B9 RV67 L1 B9 CMD25 A10 WE#

NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
10K_0402_5% L9 D8 L9 D8 CMD9 A12 A0
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
E8 E8 CMD1 CS1#_L
2

VSSQ VSSQ
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD11 RAS# RAS#
VSSQ G9 VSSQ G9
CMD0 ODT_L
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD5 A6 A7
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
CMD16 CKE_H
@ @
CMD20 RST RST
+VRAM_1.5VS +VRAM_1.5VS CMD14 A14 A13
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z CMD30 A15 BA2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV152 CV153 CV154 CV155 CV156 CV157 CV158 CV222 CV221 CV224 CV223 CV225 CV159 CV160 CV161 CV162 CV163 CV164 CV165 CV227 CV226 CV229 CV228 CV230

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(8/12)-VRAM A Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 37 of 54
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits

MDA[0..63] 35,37

CMDA[30..0] 35,37
UV8 UV7
+VRAM_1.5VS
DQMA[7..0] 35,37
+FBA_VREF1 M8 E3 MDA38 +FBA_VREF1 M8 E3 MDA58
VREFCA DQL0 MDA33 VREFCA DQL0 MDA59
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSA[7..0] 35,37
1
F2 MDA39 F2 MDA57
RV68 CMDA9 DQL2 MDA35 CMDA9 DQL2 MDA61
D N3 A0 DQL3 F8 N3 A0 DQL3 F8 DQSA#[7..0] 35,37 D
CMDA24 P7 H3 MDA36 Group4 CMDA24 P7 H3 MDA60 Group7
1.1K_0402_1% CMDA10 A1 DQL4 MDA34 CMDA10 A1 DQL4 MDA62
P3 A2 DQL5 H8 P3 A2 DQL5 H8
CMDA13 N2 G2 MDA37 CMDA13 N2 G2 MDA56
2

+FBA_VREF1 CMDA26 A3 DQL6 MDA32 CMDA26 A3 DQL6 MDA63

P8 A4 DQL7 H7 P8 A4 DQL7 H7
CMDA22 P2 CMDA22 P2
A5 A5
1

1 CMDA21 R8 CMDA21 R8
RV69 CV166 CMDA5 A6 MDA42 CMDA5 A6 MDA51
R2 D7 R2 D7
0.01U_0402_25V7K CMDA8 T8
A7
A8
DQU0
DQU1 C3 MDA45 CMDA8 T8
A7
A8
DQU0
DQU1 C3 MDA52 Mode E - Mirror Mode Mapping
1.1K_0402_1% CMDA23 R3 C8 MDA40 CMDA23 R3 C8 MDA48
2 CMDA28 A9 DQU2 MDA46 CMDA28 A9 DQU2 MDA53
L7 C2 L7 C2 DATA Bus
2

CMDA4 A10/AP DQU3 MDA41 CMDA4 A10/AP DQU3 MDA49

R7 A11 DQU4 A7 Group5 R7 A11 DQU4 A7 Group6
CMDA7 N7 A2 MDA47 CMDA7 N7 A2 MDA54 Address 0..31 32..63
CMDA14 A12 DQU5 MDA43 CMDA14 A12 DQU5 MDA50
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDA12 T7 A3 MDA44 CMDA12 T7 A3 MDA55 CMD3 CKE_L
CMDA27 A14 DQU7 CMDA27 A14 DQU7
M7 A15/BA3 M7 A15/BA3
+VRAM_1.5VS +VRAM_1.5VS
CMD8 A8 A8
CMDA29 M2 B2 CMDA29 M2 B2 CMD2 CS0#_L
CMDA6 BA0 VDD CMDA6 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9
CLKA1 CMDA30 M3 G7 CMDA30 M3 G7 CMD21 A7 A6
BA2 VDD BA2 VDD
VDD K2 VDD K2
VDD K8 VDD K8 CMD24 A2 A1
2

VDD N1 VDD N1
RV70 CLKA1 J7 N9 CLKA1 J7 N9 CMD23 A11 A9
35 CLKA1 CK VDD CK VDD
160_0402_1% CLKA1# K7 R1 CLKA1# K7 R1
35 CLKA1# CK VDD CK VDD
CMDA16 K9 R9 CMDA16 K9 R9 CMD26 A5 A4
CKE/CKE0 VDD CKE/CKE0 VDD
C C
1

CMD7 A0 A12
CLKA1# CMDA19 K1 A1 CMDA19 K1 A1
CMDA18 ODT/ODT0 VDDQ CMDA18 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 CMD15 CAS# CAS#
CMDA11 J3 C1 CMDA11 J3 C1
CMDA15 RAS VDDQ CMDA15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9 CMD13 BA1 A3
CMDA25 L3 D2 CMDA25 L3 D2
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9 CMD4 A9 A11
VDDQ F1 VDDQ F1
DQSA4 F3 H2 DQSA7 F3 H2 CMD18 CS0#_H
DQSA5 DQSL VDDQ DQSA6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9
CMD29 BA0 BA0
DQMA4 E7 A9 DQMA7 E7 A9 CMD27 BA2 A15
CMDA16 DQMA5 DML VSS DQMA6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3
VSS E1 VSS E1 CMD6 A3 BA1
VSS G8 VSS G8
CMDA19 DQSA#4 G3 J2 DQSA#7 G3 J2 CMD17 CS1#_H
DQSA#5 DQSL VSS DQSA#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1 CMD19 ODT_H
VSS M9 VSS M9
2

VSS P1 VSS P1 CMD22 A4 A5

RV100 RV104 CMDA20 T2 P9 CMDA20 T2 P9
10K_0402_5% 10K_0402_5% RESET VSS RESET VSS
VSS T1 VSS T1 CMD12 A13 A14
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
CMD28 WE# A10
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 CMD10 A1 A2 B
RV71 L1 B9 RV72 L1 B9
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1 CMD25 A10 WE#
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8
E2 E2 CMD9 A12 A0
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 CMD1 CS1#_L
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9 CMD11 RAS# RAS#
96-BALL 96-BALL CMD0 ODT_L
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96 CMD5 A6 A7
@ @ CMD16 CKE_H
CMD20 RST RST
+VRAM_1.5VS +VRAM_1.5VS
CMD14 A14 A13
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
CMD30 A15 BA2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV167 CV168 CV169 CV170 CV171 CV172 CV173 CV232 CV231 CV234 CV233 CV235 CV174 CV175 CV176 CV177 CV178 CV179 CV180 CV237 CV236 CV239 CV238 CV240

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(9/12)-VRAM A Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 38 of 54
5 4 3 2 1
 5 4 3 2 1

MDB[0..63] 36,40
Memory Partition C - Lower 32 bits CMDB[30..0] 36,40

DQMB[7..0] 36,40

DQSB[7..0] 36,40
+VRAM_1.5VS UV9 UV10
DQSB#[7..0] 36,40
+FBB_VREF0 M8 E3 MDB3 +FBB_VREF0 M8 E3 MDB16
VREFCA DQL0 VREFCA DQL0
1
D H1 F7 MDB5 H1 F7 MDB17 D
RV73 VREFDQ DQL1 MDB2 VREFDQ DQL1 MDB19
DQL2 F2 DQL2 F2
CMDB7 N3 F8 MDB4 CMDB7 N3 F8 MDB18 Group2
1.1K_0402_1% CMDB10 A0 DQL3 MDB1 CMDB10 A0 DQL3 MDB23
P7 A1 DQL4 H3 Group0 P7 A1 DQL4 H3
CMDB24 P3 H8 MDB6 CMDB24 P3 H8 MDB21
Mode E - Mirror
2

+FBB_VREF0 CMDB6 A2 DQL5 MDB0 CMDB6 A2 DQL5 MDB22

N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDB22 P8 H7 MDB7 CMDB22 P8 H7 MDB20
A4 DQL7 A4 DQL7
Mode Mapping
1

1 CMDB26 P2 CMDB26 P2
RV74 CV181 CMDB5 A5 CMDB5 A5
R8 A6 R8 A6
0.01U_0402_25V7K CMDB21 R2 D7 MDB31 CMDB21 R2 D7 MDB13 DATA Bus
1.1K_0402_1% CMDB8 A7 DQU0 MDB25 CMDB8 A7 DQU0 MDB9
T8 A8 DQU1 C3 T8 A8 DQU1 C3
2 CMDB4 MDB29 CMDB4 MDB14 Address
R3 C8 R3 C8 0..31 32..63
2

CMDB25 A9 DQU2 MDB24 CMDB25 A9 DQU2 MDB11

L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
CMDB23 R7 A7 MDB28 Group3 CMDB23 R7 A7 MDB12 Group1 CMD3 CKE_L
CMDB9 A11 DQU4 MDB26 CMDB9 A11 DQU4 MDB8
N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDB12 T3 B8 MDB30 CMDB12 T3 B8 MDB15 CMD8 A8 A8
CMDB14 A13 DQU6 MDB27 CMDB14 A13 DQU6 MDB10
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDB30 M7 CMDB30 M7 CMD2 CS0#_L
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD21 A7 A6
CMDB29 M2 B2 CMDB29 M2 B2
CMDB13 BA0 VDD CMDB13 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD24 A2 A1
CLKB0 CMDB27 M3 G7 CMDB27 M3 G7
BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD23 A11 A9
VDD K8 VDD K8
2

VDD N1 VDD N1 CMD26 A5 A4

RV75 CLKB0 J7 N9 CLKB0 J7 N9
36 CLKB0 CK VDD CK VDD
C 160_0402_1% CLKB0# K7 R1 CLKB0# K7 R1 CMD7 A0 A12 C
36 CLKB0# CK VDD CK VDD
CMDB3 K9 R9 CMDB3 K9 R9
CKE/CKE0 VDD CKE/CKE0 VDD
CMD15 CAS# CAS#
1

CLKB0# CMDB0 K1 A1 CMDB0 K1 A1 CMD13 BA1 A3

CMDB2 ODT/ODT0 VDDQ CMDB2 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDB11 J3 C1 CMDB11 J3 C1 CMD4 A9 A11
CMDB15 RAS VDDQ CMDB15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDB28 L3 D2 CMDB28 L3 D2 CMD18 CS0#_H
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD29 BA0 BA0
DQSB0 F3 H2 DQSB2 F3 H2 CMDB0
DQSB3 DQSL VDDQ DQSB1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD27 BA2 A15
CMDB3 CMD6 A3 BA1
DQMB0 E7 A9 DQMB2 E7 A9
DQMB3 DML VSS DQMB1 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD17 CS1#_H
VSS E1 VSS E1

2
VSS G8 VSS G8 CMD19 ODT_H
DQSB#0 G3 J2 DQSB#2 G3 J2 RV111
DQSB#3 DQSL VSS DQSB#1 DQSL VSS RV106 10K_0402_5%
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD22 A4 A5
M1 M1 10K_0402_5%
VSS VSS
M9 M9 CMD12 A13 A14

1
VSS VSS
VSS P1 VSS P1
CMDB20 T2 P9 CMDB20 T2 P9 CMD28 WE# A10
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD10 A1 A2
B B
CMD25 A10 WE#
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
1

RV76 RV77 L1 B9 RV78 L1 B9 CMD9 A12 A0

NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
10K_0402_5% L9 D8 L9 D8 CMD1 CS1#_L
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
E8 E8 CMD11 RAS# RAS#
2

VSSQ VSSQ
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD0 ODT_L
VSSQ G9 VSSQ G9
CMD5 A6 A7
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD16 CKE_H
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
CMD20 RST RST
@ @
CMD14 A14 A13
+VRAM_1.5VS +VRAM_1.5VS
CMD30 A15 BA2
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV182 CV183 CV184 CV185 CV186 CV187 CV188 CV242 CV241 CV244 CV243 CV245 CV189 CV190 CV191 CV192 CV193 CV194 CV195 CV247 CV246 CV249 CV248 CV250

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(10/12)-VRAM C Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 39 of 54
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits MDB[0..63] 36,39

CMDB[30..0] 36,39
UV11 UV12

+VRAM_1.5VS DQMB[7..0] 36,39

+FBB_VREF1 M8 E3 MDB37 +FBB_VREF1 M8 E3 MDB56
VREFCA DQL0 MDB35 VREFCA DQL0 MDB63
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 DQSB[7..0] 36,39
D F2 MDB36 F2 MDB57 D
DQL2 DQL2
1
CMDB9 N3 F8 MDB34 CMDB9 N3 F8 MDB62
A0 DQL3 A0 DQL3 DQSB#[7..0] 36,39
RV79 CMDB24 P7 H3 MDB38 Group4 CMDB24 P7 H3 MDB58 Group7
CMDB10 A1 DQL4 MDB32 CMDB10 A1 DQL4 MDB60
P3 A2 DQL5 H8 P3 A2 DQL5 H8
1.1K_0402_1% CMDB13 N2 G2 MDB39 CMDB13 N2 G2 MDB59
CMDB26 A3 DQL6 MDB33 CMDB26 A3 DQL6 MDB61
P8 H7 P8 H7
2

+FBB_VREF1 CMDB22 A4 DQL7 CMDB22 A4 DQL7

P2 A5 P2 A5
CMDB21 R8 CMDB21 R8
A6 A6 Mode E - Mirror Mode Mapping
1

1 CMDB5 R2 D7 MDB41 CMDB5 R2 D7 MDB49

RV80 CV196 CMDB8 A7 DQU0 MDB46 CMDB8 A7 DQU0 MDB55
T8 A8 DQU1 C3 T8 A8 DQU1 C3
0.01U_0402_25V7K CMDB23 R3 C8 MDB42 CMDB23 R3 C8 MDB48 DATA Bus
1.1K_0402_1% CMDB28 A9 DQU2 MDB47 CMDB28 A9 DQU2 MDB53
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
2 CMDB4 MDB44 CMDB4 MDB51 Address
R7 A7 Group5 R7 A7 Group6 0..31 32..63
2

CMDB7 A11 DQU4 MDB45 CMDB7 A11 DQU4 MDB52

N7 A12 DQU5 A2 N7 A12 DQU5 A2
CMDB14 T3 B8 MDB40 CMDB14 T3 B8 MDB50 CMD3 CKE_L
CMDB12 A13 DQU6 MDB43 CMDB12 A13 DQU6 MDB54
T7 A14 DQU7 A3 T7 A14 DQU7 A3
CMDB27 M7 CMDB27 M7 CMD8 A8 A8
A15/BA3 +VRAM_1.5VS A15/BA3 +VRAM_1.5VS
CMD2 CS0#_L
CMDB29 M2 B2 CMDB29 M2 B2
CMDB6 BA0 VDD CMDB6 BA0 VDD
N8 BA1 VDD D9 N8 BA1 VDD D9 CMD21 A7 A6
CMDB30 M3 G7 CMDB30 M3 G7
CLKB1 BA2 VDD BA2 VDD
VDD K2 VDD K2 CMD24 A2 A1
VDD K8 VDD K8
VDD N1 VDD N1 CMD23 A11 A9
2

CLKB1 J7 N9 CLKB1 J7 N9
36 CLKB1 CK VDD CK VDD
RV81 CLKB1# K7 R1 CLKB1# K7 R1 CMD26 A5 A4
36 CLKB1# CK VDD CK VDD
C 160_0402_1% CMDB16 K9 R9 CMDB16 K9 R9 C
CKE/CKE0 VDD CKE/CKE0 VDD
CMD7 A0 A12
1

CMDB19 K1 A1 CMDB19 K1 A1 CMD15 CAS# CAS#

CLKB1# CMDB18 ODT/ODT0 VDDQ CMDB18 ODT/ODT0 VDDQ
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDB11 J3 C1 CMDB11 J3 C1 CMD13 BA1 A3
CMDB15 RAS VDDQ CMDB15 RAS VDDQ
K3 CAS VDDQ C9 K3 CAS VDDQ C9
CMDB25 L3 D2 CMDB25 L3 D2 CMD4 A9 A11
WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1 CMD18 CS0#_H
DQSB4 F3 H2 DQSB7 F3 H2
DQSB5 DQSL VDDQ DQSB6 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 CMD29 BA0 BA0
CMD27 BA2 A15
DQMB4 E7 A9 DQMB7 E7 A9
DQMB5 DML VSS DQMB6 DML VSS
D3 DMU VSS B3 D3 DMU VSS B3 CMD6 A3 BA1
CMDB16 E1 E1
VSS VSS
VSS G8 VSS G8 CMD17 CS1#_H
DQSB#4 G3 J2 +VRAM_1.5VS DQSB#7 G3 J2
CMDB19 DQSB#5 DQSL VSS DQSB#6 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 CMD19 ODT_H
VSS M1 1 VSS M1
VSS M9 VSS M9 CMD22 A4 A5
2

P1 + CV122 P1
RV108 RV112 CMDB20 VSS 330U_B2_2.5VM_R15M CMDB20 VSS
T2 RESET VSS P9 T2 RESET VSS P9 CMD12 A13 A14
10K_0402_5% 10K_0402_5% T1 T1
VSS 2 VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9 CMD28 WE# A10
1

B CMD10 A1 A2 B
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV82 L1 B9 RV83 L1 B9 CMD25 A10 WE#
NC/CS1 VSSQ NC/CS1 VSSQ
243_0402_1% J9 NC/CE1 VSSQ D1 243_0402_1% J9 NC/CE1 VSSQ D1
L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 CMD9 A12 A0
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8 CMD1 CS1#_L
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 CMD11 RAS# RAS#
VSSQ G9 VSSQ G9
CMD0 ODT_L
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 CMD5 A6 A7
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
CMD16 CKE_H
@ @
CMD20 RST RST
+VRAM_1.5VS +VRAM_1.5VS
CMD14 A14 A13
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
CMD30 A15 BA2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV198 CV199 CV200 CV201 CV202 CV203 CV204 CV252 CV251 CV254 CV253 CV255 CV205 CV206 CV207 CV208 CV209 CV210 CV211 CV257 CV256 CV259 CV258 CV260

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(11/12)-VRAM C Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 40 of 54
5 4 3 2 1
 5 4 3 2 1

Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
+3VS_DGPU
ROM_SO +3VS XCLK_417 FB_0_BAR_SIZE SMB_ALT_ADDR VGA_DEVICE
ROM_SCLK +3VS PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLLEN_TERM
ROM_SI +3VS RAMCFG[3] RAMCFG[2] RAMCFG[1] RAMCFG[0]

2
RV87 RV85 RV86 STRAP2 +3VS PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
45.3K_0402_1% 34.8K_0402_1% 15K_0402_1%
@ STRAP1 +3VS 3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
D @ D

1
STRAP0 +3VS USER[3] USER[2] USER[1] USER[0]
31 STRAP0 STRAP0
31 STRAP1 STRAP1
31 STRAP2 STRAP2

Resistor Values Pull-up to +3VS Pull-down to Gnd

2
GPU DeviceID ROM_SCLK STRAP2
@ RV84
@RV84 RV88 RV89 5K 1000 0000
45.3K_0402_1% 4.99K_0402_1% 24.9K_0402_1%
10K 1001 0001 N12M-GE 0x0A7A Pull up 15K Pull up 15K
1

1
15K 1010 0010
N12P-GS 0x0DF4 Pull up 15K Pull down 25K
20K 1011 0011
25K 1100 0100 N12P-GE 0x0DF5 Pull up 15K Pull down 30K
30K 1101 0101

+3VS_DGPU
35K 1110 0110
45K 1111 0111
2

2
C C
RV90 RV91 RV92
4.99K_0402_1%
@
4.99K_0402_1%
@
15K_0402_1%
EϭϮWͲ'^Ͳϭ͗
ZKDͺ^K͗W>ͲϭϬ<
1

ZKDͺ><͗W,Ͳϭϱ<
ROM_SI
31 ROM_SI
ROM_SO ZKDͺ^/͗W>ϰϱ͘ϯ<;^ĂŵƐƵŶŐϮ'Ϳ
31 ROM_SO
31 ROM_SCLK ROM_SCLK
^ƚƌĂƉϮ͗W>Ͳϱ< SUB_VENDOR XCLK_417
^ƚƌĂƉϭ͗W,Ͳϯϱ<
2

0 No VBIOS ROM 0 277MHz (Default)

2

X76 RV93
45.3K_0402_1% RV94 RV95
^ƚƌĂƉϬ͗W,Ͳϰϱ<
10K_0402_1% 15K_0402_1% 1 BIOS ROM is present (Default) 1 Reserved
@ @
1

FB_0_BAR_SIZE USER Straps

0 256MB (Default) User[3:0]

Hynix (900MHZ) 1 Reserved 1000-1100 Customer defined

B B
64MX16 H5TQ1G63DFR-11C 1GB 0010 PD 15K (SD034150280)
SA000041S20 3GIO_PADCFG PEX_PLL_EN_TERM
Hynix (900MHZ) 3GIO_PADCFG[3:0] 0 Disable (Default)
128MX16 H5TQ2G63BFR-11C 2GB 0110 PD 34.8k(SD034348280) 0110 Notebook Default 1 Enable
SA00003YO00
SLOT_CLK_CFG
Samsung (900MHZ)
64MX16 K4W1G1646E-HC11 1GB 0011 PD 20K (SD034200280) 0 GPU and MCH don't share a common reference clock
SA000041T00 1 GPU and MCH share a common reference clock (Default)
Samsung (900MHZ)
SMBUS_ALT_ADDR VGA_DEVICE
128M16 K4W2G1646C-HC11
2GB 0111 PD 45.3K(SD034453280) 0 0x9E (Default) 0 3D Device
SA000047Q00
A 1 0x9C (Multi-GPU usage) 1 VGA Device (Default) A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/05/27 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA(12/12)-MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 41 of 54
5 4 3 2 1
 5 4 3 2 1

+3VALW
Touch pad Connector JTP1
MB_Power On/Off SW
+5VS 1 1

1
2
2
25
25
TP_CLK
TP_DATA 3
2
3
For Debug Only R1073

100P_0402_50V8J
4 4
C1236 1 C1234 1 5 100K_0402_5%
G1

100P_0402_50V8J
1U_0402_6.3V4Z C1235 6 SW1

2
1 G2

PJDLC05C_SOT23-3
SMT1-05_4P D20
TYCO_2041084-4 1 3 ON/OFFBTN# 2
2 2 ON/OFF# 25
CONN@ ON/OFFBTN# 1
27 ON/OFFBTN#

D19
2 4 3 51ON# 44
D D
1

1
@ C1237 DAN202UT106_SC70-3
Power ON Circuit

6
5
J5
10K_0603_5% 0.1U_0402_25V6

1
2
@ @

1
1000P_0402_50V7K
1

1
D C1238 D21
2 Q93
25,47 EC_ON
G

2
S 2 RLZ20A_LL34

2
R1074
2N7002LT1G_SOT23-3
10K_0402_5%

1
JKB1
KSO8 @ C736 100P_0402_25V8K 100P_0402_25V8K C737 @ KSI7 KSI7 1
KSI6 1
2 2
KSI3 @ C738 100P_0402_25V8K 100P_0402_25V8K C739 @ KSI6 KSI4 3 JKBBL1
KSI2 3
4 4 8 GND
KSO9 @ C740 100P_0402_25V8K 100P_0402_25V8K C741 @ KSI5 KSI5 5 7
KSI1 5 GND
6 6 +5VS 6 6
C KSI2 @ C742 100P_0402_25V8K 100P_0402_25V8K C743 @ KSO0 KSI3 7 5 C
KSI0 7 5
8 8 4 4
KSI1 @ C744 100P_0402_25V8K 100P_0402_25V8K C745 @ KSO1 KSO5 9 3
9 27 KB_LED_R_DRV# 3
KSO4 10 2
10 27 KB_LED_G_DRV# 2
KSO10 @ C746 100P_0402_25V8K 100P_0402_25V8K C747 @ KSO2 KSO7 11 1
11 27 KB_LED_B_DRV# 1
KSO6 12
KSO11 @ C750 100P_0402_25V8K 100P_0402_25V8K C751 @ KSI4 KSO8 12 TYCO_2041070-6~D
13 13
KSO3 14 SP01000V80L
KSI0 @ C752 100P_0402_25V8K 100P_0402_25V8K C753 @ KSO3 KSO1 14 CONN@
15 15
KSO2 16
KSO12 @ C754 100P_0402_25V8K 100P_0402_25V8K C755 @ KSO4 KSO0 16
17 17
KSO12 18
KSO13 @ C756 100P_0402_25V8K 100P_0402_25V8K C757 @ KSO5 KSO16 18
19 19
KSO15 20
KSO14 @ C760 100P_0402_25V8K 100P_0402_25V8K C761 @ KSO6 KSO13 20
21 21
KSO14 22
KSO15 @ C762 100P_0402_25V8K 100P_0402_25V8K C763 @ KSO7 KSO9 22
23 23
KSO11 24
KSO16 @ C764 100P_0402_25V8K KSO10 24
25 25
GND 27
GND 26

ACES_88502-2501
SP010013N0L
CONN@
KSI[0..7]
KSI[0..7] 25
KSO[0..16]
KSO[0..16] 25

B B

H_2P3 *8 H_2P3N*1 H_2P5 *2 H_2P0N *1 H_3P0 *4

H19 H27 H30 H26
H1 H2 H3 H4 H10 H6 H7 H8 H9 H11 H_3P0 H_3P0 H_3P0 H_3P0
H_2P3 H_2P3 H_2P3 H_2P3 H_2P3 H_2P3 H_2P3N H_2P5 H_2P5 H_2P0N @ @ @ @
@ @ @ @ @ @ @ @ @ @

1
1

1
H_3P8 *7 H_2P0X3P0N *1
H18
H5 H22 H23 H24 H15 H16 H17 H20 H_3P3
FD1 FD2 FD3 FD4 H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 H_2P0X3P0N @
@ @ @ @ @ @ @ @

1
@ @ @ @
1

1
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/07/25 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SW/TP/SCREW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6961P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 24, 2011 Sheet 42 of 54
5 4 3 2 1
 5 4 3 2 1

+3VALW to +3VS Transfer +5VALW to +5VS Transfer +1.05V to +1.05VS_DGPU Transfer

+1.05VS +1.05VS_DGPU
+5VALW U46 +5VS U621
+3VALW U45 +3VS SI4800BDY-T1-E3_SO8 SI4634DY-T1-E3_SO8~D
SI4800BDY-T1-E3_SO8 B+_BIAS

0.1U_0402_16V4Z~D
8 1 8 1

10U_0805_10V4Z~D

0.1U_0402_16V7K~D

10U_0805_10V4Z~D

10U_0805_10V4Z
8 1 7 2 1 7 2 1 1

10U_0805_10V4Z~D

0.1U_0402_16V7K~D

10U_0805_10V4Z~D
7 2 6 3 C1255 6 3 C1256 C1257

1
B+_BIAS

10U_0805_10V4Z
6 3 1 5 1 1 5
1 5 1 1 R1083
2 2 2

C1244

C1241

C1242
510K_0402_5%

4
C1239

C1243

C1240
4
1

2 2 2

2
2 2 2
R1075

D D
102K_0402_5%

+1.05VS_GATE R1013 1 2
R1078
2

R1077 RUNON 1 2 5VS_GATE 0_0402_5%

1
RUNON 1 2 3VS_GATE R1086 1

1
0_0402_5% R1079 D C1259

2M_0402_5%~D
0_0402_5% 1 1 DGPU_PWR_EN# 1 2 1 2
1

C1250

C1260
C1249 G 0.1U_0603_25V7K
SUSP Q95 0_0402_5% 2
2 S

2
G SSM3K7002FU_SC70-3 0.1U_0603_25V7K 0.1U_0603_25V7K 0.1U_0603_25V7K Q99
S 2 2 2
3

2N7002_SOT23

+3VALW +3V_PCH

JP3 @ +3VALW to +3V_PCH

+1.5VS to +1.5VSDGPU Transfer 1 1 2 2

SB54392008L EOL, P/N change to SB54800038L JUMP_43X79

Q41
+1.5VS +VRAM_1.5VS SI4800BDY-T1-E3_SO8
B+_BIAS 8 1
U47 7 2
10U_0805_10V4Z~D

8 3 1 1 6 3 1 1
1

C1252

1 7 2 0.1U_0402_16V4Z~D 5
C1253

10U_0805_10V4Z~D
C1254
R1082 6 1 C349 C350 C351 C352
5 1 1 10U_0805_10V4Z~D 10U_0805_10V4Z~D 10U_0805_10V4Z~D 1U_0603_10V4Z

4
C 330K_0402_5% 2 2 2 2 C
2 SI4634DY-T1-E3_SO8~D
2

2 2
0.1U_0402_25V6

R1012 1 2 470_0402_5% R277

1 C1258 B+_BIAS 1 2

0.1U_0603_50V_X7R
R280
1

R1084 102K_0402_1% 0_0402_5% 1

1

1
R1080 D D @
2
2M_0402_5%~D

C355
DGPU_PWR_EN# 1 2 2 PCH_PWR_EN# 2 Q31 R282
1 G Q98 G 2N7002_SOT23 0_0402_5%
2
C1262

0_0402_5% S PMF3800SN_SC70-3 S
3

3
+3VALW +5VALW
0.1U_0603_25V7K
2
+5VALW
+1.5V

1
+5VALW +5VALW +1.5V_CPU_VDDQ

2
R286
10K_0402_5% R287 R1081
1

100K_0402_5% 100K_0402_5%

1
R1087 R1088

2
1
220_0402_5%~D R1112 PCH_PWR_EN#
18 PCH_PWR_EN#

1
100K_0402_5% 100K_0402_5%

1
D
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

470_0402_5%
2

SYSON# SUSP R464 2 Q32 DGPU_PWR_EN#

25 PCH_PWR_EN

2
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
G 2N7002_SOT23

0.1U_0603_50V_X7R
S SUSP# 1 2

3
6

1
@ 1

1
Q100A Q100B R290 @ CH751H-40PT_SOD323-2 D22 D

C359
Q109A Q109B 100K_0402_5% 2
15,30,33,53 DGPU_PWR_EN
SYSON 2 5 SUSP# G
B 25,48 SYSON SUSP# 9,17,25,48,49,50,51 2 B
2 SYSON# 5 Q97 S
5,9 RUN_ON_CPU1.5VS3#

3
1
2N7002_SOT23
1

4
1

2
10K_0402_5%

R1085
1

4
R300 100K_0402_5%
R1089

100K_0402_5%~D

2
2

+3V_PCH +VRAM_1.5VS +1.05VS_DGPU +1.5VS +1.05VS +1.8VS +0.75VS +5VS +3VS

1

1
1

1
R1107 R1101 R1091 R1092 R1093 R1094
R289 22_0402_5%~D
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% R1090 R1096
470_0402_5% 470_0402_5% 470_0402_5%
2

2
2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6
2

2
6

3
Q108A Q108B Q104A Q103B Q103A Q104B

1
D D
1

D DGPU_PWR_EN# DGPU_PWR_EN# SUSP SUSP SUSP SUSP SUSP SUSP 2

2 5 2 5 2 5 2
PCH_PWR_EN# 2 G Q101 G Q105
G Q34 S SSM3K7002FU_SC70-3 S
1

3
S SSM3K7002FU_SC70-3
3

SSM3K7002FU_SC70-3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/07/25 Deciphered Date 2011/07/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC INTERFACE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-6961P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 24, 2011 Sheet 43 of 54
5 4 3 2 1
 5 4 3 2 1

PQ1
VIN PR1 TP0610K-T1-E3_SOT23-3
1K_1206_5% PD1 B+
PL1 1 2 2 1 3 1
PJPDC1 FBM-L11-160808-601LMT 0603~D ADPIN VIN
4 V- ID 3 2 1 DETECT_PSID LL4148_LL34-2
D PR2 D
5 PL2 1K_1206_5%
@ @
V-

470K_0402_5%

470K_0402_5%
FBMJ4516HS720NT_1806~D 1 2

1
PR3
6 DC_IN_S1 1 2
GND_1

PR4
1 PR5

2
V+ 1K_1206_5%
7 GND_2

1000P_0402_50V7K~D

1000P_0402_50V7K~D
1 @ 2

100P_0402_50V8J~D

100P_0402_50V8J~D
8

2
GND_3 @

1
PR6

PC1

PC2

PC3

PC4
9 2 1K_1206_5%
GND_4 V+

1
1@ 2

2
FOX_JPD1131-DB371-7F @ @ PR7
@ PreCHG 470K_0402_5%

1
@

1 2
PQ2
PD2 DTC115EUA_SC70-3
25,46 ACOFF 2 @ PQ3
1 2 DTC115EUA_SC70-3
+5VALW 3
2
RB715F_SOT323-3

3
@

3
@
VIN
@

2
PD7 +5VALW +3VALW
LL4148_LL34-2
C C

DA204U_SOT323~D
PD8
LL4148_LL34-2 PR21
BATT+ 2 1

2
PD5

2.2K_0402_5%~D
PR20 68_1206_5% @ PR8
1 2

2
68_1206_5% VS 0_0402_5%~D
Pre-V

PR11
2

2
PQ7 PR12

1
Pre-V 3 TP0610K-T1-E3_SOT23-3
1 33_0402_5%~D

1
0.22U_0603_25V7K

DETECT_PSID

S
1 3 1 2 PS_ID 25
1

PQ5
1

1
PR25 PC10 FDV301N_NL_SOT23-3~D

G
2
15K_0402_1%~D 100K_0402_1%~D
PC9

100K_0402_5% +5VALW

2
0.1U_0603_25V7K +5VALW
2

PR14

DA204U_SOT323~D
PR26
2

22K_0402_1%

10K_0402_1%~D
42 51ON# 1 2

2
PD9
1
2

PR16
C
2 PQ6
B MMST3904-7-F_SOT323~D @

2
E

2
PR17

1
@

1
PD6 PR18
SM24_SOT23 1 2

1
PSID_DISABLE#
@ 10K_0402_1%~D
@PR160
@ PR160
B 2.2M_0402_5% B
2 1
VL
+3VALW VS B+
@PR15
@ PR15

1
0_0402_5% @

1
2 1 PR178
1

100K_0402_1% PR179
PR91 @ 499K_0402_1%
10K_0402_1% 1000P_0402_50V7K

8
VL @PD4
@ PD4 @

2
PC72 2 5

P
2

25,54 MAINPWON +
2

@ 1 7 O

0.01U_0402_25V7K
3 6
25,54 ACON -

1
PU11A 0_0402_5% LM393DR_SO8
1
8

1
1000P_0402_50V7K

32.4

PC74
@ PR39 LM393DR_SO8 PR90 RB715F_SOT323-3 PU12B @PR124
@PR124 @ @

4
1

1
0_0402_5% @ @ 191K_0402_1%
+ 3 2 1
P

ADP_I 25,46

PC75
2 1 1 PC73 PR198

2
25 Dyn_Turbo_Sel 0 0.1U_0603_25V7K 499K_0402_1%
DMN66D0LDW-7 2N SOT363-6

2 2 1
AC_SEL 25

PRG++ 2

2
-
G

PR92
1000P_0402_50V7K

@ 0_0402_5% PR35 0_0402_5%

4

46 EMC_THERM# 2 1
3
PQ507B

PC71

@
PR103
2

0_0402_5% @PR197
@ PR197 PQ8 @ @ PR196

1
34K_0402_1% D RHU002N06_SOT323-3 47K_0402_5%
2 1 5
25,54 H_PROCHOT# 2 1 2 2 1
+RTCBATT G PACIN 25
4

1
S

3
PQ15 @
DTC115EUA_SC70-3

A 2 +5VALW A

3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/12/01 Deciphered Date 2010/05/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 44 of 54
5 4 3 2 1
 5 4 3 2 1

1
PD12 PD14
D D
PJSOT24C_SOT23-3 PJSOT24C_SOT23-3
BATT+ @ @
BATT++

3
PL7
BATT+

SMB3025500YA_2P

1 2 BATT++
+3VALWP
Battery Connect/OTP

100P_0402_50V8J~D
1

1
100P_0402_50V8J~D
1

PC21
PC7
PC8

PC55 1000P_0402_50V7K~D
2

2
0.01U_0402_25V7K~D
2

PR19 Place clsoe to EC pin

47K_0402_5%~D PH3 under CPU botten side :
1 2 BATT_TEMP CPU thermal protection at 90 degree C
BATT_TEMP 25

1
PR22
Recovery at 50 degree C

2
1K_0402_5%~D
MOLEX_87437-1173_11P-T PC35
SP020907230 0.1U_0402_16V7K~D

1
11

@
11 PR30
10 10
9 9
1K_0402_5%~D
PJP31 battery connector 8 8
7 2 1 VL VL
7
6 6 1 2 +3VALWP
5 5
60$57 4 4
3
PR23
6.49K_0402_1%~D
3

2
C %DWWHU\ 2 2
1 PH5 PR202 C
1 29.4K_0402_1%
1 2
@ PJP31 EC_SMB_DA1 25 100K_0402_1%_TSM0B104F4251RZ
%$7 PR24

1
100_0402_5%~D PR203
MAINPWON 47
%$7
47K_0402_1%

DMN66D0LDW-7 2N SOT363-6
1 2
%$7

6
1 2 PR205 VL
EC_SMB_CK1 25

PQ507A
,' PR28 OTP-1
15K_0402_1%
1 2 OTP-25

P
+
%, 100_0402_5%~D
OTP-4 6
0 7 OTP-3 2
-

G
76 PQ57 PU11B

1
TP0610K-T1-E3_SOT23-3 LM393DR_SO8

4
60'

1000P_0402_50V7K
60&

16.5K_0402_1%
B+ 3 1 B+_BIAS

1
0.22U_0603_25V7K
1

1
*1'
100K_0402_1%

PR207
0.22U_1206_25V7K

2 1 VL
1

PC178

PC179
1

*1'
PR210

PC180

PR208

1
@ PC181 100K_0402_1%

2
*1' 0.1U_0603_25V7K
2

@ PR209
2

PR211 100K_0402_1%
+5VALWP 22K_0402_1%

2
1 2
2

PR212
100K_0402_1%
B B
PR213
1

0_0402_5% D
1 2 2 PQ58
47 SPOK
G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K

S
3
1

PC182
2

@
COIN RTC Battery

@ PJP32
1 1 +RTCBATT
2 2

MOLEX_53261-0271~D
SP020009Z0L

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/05/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 45 of 54
5 4 3 2 1
 A B C D

CP = 85%*Iada ; CP = 4.07A
Iada=0~4.74A(90W/19V=4.736A) ADP_I = 19.9*Iadapter*Rsense

0.02_2512_1%
PQ9
P2 PQ10 P3 B+ CHG_B+ SI4459ADY-T1-GE3_SO8
AO4407A_SO8 PR27 PL102
SI4459ADY-T1-GE3_SO8
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
VIN 8 1 1 8 1 4 1 2 1 PQ11 8
7 2 2 7 2 7
6 3 3 6 2 3 CSIN 3 6
5 5 5

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0603_25V7K
EMC_SENSE-

5600P_0402_25V7K
CSIP PR29

4
1

1
1 1

PC12

PC13
47K_0402_1%
VIN VIN PreCHG VIN

PC14

PC15
EMC_SENSE+ 1 2

2 191K_0402_1%

191K_0402_1%
PC11
PD15

2
1

3
1SS355_SOD323

1
1

2
6251VDD
PR31 47K 1 2 ACOFF

0.1U_0603_25V7K
200K_0402_1% PR34

PR113

PR33
2 47K PR32 ACSETIN @ 10K_0402_1% @ @ PR112

PC16
200K_0402_1% 200K_0402_1%~D
2

2.2U_0603_6.3V6K
PD10 1 2 VIN

1 1
40.2

1000P_0402_50V7K
PC17
RB751V-40_SOD323-2 ACSETIN

1 1

15K_0402_1%
1

1
10_1206_5%

PC18
2 PQ12 PD11 1SS355_SOD323-2 @PD16
@ PD16

PR36

PR37
PDTA144EU_SOT323-3 1 2 PQ14 1SS355_SOD323

2200P_0402_25V7K
PDTC115EU_SOT323 2 1 2

2
PQ13 PR38 @ PQ27

2
PDTC115EU_SOT323 10K_0402_5% SSM3K7002FU_SC70-3
3

1
D

PC201

0.1U_0603_25V7K~D
2 1 PU2 PC20
25 FSTCHG

1
0.1U_0603_25V7K 2 PACIN
PACIN 25

PC66
1 2 1 24 DCIN
2 1 G

2
VDD DCIN
1

100K_0402_1%
V1 PR41 0_0402_5% PC19 PR43 S

3
6251VDD 1 2 0.1U_0402_16V7K 100K_0402_1%

PR42
PR40 ACPRN V1 1 @ @
DMN66D0LDW-7 2N SOT363-6

2 ACSET ACPRN 23 ACPRN 47 2

150K_0402_1% PR44
6

20_0402_5%
2

2
PQ16A

6251_EN 3 22 1 2 CSON
EN CSON

1
PC22 D

5
6
7
8
0.047U_0402_16V7K ACPRN
DMN66D0LDW-7 2N SOT363-6

2 2
4 21 1 2 CSOP PQ19 G

1
CELLS CSOP PR45 AO4466_SO8 S@
1

3
PC23 6800P_0402_25V7K 20_0402_5% PQ18
3

PQ16B

2
1 2 5 20 2 1 SSM3K7002FU_SC70-3 2

ICOMP CSIN

2
PR46 4
PC24 20_0402_5%
5 1 2 1 PR47 2 10K_0402_1% 6 19 0.1U_0603_25V7K
1 2 TCR=50ppm / C
<40,41>

1
PR49 VCOMP CSIP PR48 PL3 PR50
PC25 1 2 100_0402_1% 2_0402_5% 10UH_PCMB063T-100MS_4A_20% 0.02_1206_1% BATT+
4

3
2
1
0.01U_0402_25V7K PC26 1 2 7 18 LX_CHG 1 2 CHG 1 4
25,54 ACON ICM PHASE

4.7_1206_5%
@ 100P_0402_50V8J

5
6
7
8

1
6251VREF 2 3
25,44 ADP_I

PR51
PR52 PC27 6251VREF 8 17 DH_CHG
47K_0402_5% PR53 VREF UGATE PR54 PC28
1 2
PACIN

10U_0805_25V6K

10U_0805_25V6K
PACIN 1 2 147K_0402_1% 2.2_0603_5% 0.1U_0603_25V7K

10U_0805_25V6K
25 2 1 .1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1 PQ20

2
25 IREF CHLIM BOOT

1
0.01U_0402_25V7K

4 AO4466_SO8
1

1
6251VREF

PC700
PC31

PC32
PQ21 PR56

680P_0402_50V7K
PC29

PDTC115EU_SOT323 PR55 6251VREF

1 2 6251aclim 10 15 6251VDDP PD13
ACLIM VDDP

PC30
100K_0402_1% RB751V-40_SOD323-2
2

2
11.5K_0402_1% 1 26251VDD

3
2
1

2
1

ACOFF 2 11 14 DL_CHG
25,44 ACOFF
2

VADJ LGATE

2
PR57
4.7_0603_5%
24.3K_0402_1%~D PR58 12 13 PC33

1
GND PGND 4.7U_0603_6.3V6M
3

ISL6251AHAZ-T_QSOP24

PR59
25.5K_0402_1%

3
CP mode 25 CHGVADJ 1 2
add 8/17 3

Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) customer request

2

where Vaclm=1.502V, Iinput=4.07A PR60

43.2K_0402_1%
1

PU102 +3VS

CC=0.6~4.48A EMC1701-1-AIZL-TR_MSOP10

2
PR110
IREF=0.7224*Icharge 0_0402_5%

2
6251VDD
@
IREF=0.43V~3.24V

N/C

1
PR63 EMC_SENSE- 3 1 PCH_SMLCLK 13,23,25,26,31
10K_0402_1% SENSE- SMCLK
1

1 2 ACIN 25,27,30 EMC_SENSE+ 4 10

SENSE+ SMDATA
1

PR104 PCH_SMLDATA 13,23,25,26,31

PR61 PR62 +5VS 5 9 1 @ 2 EC_ALERT# 25

ADDR_SEL
47K_0402_1% 10K_0402_1% VDD ALERT# 0_0402_5%

0.1U_0402_16V7K
1U_0402_6.3V6K
PACIN 8 EMC_THERM# 44
PACIN 25
2

THERM#

2
PC166

PC167

GND
2

2
1

PR111

1
PQ22 0_0402_5%

7
DTC115EUA_SC70-3
Charging Voltage @
BATT Type CV mode

1
1

(0x15) ACPRN 2

20K_0402_1%
PR64 +3VS

PR194
14.3K_0402_1%

4
Normal 3S LI-ON Cells 4
3

12600mV 12.60V slave address : 0101101

2
please placemnet near R-sense

Security Classification Compal Secret Data Compal Electronics, Inc.

- Issued Date 2009/12/01 Deciphered Date 2010/05/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 46 of 54
A B C D
 5 4 3 2 1

2VREF_51125

Note:

1U_0603_10V6K
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

1
PC34

2
D D

PR65 PR66
13K_0402_1% 30K_0402_1%
1 2 1 2

PR67 PR68
TPS51125_B+ 20K_0402_1% 20K_0402_1%
1 2 1 2 TPS51125_B+
PL103 Typ: 175mA
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
B+ 1 2 +3VLP

ENTRIP2

ENTRIP1
2200P_0402_50V7K

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0603_25V7K

0.1U_0603_25V7K
PR69 PR70
174K_0402_1% 140K_0402_1%
PC36

PC43
4.7U_0805_10V6K
1 2 1 2
1

1
PC37

PC38

PC39

PC40

PC41

PC42
PQ24

5
PQ23

SIS412DN-T1-GE3_PAK1212-8
PU3
2

2
SIS412DN-T1-GE3_PAK1212-8

PC44

ENTRIP2

FB2

TONSEL

REF

FB1

ENTRIP1
1
25 P PAD
4

2
4
7 24
VO2 VO1 SPOK 45
PC45 8 23 PR72 PC46

3
2
1
C 0.1U_0603_25V7K
PR71 VREG3 PGOOD 2.2_0603_5%
0.1U_0603_25V7K C
1
2
3
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
2.2_0603_5%
PL5 UG_3V 10
VFB=2.0V 21 UG_5V PL6
2.2UH 20% FDVE0630-H-2R2M=P3 8.3A UGATE2 UGATE1 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%
1 2 LX_3V 11 20 LX_5V 1 2 +5VALWP
+3VALWP PHASE2 PHASE1
1

1
4.7_1206_5%

4.7_1206_5%
PQ25 LG_3V 12 19 LG_5V
LGATE2 LGATE1

5
PR73

PR74
330U_D2E_6.3VM_R25~D

PQ26

SKIPSEL
SIS406DN-T1-GE3_PAK1212-8

VREG5

SIS406DN-T1-GE3_PAK1212-8
GND
45 MAINPWON

VIN
RT8205EGQW_WQFN24_4X4

NC
EN
1 1
2

2
4 1 2
PJP3 PC47 + PR266 4 +

13

14

15

16

17

18
1

1
680P_0402_50V7K

680P_0402_50V7K
2 1 PR75 0_0402_5%~D@
2 1
PC49

PC50
499K_0402_1% PC48
@ JUMP_43X118 2 @ 2
330U_D2E_6.3VM_R25~D
1 2
2

1
2
3

2
B+

3
2
1
PJP4 PR76

100K_0402_1%

1U_0603_10V6K
2 1 499K_0402_1% 1 2
+3VALWP 2 1 +3VALW VL

1
PC51
1 2

1
PR77

PC52
4.7U_0805_10V6K
@ JUMP_43X118 PR78 Typ: 175mA
VS PR222 @ 0_0402_5%

2
ENTRIP1 ENTRIP2 @ 499K_0402_1%
Pre-V

2
DMN66D0LDW-7 2N SOT363-6

1 2

PJP5
DMN66D0LDW-7 2N SOT363-6

1
TPS51125_B+ 2 2 1 1
3

6
PQ63B

0.1U_0603_25V7K
PQ63A

B @ JUMP_43X118 B

2
PC53
PJP6
5 2 2VREF_51125 +5VALWP 2 2 1 1 +5VALW
@ JUMP_43X118
4

VL 2 1

PR79
1

100K_0402_1%
1 2
45 MAINPWON PR264
0_0402_5%~D
1 2 2
5VALWP
VS TDC 5.7 A
3.3VALWP
40.2K_0402_1%

2.2U_0603_16V5K

PR80
1

Peak Current 9.636 A

SSM3K7002FU_SC70-3

100K_0402_1% PQ29 TDC 6.5 A

1
PR81

PC54

DTC115EUA_SC70-3
3

PR221 Peak Current 10.874 A OCP current 12.5A low side mos
1

200K_0402_1% D
RDS 14.5m ohm 11.5m ohm
2

OCP current 14.1A

PQ61

ACPRN1 2 2
46 ACPRN
2

G
S
3
1

EC_ON 2
25,42
A EC_ON A

PQ62
DTC115EUA_SC70-3
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/05/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 47 of 54
5 4 3 2 1
 A B C D

PJP7
1.5_51117_B+ 2 1
2 1 B+
@ JUMP_43X118

2200P_0402_50V7K

0.1U_0603_25V7K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
1

1
5

PC56

PC57

PC58

PC59

PC60
PQ30

2
PR82
267K_0402_1% 4
1
PR83 1 2 1

0_0402_5%
1 2
25,43 SYSON FDMC7692 1N MLP

3
2
1
PR84 PC62 PL8
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMC063T-1R0MN_11A_20%

15

14
+1.5VP

1
PU4 BST_1.5V 1 2BST_1.5V-1 1 2 1 2
PC61

EN/DEM

NC

BOOT
.1U_0402_16V7K

2
2 13 DH_1.5V
TON UGATE

10U_0805_6.3V6M
.1U_0402_16V7K
1

330U_D2_2VM_R6M~D
PR87 3 12 LX_1.5V
VOUT PHASE

1
PC64

PC65
10_0603_5% PR85 +

PC63
1 2 4 11 1 2 +5VALW PQ31 4.7_1206_5%
+5VALW VDD CS PR86

2
1
10K_0402_1% 2
5 10

2
PC70 FB VDDP

1
1U_0603_10V6K 6 9 4

2
PGOOD LGATE

PGND
PC67

GND

1
4.7U_0805_10V6K PC68

2
@ PC69
@PC69 680P_0402_50V7K
47P_0402_50V8J RT8209MGQW WQFN 14P PWM DL_1.5V

3
2
1

2
1 2 FDMC7672S 1N MLP

PR88
1 2

1
2
10K_0402_1% 2
1

DDR GPIO Output Voltage Selection

PR248 PR89
+3VALW @ 150K_0402_1%~D 10K_0402_1% 1.5VP
bit2 = 1.5DDR_VID0 bit1 = 1.5DDR_VID1 DDR Vout TDC 8.9A
2
2
1

Peak Current 12.72 A

PR242
DMN66D0LDW-7 2N SOT363-6

0 0 1.65V
10K_0402_5%~D OCP current 16.5A
6

+3VALW PQ69A 0 1 1.6V low side mos RDS 4.5ohm 3.6ohm

2

PR240 2
1

10K_0402_5%~D 1 0 1.55V
10K_0402_5%~D

0.01UF_0402_25V7K

@ PJP8
DMN66D0LDW-7 2N SOT363-6

2 2 1 1
3

1 1 1.5V (Default)
1

PC618

PR244 PQ69B @ JUMP_43X118

15 1.5VDDR_VID0
2

PR250

10K_0402_5%~D
1 2 5 +1.5VP PJP9 +1.5V
2

@ 2 1
2

2 1
1

1
0.01UF_0402_25V7K

+3VALW
4
1
10K_0402_5%~D
PR246

PC616

PR249 @ JUMP_43X118
75K_0402_1%~D
2
2

1
PR100
1.2K_0402_1%~D
+3VALW

2
3 3

PJP10
1

1
+0.75VSP 2 2 1 1 +0.75VS
PR243 PR101
DMN66D0LDW-7 2N SOT363-6

10K_0402_5%~D 1K_0402_1%~D PU5 @ JUMP_43X79

6

+3VALW RT9026_MSOP10

4.7U_0805_6.3V6K~D

4.7U_0805_6.3V6K~D
PQ68A
2

2
1

1U_0603_10V6K~D
PR241 2 1 10 +3VALW
10K_0402_5%~D @PJP22
@ PJP22 VDDQSNS VIN
DMN66D0LDW-7 2N SOT363-6

1
PC104
@ +1.5V 1 2 2
1

1 2 VLDOIN
3

1
PC82
10K_0402_5%~D

PC146
0.01UF_0402_25V7K

PR245 PQ68B
15 1.5VDDR_VID1
2

2
10K_0402_5%~D JUMP_43X118
8
2

2
GND
1

1 2 5 @ 6
VTTREF
1
PR251

PC619
0.01UF_0402_25V7K

+0.75VSP 3 VTT
4
1

1
4.7U_0805_6.3V6K~D

4.7U_0805_6.3V6K~D

5 9 PR166
2

VTTSNS S5
1

PC617

PR247 10K_0402_1%~D PC143

2

PGND
10K_0402_5%~D 7 1 2 0.1U_0402_16V7K~D

GND

2
S3
1

1
2

PC171

PC103
2

11
+0.75VSP

1
@
PC105 Thermal Design Current:0.7A
.1U_0402_16V7K~D

2
Peak current:1A
Vout=VDDQSNS/2=1.5V/2=0.75V
4 4

SUSP# 9,17,25,43,49,50,51,53

Security Classification Compal Secret Data

2009/12/01 2010/05/28 Title
Issued Date Deciphered Date PWR-+1.5VP/+0.75VSP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 48 of 54
A B C D
 5 4 3 2 1

PJP503
D D
1.35V_B+ 2 1
2 1 B+
@ JUMP_43X118

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0603_25V7K
1

1
5

PC517

PC518

PC519

PC520

PC521
PQ505

2
@
PR518
267K_0402_1% 4
PR519 1 2

1 2
9,17,25,43,48,50,51,53 SUSP# SIS412DN-T1-GE3_POWERPAK8-5

3
2
1
102K_0402_1%
PR520 PC522 PL504
2.2_0603_5% 0.1U_0603_25V7K 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

15

14
+1.5VSP
1

1
PU502 BST_1.35V 1 2BST_1.35V-1 1 2 1 2
PC523

EN/DEM

NC

BOOT
.1U_0402_16V7K
2

2 13 DH_1.35V
TON UGATE

10U_0805_6.3V6M
.1U_0402_16V7K

220U_D2_2VY_R15M
1

1
3 12 LX_1.35V
VOUT PHASE

1
PC527

PC525
PR521 +

PC524
4 VFB=0.75V 11 1 2 +5VALW PQ506 @ 4.7_1206_5%
VDD CS PR522

2
8.87K_0402_1% 2 PJP504
5 10

2
FB VDDP +1.5VSP +1.5VS
2 2 1 1

1
6 PGOOD LGATE 9 4

PGND
PR523 PC528 @ JUMP_43X118

GND

1
10_0603_5% 4.7U_0805_10V6K @ PC529

2
1 2 @PC530
@ PC530 680P_0402_50V7K
+5VALW 47P_0402_50V8J RT8209MGQW WQFN 14P PWM DL_1.35V

3
2
1

2
1 2
1

C C
PC531
1U_0603_10V6K SIS406DN-T1-GE3 1N POWERPAK1212-8
2

1.5VSP (for VRAM)

PR524
TDC 4 A
1 2
Peak Current 5.55 A
10.2K_0402_1% OCP current 7.215 A
1

PR525
10K_0402_1%
Low Side MOS RDS(on)=11.7m ohm(Typ),14.2m ohm(Max)
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/08/03 Deciphered Date 2011/08/03 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+VCCSAP/+1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 49 of 54
5 4 3 2 1
 5 4 3 2 1

PJP11
VCCP_51117_B+ 2 1
2 1 B+

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K
@ JUMP_43X118

0.1U_0603_25V7K
1

1
PC76

PC77

PC78
5

1
PC175
PC176
PR93 PQ33

2
267K_0402_1%

2
1 2
D PR94 D
0_0402_5% 4
1 2
9,17,25,43,48,49,51,53 SUSP# SIR472DP-T1-GE3_POWERPAK8-5~D

1
PR95 PC80

15

14
1
@PC81
@PC81 PU6 2.2_0603_5% 0.1U_0603_25V7K PL10

3
2
1
0.1U_0402_16V7K BST_VCCP 1 2BST_VCCP-11 2 0.68UH_PCMC063T-R68MN_15.5A_20%

EN/DEM

NC

BOOT
+VCCPP

2
1 2
2 13 DH_VCCP
TON UGATE

1
PR96

5
3 12 LX_VCCP
VOUT PHASE PQ34

10U_0805_6.3V6M
.1U_0402_16V7K
PR97

330U_D2_2.5VY_R9M
4 VDD CS 11 1 2 1
+5VALW 4.7_1206_5%

1 2

PC83
5 VFB=0.75V 10 8.45K_0402_1% PR99 +
FB VDDP

2
4

PC410

PC413
PR98 6 9 10_0603_5%

2
PGOOD LGATE 2

PGND
10_0603_5% PC85

GND

2
1 2 4.7U_0805_10V6K PC86
+5VALW

2
+5VS

3
2
1

1
RT8209MGQW WQFN 14P PWM DL_VCCP 680P_0402_50V7K

8
1
@PC88
@ PC88
PC89 47P_0402_50V8J
2

1U_0603_10V6K 1 2 SIR164DP-T1-GE3 1N POWERPAK SO8

2

2
PR409

VCCP_AGND
@ 10K_0402_5% PR102
@ PR410
@PR410 PR411 0_0402_5%
1 2 2 1
1

2
100K_0402_5%

G
0.01U_0402_16V7K

10K_0402_5% PR414 PR105

1
PR413

C 0_0402_5% @ 35.7K_0402_1% 4.02K_0402_1% C

1

PC417

3 1 1 2 1 2 PJP12
S

2 2 1 1
BSS138W-7-F_SOT323~D

@ PR107 PR108
2

@ @ 10_0402_5% 0_0402_5% @ JUMP_43X118

PQ403 8 VSSIO_SENSE VCCIO_SENSE 8
PR109 1 2 VCCP_AGND 2 1
2

PR106 +VCCPP PJP13 +1.05VS

VCCP_PWRCTRL @ 10K_0402_1%
1 2 +3VS
2 1
10K_0402_1% 2 1
2

52 VTTPWRGOOD @ JUMP_43X118

PJP14
2 2 1 1

@ JUMP_43X118

VCCP
TDC 11.5 A
Peak Current 16.458 A
OCP 21.4 currentA
B low side mos RDS 4.5 ohm(MAX) B

3.6ohm(MAX)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/05/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR+1.05VSP/+VCCPP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 50 of 54
5 4 3 2 1
 A B C D

1 1

PJP27
1.8VSP_RT8290B_B+ 2 1
2 1 B+
@ JUMP_43X79

2200P_0402_50V7K~D

10U_0805_25V6K
0.1U_0603_25V7K~D
PC216

1
PC217

PC218
2

2
2 2

5
PR276 PQ66
267K_0402_1%~D
1 2

PR277 4
0_0402_5%~D
1 2
9,17,25,43,48,49,50,53 SUSP#
1

PR278 PC219 AON7408L_DFN8-5~D PL22

15

14

3
2
1
1
PC220 PU13 2.2_0603_5% 0.1U_0603_25V7K~D 3.3UH_PCMB064T-3R3MS_7A_20%
0.1U_0402_16V7K~D BST_1.8VSP 1 2 BST_1.8VSP-1 2 1 1 2 +1.8VSP

EN/DEM

NC

BOOT
2

TON_1.8VSP 2 13 DH_1.8VSP
TON UGATE

10U_0805_6.3V6M
.1U_0402_16V7K
PR279 VOUT_1.8VSP 3 12 LX_1.8VSP
VOUT PHASE

5
10_0603_5%

1
4.7_1206_5%~D

PC425

PC426
1 2 VDD_1.8VSP 4 11 PQ67
+5VALW VDD CS

PR280
+5VALW 1 PC222
1

FB_1.8VSP 5 VFB=0.75V 10 220U_B2_2.5VM_R15M

2
PC221 FB VDDP +
1U_0603_10V6K~D 6 9 DL_1.8VSP 4
2

2
PGOOD LGATE

PGND
GND

2
AON7408L_DFN8-5~D

680P_0402_50V7K~D
6.19K_0402_1%
RT8209MGQW WQFN 14P PWM
7

3
2
1

1
PR281

PC225
@PC224
@ PC224 PC223
47P_0402_50V8J~D 4.7U_0805_10V6K~D

2
1 2

2
2
3 3

PR282
14.3K_0402_1%~D
1 2
1

PR283
1.8VSP
10K_0402_1%~D TDC 1.225A
2

Peak Current 1.75A

OCP current 2.275A
Low side mos RDS 32
ohm(MAX) 26ohm(typ)

PJP28
+1.8VSP 2 2 1 1 +1.8VS
@ JUMP_43X79

4 4

Security Classification Compal Secret Data

Issued Date 2009/12/01 Deciphered Date 2010/05/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-+1.8VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6961P
Date: Monday, January 24, 2011 Sheet 51 of 54
A B C D
 5 4 3 2 1

D D

PJP16
VCCSAP_IN 2 1
2 1 B+
@ JUMP_43X118

2200P_0402_50V7K

10U_0805_25V6K
0.1U_0603_25V7K
1

1
5

PC98

PC99

PC100
2

2
C PR115 C
267K_0402_1% 4
PR116 1 2 PQ36
0_0402_5% SIS412DN-T1-GE3_PAK1212-8
50 VTTPWRGOOD 1 2

3
2
1
PR117 PC101 PL14
2.2_0603_5% 0.1U_0603_25V7K 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20%

15

14
1

1
PU8 BST_SAP 1 2BST_SAP-1 1 2 2 1 +VCCSAP
PC102

330U_D2_2.5VY_R9M
EN/DEM

NC

BOOT
@ .1U_0402_16V7K
2

2 13 DH_SAP
TON UGATE

10U_0805_6.3V6M
.1U_0402_16V7K
1

1
3 12 LX_SAP
VOUT PHASE

1
PC510

PC508
PR119 +

PC509
4 VFB=0.75V 11 1 2 +5VALW 4.7_1206_5%
VDD CS PR118 PR508

2
2
2

10_0402_5%
5 10 12.1K_0402_1% 0_0402_5%

2
FB VDDP

PR507
4 1 2

1
6 PGOOD LGATE 9

PGND
PR120 PC106 VSSSA_SENSE 9

GND
2

1
10_0603_5% 4.7U_0805_10V6K PC107

1
1 2 @PC108
@ PC108 680P_0402_50V7K
+5VALW

3
2
1
47P_0402_50V8J RT8209MGQW WQFN 14P PWM DL_SAP

2
1 2 PR158
1

0_0402_5%
1

PC109
1U_0603_10V6K
2

PQ37
SI7716ADN-T1-GE3_PAK1212-8 PR510
PR121
0_0402_5%
+3VS 1 2 PR265 1 2 VCCSA_SENSE 9
1 2 +3VS
1K_0402_1%
1

10K_0402_1%
2

PR200 PR122 +VCCSAP PJP17 +VCCSA

SA_PGOOD25
1

B 7.5K_0402_1% B
10K_0402_5% 2 1
9 VCCSA_SEL 2 1
2

PR123 @ JUMP_43X118
1

PR165 15K_0402_1%
1

10K_0402_5% D
2

1 2 2
G
1

1
PMBT2222A_SOT23-3

PR204 S
3
1

100K_0402_5%

@PC177
@ PC177
1 2 2 +VCCSAP
PQ45

PR201

PQ38
2
2

0_0402_5% .1U_0402_16V7K TDC 4.2A

3

@PR192
@ PR192
@ SSM3K7002F_SC59-3 VID[0] VID[1] VCCSA Vout Required Require on 2012 Peak Current 6A
2

10K_0402_5%
0 0 0.9V Yes Yes OCP current 7.8 A
1

0 1 0.8V Yes Yes Low side mos RDS 16.5(MAX)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/12/01 Deciphered Date 2010/05/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-VCCSA_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6761P
Date: Monday, January 24, 2011 Sheet 52 of 54
5 4 3 2 1
 5 4 3 2 1

PL15
VGA_COREP FBMA-L18-453215-900LMA90T_1812

+3VS_DGPU
TDC 22A +VGA_B+ 2 1 B+
15,16,30 DGPU_PWROK

2200P_0402_50V7K
Peak Current 30.54A

0.1U_0603_25V7K
0.1U_0402_16V7K~D
OCP current 36.7A

100K_0402_1%~D

100K_0402_1%~D

10U_0805_25V6K

10U_0805_25V6K
1

1
PC112
Low side mos RDS

PC111

PC113

PC114
1

PC115

PR253

PR239
3.2ohm(max) 2.6ohm(typ)

2
5
+3VS_DGPU
PQ39

2
@ @

2
D D

PR252 PR125 PC116

0_0402_5%~D 2.2_0603_5% 0.1U_0603_25V7K 4
1 2 BST_VGA 1 2 1 2

2
@ PR126
10K_0402_5% PU9 SIR472DP-T1-GE3 1N POWERPAK SO8

3
2
1
PR127 1 10
47.5K_0402_1% PGOOD VBST
1
PR128 1 2 TRIP_VGA 2 9 UG_VGA PL16
22.1K_0402_1% TRIP DRVH 0.56UH_FDUE1040J-H-R56M=P3_31A_20%~D
1 2 EN_VGA 3 8 SW_VGA 1 2 +VGA_COREP
8,49,50,51 EN SW
FB_VGA 4 7 +5VALW
DGPU_PWR_EN VFB V5IN
1

5
PC117

10U_0805_6.3V6M

10U_0805_6.3V6M
1U_0603_6.3V6M

0.1U_0402_10V7K

330U_2VYD2_R7M

330U_2VYD2_R7M
0.1U_0402_16V7K RF_VGA 5 6 LG_VGA PQ40 PQ41 1 1
RF DRVL
1 1 1
2

1
PC118

PC120

PC121
11 PR129 + +
TP

PC119
4.7_1206_5%

PC122

PC123
PR130 TPS51218DSCR_SON10_3X3~D 4 4

2
470K_0402_5% 2 2 2 2 2

1
2 PC124

3
2
1

3
2
1
680P_0603_50V7K

1
SIR164DP-T1-GE3 1N POWERPAK SO8 PR131
100_0402_5%
SIR164DP-T1-GE3 1N POWERPAK SO8

2
PR133 PR134
C 2.74K_0402_1% 0_0402_5% C
VFB=0.7V
2 1 2 1 1 2 +VGASENSE 31
@

PR132
15K_0402_1% PJP19
+VGA_COREP 2 2 1 1 +VGA_CORE
+3VS_DGPU @ JUMP_43X118
2

PJP20
2 2 1 1
PR135
GVID1-2
1

13K_0402_5% @ JUMP_43X118
PR136
1

10K_0402_5% PJP21
2 2 1 1
2

@ JUMP_43X118
PR137
1

10K_0402_5% D PJP23
2 1 2 2 1
30 GPU_VID1 G 2 1
0.01UF_0402_25V7K

S PQ42 @ JUMP_43X118
3

SSM3K7002FU_SC70-3
1
100K_0402_5%

1
PR138

PC125

PR139 GPIO5 GPIO6 N12P-GS

@ 75K_0402_1%
2

GPU_VID0 GPU_VID1 Core Voltage Level

2

B B
1 1 1V
+3VS_DGPU
0 1 0.975V
1

0 0 0.825V
PR140
@ 10K_0402_5%
2

D
2 1 2
30 GPU_VID0 G
PR141 S PQ43
3
0.01UF_0402_25V7K

10K_0402_5%
SSM3K7002FU_SC70-3
1

100K_0402_5%

1
PR142

PC126
2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/13 Deciphered Date 2011/01/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, January 25, 2011 Sheet 53 of 54
5 4 3 2 1
 5 4 3 2 1

CPU_B+ 1 2 B+

10U_0805_25V6K

10U_0805_25V6K
PL17

PC128

PC129
1 HCB4532KF-800T90_1812

5
1

PC130
3.83K_0402_1% 2 1PH1 PQ44 +
PR270 2 1 NTCG
2K_0402_1% 470KB_0402_5%_ERTJ0EV474J UGATEG

2
2

1000P_0402_50V7K
8.06K_0402_1%
PR143
4
1 2

1
1 2

1
PR144
PC204 SIR472DP-T1-GE3 1N POWERPAK SO8 PL18 +VCC_GFXCORE_AXG

PC131
220P_0402_50V7K~D PR145
27.4K_0402_1% 4 1
2

3
2
1
+VCC_GFXCORE_AXG 0.36UH_ETQP4LR36AFC_28A_20%~D

2
PR146 PHASEG 3 2

10K_0402_1%
2 1 PC133

2 PR148 1

1
330P_0402_50V7K
D PC132 10_0402_1% BOOTG 2 PR147 1 2 1 PQ53 D

1
680P_0402_50V7K 4.7_1206_5%
1 2 2.2_0603_5% PQ46 PR151
1

PR150
PC134 PC135 0.22U_0603_10V7K 1_0402_5%
VCC_AXG_SENSE 9

1
PR149 @ 39P_0402_50V7K PR153 680P_0402_50V7K 330P_0402_50V7K PC138

PC136
499K_0402_1% 2 1 2 1 2 1 PC137 4 .1U_0402_16V7K

2
422_0402_1% VSS_AXG_SENSE 9 LGATEG PH22
2 1 4 1 2 1 1 2

1 2
PC139 7.5K_0402_1%
2

150P_0402_50V8J 1000P_0402_50V7K PR156 PR152 10K_0402_5%_ERTJ0ER103J

PC140
2 1 2 1 2 1 2 1 1 PR157 2

3
2
1
PR154 PR155 10_0402_1% 11K_0402_1%

3
2
1

2
475K_0402_1% 2.87K_0402_1% 1 2

ISNG
ISPG
GFXVR_IMON
1
20K_0402_1%

PC141

1
+1.05VS

487_0402_1%~D
0.047U_0603_16V7K PC144 @ SIR164DP-T1-GE3 1N POWERPAK SO8 0.1U_0402_25V6
1

PC142

54.9_0402_1%
.1U_0402_16V7K SIR164DP-T1-GE3 1N POWERPAK SO8

UGATEG

PHASEG

LGATEG
BOOTG
2
0_0402_5%
PR159

PR161
NTCG
2

1
130_0402_1%

PR114

2
PR163

ISNG
ISPG
1

PR162 1 2

1
For shortage changed +3VS @
2

2
PC145

49

48

47

46

45

44

43

42

41

40

39

38

37
0.022U_0402_16V7K

PROG2
GND

COMPG

FBG

VSENG

RTNG

ISPG

ISNG

NTCG

BOOTG

UGG

PHG

LGG
8 VR_SVID_DAT

1
1.91K_0402_1%
8 VR_SVID_ALRT# 1 VWG BOOT2 36
PR164
8 VR_SVID_CLK 2 2 IMONG UG2 35

3 PGOODG PH2 34

SVID_SDA 4 33
GFX_CORE_PWRGD SDA VSSP2
SVID_ALERT# 5 32
C ALERT# LG2 C

PC148
2.2U_0603_10V6K
SVID_SCLK 1 PR167
25 VR_ON 6 SCLK VDDP 31 2 +5VS GFX_CORE

1
0.047U_0603_16V7K

PR169
1 PR168 2 7 VR_ON PWM3 30 0_0603_5% TDC 21.5A

2
IMON +3VS 1 2 0_0402_5% 8 PGOOD LG1 29 LGATE1 CPU_B+ Peak Current 33A

10U_0805_25V6K

10U_0805_25V6K
19.6K_0402_1%

PC147

ISL95831CRZ-T_TQFN48_6X6
OCP current 44A
1

5
1.91K_0402_1% 9 28
IMON VSSP1
1
PR170

PQ48
LL=3.9m

1
PC149

PC150
10 27 PHASE1
VR_HOT# PH1
2

VGATE 5,14,25 11 26 UGATE1

2

2
ISEN3/ FB2

NTC UG1
4
BOOT1

PROG1
12 25

ISUMN

ISUMP
VW BOOT1
COMP

ISEN2

ISEN1

VSEN

VDD
RTN
25,44 VR_HOT#

VIN
0.36UH_ETQP4LR36AFC_28A_20%~D
FB
1

PR171 SIR472DP-T1-GE3 1N POWERPAK SO8 PL19

3
2
1
+1.05VS 1 2 PU10
13

14

15

16

17

18

19

20

21

22

23

24
499_0402_1% PR172 4 1 +VCC_CORE
2

@ 1 2 1 PH32
3 2

1
680P_0402_50V7K 4.7_1206_5%
3.83K_0402_1% 470KB_0402_5%_ERTJ0EV474J PR173 PC153

PR175
2 1 2 1 PQ51 PQ52
PC151 2 PR1741 2.2_0603_5%

0_0402_5%
47P_0402_50V8J 27.4K_0402_1% 0.22U_0603_10V7K
PR176

PR177

1 2
1000P_0402_50V7K
8.06K_0402_1%

1 2 CPU_B+ 4 4
1

2
PR180

PC154

PC155
PR526

1
0_0603_5%
0_0402_5%
2

2
PR181 SI7658ADP-T1-GE3_POWERPAK8-5~D PR182
SI7658ADP-T1-GE3_POWERPAK8-5~D

3
2
1

3
2
1
2 1 +5VS VSUM+
2 1
2

PC157

1.82K_0603_1%~D
1U_0603_10V6K

1_0603_5% PR183
2

B VSUM-2 1 B
PC158

PR195 1_0402_5%
499_0402_1% 0.22U_0603_25V7K
2

PC160 +5VS
33P_0402_50V8J
PR184 CPU_CORE
21

PR185 PC161 VSUM+

2.61K_0402_1%
1 2 2 1 2 1 2 1 PC162 TDC 21.5A
499_0402_1% 470P_0402_50V7K 1
1

Peak Current 33A

PR186
0.022U_0402_16V7K

@ 470P_0402_50V7K
499K_0402_1%
0.33U_0603_10V7K

PC163 PR187 PR188

2 1 2 1 2 1 @ OCP current 43.5A LL=2.9m
1

1.96K_0402_1%
Low side mos RDS 3.2m ohm(max)
1 2
1

1
11K_0402_1%

150P_0402_50V8J 412K_0402_1% PR220

PC164

PC165

PR189

2K_0402_1%
@ PH4 2.6m ohm(typ)
2

2
1 2

10K_0402_5%_ERTJ0ER103J
2

PC202 PR191
2

@ 560P_0402_50V7K~D 2 1 VSUM-
909_0402_1%~D
2

.1U_0402_16V7K
PC172
2

PR190
+VCC_CORE 2 1 create symbol
330P_0402_50V7K

@ 100_0402_1% PC168
1

2 1
PC169

330P_0402_50V7K
8 VCCSENSE
2

8 VSSSENSE 2 1
PC170
PR193 1000P_0402_50V7K
A A
2 1
100_0402_1%
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/01/25 Deciphered Date 2010/05/28 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR +CPU_CORE/+VGFX_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6761P
Date: Monday, January 24, 2011 Sheet 54 of 54
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Version change list (P.I.R. List) EE section Page 1 of 2

Item Reason for change PG# Modify List Date Phase
1 SYSON signal Pull low 43 Add R300 2010/10/15 PT

2 Q21 Reverse 25 Change Q21 DS pin 2010/10/15 PT

3 Fan voltage need to stable 26 Add C1923 2010/10/15 PT

4 Timing change 5 Add RC127,RC128,and Change BOM RC6 resrve 2010/10/15 PT

D D

5 Leakge +3vs 13 Change BOM RH95 to resrve 2010/10/15 PT

6 EA crystal fail 25 Change BOM of C287,C288 2010/10/15 PT

7 EA crystal fail 13 Change BOM of CH23,CH24 2010/10/15 PT

8 EA crystal fail 21 Change BOM of CL18,CL19 2010/10/15 PT

9 High pot 21 Change CL39 to SE120102K1L 2010/10/15 PT

10 DFX request 42 Change JKB1 symbol 2010/10/15 PT

11 ME request 23 Change JBT1 symbol 2010/10/15 PT

12 PCH change version 12 Change BOM UH1 SA00004IV0L 2010/10/15 PT

13 Control LAN LED limiting light 21 Add series connection RL26,RL25,Change BOM RL20 to 0ohm 2010/10/17 PT

14 HuronRiver DG updated for HAD_SYNC pull-down 1M ohm 12 Add RH275 resister connect to HDA_SYNC_R & GND 2010/10/17 PT

15 Control the LCD sequence for AUO requirement 20 Add R2005,R2006 to reserve EN_INVPWR & +LCDVDD solution 2010/10/17 PT

16 Control the LCD sequence for AUO requirement 20 Add R2013,R2014,Q305 to reserve INVPWR_B+ Discharg Circuit 2010/10/20 PT

17 USB3.0 controller change to UPD720200AF1DAPA 24 Add R1962,R1963 to UPD720200AF1DAPA solution 2010/10/20 PT

18 NV request 28 Change R463,R465 pin2 net to +3VS_DGPU 2010/10/22 PT

19 NV request 33 Change BOM of RV109,RV116 to 1Kohm 2010/10/22 PT

20 The double pull low 29 Change BOM R937 to resrve 2010/10/22 PT

C C

21 Modify screw H18 for ME request 39 Change H18 symbol 2010/10/22 PT

22 The EC request 25 Change R1095 to EC_CRY2 net, 2010/10/22 PT

23 The EC request 25 Change BOM R253 to 0ohm,R1095 to 100Kohm,C287,C288, X1 resrve 2010/10/24 PT

24 The EC request 25 Change BOM R225 to 8.2kohm 2010/10/24 PT

25 The EC request 25 Change R222 to D71 2010/10/26 PT

26 Intel request 12~19 Change BOM UH1 SA00004IV1L 2010/12/1 ST

27 Changed from +3vs to +valw to fix issue can't wake from S3 by port of USB3.0 24 Change BOM Del R1963 ,Add R1962 2010/12/1 ST

28 NV request 41 Change BOM RV88 to 4.99K ohm 2010/12/1 ST

29 Maximum derateing changed from 12V to 20V 9 Change BOM QC4 to SB00000HK0L 2010/12/1 ST

30 Maximum derateing changed from 2V to 2.5V 9 Change BOM CC176 to SGA00005H0L 2010/12/1 ST

31 EMI request 20 Add L5 to SM01000DH0L 2010/12/6 ST

32 EMI request 20 Change BOM CU63 to 100PF 2010/12/6 ST

33 EMI request 20 Change BOM C1167 to 22PF 2010/12/6 ST

34 GLAN orange LED too dark 21 Change BOM RL26 to 200ohm 2010/12/6 ST

35 The EC request 25 Add C1947 to SE071200J8L 2010/12/8 ST

36 The safety request 12 Change DH4 pin1,2,3 2010/12/8 ST

B B

37 The USB3_SMI# signal change to GPIO14 15 Change UH1 pin C23 and H15 2010/12/8 ST

38 The DP Power Dongle 29 Add C110 2010/12/8 ST

39 The ME request 8 Change BOM C110 to C112 2010/12/9 ST

40 For ENE EC protect 20 1/12 add D13, R395

41
42
43
44
45
46
47
48
49
50
51
A 52 A

53
54

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/07/25 Deciphered Date 2010/07/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW Changed-List History-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-6961P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 24, 2011 Sheet 55 of 55
5 4 3 2 1
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