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    CAO IAT 2 QP 2019 Set 2

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    formyphd
    1) The document outlines the course objectives, outcomes, and assessment for a Computer Architecture and Organization course. It covers topics like data representation, arithmetic operations, control unit design, memory interfacing, and parallel processing. 2) The assessment contains 3 parts - multiple choice questions, problems to explain concepts, and numerical problems. It evaluates the students on different cognitive levels from remembering to evaluating. 3) Sample questions assess subtraction using 2's complement, floating point addition rules, pipeline characteristics like bubbles, and representation of floating point numbers in IEEE 754 format.

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    CAO IAT 2 QP 2019 Set 2

    Uploaded by

    formyphd
    36 views2 pages
    1) The document outlines the course objectives, outcomes, and assessment for a Computer Architecture and Organization course. It covers topics like data representation, arithmetic operations, control unit design, memory interfacing, and parallel processing. 2) The assessment contains 3 parts - multiple choice questions, problems to explain concepts, and numerical problems. It evaluates the students on different cognitive levels from remembering to evaluating. 3) Sample questions assess subtraction using 2's complement, floating point addition rules, pipeline characteristics like bubbles, and representation of floating point numbers in IEEE 754 format.

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    1) The document outlines the course objectives, outcomes, and assessment for a Computer Architecture and Organization course. It covers topics like data representation, arithmetic operations, control unit design, memory interfacing, and parallel processing. 2) The assessment contains 3 parts - multiple choice questions, problems to explain concepts, and numerical problems. It evaluates the students on different cognitive levels from remembering to evaluating. 3) Sample questions assess subtraction using 2's complement, floating point addition rules, pipeline characteristics like bubbles, and representation of floating point numbers in IEEE 754 format.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    36 views2 pages

    CAO IAT 2 QP 2019 Set 2

    Uploaded by

    formyphd
    1) The document outlines the course objectives, outcomes, and assessment for a Computer Architecture and Organization course. It covers topics like data representation, arithmetic operations, control unit design, memory interfacing, and parallel processing. 2) The assessment contains 3 parts - multiple choice questions, problems to explain concepts, and numerical problems. It evaluates the students on different cognitive levels from remembering to evaluating. 3) Sample questions assess subtraction using 2's complement, floating point addition rules, pipeline characteristics like bubbles, and representation of floating point numbers in IEEE 754 format.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 2

    Reg. No.

    :
    Mohamed Sathak A J College of Engineering
    Siruseri IT Park, OMR, Chennai - 603103.
    Assessment – II Exam(Set B)
    Date /Time Max. Marks 50 Marks
    Subject with Code EC 8552 - Computer Architecture And Time 90 minutes
    Organization
    Branch ECE Year/Semester III/V

    Course Objectives
    The Student should be able
    S. No. Course Objective
    1 To make students understand the basic structure and operation of digital computer
    2 To familiarize with implementation of fixed point and floating-point arithmetic operations
    3 To study the design of data path unit and control unit for processor
    4 To understand the concept of various memories and interfacing
    5 To introduce the parallel processing technique
    Course Outcomes:
    On Completion of the course the students will be able to
    CO No. Course Outcome
    1 Describe data representation, instruction formats and the operation of a digital computer
    2 Illustrate the fixed point and floating-point arithmetic for ALU operation
    3 Discuss about implementation schemes of control unit and pipeline performance
    4 Explain the concept of various memories, interfacing and organization of multiple processors
    5 Discuss parallel processing technique and unconventional architectures

    BLOOMS TAXONOMY(BT Level)


    K1-Remembering , K2-Understanding, K3-Applying, K4-Analyzing, K5-Evaluating ,K6-Creating
    Part A (7x2=14 marks) CO BT level Univ. QP
    (Answer all the questions) Mapping Reference
    1 Subtract (11011)2-(10011)2 using 2‘s complement. 2 K2 May 2017

    2 What do mean by Subword Parallelism? 2 K2 15,16,18

    3 What is guard bit? What are the ways to truncate the guard bits? 2 K2 Nov16

    4 State the rule for floating point addition. 2 K2 Apr 2017

    5 What are the major characteristics of a pipeline? 3 K1 Nov2014

    6 What is meant by pipeline bubble? 3 K2 Nov 2016

    7 What is the ideal CPI of a pipelined processor? 3 K1 Apr2018


    Part B (2x13=26marks) CO BT Univ.QP Marks
    (Answer all the questions) level Reference Alloted
    8 (a) Explain the Booth’s multiplication algorithm with suitable 2 K4 Apr2018 13
    example.

    (OR)

    (b) Explain how floating point addition is carried out in a 2 K3 Apr 2017 13
    computer system. Give an example for a binary floating
    point addition.

    9 (a) What is data hazard? Explain the ways and means of 3 K3 Apr2018 13
    handing it in pipelined datapath.

    OR

    (b) Draw a simple MIPS data path with the control unit and 3 K3 Dec 2018 13
    explain the execution of ALU instructions.

    Part C (1x10=10marks) CO BT Univ.QP Marks


    level Reference Alloted
    10. (a) How IEEE 752 single,Double precision floating point 2 K4 Nov18 10
    number -0.75 is represented?
    OR
    (b) A processor has five individual stages, namely IF 3 K5 Dec 2018 10
    ,ID, EX, MEM, and WB and their latencies are
    250ps,350 ps,150ps,300ps and 200ps respectively.
    The frequency of the instructions executed by the
    processor are as follows: ALU 40%, Branch 25%,
    Load 20% and Store 15%.What is the clock
    cycle time in a pipelined and non-pipelined
    processor? If you can split one stage of the
    pipelined data path into two stages, each with
    half the latency of the original stage, which
    stage would you split and what is the new clock
    cycle time of the processor? Assuming there are
    no stalls or hazards, what is the utilization of the
    data memory? Assuming there are no stalls or
    hazards, what is the utilization of the write-
    register port of the ‘Registers” unit?

    *****ALL THE BEST****

    Prepared By Verified By Approved By

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