A B C D E

1 1

Compal Confidential
2 2

QIWY3 M/B Schematics Document

Intel IVY Bridge Processor with DDRIII + Panther Point PCH
nVIDIA N13X

3 2011-12-23 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 1 of 64
A B C D E
 A B C D E

Compal confidential
File Name : Y480
Chief River
nVIDIA N13P-GT/GL1 Intel
1 PCI-E X16 IVY Bridge 1

Gen 1/2/3 Processor DDR3-SO-DIMM X2

VRAM 64*32 BANK 0, 1, 2, 3
GDDR5*8 Socket-rPGA989
37.5mm*37.5mm Dual Channel UP TO 16G
DDR3-1333(1.5V)
HDMI DDR3-1600(1.5V)
HDMI1.4a
SATA3.0 HDD CONN
CONN FDI *8 DMI2 *4
100MHz 100MHz SATA3.0 HDD (SSD)
optimus 2012 2.7GT/s 5GT/s
CRT Connector 6*SATA SATA ODD CONN
(port0,1 Support SATA3)
2

LVDS
optimus 2012 Intel 4*USB3.0
2

Connector Panther Point 14*USB2.0

CMOS Camera
PCI Express USB(WiMAX) PCH
6*PCI-E x1 BlueTooth CONN
Mini card Slot 1 PCI-E(WLAN) FCBGA 989 Balls
WLAN/WiMAX
25mm*25mm USB PORT 3.0 x2(Left)
PCI Express SATA(SSD)
Mini card Slot 2 HD Audio WLAN/WiMAX
SSD
USB PORT 2.0 x1(Right)
SPI ROM LPC BUS
BIOS USB PORT 3.0 x1 (Right)
3 with USB charger Audio Board 3

EC
ENE KB9012
Card Reader
JBM389C LAN(Gbe) 2Channel Speaker
SD/MMC/MS/XD Arthros
AR8161/AR8151
Audio Board Int.KBD Audio Codec Array Digital MIC
RealTek
WLAN/WiMAX Touch Pad ALC269-VC
RJ45 CONN Audio Jacks
Stereo
HeadPhone Output
Sub-borad Microphone Input
Thermal Sensor
4
Audio Board 4
POWER BOARD EMC1403/2103

Function BOARD
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

Audio Board THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 2 of 64
A B C D E
 A B C D E

Voltage Rails
SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+1.5VS
power +VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
plane +V1.5S_VCCP
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1
+CPU_CORE 1
+5VALW +1.5V
+VGA_CORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+B
+GFX_CORE
+3VALW S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.8VS
+1.05VS
State
+0.75VS BOARD ID Table Board ID / SKU ID Table for AD channel
+3.3VS_VGA Vcc 3.3V +/- 5%
+1.5VS_VGA
Board ID PCB Revision
Ra/Rc/Re 10K +/- 5%
+1.05VS_VGA
0 0.1 Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max Project
1 QIWY3
0 0 0 V 0 V 0 V EVT
2 QIWY3
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V DVT
3 QIWY3
S0
2 18K +/- 5% 0.436 V 0.503 V 0.538 V PVT
O O O O 4
3 33K +/- 5% 0.712 V 0.819 V 0.875 V QIWY3 MP
5 QIWY4
4 56K +/- 5% 1.036 V 1.185 V 1.264 V EVT
6 QIWY4
S3
5 100K +/- 5% 1.453 V 1.650 V 1.759 V DVT
O O O X 7 QIWY4
6 200K +/- 5% 1.935 V 2.200 V 2.341 V PVT
2 7 NC 2.500 V 3.300 V 3.300 V QIWY4 MP 2
S5 S4/AC
O O X X USB Port Table
4 External BOM Structure Table
S5 S4/ Battery only USB 2.0 USB 3.0 Port
O X X X USB Port BOM Structure BTO Item
1 0 USB Port (Right Side) OPTI@ OPTIMUS part
S5 S4/AC & Battery
don't exist X X X X 2 1 HDMI@ HDMI part
XHCI TV module part
3 2 USB Port (Left Side) TV@
SMBUS Control Table EHCI1
4 3
4
USB Port (Left Side) CHG@
NOCHG@
USB charger part
No USB charger part
Thermal
WLAN Sensor 5 Camera BT@ Blue Tooth part
SOURCE VGA BATT KE9012 SODIMM WWAN PCH CMOS Camera part
6 CMOS@
SMB_EC_CK1
SMB_EC_DA1
KB9012
+3VALW
X V
+3VALW
X X X X X 7
8
8161@
8151@
AR8161 LAN part
AR8151 LAN part
SMB_EC_CK2
SMB_EC_DA2
KB9012
+3VALW
X X X X X X V
+3VS
9
10
USB Port (Right Side)
Mini Card(WLAN)
8161S@
8151S@
AR8161 LAN surge part
AR8151 LAN surge part
EHCI2

3
SMBCLK
SMBDATA
PCH
+3VALW
X X X V
+3VS
V
+3VS
X X 11
12 Mini Card(TV)
SURGE@
61@
AR8151&8161 LAN surge part
X76 P/N for AR8161 3

SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X 13 Blue Tooth 51@
X76@
X76 P/N for AR8151
X76 Level part for VRAM
SML1CLK
SML1DATA
PCH
+3VALW
V
+3VS
X V
+3VS
X X V
+3VS
X PCIE PORT LIST
Port Device
S1G@
S2G@
X76 P/N for Samsun VRAM 1G
X76 P/N for Samsun VRAM 2G
H1G@ X76 P/N for Hynix VRAM 1G
Address
1 LAN
H2G@ X76 P/N for Hynix VRAM 2G
EC SM Bus1 address EC SM Bus2 address 2 WLAN GL@ N13P-GL part
3 TV
GT@ N13P-GT part
Device Device Address 4 Card Reader
GE@ N13E-GE part
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb 5 GTGE@ N13P-GT&N13E-GE common part
6 GC6@ NV CG6 support part
7 NOGC6@ NV no CG6 support part
PCH SM Bus address 8 1403@ EMC1403 thermal part
2103@ EMC2103 thermal part
Device Address
KBL@ K/B Light part
DDR DIMM0 1001 000Xb
4 ME@ ME part 4
DDR DIMM2 1001 010Xb
@ Unpop

ZZZ1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

DA80000Q800
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 3 of 64
A B C D E
 5 4 3 2 1

Hot plug detect for IFP link C

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
FBVDDQ PCI Express I/O and I/O and Other
VGA and GDDR5 Voltage Rails (N13Px GPIO) GPU Mem NVCLK FBVDD (GPU+Mem) (1.05V) PLLVDD PLLVDD
(4) (1,5) /MCLK NVVDD (1.35V) (1.35V) (6) (1.8V) (1.05V) (3.3V)
GPIO I/O ACTIVE Function Description Products (W) (W) (MHz) (V) (A) (W) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W)

GPIO0 OUT - GPU VID4 N13X

128bit TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
D
1GB D
GPIO1 OUT - GPU VID3 GDDR5

GPIO2 OUT N/A

Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
GPIO3 OUT N/A
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
GPIO4 OUT N/A ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE
GPIO5 OUT - GPU VID1
STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
GPIO6 OUT - GPU VID2 STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
GPIO7 OUT N/A
STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
GPIO8 I/O - Thermal Catastrophic Over Temperature STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
CHANGE_GEN3
GPIO9 OUT - GC6 event
Device ID
GPIO10 OUT - Memory VREF Control N13P-GT
(28nm) 0x0FDB
GPIO11 OUT - GPU VID0
C
N13E-GE C
(28nm) 0x0FDB
GPIO12 IN AC Power Detect Input (10K pull High)
N13P-GL1
GPIO13 OUT - GPU VID5 (40nm) 0x0DE9

GPIO14 OUT N/A

GPIO15 IN N/A (100K pull low) GPU ROM_SO ROM_SCLK STRAP4 STRAP3 STRAP2 STRAP1 STRAP0

GPIO16 OUT N/A N13P-GT PU 10K PU 5K PD 45K PD 5K PD 10K PD 35K PU 45K

GPIO17 IN N/A N13E-GE PU 10K PU 5K PD 45K PD 5K PD 25K PD 35K PU 45K

GPIO18 IN N/A N13P-GL PD 10K PD 15K NC NC PU 10K PD 45K PU 45K

GPIO19 IN N/A
GPU N13P-GT N13E-GE N13P-GL

FB Memory (GDDR5) ROM_SI ROM_SI ROM_SI

Samsung K4G10325FG-HC04
B
+3VS_VGA 2500MHz B

32Mx32 PD 45K PD 45K PD 45K

+VGA_CORE
Hynix H5GQ1H24BFR-T2C
tNVVDD >0 2500MHz
+1.5VS_VGA 32Mx32 PD 35K PD 35K PD 35K
tFBVDDQ >0
Samsung K4G20325FD-FC04
+1.05VS_VGA 2500MHz
tPEX_VDD >0 64Mx32 PD 30K PD 30K PD 30K

1. all power rail ramp up time should be larger than 40us

Hynix H5GQ2H24MFR-T2C
2500MHz
64Mx32 PD 25K PD 25K PD 25K

Other Power rail

+3VS_VGA
A A

Tpower-off <10ms

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
1.all GPU power rails should be turned off within 10ms
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 4 of 64
5 4 3 2 1
 5 4 3 2 1

D D
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+1.05VS impedance = 43 mohms
PEG_ICOMPO signals should be routed with -

1
max length = 500 mils
R1
24.9_0402_1%
- typical impedance = 14.5 mohms
JCPU1A

2
J22 PEG_COMP
PEG_ICOMPI
J21
PEG_ICOMPO
<16> DMI_CRX_PTX_N0 B27 H22
DMI_RX#[0] PEG_RCOMPO
<16> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 A25 PCIE_CRX_GTX_N[0..15] <23>
DMI_RX#[2] PCIE_CRX_GTX_N15
<16> DMI_CRX_PTX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33
M35 PCIE_CRX_GTX_N14
PEG_RX#[1] PCIE_CRX_GTX_N13
<16> DMI_CRX_PTX_P0 B28 L34
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12
<16> DMI_CRX_PTX_P1 B26
DMI_RX[1] PEG_RX#[3]
J35 PEG Static Lane Reversal - CFG2 is for the 16x
A24 J32 PCIE_CRX_GTX_N11
<16> DMI_CRX_PTX_P2

DMI
DMI_RX[2] PEG_RX#[4] PCIE_CRX_GTX_N10
<16> DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches
PEG_RX#[6] PCIE_CRX_GTX_N8
<16> DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 CFG2 socket pin map definition
E22 G30 PCIE_CRX_GTX_N7
<16> DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PCIE_CRX_GTX_N6
<16> DMI_CTX_PRX_N2 F21 F35
DMI_TX#[2] PEG_RX#[9] PCIE_CRX_GTX_N5
D21 E34 0:Lane Reversed
<16>

<16>
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 G22
DMI_TX#[3]

DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3 *
D22 D31 PCIE_CRX_GTX_N2
C <16> DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PCIE_CRX_GTX_N1 C
<16> DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33

PCI EXPRESS* - GRAPHICS

C21 C32 PCIE_CRX_GTX_N0
<16> DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] <23>
J33 PCIE_CRX_GTX_P15
PEG_RX[0] PCIE_CRX_GTX_P14
PEG_RX[1] L35
K34 PCIE_CRX_GTX_P13
PEG_RX[2] PCIE_CRX_GTX_P12
<16> FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PCIE_CRX_GTX_P11
<16> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] PCIE_CRX_GTX_P10
<16> FDI_CTX_PRX_N2 E19 FDI0_TX#[2] PEG_RX[5] G34
F18 G31 PCIE_CRX_GTX_P9
<16> FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]

Intel(R) FDI
B21 F33 PCIE_CRX_GTX_P8
<16> FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PCIE_CRX_GTX_P7
<16> FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PCIE_CRX_GTX_P6
<16> FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] PCIE_CRX_GTX_P5
<16> FDI_CTX_PRX_N7 E17 E33
FDI1_TX#[3] PEG_RX[10] PCIE_CRX_GTX_P4
F32
PEG_RX[11] PCIE_CRX_GTX_P3
D34
PEG_RX[12] PCIE_CRX_GTX_P2
<16> FDI_CTX_PRX_P0 A22 E31
FDI0_TX[0] PEG_RX[13] PCIE_CRX_GTX_P1
<16> FDI_CTX_PRX_P1 G19 C33
FDI0_TX[1] PEG_RX[14] PCIE_CRX_GTX_P0
<16> FDI_CTX_PRX_P2 E20 B32
FDI0_TX[2] PEG_RX[15] OPT@
<16> FDI_CTX_PRX_P3 G18 FDI0_TX[3] PCIE_CTX_GRX_N[0..15] <23>
B20 M29 PCIE_CTX_GRX_C_N15 C1 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_N15
<16> FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PCIE_CTX_GRX_C_N14 C2 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_N14
<16> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_N13
D19 M31 C3 1 OPT@
2 0.22U_0402_10V6K
<16> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PCIE_CTX_GRX_C_N12 C4 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_N12
<16> FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_N11
L29 C5 1 OPT@
2 0.22U_0402_10V6K
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_C_N10 C6 1 OPT@ PCIE_CTX_GRX_N10
<16> FDI_FSYNC0 J18 K31 2 0.22U_0402_10V6K
+1.05VS FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PCIE_CTX_GRX_C_N9 C7 1 OPT@ PCIE_CTX_GRX_N9
<16> FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28 2 0.22U_0402_10V6K
J30 PCIE_CTX_GRX_C_N8 C8 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_N8
FDI_INT PEG_TX#[7] PCIE_CTX_GRX_C_N7 C9 1 OPT@ PCIE_CTX_GRX_N7
<16> FDI_INT H20 J28 2 0.22U_0402_10V6K
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_C_N6 C10 1 OPT@ PCIE_CTX_GRX_N6
H29 2 0.22U_0402_10V6K
PEG_TX#[9]
1

FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 1 OPT@

2 0.22U_0402_10V6K PCIE_CTX_GRX_N5
<16> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
R7 FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_C_N4 C12 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_N4
B <16> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] B
24.9_0402_1% F27 PCIE_CTX_GRX_C_N3 C13 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_N3
PEG_TX#[12] PCIE_CTX_GRX_C_N2 C14 1 OPT@ PCIE_CTX_GRX_N2
PEG_TX#[13] D28 2 0.22U_0402_10V6K
F26 PCIE_CTX_GRX_C_N1 C15 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_N1
2

PEG_TX#[14] PCIE_CTX_GRX_C_N0 C16 1 PCIE_CTX_GRX_N0

PEG_TX#[15] E25 2 0.22U_0402_10V6K
EDP_COMP A18 OPT@
eDP_COMPIO PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P[0..15] <23>
eDP_COMPIO and ICOMPO signals A17
eDP_ICOMPO PEG_TX[0]
M28 C20 1 OPT@
2 0.22U_0402_10V6K
B16 M33 PCIE_CTX_GRX_C_P14 C23 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_P14
should be shorted near balls eDP_HPD eDP_HPD# PEG_TX[1]
M30 PCIE_CTX_GRX_C_P13 C25 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_P13
PEG_TX[2]
and routed with typical PEG_TX[3]
L31 PCIE_CTX_GRX_C_P12 C30 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_P12
C15 L28 PCIE_CTX_GRX_C_P11 C18 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_P11
impedance <25 mohms D15
eDP_AUX PEG_TX[4]
K30 PCIE_CTX_GRX_C_P10 C22 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_P10
eDP_AUX# PEG_TX[5] PCIE_CTX_GRX_C_P9 C28 1 OPT@ PCIE_CTX_GRX_P9
K27 2 0.22U_0402_10V6K
eDP

PEG_TX[6] PCIE_CTX_GRX_C_P8 C32 1 OPT@ PCIE_CTX_GRX_P8

PEG_TX[7] J29 2 0.22U_0402_10V6K
C17 J27 PCIE_CTX_GRX_C_P7 C19 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_P7
eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_C_P6 C24 1 OPT@ PCIE_CTX_GRX_P6
F16 eDP_TX[1] PEG_TX[9] H28 2 0.22U_0402_10V6K
C16 G28 PCIE_CTX_GRX_C_P5 C29 1 OPT@
2 0.22U_0402_10V6K PCIE_CTX_GRX_P5
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_C_P4 C17 1 OPT@ PCIE_CTX_GRX_P4
G15 E28 2 0.22U_0402_10V6K
eDP_TX[3] PEG_TX[11] PCIE_CTX_GRX_C_P3 C21 1 OPT@ PCIE_CTX_GRX_P3
F28 2 0.22U_0402_10V6K
PEG_TX[12] PCIE_CTX_GRX_C_P2 C27 1 OPT@ PCIE_CTX_GRX_P2
C18 D27 2 0.22U_0402_10V6K
eDP_TX#[0] PEG_TX[13] PCIE_CTX_GRX_C_P1 C26 1 OPT@ PCIE_CTX_GRX_P1
E16 E26 2 0.22U_0402_10V6K
eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_C_P0 C31 1 PCIE_CTX_GRX_P0
D16 D25 2 0.22U_0402_10V6K
eDP_TX#[2] PEG_TX[15]
F15 eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 5 of 64
5 4 3 2 1
 5 4 3 2 1

H : Sandy Bridge
PROC_SEL
L : IVY Bridge JCPU1B Place R10,R11 close to U4
D D
R10 0_0402_5%
A28 CLK_CPU_DMI_R 1 2
BCLK CLK_CPU_DMI <15>
C26 A27 CLK_CPU_DMII#_R R11 1 2

MISC

CLOCKS
<19> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
0_0402_5%
AN34
SKTOCC# R12
DPLL_REF_CLK A16 2 1 1K_0402_5%
A15 R13 2 1 1K_0402_5% +1.05VS
DPLL_REF_CLK#
+1.05VS
T14 PAD H_CATERR# AL33
CATERR#
R9 1 Reserve 43 Ohm resistor closs to EC(250~750mils)
62_0402_5%

THERMAL
H_PECI AN33 R8 H_DRAMRST#
<19,42> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
2

R15

DDR3
MISC
56_0402_5%
<42,50> H_PROCHOT# H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 R16 2 1 140_0402_1%
PROCHOT# SM_RCOMP[0] SM_RCOMP1
SM_RCOMP[1]
A5 R17 2 1 25.5_0402_1% DDR3 Compensation Signals
A4 SM_RCOMP2 R18 2 1 200_0402_1%
SM_RCOMP[2]
H_THEMTRIP# AN32
<19> H_THRMTRIP# THERMTRIP#

AP29 XDP_PRDY# +1.05VS

PRDY# XDP_PREQ#
PREQ# AP27

R22 AR26 XDP_TCK XDP_TMS R20 2 1 51_0402_5%

C TCK XDP_TMS XDP_TDI C
0_0402_5% AR27 R21 2 1 51_0402_5% PU/PD for JTAG signals

PWR MANAGEMENT
TMS

JTAG & BPM

1 2 H_PM_SYNC_R AM34 AP30 XDP_TRST# XDP_TDO R23 2 1 51_0402_5%
<16> H_PM_SYNC PM_SYNC TRST# @
AR28 XDP_TDI XDP_TCK R24 2 1 51_0402_5%
R26 TDI XDP_TDO XDP_TRST# R25 51_0402_5%
TDO AP26 2 1
0_0402_5%1 2 H_CPUPWRGD_R AP33
<19> H_CPUPWRGD UNCOREPWRGOOD
2

1 R29
DBR# AL35 XDP_DBRESET# R28 2 1 1K_0402_5% +3VS
C550 R27 1 2 PM_DRAM_PWRGD_R V8
130_0402_5% SM_DRAMPWROK
100P_0402_50V8J 10K_0402_5% AT28 XDP_BPM#0
2 BPM#[0] XDP_BPM#1
AR29
1

BPM#[1] XDP_BPM#2
AR30
BUF_CPU_RST# BPM#[2] XDP_BPM#3
AR33 AT30
RESET# BPM#[3] XDP_BPM#4
9/23 ESD Request BPM#[4]
AP32
AR31 XDP_BPM#5
BPM#[5] XDP_BPM#6
AT31
BPM#[6] XDP_BPM#7
AR32
BPM#[7]

TYCO_2013620-2_IVY BRIDGE
ME@

+3VS +3VALW
Buffered reset to CPU
<16> SYS_PWROK
+1.5V_CPU_VDDQ
1
1

C33 +3VS
B R65 R338 0.1U_0402_16V4Z B
1

0_0402_5% @ 10K_0402_5%
2 R30
U1 200_0402_5% +1.05VS
1
2

C34
5

0.1U_0402_16V4Z
2

1
P

B PM_SYS_PWRGD_BUF R32 2
4
O 75_0402_5%
<16> PM_DRAM_PWRGD 2
A 1.05V
G

5
74AHC1G09GW_TSSOP5 R34 U2 3V
3

@ 43_0402_1% 1

P
R33 BUF_CPU_RST# BUFO_CPU_RST# 4 NC
1 2 Y
39_0402_5% 2 PCH_PLTRST#
A PCH_PLTRST# <18>

G
1

SN74LVC1G07DCKR_SC70-5
1 2

3
D @ R35 @
<10> RUN_ON_CPU1.5VS3# 2 Q1 0_0402_5%
G 2N7002_SOT23
2

S
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 6 of 64
5 4 3 2 1
 5 4 3 2 1

JCPU1C JCPU1D

<12> DDR_A_D[0..63] SA_CLK[0] AB6 M_CLK_DDR0 <12> <13> DDR_B_D[0..63] SB_CLK[0] AE2 M_CLK_DDR2 <13>
AA6 M_CLK_DDR#0 <12> AD2 M_CLK_DDR#2 <13>
DDR_A_D0 SA_CLK#[0] DDR_B_D0 SB_CLK#[0]
C5 SA_DQ[0] SA_CKE[0] V9 DDR_CKE0_DIMMA <12> C9 SB_DQ[0] SB_CKE[0] R9 DDR_CKE2_DIMMB <13>
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 SA_DQ[1] DDR_B_D2 SB_DQ[1]
D3 SA_DQ[2] D10 SB_DQ[2]
DDR_A_D3 D2 DDR_B_D3 C8
DDR_A_D4 SA_DQ[3] DDR_B_D4 SB_DQ[3]
D6 SA_DQ[4] SA_CLK[1] AA5 M_CLK_DDR1 <12> A9 SB_DQ[4] SB_CLK[1] AE1 M_CLK_DDR3 <13>
D DDR_A_D5 DDR_B_D5 D
C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR#1 <12> A8 SB_DQ[5] SB_CLK#[1] AD1 M_CLK_DDR#3 <13>
DDR_A_D6 C2 V10 DDR_B_D6 D9 R10
DDR_A_D7 SA_DQ[6] SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D7 SB_DQ[6] SB_CKE[1] DDR_CKE3_DIMMB <13>
C3 SA_DQ[7] D8 SB_DQ[7]
DDR_A_D8 F10 DDR_B_D8 G4
DDR_A_D9 SA_DQ[8] DDR_B_D9 SB_DQ[8]
F8 F4
DDR_A_D10 SA_DQ[9] DDR_B_D10 SB_DQ[9]
G10 SA_DQ[10] RSVD_TP[1] AB4 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D11 G9 AA4 DDR_B_D11 G1 AA2
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
F9 SA_DQ[12] RSVD_TP[3] W9 G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D13 F7 DDR_B_D13 F5
DDR_A_D14 SA_DQ[13] DDR_B_D14 SB_DQ[13]
G8 F2
DDR_A_D15 SA_DQ[14] DDR_B_D15 SB_DQ[14]
G7 SA_DQ[15] G2 SB_DQ[15]
DDR_A_D16 K4 AB3 DDR_B_D16 J7 AA1
DDR_A_D17 SA_DQ[16] RSVD_TP[4] DDR_B_D17 SB_DQ[16] RSVD_TP[14]
K5 SA_DQ[17] RSVD_TP[5] AA3 J8 SB_DQ[17] RSVD_TP[15] AB1
DDR_A_D18 K1 W10 DDR_B_D18 K10 T10
DDR_A_D19 SA_DQ[18] RSVD_TP[6] DDR_B_D19 SB_DQ[18] RSVD_TP[16]
J1 K9
DDR_A_D20 SA_DQ[19] DDR_B_D20 SB_DQ[19]
J5 J9
DDR_A_D21 SA_DQ[20] DDR_B_D21 SB_DQ[20]
J4 SA_DQ[21] J10 SB_DQ[21]
DDR_A_D22 J2 AK3 DDR_B_D22 K8 AD3
SA_DQ[22] SA_CS#[0] DDR_CS0_DIMMA# <12> SB_DQ[22] SB_CS#[0] DDR_CS2_DIMMB# <13>
DDR_A_D23 K2 AL3 DDR_B_D23 K7 AE3
DDR_A_D24 SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# <12> DDR_B_D24 SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# <13>
M8 AG1 M5 AD6
DDR_A_D25 SA_DQ[24] RSVD_TP[7] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
N10 AH1 N4 AE6
DDR_A_D26 SA_DQ[25] RSVD_TP[8] DDR_B_D26 SB_DQ[25] RSVD_TP[18]
N8 N2
DDR_A_D27 SA_DQ[26] DDR_B_D27 SB_DQ[26]
N7 SA_DQ[27] N1 SB_DQ[27]
DDR_A_D28 M10 DDR_B_D28 M4
DDR_A_D29 SA_DQ[28] DDR_B_D29 SB_DQ[28]
M9 AH3 M_ODT0 <12> N5 AE4 M_ODT2 <13>
DDR_A_D30 SA_DQ[29] SA_ODT[0] DDR_B_D30 SB_DQ[29] SB_ODT[0]
N9 AG3 M_ODT1 <12> M2 AD4 M_ODT3 <13>

DDR SYSTEM MEMORY B

DDR_A_D31 SA_DQ[30] SA_ODT[1] DDR_B_D31 SB_DQ[30] SB_ODT[1]

DDR SYSTEM MEMORY A

M7 AG2 M1 AD5
DDR_A_D32 SA_DQ[31] RSVD_TP[9] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
AG6 AH2 AM5 AE5
DDR_A_D33 SA_DQ[32] RSVD_TP[10] DDR_B_D33 SB_DQ[32] RSVD_TP[20]
AG5 SA_DQ[33] AM6 SB_DQ[33]
DDR_A_D34 AK6 DDR_B_D34 AR3
DDR_A_D35 SA_DQ[34] DDR_B_D35 SB_DQ[34]
AK5 AP3
DDR_A_D36 SA_DQ[35] DDR_B_D36 SB_DQ[35]
AH5 DDR_A_DQS#[0..7] <12> AN3 DDR_B_DQS#[0..7] <13>
C DDR_A_D37 SA_DQ[36] DDR_A_DQS#0 DDR_B_D37 SB_DQ[36] DDR_B_DQS#0 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AN2 SB_DQ[37] SB_DQS#[0] D7
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D38 AN1 F3 DDR_B_DQS#1
DDR_A_D39 SA_DQ[38] SA_DQS#[1] DDR_A_DQS#2 DDR_B_D39 SB_DQ[38] SB_DQS#[1] DDR_B_DQS#2
AJ6 J3 AP2 K6
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
AJ8 SA_DQ[40] SA_DQS#[3] M6 AP5 SB_DQ[40] SB_DQS#[3] N3
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D41 AN9 AN5 DDR_B_DQS#4
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
AJ9 AM8 AT5 AP9
DDR_A_D43 SA_DQ[42] SA_DQS#[5] DDR_A_DQS#6 DDR_B_D43 SB_DQ[42] SB_DQS#[5] DDR_B_DQS#6
AK9 SA_DQ[43] SA_DQS#[6] AR12 AT6 SB_DQ[43] SB_DQS#[6] AK12
DDR_A_D44 AH8 AM15 DDR_A_DQS#7 DDR_B_D44 AP6 AP15 DDR_B_DQS#7
DDR_A_D45 SA_DQ[44] SA_DQS#[7] DDR_B_D45 SB_DQ[44] SB_DQS#[7]
AH9 SA_DQ[45] AN8 SB_DQ[45]
DDR_A_D46 AL9 DDR_B_D46 AR6
DDR_A_D47 SA_DQ[46] DDR_B_D47 SB_DQ[46]
AL8 SA_DQ[47] AR5 SB_DQ[47]
DDR_A_D48 AP11 DDR_B_D48 AR9
SA_DQ[48] DDR_A_DQS[0..7] <12> SB_DQ[48] DDR_B_DQS[0..7] <13>
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AL12 F6 AT8 G3
DDR_A_D51 SA_DQ[50] SA_DQS[1] DDR_A_DQS2 DDR_B_D51 SB_DQ[50] SB_DQS[1] DDR_B_DQS2
AM12 K3 AT9 J6
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AM11 N6 AH11 M3
DDR_A_D53 SA_DQ[52] SA_DQS[3] DDR_A_DQS4 DDR_B_D53 SB_DQ[52] SB_DQS[3] DDR_B_DQS4
AL11 AL5 AR8 AN6
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AP12 AM9 AJ12 AP8
DDR_A_D55 SA_DQ[54] SA_DQS[5] DDR_A_DQS6 DDR_B_D55 SB_DQ[54] SB_DQS[5] DDR_B_DQS6
AN12 AR11 AH12 AK11
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AJ14 SA_DQ[56] SA_DQS[7] AM14 AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D57 AH14 DDR_B_D57 AN14
DDR_A_D58 SA_DQ[57] DDR_B_D58 SB_DQ[57]
AL15 AR14
DDR_A_D59 SA_DQ[58] DDR_B_D59 SB_DQ[58]
AK15 AT14
DDR_A_D60 SA_DQ[59] DDR_B_D60 SB_DQ[59]
AL14 DDR_A_MA[0..15] <12> AT12 DDR_B_MA[0..15] <13>
DDR_A_D61 SA_DQ[60] DDR_A_MA0 DDR_B_D61 SB_DQ[60] DDR_B_MA0
AK14 AD10 AN15 AA8
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
AJ15 W1 AR15 T7
DDR_A_D63 SA_DQ[62] SA_MA[1] DDR_A_MA2 DDR_B_D63 SB_DQ[62] SB_MA[1] DDR_B_MA2
AH15 SA_DQ[63] SA_MA[2] W2 AT15 SB_DQ[63] SB_MA[2] R7
W7 DDR_A_MA3 T6 DDR_B_MA3
SA_MA[3] DDR_A_MA4 SB_MA[3] DDR_B_MA4
V3 T2
SA_MA[4] DDR_A_MA5 SB_MA[4] DDR_B_MA5
V2 T4
SA_MA[5] DDR_A_MA6 SB_MA[5] DDR_B_MA6
W3 T3
SA_MA[6] DDR_A_MA7 SB_MA[6] DDR_B_MA7
<12> DDR_A_BS0 AE10 W6 <13> DDR_B_BS0 AA9 R2
B SA_BS[0] SA_MA[7] DDR_A_MA8 SB_BS[0] SB_MA[7] DDR_B_MA8 B
<12> DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 <13> DDR_B_BS1 AA7 SB_BS[1] SB_MA[8] T5
V6 W5 DDR_A_MA9 R6 R3 DDR_B_MA9
<12> DDR_A_BS2 SA_BS[2] SA_MA[9] DDR_A_MA10 <13> DDR_B_BS2 SB_BS[2] SB_MA[9] DDR_B_MA10
AD8 AB7
SA_MA[10] DDR_A_MA11 SB_MA[10] DDR_B_MA11
SA_MA[11] V4 SB_MA[11] R1
W4 DDR_A_MA12 T1 DDR_B_MA12
SA_MA[12] DDR_A_MA13 SB_MA[12] DDR_B_MA13
<12> DDR_A_CAS# AE8 AF8 <13> DDR_B_CAS# AA10 AB10
SA_CAS# SA_MA[13] DDR_A_MA14 SB_CAS# SB_MA[13] DDR_B_MA14
<12> DDR_A_RAS# AD9 V5 <13> DDR_B_RAS# AB8 R5
SA_RAS# SA_MA[14] DDR_A_MA15 SB_RAS# SB_MA[14] DDR_B_MA15
<12> DDR_A_WE# AF9 V7 <13> DDR_B_WE# AB9 R4
SA_WE# SA_MA[15] SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

ME@ +1.5V ME@

@ R36
1

0_0402_5%
1 2 R37
1K_0402_5%

R38
2

1K_0402_5%
S

<6> H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# <12,13>

2

Q2
R39 BSS138_NL_SOT23-3
G
2

4.99K_0402_1%
1

A A

<15> DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL

R40 0_0402_5%
<10> DRAMRST_CNTRL
1 2
<42> DRAMRST_CNTRL_EC
R64
@
0_0402_5%
1
C35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
9/5 Reserve for Deep S3 0.047U_0402_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
Module design used 0.047u AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 7 of 64

5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

1
R41
1K_0402_1%

2
D D

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

CFG2 socket pin map definition

0:Lane Reversed
* CFG4

1
@ R42
JCPU1E 1K_0402_1%

2
AH27 PAD T13
VCC_DIE_SENSE
AK28 AH26
CFG[0] VSS_DIE_SENSE
AK29
CFG[1]

2
CFG2 AL26 CFG[2] R2
AL27 CFG[3] Display Port Presence Strap
CFG4 AK26 L7 0_0402_5%
CFG5 CFG[4] RSVD28
AL29 AG7
C CFG6 CFG[5] RSVD29 C
AL30 AE7 1 : Disabled; No Physical Display Port
*

1
CFG7 CFG[6] RSVD30
AM31
CFG[7] RSVD31
AK2 CFG4 attached to Embedded Display Port
AM32
CFG[8]
AM30 W8

CFG
CFG[9] RSVD32
+VCC_GFXCORE_AXG
AM28 CFG[10] 0 : Enabled; An external Display Port device is
AM26 connected to the Embedded Display Port
CFG[11]
AN28 CFG[12] RSVD33 AT26
2

AN31 AM33
R161 CFG[13] RSVD34
AN26 CFG[14] RSVD35 AJ27
49.9_0402_1% AM27
+VCC_CORE CFG[15] CFG6
AK31 CFG[16]
AN29
1

CFG[17]
2

CFG5
R187

1
49.9_0402_1% T8
RSVD37 @ R43 @ R44
J16
VCC_AXG_VAL_SENSE RSVD38 1K_0402_1% 1K_0402_1%
AJ31 H16
1

VAXG_VAL_SENSE RSVD39
@R71
@ R71 1 2 100_0402_1% VSS_AXG_VAL_SENSE AH31 G16
VCC_VAL_SENSE VSSAXG_VAL_SENSE RSVD40
AJ33

2
VCC_VAL_SENSE
@R72
@ R72 1 2 100_0402_1% VSS_VAL_SENSE AH33 VSS_VAL_SENSE

AJ26 AR35
RSVD5 RSVD_NCTF1
AT34
RSVD_NCTF2

RESERVED
VSS_AXG_VAL_SENSE AT33
RSVD_NCTF3
AP35
VSS_VAL_SENSE RSVD_NCTF4
RSVD_NCTF5 AR34
PCIE Port Bifurcation Straps
2

F25
RSVD8
R291 R196 F24 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
49.9_0402_1% 49.9_0402_1% F23
D24
RSVD9
RSVD10
RSVD11 RSVD_NCTF6 B34 CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B
G25 A33 disabled
1

RSVD12 RSVD_NCTF7
G24 A34
RSVD13 RSVD_NCTF8
E23 RSVD14 RSVD_NCTF9 B35 01: Reserved - (Device 1 function 1 disabled ; function
D23 C35 2 enabled)
RSVD15 RSVD_NCTF10
C30
RSVD16
A31
RSVD17 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
B30
RSVD18
B29
RSVD19
INTEL 12/28 recommand D30
B31
RSVD20 RSVD51 AJ32
AK32
RSVD21 RSVD52
to add R187, R161, R291, R196 A30
RSVD22
CFG7
C29
Please place as close as JCPU1 RSVD23

1
AN35 @R45
@ R45
BCLK_ITP 1K_0402_1%
J20 AM35
RSVD24 BCLK_ITP#
B18
RSVD25

2
J15 AT2
RSVD27 RSVD_NCTF11
RSVD_NCTF12 AT1
AR1
RSVD_NCTF13
PEG DEFER TRAINING

KEY B1
1: (Default) PEG Train immediately following xxRESETB
CFG7 de assertion

A
0: PEG Wait for BIOS for training A
TYCO_2013620-2_IVY BRIDGE

ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 8 of 64
5 4 3 2 1
 5 4 3 2 1

JCPU1F POWER
+VCC_CORE
+1.05VS
QC=94A
8.5A
DC=53A AG35 VCC1
AG34 AH13
VCC2 VCCIO1
AG33 VCC3 VCCIO2 AH10
AG32 AG10
VCC4 VCCIO3
AG31 VCC5 VCCIO4 AC10
D D
AG30 VCC6 VCCIO5 Y10
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 L10
VCC9 VCCIO8
AG26 J14
VCC10 VCCIO9
AF35 VCC11 VCCIO10 J13
AF34 J12
VCC12 VCCIO11
AF33 VCC13 VCCIO12 J11
AF32 VCC14 VCCIO13 H14
AF31 H12
VCC15 VCCIO14
AF30 VCC16 VCCIO15 H11
AF29 G14
VCC17 VCCIO16
AF28 VCC18 VCCIO17 G13
AF27 G12

PEG AND DDR

VCC19 VCCIO18
AF26 F14
VCC20 VCCIO19
AD35 F13
VCC21 VCCIO20
AD34 VCC22 VCCIO21 F12
AD33 F11
VCC23 VCCIO22
AD32 VCC24 VCCIO23 E14
AD31 E12
VCC25 VCCIO24
AD30
VCC26
AD29 E11
VCC27 VCCIO25
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 D12
VCC30 VCCIO28
AC35 VCC31 VCCIO29 D11
AC34 C14
VCC32 VCCIO30
AC33 C13
VCC33 VCCIO31
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
AC30 B14
VCC36 VCCIO34
AC29 B12
C VCC37 VCCIO35 C
AC28 VCC38 VCCIO36 A14
AC27 A13
VCC39 VCCIO37
AC26 A12
VCC40 VCCIO38
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 J23
VCC43 VCCIO40
AA32 VCC44
AA31
VCC45
AA30 VCC46
AA29
VCC47
AA28 VCC48
AA27
VCC49
AA26 VCC50
Y35 +1.05VS

CORE SUPPLY
VCC51
Y34
VCC52 Place the PU resistor close to CPU
Y33
VCC53
Y32 1
VCC54

1
Y31
VCC55 C36 R46
Y30
VCC56 0.1U_0402_10V7K
Y29 VCC57 75_0402_5%
Y28 2
VCC58
Y27

2
VCC59
Y26
VCC60
V35
VCC61 H_CPU_SVIDALRT# R47
V34 AJ29 1 2 43_0402_5%

SVID
VCC62 VIDALERT# H_CPU_SVIDCLK VR_SVID_ALRT# <57>
V33 AJ30 R48 1 2 0_0402_5%
VCC63 VIDSCLK VR_SVID_CLK <57>
V32 AJ28 H_CPU_SVIDDAT R49 1 2 0_0402_5%
VCC64 VIDSOUT VR_SVID_DAT <57>
V31
VCC65
V30
VCC66 R50
V29 2 1 130_0402_5% +1.05VS
VCC67
V28
VCC68
V27
B VCC69 B
V26 VCC70
U35 VCC71 Place the PU resistor close to CPU
U34
VCC72
U33 VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
U28
VCC77 VCC_SENCE 100ohm +-1% pull-up to VCC near processor
VCC78
U27 VCC79
U26 VCC80
R35 +VCC_CORE
VCC81
R34 VCC82
R33
VCC83

1
R32 VCC84
R31 R51
VCC85
R30 100_0402_1%
VCC86
R29
VCC87
R28
SENSE LINES

2
VCC88
R27 AJ35 VCCSENSE_R R52 1 2 0_0402_5%
VCCSENSE <57>
VCC89 VCC_SENSE
R26 AJ34 VSSSENSE_R R53 1 2 0_0402_5%
VSSSENSE <57>
VCC90 VSS_SENSE R1294 10_0402_1%
P35 VCC91
P34 2 1 +1.05VS @ R73 1 2 100_0402_1%
VCC92

1
P33 VCC93
P32 B10 R54
VCC94 VCCIO_SENSE VCCIO_SENSE <55>
P31 A10 VSSIO_SENSE 100_0402_1%
VCC95 VSS_SENSE_VCCIO VSSIO_SENSE <55>
P30 VCC96

2
P29

2
VCC97 R1297
P28
VCC98
P27 10_0402_1%
VCC99
P26
VCC100
1
A A

VSS_SENCE 100ohm +-1% pull-down to GND near processor

TYCO_2013620-2_IVY BRIDGE
Security Classification Compal Secret Data Compal Electronics, Inc.
ME@ Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) PWR,BYPASS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 9 of 64
5 4 3 2 1
 5 4 3 2 1

+1.5V @ J1 +1.5V_CPU_VDDQ
1 2

1
PAD-OPEN 4x4m +1.5V
1
R55
1 2 220_0402_5% @ C92
<48,53,55> SUSP 0_0402_5% R668 @ 0.1U_0402_10V6K
2

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
1
+VSB D

C95

C96

C286

C287
+3VALW U3 1 1 1 1
8 1 Q3 2 RUN_ON_CPU1.5VS3#
D D S 2N7002_SOT23 G D
7 D S 2

1
6 3 @ S

3
R667 D S +1.5V_CPU_VDDQ 2 2 2 2
5 D G 4
100K_0402_5%
@ R56 DMN3030LSS-13_SOP8L-8
100K_0402_5%

2
R1349
RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3 1 2

1
1

1
D D 470K_0402_5%
<42,48,55> CPU1.5V_S3_GATE 1 2 2 Q9 2 Q4 R57 C97 Place the PU/PD resistor close to CPU within 2 inch
0_0402_5% R58 @ G 2N7002_SOT23 G 2N7002_SOT23 330K_0402_5% 0.01U_0603_50V7K
S @ S @ 2 (Reserve power side)

2
<42,48,53,55,56> SUSP# 1 2
0_0402_5% R59 @
+VCC_GFXCORE_AXG VCC_AXG_SENSE <57>
<6> RUN_ON_CPU1.5VS3#

POWER VSS_AXG_SENSE <57>

2
+VCC_GFXCORE_AXG R66
JCPU1G 100_0402_1%
+1.5V_CPU_VDDQ +1.5V
46A R76 @ 100_0402_1% @ R61

1
AT24 AK35 1 2 0_0402_5%

SENSE
LINES
VAXG1 VAXG_SENSE

1
AT23 VAXG2 VSSAXG_SENSE AK34 2 1
AT21 R89 100_0402_1% R77 @ R62
VAXG3 1K_0402_1% 1K_0402_1%
AT20 2 1
VAXG4
AT18 VAXG5
AT17

2
VAXG6 +V_SM_VREF_CNT +V_SM_VREF
AR24 2 3
VAXG7
AR23
VAXG8

1
C 0.1U_0402_16V4Z 1 @Q5
@ Q5 C
AR21 VAXG9
AR20 C114 R88 AP2302GN-HF_SOT23-3 @ R63
VAXG10 1K_0402_1% 1K_0402_1%
AR18 AL1
VAXG11 SM_VREF 1
AR17 VAXG12
AP24 2 RUN_ON_CPU1.5VS3

VREF

2
VAXG13
AP23
VAXG14
AP21 VAXG15
AP20 B4 +V_DDR_REFA_R All VREF traces should keep 20/20 mils(wide/spacing)
VAXG16 SA_DIMM_VREFDQ +V_DDR_REFB_R
AP18 VAXG17 SB_DIMM_VREFDQ D1
AP17
VAXG18 6/28 Follow module design
AN24 VAXG19
AN23
VAXG20
AN21 VAXG21
AN20
<7> DRAMRST_CNTRL VAXG22
AN18
VAXG23 5A

DDR3 -1.5V RAILS

AN17 +1.5V_CPU_VDDQ
VAXG24
2

Q8 BSS138_SOT23
G

AM24 AF7

GRAPHICS
VAXG25 VDDQ1
AM23 AF4
VAXG26 VDDQ2

330U_D2_2.5VY_R9M
1 3 AM21 AF1 1
VAXG27 VDDQ3

C123
AM20 AC7
D

+VREF_DQ_DIMMA VAXG28 VDDQ4 1 1 1 1 1 1

10U_0603_6.3V6M
C117

10U_0603_6.3V6M
C118

10U_0603_6.3V6M
C119

10U_0603_6.3V6M
C120

10U_0603_6.3V6M
C121

10U_0603_6.3V6M
C122
AM18 AC4 +
VAXG29 VDDQ5
AM17 AC1
VAXG30 VDDQ6 @
AL24 Y7
+VREF_DQ_DIMMB @ VAXG31 VDDQ7 2 2 2 2 2 2 2
AL23 Y4
R74 +V_DDR_REFA_R VAXG32 VDDQ8
1 2 0_0402_5% AL21 Y1
R75 +V_DDR_REFB_R VAXG33 VDDQ9
1 2 0_0402_5% AL20 U7
@ VAXG34 VDDQ10
AL18 VAXG35 VDDQ11 U4
AL17 U1
VAXG36 VDDQ12
1

AK24 P7
VAXG37 VDDQ13
AK23 P4
R139 R132 VAXG38 VDDQ14
AK21 P1
1K_0402_1% 1K_0402_1% VAXG39 VDDQ15
1 3 AK20
D

B @ @ VAXG40 B
AK18
2

Q7 BSS138_SOT23 VAXG41
AK17 VAXG42
AJ24
G
2

DRAMRST_CNTRL VAXG43
AJ23 VAXG44
AJ21
VAXG45 +VCCSA
6/8 Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ) AJ20
VAXG46 6A
AJ18
VAXG47 +VCCSA
AJ17 M27
VAXG48 VCCSA1

SA RAIL
AH24 M26
VAXG49 VCCSA2
AH23 VAXG50 VCCSA3 L26

330U_D2_2.5VY_R9M
AH21 VAXG51 VCCSA4 J26 1 1 1 1 1

10U_0603_6.3V6M
C124

10U_0603_6.3V6M
C125

10U_0603_6.3V6M
C126

10U_0603_6.3V6M
C127

C128
AH20 J25
VAXG52 VCCSA5 @ + @
AH18 VAXG53 VCCSA6 J24
AH17 H26
VAXG54 VCCSA7 2 2 2 2
VCCSA8 H25
2

11/07 Change type to 0603

1.8V RAIL

H23 +VCCSA_SENSE <54>

+1.8VS R67 VCCSA_SENSE
0_0805_5% @
1 2 +1.8VS_VCCPLL B6 R68 1 2 0_0402_5%
VCCPLL1
A6 C22
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 <54>

10U_0603_6.3V6M
C130

1U_0402_6.3V6K
C131

1U_0402_6.3V6K
C132

1 1 1 1 A2
VCCPLL3 VCCSA_VID[1]
C24 H_VCCSA_VID1 <54>6/3 modify for VCCSA 4-Level voltage
22U_0805_6.3V6M
C279

22U_0805_6.3V6M
C345

2 2 2 2
@ @
2 VCCIO_SEL
A19 6/3 Add VCCIO_SEL for processor select
VCCIO_SEL Voltage
A TYCO_2013620-2_IVY BRIDGE H_VCCP_SEL R69 A
1 2 0_0402_5%
1 1.05V
11/07 Change type to 0603 ME@ R234 2 1 +3VS
10K_0402_5%
R266 2 1 +3VALW 0 1.0V
@ 10K_0402_5%
6/9 change 330U to 22U X2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 10 of 64
5 4 3 2 1
 5 4 3 2 1

JCPU1H JCPU1I
D D
AT35 VSS1 VSS81 AJ22
AT32 VSS2 VSS82 AJ19
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
AT27 AJ13 T34 F19
VSS4 VSS84 VSS162 VSS235
AT25 AJ10 T33 E30
VSS5 VSS85 VSS163 VSS236
AT22 VSS6 VSS86 AJ7 T32 VSS164 VSS237 E27
AT19 AJ4 T31 E24
VSS7 VSS87 VSS165 VSS238
AT16 VSS8 VSS88 AJ3 T30 VSS166 VSS239 E21
AT13 VSS9 VSS89 AJ2 T29 VSS167 VSS240 E18
AT10 AJ1 T28 E15
VSS10 VSS90 VSS168 VSS241
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 AH34 T26 E10
VSS12 VSS92 VSS170 VSS243
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 AH30 P8 E8
VSS14 VSS94 VSS172 VSS245
AR22 AH29 P6 E7
VSS15 VSS95 VSS173 VSS246
AR19 AH28 P5 E6
VSS16 VSS96 VSS174 VSS247
AR16 VSS17 VSS98 AH25 P3 VSS175 VSS248 E5
AR13 AH22 P2 E4
VSS18 VSS99 VSS176 VSS249
AR10 VSS19 VSS100 AH19 N35 VSS177 VSS250 E3
AR7 AH16 N34 E2
VSS20 VSS101 VSS178 VSS251
AR4 AH7 N33 E1
VSS21 VSS102 VSS179 VSS252
AR2 AH4 N32 D35
VSS22 VSS103 VSS180 VSS253
AP34 VSS23 VSS104 AG9 N31 VSS181 VSS254 D32
AP31 VSS24 VSS105 AG8 N30 VSS182 VSS255 D29
AP28 AG4 N29 D26
VSS25 VSS106 VSS183 VSS256
AP25 VSS26 VSS107 AF6 N28 VSS184 VSS257 D20
AP22 AF5 N27 D17
VSS27 VSS108 VSS185 VSS258
AP19 AF3 N26 C34
VSS28 VSS109 VSS186 VSS259
AP16 VSS29 VSS110 AF2 M34 VSS187 VSS260 C31
AP13 VSS30 VSS111 AE35 L33 VSS188 VSS261 C28
AP10 AE34 L30 C27
VSS31 VSS112 VSS189 VSS262
AP7 AE33 L27 C25
C VSS32 VSS113 VSS190 VSS263 C
AP4 VSS33 VSS114 AE32 L9 VSS191 VSS264 C23
AP1 AE31 L8 C10
VSS34 VSS115 VSS192 VSS265
AN30 AE30 L6 C1
VSS35 VSS116 VSS193 VSS266
AN27 VSS36 VSS117 AE29 L5 VSS194 VSS267 B22
AN25 AE28 L4 B19
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
AN16 AE9 L1 B13
VSS40 VSS121 VSS198 VSS271
AN13 VSS41 VSS122 AD7 K35 VSS199 VSS272 B11
AN10 AC9 K32 B9
VSS42 VSS123 VSS200 VSS273
AN7 VSS43 VSS124 AC8 K29 VSS201 VSS274 B8
AN4 AC6 K26 B7
VSS44 VSS125 VSS202 VSS275
AM29 VSS45 VSS126 AC5 J34 VSS203 VSS276 B5
AM25 AC3 J31 B3
VSS46 VSS127 VSS204 VSS277
AM22 AC2 H33 B2
VSS47 VSS128 VSS205 VSS278
AM19 AB35 H30 A35
VSS48 VSS129 VSS206 VSS279
AM16 AB34 H27 A32
VSS49 VSS130 VSS207 VSS280
AM13 AB33 H24 A29
VSS50 VSS131 VSS208 VSS281
AM10 AB32 H21 A26
VSS51 VSS132 VSS209 VSS282
AM7 VSS52 VSS133 AB31 H18 VSS210 VSS283 A23
AM4 AB30 H15 A20
VSS53 VSS134 VSS211 VSS284
AM3 AB29 H13 A3
VSS54 VSS135 VSS212 VSS285
AM2 AB28 H10
VSS55 VSS136 VSS213
AM1 AB27 H9
VSS56 VSS137 VSS214
AL34 AB26 H8
VSS57 VSS138 VSS215
AL31 Y9 H7
VSS58 VSS139 VSS216
AL28 VSS59 VSS140 Y8 H6 VSS217
AL25 Y6 H5
VSS60 VSS141 VSS218
AL22 Y5 H4
VSS61 VSS142 VSS219
AL19 Y3 H3
VSS62 VSS143 VSS220
AL16 Y2 H2
VSS63 VSS144 VSS221
AL13 W35 H1
B VSS64 VSS145 VSS222 B
AL10 VSS65 VSS146 W34 G35 VSS223
AL7 VSS66 VSS147 W33 G32 VSS224
AL4 W32 G29
VSS67 VSS148 VSS225
AL2 VSS68 VSS149 W31 G26 VSS226
AK33 W30 G23
VSS69 VSS150 VSS227
AK30 W29 G20
VSS70 VSS151 VSS228
AK27 W28 G17
VSS71 VSS152 VSS229
AK25 W27 G11
VSS72 VSS153 VSS230
AK22 W26 F34
VSS73 VSS154 VSS231
AK19 VSS74 VSS155 U9 F31 VSS232
AK16 VSS75 VSS156 U8 F29 VSS233
AK13 U6
VSS76 VSS157
AK10 VSS77 VSS158 U5
AK7 U3
VSS78 VSS159
AK4 VSS79 VSS160 U2
AJ25
VSS80

TYCO_2013620-2_IVY BRIDGE TYCO_2013620-2_IVY BRIDGE

ME@ ME@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 11 of 64
5 4 3 2 1
 5 4 3 2 1

<7> DDR_A_D[0..63]
+1.5V
+VREF_DQ_DIMMA <7> DDR_A_DQS[0..7]
+1.5V +1.5V

1
3A@1.5V
<7> DDR_A_DQS#[0..7]
R78
1K_0402_1% DDR3 SO-DIMM A <7> DDR_A_MA[0..15]
JDIMM1

2
+VREF_DQ_DIMMA 1 2
VREF_DQ VSS1 DDR_A_D4
3 VSS2 DQ4 4

0.1U_0402_10V6K

2.2U_0603_6.3V6K
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C140

C141
1 1 DDR_A_D1 7 8
D DQ1 VSS3 DDR_A_DQS#0 D
9 VSS4 DQS#0 10
R79 DDR_A_DM0 11 12 DDR_A_DQS0
1K_0402_1% DM0 DQS0
13 VSS5 VSS6 14
2 2 DDR_A_D2 DDR_A_D6
15 16
2 DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# <7,13>
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72
C C

<7> DDR_CKE0_DIMMA DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA

CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
<7> DDR_A_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92

DDR_A_MA3
93
95
VDD7 VDD8 94
96 DDR_A_MA2 OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98

<7> M_CLK_DDR0 M_CLK_DDR0

99
101
VDD9 VDD10 100
102 M_CLK_DDR1
Layout Note: (10uF_0603_6.3V)*8
CK0 CK1 M_CLK_DDR1 <7>
<7> M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
M_CLK_DDR#1 <7>
Place near DIMM
CK0# CK1#
DDR_A_MA10
105
107
VDD11 VDD12 106
108 DDR_A_BS1 (0.1uF_402_10V)*4
A10/AP BA1 DDR_A_BS1 <7>
<7> DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS# +1.5V
BA0 RAS# DDR_A_RAS# <7>
111 VDD13 VDD14 112
<7> DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA#
WE# S0# DDR_CS0_DIMMA# <7>

1
<7> DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 <7>
117 118 R80 +1.5V
DDR_A_MA13 VDD15 VDD16 M_ODT1 1K_0402_1%
119 A13 ODT1 120 M_ODT1 <7>
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
S1# NC2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
123 124

2
VDD17 VDD18

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
125 126 +VREF_CA 1
NCTEST VREF_CA

C151

C142

C143

C152

C144

C145

C153

C146

C154

C155

C147

C156
127 VSS27 VSS28 128 1 1 1 1 1 1 1 1 1 1 1 1

0.1U_0402_10V6K

2.2U_0603_6.3V6K
DDR_A_D32 129 130 DDR_A_D36 + C148
DQ32 DQ36

1
C149

C150
B DDR_A_D33 131 132 DDR_A_D37 1 1 220U_6.3V_M B
DQ33 DQ37 @ @
133 VSS29 VSS30 134
DDR_A_DQS#4 DDR_A_DM4 R81 2 2 2 2 2 2 2 2 2 2 2 2 2
135 DQS#4 DM4 136
DDR_A_DQS4 137 138 1K_0402_1%
DQS4 VSS31 DDR_A_D38 2 2
139 140

2
DDR_A_D34 VSS32 DQ38 DDR_A_D39
141 DQ34 DQ39 142
DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44
145 VSS34 DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_A_DQS#5
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 DM5 DQS5 154
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46 Layout Note:
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 162 Place near DIMM
DDR_A_D48 VSS39 VSS40 DDR_A_D52
163 DQ48 DQ52 164
DDR_A_D49 165 166 DDR_A_D53
DQ49 DQ53
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6
DDR_A_DQS6 DQS#6 DM6 +0.75VS
171 DQS6 VSS43 172
173 174 DDR_A_D54 DDR_A_DM0
DDR_A_D50 VSS44 DQ54 DDR_A_D55 DDR_A_DM1
175 DQ50 DQ55 176
DDR_A_D51 177 178 DDR_A_DM2
DQ51 VSS45 DDR_A_D60 DDR_A_DM3
179 VSS46 DQ60 180

C288

1U_0402_6.3V6K
C158

1U_0402_6.3V6K
C159

1U_0402_6.3V6K
C160

1U_0402_6.3V6K
DDR_A_D56 181 182 DDR_A_D61 DDR_A_DM4
DDR_A_D57 DQ56 DQ61 DDR_A_DM5
183 DQ57 VSS47 184 1 1 1 1
185 186 DDR_A_DQS#7 DDR_A_DM6
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7 DDR_A_DM7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_A_D58 DDR_A_D62 2 2 2 2
191 DQ58 DQ62 192
DDR_A_D59 193 194 DDR_A_D63 Layout Note:
A DQ59 DQ63 A
1 R82 2 195 VSS51 VSS52 196
10K_0402_5% 197 SA0 EVENT# 198 Place near DIMM
199 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 <13,15,36>
2.2U_0603_6.3V6K

0.1U_0402_10V6K

201 202 SMB_CLK_S3

SA1 SCL SMB_CLK_S3 <13,15,36>
C290

C162

1 203 VTT1 VTT2 204 +0.75VS

1 10K_0402_5%
R83

1
205 206 0.65A@0.75V
G1 G2

2
2 LCN_DAN06-K4806-0103 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
2

ME@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 12 of 64
5 4 3 2 1
 5 4 3 2 1

+1.5V <7> DDR_B_D[0..63]

<7> DDR_B_DQS[0..7]
3A@1.5V

1
+VREF_DQ_DIMMB <7> DDR_B_DQS#[0..7]
R84
1K_0402_1% +1.5V +1.5V
<7> DDR_B_MA[0..15]
JDIMM2

2
+VREF_DQ_DIMMB 1 2
VREF_DQ VSS1 DDR_B_D4
3 VSS2 DQ4 4

2.2U_0603_6.3V6K

0.1U_0402_10V6K
DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5

1
1 1 DDR_B_D1 7 8
DQ1 VSS3

C289
9 10 DDR_B_DQS#0
VSS4 DQS#0

C157
D R85 DDR_B_DM0 11 12 DDR_B_DQS0 D
1K_0402_1% DM0 DQS0
13 VSS5 VSS6 14
2 2 DDR_B_D2 DDR_B_D6
15 16
2 DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
19 VSS7 VSS8 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# <7,12>
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D24 57 58 DDR_B_D29
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_B_D26 67 68 DDR_B_D30
DDR_B_D27 DQ26 DQ30 DDR_B_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72
C C

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
<7> DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD9 VDD10 100
M_CLK_DDR2 M_CLK_DDR3
<7> M_CLK_DDR2
<7> M_CLK_DDR#2 M_CLK_DDR#2
101
103
CK0 CK1 102
104 M_CLK_DDR#3
M_CLK_DDR3 <7> Layout Note: (10uF_0603_6.3V)*8
CK0# CK1# M_CLK_DDR#3 <7>
105 106 Place near DIMM
DDR_B_MA10 VDD11 VDD12 DDR_B_BS1
<7> DDR_B_BS0 DDR_B_BS0
107
109
A10/AP BA1 108
110 DDR_B_RAS#
DDR_B_BS1 <7> +1.5V (0.1uF_402_10V)*4
BA0 RAS# DDR_B_RAS# <7>
111 VDD13 VDD14 112
<7> DDR_B_WE# DDR_B_WE# 113 114 DDR_CS2_DIMMB#
WE# S0# DDR_CS2_DIMMB# <7>

1
<7> DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2
CAS# ODT0 M_ODT2 <7>
117 118 R86
DDR_B_MA13 VDD15 VDD16 M_ODT3 1K_0402_1% +1.5V
119 A13 ODT1 120 M_ODT3 <7>
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC2
123 124

2
VDD17 VDD18

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
125 126 +VREF_CB
NCTEST VREF_CA

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K
127 VSS27 VSS28 128

2.2U_0603_6.3V6K

C161

C282

C163

C164

C165

C166

C167

C168

C169

C170

C171

C172
DDR_B_D32 129 130 DDR_B_D36 1 1 1 1 1 1 1 1 1 1 1 1
DQ32 DQ36

1
C280
DDR_B_D33 131 132 DDR_B_D37 1 1
DQ33 DQ37

C281
B 133 134 B
DDR_B_DQS#4 VSS29 VSS30 DDR_B_DM4 R87 @ @
135 DQS#4 DM4 136
DDR_B_DQS4 1K_0402_1% 2 2 2 2 2 2 2 2 2 2 2 2
137 DQS4 VSS31 138
DDR_B_D38 2 2
139 140

2
DDR_B_D34 VSS32 DQ38 DDR_B_D39
141 DQ34 DQ39 142
DDR_B_D35 143 144
DQ35 VSS33 DDR_B_D44
145 VSS34 DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS36 DQS#5 DDR_B_DQS5
153 DM5 DQS5 154
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46 Layout Note:
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162 Place near DIMM
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6 +0.75VS
171 DQS6 VSS43 172
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55 DDR_B_DM0
175 DQ50 DQ55 176
DDR_B_D51 177 178 DDR_B_DM1
DQ51 VSS45 DDR_B_D60 DDR_B_DM2
179 VSS46 DQ60 180

C173

1U_0402_6.3V6K
C174

1U_0402_6.3V6K
C175

1U_0402_6.3V6K
C176

1U_0402_6.3V6K
DDR_B_D56 181 182 DDR_B_D61 DDR_B_DM3
DDR_B_D57 DQ56 DQ61 DDR_B_DM4
183 DQ57 VSS47 184 1 1 1 1
185 186 DDR_B_DQS#7 DDR_B_DM5
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7 DDR_B_DM6
187 DM7 DQS7 188
189 190 DDR_B_DM7
DDR_B_D58 VSS49 VSS50 DDR_B_D62 2 2 2 2
191 DQ58 DQ62 192
DDR_B_D59 193 194 DDR_B_D63
DQ59 DQ63
195 VSS51 VSS52 196
A 1 R95 A
10K_0402_5%
2 197 SA0 EVENT# 198
SMB_DATA_S3
Layout Note:
199 VDDSPD SDA 200 SMB_DATA_S3 <12,15,36>
+3VS 1 2 201 SA1 SCL 202 SMB_CLK_S3
SMB_CLK_S3 <12,15,36>
Place near DIMM
2.2U_0603_6.3V6K

0.1U_0402_10V6K

R97 10K_0402_5% 203 204 +0.75VS

VTT1 VTT2 0.65A@0.75V
C178

1 1
C177

205 G1 G2 206

TYCO_2-2013287-1
2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
ME@ Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 13 of 64
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

W=20mils W=20mils 1 2 PCH_RTCX2

R98 10M_0402_5%
+RTCVCC +RTCBATT
Y1
R99 1 2
1K_0402_5%
1 2 32.768KHZ_12.5PF_CM31532768DZFT

15P_0402_50V8J
1
1
C179 CLRP1 1 1
1U_0603_10V4Z SHORT PADS C181

2
C180 18P_0402_50V8J
2
D 2 2 D

CMOS
+RTCVCC
U4A

SHORT PADS
CLRP2
R101 1 2 1M_0402_5% SM_INTRUDER#
+RTCVCC PCH_RTCX1 A20 C38 LPC_AD0
1 RTCX1 FWH0 / LAD0 LPC_AD0 <36,42>

1
R102 1 2 330K_0402_5% PCH_INTVRMEN A38 LPC_AD1
FWH1 / LAD1 LPC_AD1 <36,42>

LPC
C183 PCH_RTCX2 C20 B37 LPC_AD2 EC and Mini card debug port
RTCX2 FWH2 / LAD2 LPC_AD3 LPC_AD2 <36,42>
1U_0603_10V4Z C37 LPC_AD3 <36,42>

2
2 PCH_RTCRST# FWH3 / LAD3
1 2 D20
R103 20K_0402_5% RTCRST# LPC_FRAME#
INTVRMEN FWH4 / LFRAME#
D36 LPC_FRAME# <36,42>
：Integrated 1 2 PCH_SRTCRST# G22
SRTCRST#
* LH： Integrated VRM enable R100 20K_0402_5% 1 LDRQ0# E36

1
SHORT PADS
CLRP3
SM_INTRUDER#

RTC
VRM disable K22
INTRUDER# LDRQ1# / GPIO23
K36
C182 +3VS
(INTVRMEN should always be pull high.) 1U_0603_10V4Z PCH_INTVRMEN C17 V5 R104 2 1 10K_0402_5%

2
2 INTVRMEN SERIRQ
SERIRQ
SERIRQ <42>
AM3 SATA_DTX_C_IRX_N0
+3VS SATA0RXN SATA_DTX_C_IRX_N0 <36>
HDA_BIT_CLK N34 AM1 SATA_DTX_C_IRX_P0
HDA_BCLK SATA0RXP SATA_DTX_C_IRX_P0 <36>
SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2 1 C184 SATA_ITX_DRX_N0 SSD

SATA 6G
AP7 SATA_ITX_DRX_N0 <36>
R105 1 @ HDA_SPKR HDA_SYNC SATA0TXN SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2 SATA_ITX_DRX_P0
2 1K_0402_5% L34 HDA_SYNC SATA0TXP AP5 1 C185 SATA_ITX_DRX_P0 <36>

HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10 SATA_DTX_C_IRX_N1

<41> HDA_SPKR SPKR SATA1RXN SATA_DTX_C_IRX_N1 <40>
LOW= Disable (Default) SATA_DTX_C_IRX_P1
* HDA_RST# K34 HDA_RST#
SATA1RXP
SATA1TXN
AM8
AP11 SATA_ITX_C_DRX_N1 0.01U_0402_16V7K 2 1 C273 SATA_ITX_DRX_N1
SATA_DTX_C_IRX_P1 <40>
SATA_ITX_DRX_N1 <40> HDD
AP10 SATA_ITX_C_DRX_P1 0.01U_0402_16V7K 2 1 C272 SATA_ITX_DRX_P1
SATA1TXP SATA_ITX_DRX_P1 <40>
C +3V_PCH HDA_SDIN0 E34 AD7 SATA_DTX_C_IRX_N2 C
<41> HDA_SDIN0 HDA_SDIN0 SATA2RXN SATA_DTX_C_IRX_N2 <40>
AD5 SATA_DTX_C_IRX_P2 SATA_DTX_C_IRX_P2 <40>
HDA_SDOUT SATA2RXP SATA_ITX_C_DRX_N2 0.01U_0402_16V7K 2 SATA_ITX_DRX_N2_CONN
R106 2 @ 1 1K_0402_5% G34
HDA_SDIN1 SATA2TXN
AH5 1 C186 SATA_ITX_DRX_N2_CONN <40> ODD
AH4 SATA_ITX_C_DRX_P2 0.01U_0402_16V7K 2 1 C187 SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_P2_CONN <40>
SATA2TXP
Low = Disabled (Default)
* C34 HDA_SDIN2

IHDA
High = Enabled [Flash Descriptor Security Overide] AB8
SATA3RXN
A34 HDA_SDIN3 SATA3RXP AB10
AF3
R109 SATA3TXN
SATA3TXP AF1
ME_FLASH 1 2 HDA_SDOUT A36
+3V_PCH <42> ME_FLASH HDA_SDO
0_0402_5%

SATA
SATA4RXN Y7
Y5
SATA4RXP
SPI ROM FOR ME
R108 2 1 1K_0402_5% HDA_SYNC R107 1 @ 2 1K_0402_1% PCH_GPIO33 C36 AD3
HDA_DOCK_EN# / GPIO33 SATA4TXN
AD1
R317 2 PCH_GPIO13 SATA4TXP
This signal has a weak internal pull-down 1 10K_0402_5% N32
& Non-share ROM.
+3V_PCH HDA_DOCK_RST# / GPIO13
Y3
SATA5RXN
@ Y1
On Die PLL VR Select is supplied by SATA5RXP
AB3
SATA5TXN
2MB P/N : SA00003FO10
1.5V when smapled high PCH_JTAG_TCK
* 1.8V when sampled low
2 1 J3
JTAG_TCK SATA5TXP
AB1

51_0402_5% PCH_JTAG_TMS H7 Y11 R111 +3VS

Needs to be pulled High for Chief River platfrom JTAG_TMS SATAICOMPO 37.4_0402_1% +1.05VS_VCC_SATA

JTAG
R110
11/08 Follow DG change to +5VS PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI
R112 PCH_JTAG_TDO H1 R292 1 2 SPI_WP#_1
33_0402_5% +5VS JTAG_TDO R113 +1.05VS_SATA3 3.3K_0402_5%
AB12
HDA_BIT_CLK SATA3RCOMPO 49.9_0402_1%
<41> HDA_BITCLK_AUDIO 1 2
2

+3VS
G

R114 Q10 AB13 SATA3_COMP 1 2 R246 1 2 SPI_HOLD#_1

33_0402_5% BSS138_NL_SOT23-3 SATA3COMPI 3.3K_0402_5%
1 2 HDA_SYNC_R 3 1 HDA_SYNC C275
<41> HDA_SYNC_AUDIO
R116 SPI_CLK_PCH RBIAS_SATA3 R115 1 2 750_0402_1%
S

T3 AH1 1 2
SPI_CLK SATA3RBIAS
1

1M_0402_5%

33_0402_5% R303
B HDA_RST# SPI_SB_CS0# 0_0402_5% U9 0.1U_0402_16V4Z B
<41> HDA_RST_AUDIO# 1 2 Y14 SPI_CS0#
R118 SPI_SB_CS1# 1 2 SPI_SB_CS1#_R 1 8 R299
CS# VCC
R1353

33_0402_5% SPI_SB_CS1# T1 SPI_SO_R 1 2 SPI_SO_L1 2 7 SPI_HOLD#_1 33_0402_5%

SPI_CS1# DO(IO1) HOLD#(IO3)
SPI

1 2 HDA_SDOUT P3 SATALED# 2 R120 1 SPI_WP#_1 3 6 SPI_CLK_PCH_1 1 2 SPI_CLK_PCH

<41> HDA_SDOUT_AUDIO +3VS
2

SATALED# 33_0402_5% WP#(IO2) CLK SPI_SI_R1

10K_0402_5% 4 5 1 2 SPI_SI
SPI_SI PCH_GPIO21 R119 1 R294 GND DI(IO0)
V4 V14 2 +3VS
SPI_MOSI SATA0GP / GPIO21 10K_0402_5% W25Q16BVSSIG_SO8 33_0402_5%
SPI_SO_R U3 P1 BBS_BIT0_R 2 1 R199
+3V_PCH +3V_PCH +3V_PCH SPI_MISO SATA1GP / GPIO19 SATA_DET# <36>
R1418 @ 0_0402_5%

PANTHER-POINT_FCBGA989 R316 2 1 10K_0402_5% +3VS

1

4MB P/N : SA00003K800

R121 R122 R123
200_0402_5% 200_0402_5% 200_0402_5% SPI_CLK_PCH
@ @ @ +3VS
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

1
1

R127 1 2 SPI_WP# R124

R125 R126 R128 3.3K_0402_5% 33_0402_5%
100_0402_1% 100_0402_1% 100_0402_1% @
R129 1 2 SPI_HOLD# +3VS

2
@ @ @ 3.3K_0402_5%
2

C191
1 2 C190
R130 22P_0402_50V8J
0_0402_5% U5 0.1U_0402_16V4Z @
SPI_SB_CS0# 1 2SPI_SB_CS0#_R 1 8 R298
SPI_SO_R CS# VCC
1 2 SPI_SO_L 2 7 SPI_HOLD# 33_0402_5%
SPI_WP# DO HOLD# SPI_CLK_PCH_0 1
3 6 2 SPI_CLK_PCH
33_0402_5% WP# CLK SPI_SI_R
4 5 1 2 SPI_SI
R131 GND DI
A W25Q32BVSSIG_SO8 33_0402_5% A
R133

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/8) SATA,HDA,SPI, LPC, XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 14 of 64
5 4 3 2 1
 5 4 3 2 1

U4B
Q60A
DMN66D0LDW-7 2N_SOT363-6
PCIE_PRX_DTX_N1 BG34 10K_0402_5% 6 1 SMB_CLK_S3
<37> PCIE_PRX_DTX_N1 PERN1 SMB_CLK_S3 <12,13,36>
LAN <37> PCIE_PRX_DTX_P1 PCIE_PRX_DTX_P1 BJ34 E12 PCH_GPIO11 2 1 +3V_PCH
C192 PCIE_PTX_DRX_N1 PERP1 SMBALERT# / GPIO11
2 0.1U_0402_10V7K 2.2K_0402_5% 2.2K_0402_5%
<37> PCIE_PTX_C_DRX_N1
<37> PCIE_PTX_C_DRX_P1
C193
1
1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1
AV32
AU32
PETN1
H14 PCH_SMBCLK R134 1 R136 2 1 2 R137 DIMM1

2
PETP1 SMBCLK

<36> PCIE_PRX_DTX_N2
PCIE_PRX_DTX_N2 BE34 PERN2 SMBDATA C9 PCH_SMBDATA
+3V_PCH
1 2 1
+3VS
2 DIMM2

5
PCIE_PRX_DTX_P2 R135 R138
WLAN
<36> PCIE_PRX_DTX_P2
<36> PCIE_PTX_C_DRX_N2
C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2
BF34
BB32
PERP2
PETN2
2.2K_0402_5% 2.2K_0402_5% MINI CARD
C195 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 AY32 3 4 SMB_DATA_S3
<36> PCIE_PTX_C_DRX_P2 PETP2 SMB_DATA_S3 <12,13,36>

SMBUS
A12 DRAMRST_CNTRL_PCH
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7>
BG36 DMN66D0LDW-7 2N_SOT363-6
PERN3
BJ36 PERP3 SML0CLK C8 1 2 Q60B
D R335 2.2K_0402_5% D
AV34 PETN3 2 R329 1 +3V_PCH
AU34 PETP3 SML0DATA G12 1 2 +3V_PCH 1K_0402_5% Q61A
R336 2.2K_0402_5%
PCIE_PRX_DTX_N4 BF36 2 1 DMN66D0LDW-7 2N_SOT363-6
<46> PCIE_PRX_DTX_N4 PERN4 +3V_PCH
PCIE_PRX_DTX_P4 BE36 R140 10K_0402_5% 6 1 EC_SMB_CK2
<46> PCIE_PRX_DTX_P4 PERP4 EC_SMB_CK2 <23,39,42>
Card Reader C277 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 AY34 C13 PCH_HOT#
<46> PCIE_PTX_C_DRX_N4 PCIE_PTX_DRX_P4 PETN4 SML1ALERT# / PCHHOT# / GPIO74 PCH_HOT# <42>
C276 1 2 0.1U_0402_10V7K BB34 2.2K_0402_5%
<46> PCIE_PTX_C_DRX_P4 PETP4
E14 SML1CLK 1 R141 2 VGA

2
SML1CLK / GPIO58

PCI-E*
BG37
BH37
PERN5
PERP5 SML1DATA / GPIO75
M16 SML1DATA
+3V_PCH
1 2
+3VS EC

5
R142
AY36
BB36
PETN5
PETP5
2.2K_0402_5% thermal sensor
3 4 EC_SMB_DA2
EC_SMB_DA2 <23,39,42>
BJ38
PERN6 DMN66D0LDW-7 2N_SOT363-6
BG38
PERP6

Controller
AU36 M7 Q61B
PETN6 CL_CLK1
AV36 PETP6

Link
BG40 PERN7 CL_DATA1 T11
BJ40 +3V_PCH
PERP7
AY40
PETN7
BB40 P10
PETP7 CL_RST1#

2
BE38 R143
PERN8
BC38 10K_0402_5%
PERP8
AW38 PETN8
AY38 R144

1
PETP8 0_0402_5%
PEG_A_CLKRQ# / GPIO47 M10 PEG_CLKREQ#_R 1 2 CLK_REQ_VGA# <23>
R153 1 2 0_0402_5% CLK_PCIE_LAN#_R Y40
<37> CLK_PCIE_LAN# CLK_PCIE_LAN_R CLKOUT_PCIE0N
LAN <37> CLK_PCIE_LAN
R154 1 2 0_0402_5% Y39
CLKOUT_PCIE0P
AB37 CLK_PCIE_VGA#_R R146 1 2 0_0402_5% CLK_PCIE_VGA#
C CLKREQ_LAN#_R CLKOUT_PEG_A_N CLK_PCIE_VGA_R CLK_PCIE_VGA CLK_PCIE_VGA# <23> C
R151 2 0_0402_5% R148 1 2 0_0402_5%

CLOCKS
<37> CLKREQ_LAN# 1 J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 CLK_PCIE_VGA <23>
+3V_PCH R152 2 1 10K_0402_5%

R149 1 2 0_0402_5% CLK_PCIE_WLAN1#_R AB49 AV22 CLK_CPU_DMI# CLK_CPU_DMI# R349 1 @ 2 10K_0402_5%

<36> CLK_PCIE_WLAN1# CLK_PCIE_WLAN1_R CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI CLK_CPU_DMI# <6> CLK_CPU_DMI
R150 1 2 0_0402_5% AB47 AU22 R347 1 2 10K_0402_5%
<36> CLK_PCIE_WLAN1 CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI <6>
WLAN @
<36> WLAN_CLKREQ1# R156 1 2 0_0402_5% WLAN_CLKREQ1#_R M1
R158 PCIECLKRQ1# / GPIO18
+3VS 2 1 10K_0402_5% AM12
CLKOUT_DP_N
CLKOUT_DP_P AM13
AA48
CLKOUT_PCIE2N
AA47 CLKOUT_PCIE2P
BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5%
R301 PCH_GPIO20 CLKIN_DMI_N CLK_BUF_CPU_DMI
+3VS 2 1 10K_0402_5% V10 PCIECLKRQ2# / GPIO20 CLKIN_DMI_P BE18 R157 1 2 10K_0402_5%

<46> CLK_PCIE_CARD_PCH#
R312 1 2 0_0402_5% CLK_PCIE_CARD_PCH#_R Y37 BJ30 CLKIN_DMI2# R159 1 2 10K_0402_5%
CLKOUT_PCIE3N CLKIN_GND1_N
<46> CLK_PCIE_CARD_PCH
R311 1 2 0_0402_5% CLK_PCIE_CARD_PCH_R Y36 BG30 CLKIN_DMI2 R160 1 2 10K_0402_5%
CLKOUT_PCIE3P CLKIN_GND1_P
Card Reader
R342 1 @ 2 0_0402_5% CPPE#_R A8
<46> CPPE# PCIECLKRQ3# / GPIO25 CLK_BUF_DREF_96M#
G24 R162 1 2 10K_0402_5%
R168 CLKIN_DOT_96N CLK_BUF_DREF_96M
+3V_PCH 2 1 10K_0402_5% E24 R163 1 2 10K_0402_5%
CLKIN_DOT_96P
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P CLK_BUF_PCIE_SATA# R164 1 10K_0402_5%
AK7 2
R165 PCH_GPIO26 CLKIN_SATA_N CLK_BUF_PCIE_SATA R166 1
+3V_PCH 2 1 10K_0402_5% L12 AK5 2 10K_0402_5%
PCIECLKRQ4# / GPIO26 CLKIN_SATA_P

V45 K45 CLK_BUF_ICH_14M R167 1 2 10K_0402_5%

CLKOUT_PCIE5N REFCLK14IN
V46
CLKOUT_PCIE5P
R147 2 1 10K_0402_5% PCH_GPIO44 L14 H45 CLK_PCI_LPBACK
+3V_PCH PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK <18>
B XTAL25_IN B
AB42 V47 XTAL25_IN
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT XTAL25_OUT
AB40 V49 1 2
CLKOUT_PEG_B_P XTAL25_OUT R169 1M_0402_5%
R170 2 1 10K_0402_5% PCH_GPIO56 E6 R171 +1.05VS_VCCDIFFCLKN Y2
+3V_PCH PEG_B_CLKRQ# / GPIO56 90.9_0402_1% 4 3
XCLK_RCOMP NC OSC
Y47 1 2
XCLK_RCOMP
V40 1 1 2 1
CLKOUT_PCIE6N OSC NC
V42
CLKOUT_PCIE6P C196 C197
R172 2 1 10K_0402_5% PCH_GPIO45 T13 27P_0402_50V8J 25MHZ_12PF_X3G025000DC1H~D 27P_0402_50V8J
+3V_PCH PCIECLKRQ6# / GPIO45 2 2
V38 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 K43
FLEX CLOCKS

V37
CLKOUT_PCIE7P
CLKOUTFLEX1 / GPIO65 F47
R174 2 1 10K_0402_5% PCH_GPIO46 K12
+3V_PCH PCIECLKRQ7# / GPIO46
H47 LAN_48M 1 2
CLKOUTFLEX2 / GPIO66 PCH_LAN_48M <37>
AK14 R182 @ 22_0402_5%
CLKOUT_ITPXDP_N PCH_GPIO67
AK13 K49 PCH_GPIO67 <19>
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 @ R175 @ C198
33_0402_5% 22P_0402_50V8J
PANTHER-POINT_FCBGA989 CLK_BUF_ICH_14M
BIOS Request SKU ID 2 1 1 2

Reserve for EMI please close to PCH

@ R176 @ C199
33_0402_5% 22P_0402_50V8J
CLK_PCI_LPBACK 2 1 1 2
A A

Reserve for EMI please close to PCH

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/8) PCIE, SMBUS, CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 15 of 64
5 4 3 2 1
 5 4 3 2 1

D D

U4C

DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N1 <5>
DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2
<5> DMI_CTX_PRX_N2 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N2 <5>
<5> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 BG20 BH13 FDI_CTX_PRX_N3 FDI_CTX_PRX_N3 <5>
DMI3RXN FDI_RXN3 FDI_CTX_PRX_N4
FDI_RXN4 BC12 FDI_CTX_PRX_N4 <5>
DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5
<5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N5 <5>
DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6
<5> DMI_CTX_PRX_P1 DMI1RXP FDI_RXN6 FDI_CTX_PRX_N6 <5>
DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7
<5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7 FDI_CTX_PRX_N7 <5>
DMI_CTX_PRX_P3 BJ20
<5> DMI_CTX_PRX_P3 DMI3RXP
BG14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 <5>
DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1
<5> DMI_CRX_PTX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 <5>
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2
<5> DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 FDI_CTX_PRX_P2 <5>
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 <5>
<5> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4
<5> DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 <5>
DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_CTX_PRX_P5
FDI_RXP5 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6
<5> DMI_CRX_PTX_P0 DMI0TXP FDI_RXP6 FDI_CTX_PRX_P6 <5>
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7
<5> DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
MC74VHC1G08DFT2G SC70 5P DMI_CRX_PTX_P2 AY18
<5> DMI_CRX_PTX_P2 DMI2TXP
3

DMI_CRX_PTX_P3 AU18
<5> DMI_CRX_PTX_P3 DMI3TXP
VGATE 1 AW16 FDI_INT
G

A FDI_INT FDI_INT <5>

4 SYS_PWROK <6>
PCH_PWROK Y +1.05VS_VCC_EXP FDI_FSYNC0
2 BJ24 AV12 FDI_FSYNC0 <5>
B DMI_ZCOMP FDI_FSYNC0
P

+RTCVCC
U6 1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
FDI_FSYNC1 <5>
5

DMI_IRCOMP FDI_FSYNC1
1

R177 49.9_0402_1%

1
R180 1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0
C DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
100K_0402_1% R178 750_0402_1% R179
+3VS @ 4mil width and place BB10 FDI_LSYNC1 330K_0402_5%
FDI_LSYNC1 FDI_LSYNC1 <5>
within 500mil of the PCH
2

：：

2
DSWODVREN - On Die DSW VR Enable
DSWVRMEN
A18 DSWODVREN * H Enable
L Disable
R1457 0_0402_5% 0_0402_5%

System Power Management

1
2 1 SUSACK#_R C12 E22 PCH_DPWROK_R 1 2 PCH_RSMRST#_R
<42> SUSACK# SUSACK# DPWROK
DS3@ R185 R181 R183
0_0402_5% 330K_0402_5%
For Deep S3 +3VS 2 1 SYS_RST# K3 B9 WAKE# 1 2 PCIE_WAKE# <19,36,37> @
R184 10K_0402_5% SYS_RESET# WAKE#
1 2 10K_0402_5% +3V_PCH

2
R186
R188 1 @ 2 0_0402_5% SYS_PWROK P12 N3 PM_CLKRUN# PAD T73
<57> VGATE SYS_PWROK CLKRUN# / GPIO32
1 2 +3VS
R189 @ 8.2K_0402_5%
R190 1 2 0_0402_5% PWROK L22 G8 SUS_STAT# 1 2
<42> PCH_PWROK PWROK SUS_STAT# / GPIO61 R253 10K_0402_5%
2 1
R302 1 2 0_0402_5% R191 0_0402_5% APWROK L10 N14 SUSCLK
<42> PCH_APWROK APWROK SUSCLK / GPIO62 SUSCLK <42>
AEPWROK can be connect to @
PWROK if iAMT disable PM_DRAM_PWRGD B13 D10 PM_SLP_S5#
<6> PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# <42>

1 PCH_RSMRST#_R
2 C21 H4 PM_SLP_S4#
<42> EC_RSMRST# RSMRST# SLP_S4# PM_SLP_S4# <42>
R193 0_0402_5%
R1455 0_0402_5%
2 1 SUSWARN#_R K16 F4 PM_SLP_S3#
+3V_PCH <42> SUSWARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# <42>
DS3@ Can be left NC
B
12/23 change to 300Ohm for S5 power saving For Deep S3 when IAMT is not
B
<42> PBTN_OUT# 1 2 PBTN_OUT#_R E20 G10 support on the
R198 0_0402_5% PWRBTN# SLP_A#
R192 PM_DRAM_PWRGD platfrom
2 1 300_0402_5% R1447 0_0402_5%
<42,51> ACIN
D29 1 2 RB751V_SOD323 AC_PRESENT_R H20 ACPRESENT / GPIO31 SLP_SUS# G16 PM_SLP_SUS#_R2 1 PM_SLP_SUS# <42>
R194 2 1 10K_0402_5% SUSWARN# DS3@
For Deep S3
1 R200 2 PCH_GPIO72 E10 AP14 H_PM_SYNC
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC <6>
8.2K_0402_5%
R201
R197 2 1 10K_0402_5% PCH_RSMRST#_R +3V_PCH 2 1 RI# A10 K14 PCH_GPIO29 PAD T74 Can be left NC if no use
10K_0402_5% RI# SLP_LAN# / GPIO29
integrated LAN.
PANTHER-POINT_FCBGA989
10/06 Test point request +5VALW

1
For Deep S3 100K_0402_5%
+3V_DSW R1120
DS3@

2
PM_SLP_SUS
AC_PRESENT_R <48> PM_SLP_SUS
R195 2 1 200K_0402_5%

1
D
PM_SLP_SUS# 2 Q118
R257 2 1 10K_0402_5% SUSWARN# G 2N7002_SOT23

1
S

3
@ DS3@
11/08 Resreve for Deep S3 @ 100K_0402_5%
R1121

2
+3VS
A A

@
R1290 2 1 200_0402_5% PM_DRAM_PWRGD 09/05 add for Deep S3
7/28 Modify follow Module Design.
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/8) DMI,FDI,PM,
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 16 of 64
5 4 3 2 1
 5 4 3 2 1

D D

U4D

PCH_ENBKL J47 AP43

<33> PCH_ENBKL PCH_ENVDD L_BKLTEN SDVO_TVCLKINN +3VS
<33> PCH_ENVDD M45 L_VDD_EN SDVO_TVCLKINP AP45

<33> PCH_PWM P45 L_BKLTCTL SDVO_STALLN AM42

AM40
SDVO_STALLP

1
EDID_CLK T40
<33> EDID_CLK L_DDC_CLK
Pull up R for CONN SIDE <33> EDID_DATA
EDID_DATA K47
L_DDC_DATA SDVO_INTN
AP39 R202 R203
AP40 2.2K_0402_5% 2.2K_0402_5%
R204 1 CTRL_CLK SDVO_INTP
+3VS 2 2.2K_0402_5% T45 HDMI@ HDMI@
R205 1 CTRL_DATA L_CTRL_CLK
2 2.2K_0402_5% P39

2
2.37K_0402_1% L_CTRL_DATA
R206 2 1 LVDS_IBG AF37 P38 HDMICLK
LVD_IBG SDVO_CTRLCLK HDMICLK <35>
AF36 M39 HDMIDAT
LVD_VBG SDVO_CTRLDATA HDMIDAT <35>
LVD_VREF AE48 LVD_VREFH
AE47 AT49
LVD_VREFL DDPB_AUXN
DDPB_AUXP AT47
AT40 TMDS_B_HPD <35>
DDPB_HPD
<33> LVDS_ACLK# AK39
LVDSA_CLK#

LVDS
<33> LVDS_ACLK AK40 LVDSA_CLK DDPB_0N AV42 TMDS_B_DATA2#_PCH HDMI@ C200 1 2 0.1U_0402_10V6K
HDMI_TX2-_CK <35>
DDPB_0P AV40 TMDS_B_DATA2_PCH HDMI@ C201 1 2 0.1U_0402_10V6K
HDMI_TX2+_CK <35>
<33> LVDS_A0# AN48 AV45 TMDS_B_DATA1#_PCH HDMI@ C202 1 2 0.1U_0402_10V6K
HDMI_TX1-_CK <35>
LVDSA_DATA#0 DDPB_1N
<33> LVDS_A1# AM47 AV46 TMDS_B_DATA1_PCH HDMI@ C203 1 2 0.1U_0402_10V6K
HDMI_TX1+_CK <35>
LVDSA_DATA#1 DDPB_1P

Digital Display Interface

C C
<33> LVDS_A2# AK47 LVDSA_DATA#2 DDPB_2N AU48 TMDS_B_DATA0#_PCH HDMI@ C204 1 2 0.1U_0402_10V6K
HDMI_TX0-_CK <35> HDMI
AJ48 AU47 TMDS_B_DATA0_PCH HDMI@ C205 1 2 0.1U_0402_10V6K
HDMI_TX0+_CK <35>
LVDSA_DATA#3 DDPB_2P
AV47 TMDS_B_CLK#_PCH HDMI@ C206 1 2 0.1U_0402_10V6K
HDMI_CLK-_CK <35>
DDPB_3N
<33> LVDS_A0 AN47 LVDSA_DATA0 DDPB_3P AV49 TMDS_B_CLK_PCH HDMI@ C207 1 2 0.1U_0402_10V6K
HDMI_CLK+_CK <35>
<33> LVDS_A1 AM49 LVDSA_DATA1
<33> LVDS_A2 AK49
LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
DDPC_CTRLDATA
P42 Colse connector
AF40
LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
AP49
DDPC_AUXP
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47
LVDSB_DATA#1
AF49 AY47
LVDSB_DATA#2 DDPC_0N
AF45 AY49
LVDSB_DATA#3 DDPC_0P
AY43
DDPC_1N
AH43 AY45
DAC_BLU LVDSB_DATA0 DDPC_1P
<34> DAC_BLU AH49 BA47
R208 2 LVDSB_DATA1 DDPC_2N
1 150_0402_1% AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 BB47
DAC_GRN LVDSB_DATA3 DDPC_3N
<34> DAC_GRN BB49
R209 2 DDPC_3P
1 150_0402_1%
DAC_RED N48 M43
<34> DAC_RED CRT_BLUE DDPD_CTRLCLK
R210 2 1 150_0402_1% P49 M36
CRT_GREEN DDPD_CTRLDATA
T49 CRT_RED
AT45
DDPD_AUXN

CRT
CRT_DDC_CLK T39 AT43
Pull up R for CONN SIDE <34> CRT_DDC_CLK CRT_DDC_DATA CRT_DDC_CLK DDPD_AUXP
<34> CRT_DDC_DATA M40 BH41
CRT_DDC_DATA DDPD_HPD
B B
DDPD_0N BB43
<34> CRT_HSYNC M47 CRT_HSYNC DDPD_0P BB45
<34> CRT_VSYNC M49 BF44
CRT_VSYNC DDPD_1N
DDPD_1P BE44
BF42
CRT_IREF DDPD_2N
T43 BE42
DAC_IREF DDPD_2P
T42 BJ42
CRT_IRTN DDPD_3N
BG42
DDPD_3P
1

R211 PANTHER-POINT_FCBGA989
1K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 17 of 64
5 4 3 2 1
 5 4 3 2 1

+3VS
RP2
8 1 PCI_PIRQA#
7 2 PCI_PIRQD# U4E
6 3 PCI_PIRQC# AY7
PCI_PIRQB# RSVD1
5 4 RSVD2 AV7
BG26 TP1 RSVD3 AU3
8.2K_0804_8P4R_5% BJ26 BG4
TP2 RSVD4
BH25
RP1 TP3
BJ16 TP4 RSVD5 AT10
8 1 PCH_GPIO2 BG16 BC8
DGPU_PWR_EN_R TP5 RSVD6
7 2 AH38 TP6
6 3 PCH_GPIO4 AH37 AU2
ODD_DA#_R TP7 RSVD7
5 4 AK43 TP8 RSVD8 AT4
D D
AK45 TP9 RSVD9 AT3
8.2K_0804_8P4R_5% C18 AT1
TP10 RSVD10
@
PPT EDS DOC#474146 N30 TP11 RSVD11 AY3
H3 AT5
R305 PCH_GPIO51 TP12 RSVD12
1 2 8.2K_0402_5% AH12 AV3
@ TP13 RSVD13
R297 1 2 8.2K_0402_5% DGPU_GC6_EN USB30 AM4
AM5
TP14
TP15
RSVD14
RSVD15
AV1
BB1
Y13 TP16 RSVD16 BA3
R213 1 2 8.2K_0402_5% PCH_GPIO5 PORT1 RIGHT USB (SUB/B) K24 BB5
TP17 RSVD17
L24 BB3
R225 PCH_WL_OFF# TP18 RSVD18
1 2 8.2K_0402_5% AB46 TP19 RSVD19 BB7
PORT2 AB45
TP20 RSVD20
BE8

RSVD
R212 1 2 8.2K_0402_5% DGPU_PWR_EN1 BD4
RSVD21
BF6
DGPU_HOLD_RST#_R RSVD22
R252 1 2 8.2K_0402_5% PORT3 LEFT USB
B21 AV5
@ TP21 RSVD23
M20 TP22 RSVD24 AV10
R306 1 2 8.2K_0402_5% DGPU_GC6_EN PORT4 LEFT USB AY16
TP23
BG46 TP24 RSVD25 AT8
R214 1 2 8.2K_0402_5% DGPU_HOLD_RST#_R
AY5
@ RSVD26
BA2
USB30_RX_N1 RSVD27
<46> USB30_RX_N1 BE28 USB3Rn1
BC30 USB3Rn2 RSVD28 AT12
USB30_RX_N3 BE32 BF3
<45> USB30_RX_N3 USB3Rn3 RSVD29
USB30_RX_N4 BJ32
PCH_WL_OFF# <45> USB30_RX_N4 USB30_RX_P1 USB3Rn4
R215 1 @ 2 1K_0402_5% BC28
<46> USB30_RX_P1 USB3Rp1
USB30_RX_P3
BE30
USB3Rp2 USB DEBUG=PORT1 AND PORT9
<45> USB30_RX_P3 BF32 USB3Rp3
USB30_RX_P4 BG32 C24 USB20_N0
<45> USB30_RX_P4 USB30_TX_N1 USB3Rp4 USBP0N USB20_P0 USB20_N0 <46>
A16 swap overide Strap/Top-Block <46> USB30_TX_N1 AV26
USB3Tn1 USBP0P
A24 USB20_P0 <46> RIGHT USB (SUB/B)
C
Swap Override jumper BB26
USB3Tn2 USBP1N
C25
C
USB30_TX_N3 AU28 B25
<45> USB30_TX_N3 USB30_TX_N4 USB3Tn3 USBP1P USB20_N2
Low=A16 swap <45> USB30_TX_N4 AY30
USB3Tn4 USBP2N
C26 USB20_N2 <45>
override/Top-Block USB30_TX_P1 AU26 A26 USB20_P2 LEFT USB
<46> USB30_TX_P1 USB3Tp1 USBP2P USB20_P2 <45>
PCI_GNT3# Swap Override enabled AY26 K28 USB20_N3
USB30_TX_P3 USB3Tp2 USBP3N USB20_P3 USB20_N3 <45>
High=Default * <45> USB30_TX_P3 AV28 USB3Tp3 USBP3P H28 USB20_P3 <45> LEFT USB
USB30_TX_P4 AW30 E28
<45> USB30_TX_P4 USB3Tp4 USBP4N
USBP4P D28
C28 USB20_N5
USBP5N USB20_P5 USB20_N5 <33>
USBP5P A28 USB20_P5 <33> USB Camera
C29
USBP6N
USBP6P B29
PCI_PIRQA# K40 N28 Some PCH config not support USB port 6 & 7.
DGPU_PWR_EN_R PIRQA# USBP7N
1 2 NVDD_PWR_EN PCI_PIRQB# K38 PIRQB# USBP7P M28

PCI
R319 0_0402_5% PCI_PIRQC# H38 L30
@ PCI_PIRQD# PIRQC# USBP8N
G38 K30
0_0402_5% PIRQD# USBP8P USB20_N9
G30 USB20_N9 <46>
R314 DGPU_HOLD_RST#_R C46 USBP9N USB20_P9 +3V_PCH
7/9 Reserve <23> DGPU_HOLD_RST# 1 2
REQ1# / GPIO50 USBP9P
E30 USB20_P9 <46> RIGHT USB (Cable)

USB
1 2 DGPU_PWR_EN1 C44 C30 USB20_N10
<56> NVDD_PWR_EN REQ2# / GPIO52 USBP10N USB20_N10 <36>
R318 0_0402_5% DGPU_PWR_EN_R E40 A30 USB20_P10 WLAN RP3
REQ3# / GPIO54 USBP10P USB20_P10 <36> USB_OC5#
R315 1 2 L32 4 5
<23,48> DGPU_PWR_EN PCH_GPIO51 USBP11N USB_OC2#
0_0402_5% D47 K32 3 6
DGPU_GC6_EN GNT1# / GPIO51 USBP11P USB_OC7#
<27> DGPU_GC6_EN E42 G32 2 7
PCH_WL_OFF# GNT2# / GPIO53 USBP12N USB_OC0#
<36> PCH_WL_OFF# F46 E32 1 8
GNT3# / GPIO55 USBP12P USB20_N13
C32 USB20_N13 <44>
USBP13N USB20_P13 10K_1206_8P4R_5%
GPIO53=This Signal has a weak internal pull-up. PCH_GPIO2 USBP13P
A32 USB20_P13 <44> Bluetooth
G42
NOTE: The internal pull-up is disabled after ODD_DA# ODD_DA#_R PIRQE# / GPIO2
<40,42> ODD_DA# 1 2
PCH_GPIO4
G40 PIRQF# / GPIO3 USBRBIAS
Within 500 mils
PLTRST# deasserts. 0_0402_5% R715 C42 C33 1 2
PCH_GPIO5 PIRQG# / GPIO4 USBRBIAS# R218 22.6_0402_1% RP4
@ D44
PIRQH# / GPIO5 USB_OC6# 4 5
B33 USB_OC1# 3 6
USBRBIAS USB_OC4#
<42> PCI_PME# K10 2 7
B PME# USB_OC3# B
1 8
PCH_PLTRST# C6 A14 USB_OC0#
<6> PCH_PLTRST# PLTRST# OC0# / GPIO59 USB_OC1# USB_OC0# <46>
K20 10K_1206_8P4R_5%
OC1# / GPIO40 USB_OC2# USB_OC1# <45>
OC2# / GPIO41 B17
22_0402_5% 1 2 R219 CLK_PCI_LPBACK_R H49 C16 USB_OC3#
<15> CLK_PCI_LPBACK CLK_PCI_EC_R CLKOUT_PCI0 OC3# / GPIO42 USB_OC4#
22_0402_5% 1 2 R220 H43 L16
<42> CLK_PCI_EC CLKOUT_PCI1 OC4# / GPIO43 USB_OC4# <46>
22_0402_5% 2 1 R173 CLK_PCI_DB_R J48 A16 USB_OC5#
<36> CLK_PCI_DB CLKOUT_PCI2 OC5# / GPIO9 USB_OC6#
@ K42 D14
CLKOUT_PCI3 OC6# / GPIO10 USB_OC7#
H40 C14
PCH_GPIO51 R221 @ CLKOUT_PCI4 OC7# / GPIO14
1 2 1K_0402_5%

PANTHER-POINT_FCBGA989

Boot BIOS Strap bit1 BBS1

Boot BIOS 1 2
R222 0_0402_5%
Bit11 Bit10 Destination
0 1 Reserved
GNT1#/
GPIO51 1 0 Reserved MC74VHC1G08DFT2G SC70 5P

3
@
1 1 SPI (Default) PCH_PLTRST#
* 1

G
A
<23,36,37,42,46> PLT_RST# 4
Y
0 0 LPC B 2

P
1
1 U7

5
@
C208 R223
1U_0402_6.3V6K 100K_0402_5%
A 2 +3VS A

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 18 of 64
5 4 3 2 1
 5 4 3 2 1

MB ID +3VS
Function PCH_GPIO38 PCH_GPIO67 PCH_GPIO70 PCH_GPIO69

R711 R708 R704 R703

SG 0 0 X X

2
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
Reserve 0 1 X X
@ @ @ @
DIS 1 0 X X

1
PCH_GPIO38

PCH_GPIO67
UMA 1 1 X X <15> PCH_GPIO67
D PCH_GPIO69 D

14" X X 0 0 PCH_GPIO70

14"L X X 0 1
R712 R709 R706 R705

2
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
GC6_EVENT#
<23> GC6_EVENT# 15" X X 1 0
R233 2 10K_0402_5%
R280 1 2 10K_0402_5%
+3VS 1 Reserve X X 1 1
+3V_PCH

1
@ U4F
R235 1 2 1K_0402_5% EC_SMI#
T7 C40 PCH_GPIO68
BMBUSY# / GPIO0 TACH4 / GPIO68
R227 1 2 10K_0402_5% PCH_GPIO1 A42 B41 PCH_GPIO69
TACH1 / GPIO1 TACH5 / GPIO69

+3VS R228 1 2 10K_0402_5% PCH_GPIO6 H36 TACH2 / GPIO6 TACH6 / GPIO70 C41 PCH_GPIO70 9/18 Reseve for SKU ID +3VS
EC_SCI# E38 A40
<42> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71

2
GPIO28
On-Die PLL Voltage Regulator EC_SMI# C10 R236
<42> EC_SMI# GPIO8
This signal has a weak internal pull up
：
10K_0402_5%
R229 1 @ 2 10K_0402_5% PCH_GPIO12 C4

：On-Die
+3V_PCH LAN_PHY_PWR_CTRL / GPIO12
H voltage regulator enable
*

1
L On-Die PLL Voltage Regulator disable R230 1 2 10K_0402_5% EC_LID_OUT# G2 P4
GPIO15 A20GATE GATEA20 <42>
<42> EC_LID_OUT#
R240 1 @ 2 1K_0402_5% PCH_GPIO28 PECI AU16 PCH_PECI_R 1 @ 2 H_PECI <6,42>
R231 1 2 10K_0402_5% PCH_GPIO16 U2 0_0402_5% R237
+3VS SATA4GP / GPIO16
R232 1 2 10K_0402_1% P5 KBRST#
RCIN# KBRST# <42>
@
C C

GPIO
1 2 DGPU_PWROK_R D40 AY11
<27,53,56> DGPU_PWROK TACH0 / GPIO17 PROCPWRGD H_CPUPWRGD <6>
0_0402_5% R339

CPU/MISC
R238 1 2 10K_0402_5% BT_DISABLE T5 AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
+3VS SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# <6>
R239 390_0402_5%
<36> BT_DISABLE ODD_EN
* PCH_GPIO27 (Have internal Pull-High) <40> ODD_EN E8 GPIO24 INIT3_3V# T14
AOAC@
High: VCCVRM VR Enable 0_0402_5% 2 1 R224 AOAC_WAKE# E16 AY1 NV_CLE
PCH_THRMTRIP#_R <23>
<16,36,37> PCIE_WAKE# GPIO27 DF_TVS
Low: VCCVRM VR Disable
R241 1 2 10K_0402_5% PCH_GPIO28 P8
+3V_PCH GPIO28
<36,44> PCH_BT_ON# TS_VSS1
AH8 INIT3_3V
1 2 10K_0402_5% PCH_BT_ON# K1 +3VS
+3VS STP_PCI# / GPIO34
R242
TS_VSS2
AK11 This signal has weak internal
+3V_DSW R243 1 2 10K_0402_5% PCH_GPIO35 K4 PCH_GPIO68 R255 1 2 10K_0402_5%
GPIO35 PU, can't pull low
AH10
PCH_GPIO36 TS_VSS3 KBRST# R226
V8 1 2 10K_0402_5%
AOAC@ SATA2GP / GPIO36
AK10
R207 PCH_GPIO37 TS_VSS4
2 1 10K_0402_5% M5
SATA3GP / GPIO37
PCH_GPIO38 N2 P37
AOAC_WAKE# SLOAD / GPIO38 NC_1
R245 1 @ 2 10K_0402_5% Intel schematic reviwe recommand.
R247 1 2 10K_0402_5% PCH_GPIO39 M3
+3VS SDATAOUT0 / GPIO39
R248 1 2 10K_0402_5% PCH_GPIO48 V13 BG2
SDATAOUT1 / GPIO48 VSS_NCTF_15
R249 1 2 10K_0402_5% PCH_GPIO49 V3 BG48
+3VS SATA5GP / GPIO49 / TEMP_ALERT# VSS_NCTF_16
R251 1 2 10K_0402_5% PCH_GPIO57 D6 BH3
+3V_PCH GPIO57 VSS_NCTF_17
R250 1 2 200_0402_5% PCH_GPIO36 BH47
+3VS VSS_NCTF_18
R264 1 2 10K_0402_5% A4 BJ4
VSS_NCTF_1 VSS_NCTF_19
B H : Sandy Bridge B
@ A44 VSS_NCTF_2 VSS_NCTF_20 BJ44
PROC_SEL
A45
VSS_NCTF_3 VSS_NCTF_21
BJ45 L : INV Bridge

NCTF
A46 BJ46
VSS_NCTF_4 VSS_NCTF_22 +1.8VS
R244 1 @ 2 10K_0402_5% PCH_GPIO37 A5 BJ5
+3VS VSS_NCTF_5 VSS_NCTF_23
R259 1 2 10K_0402_5% A6 BJ6
VSS_NCTF_6 VSS_NCTF_24 R216
B3 VSS_NCTF_7 VSS_NCTF_25 C2 2.2K_0402_5%

B47 VSS_NCTF_8 VSS_NCTF_26 C48

NV_CLE 1 2 H_SNB_IVB# <6>
BD1 D1 R217 1K_0402_5%
VSS_NCTF_9 VSS_NCTF_27
BD49
VSS_NCTF_10 VSS_NCTF_28
D49 CLOSE TO THE BRANCHING POINT
BE1 E1
VSS_NCTF_11 VSS_NCTF_29
BE49 E49
VSS_NCTF_12 VSS_NCTF_30
BF1 F1
VSS_NCTF_13 VSS_NCTF_31
BF49 F49
VSS_NCTF_14 VSS_NCTF_32

PANTHER-POINT_FCBGA989

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 19 of 64
5 4 3 2 1
 5 4 3 2 1

+1.05VS U4G POWER +3VS PCH Power Rail Table

L1
@ J2 1700mA BLM18PG181SN1_0603~D Refer to CPU EDS R1.5
2 1 +1.05VS_VCCCORE AA23 U48 +VCCADAC 2 1
VCCCORE[1] 63mA VCCADAC
AC23 VCCCORE[2] 1 1 1 1 S0 Iccmax

1U_0402_6.3V6K
C210

1U_0402_6.3V6K
C211

1U_0402_6.3V6K
C212
1 1 1 1 AD21 C395 @ Voltage Rail Voltage Current (A)

CRT
VCCCORE[3]

10U_0603_6.3V6M
C209
PAD-OPEN 4x4m AD23 U47 C213 C214 C215 10U_0603_6.3V6M
VCCCORE[4] VSSADAC 0.01U_0402_16V7K 0.1U_0402_10V7K 10U_0603_6.3V6M
AF21

VCC CORE
VCCCORE[5] 2 2 2 2
AF23 VCCCORE[6]
V_PROC_IO 1.05 0.001
D 2 2 2 2 +3VS D
AG21 VCCCORE[7] 11/07 Change type to 0603
AG23 VCCCORE[8]
AG24 AK36 +VCCA_LVDS 2 R295 1 V5REF 5 0.001
VCCCORE[9] 1mA VCCALVDS 0_0603_5%
AG26
VCCCORE[10]
AG27 AK37
VCCCORE[11] VSSALVDS
AG29 VCCCORE[12]
V5REF_Sus 5 0.001
AJ23 +1.8VS
VCCCORE[13]

LVDS
AJ26 AM37 L2
VCCCORE[14] VCCTX_LVDS[1]
AJ27 VCCCORE[15]
0.1UH_MLF1608DR10KT_10%_1608 Vcc3_3 3.3 0.228
AJ29 AM38 +VCCTX_LVDS 2 1
VCCCORE[16] VCCTX_LVDS[2] 0.1uH inductor, 200mA
AJ31 VCCCORE[17] 1 1 1
+1.05VS
40mA VCCTX_LVDS[3]
AP36 VccADAC 3.3 0.063
C216 C217 C218
AP37 0.01U_0402_16V7K 0.01U_0402_16V7K 22U_0805_6.3V6M
+1.05VS_VCCDPLLEXP VCCTX_LVDS[4] 2 2 2
R254 2 1 0_0603_5% AN19
VCCIO[28]
VccADPLLA 1.05 0.08

PAD T47 @ +VCCAPLLEXP BJ22 +3VS VccADPLLB 1.05 0.08

VCCAPLLEXP
This pin can be left as no connect in V33 +3VS_VCC3_3_6 2 R256 1
VCC3_3[6]

HVCMOS
AN16 0_0603_5% VccCore 1.05 1.7
On-Die VR enabled mode (default). VCCIO[15]
1
AN17 VCCIO[16]
VCC3_3[7] V34 C219 VccDMI 1.05 0.047
0.1U_0402_10V7K
2
AN21 VCCIO[17]
VccIO 1.05 3.711
AN26
VCCIO[18]
AN27 3711mA AT16 +VCCAFDI_VRM VccASW 1.05 0.903
+1.05VS_VCC_EXP VCCIO[19] VCCVRM[3]
+1.05VS AP21 +VCCP_VCCDMI +1.05VS
C VCCIO[20] C
VccSPI 3.3 0.01
1 R296 2 +1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 2 R258 1
0_0805_5% VCCIO[21] VCCDMI[1] 0_0603_5%
1
+1.05VS
1U_0402_6.3V6K
C222

1U_0402_6.3V6K
C223

1U_0402_6.3V6K
C224

1U_0402_6.3V6K
C225

DMI
1 1 1 1 1 AP24 VCCIO[22]
VccDSW 3.3 0.001
10U_0603_6.3V6M
C221

VCCIO
C220
AP26 70mA AB36 +1.05VS_VCC_DMI_CCI 2 R300 1 1U_0402_6.3V6K
VCCIO[23] VCCCLKDMI 2
1 0_0603_5% VccDFTERM 1.8 0.002
2 2 2 2 2 AT24
VCCIO[24] C226
1U_0402_6.3V6K VccRTC 3.3 6 uA
AN33 2
VCCIO[25]
11/07 Change type to 0603
AN34 VCCIO[26] VCCDFTERM[1] AG16 VccSus3_3 3.3 0.095
+3VS

1 R260 2 +3VS_VCCA3GBG BH29 AG17 +VCCPNAND +1.8VS VccSusHDA 3.3 / 1.5 0.01
0_0603_5% VCC3_3[3] 190mA VCCDFTERM[2]

DFT / SPI
1
C227
0.1U_0402_10V7K
VCCDFTERM[3]
AJ16 2 R293 1 VccVRM 1.8 / 1.5 0.167
0_0603_5%
2 +VCCAFDI_VRM AP16
VCCVRM[2] 1
VCCDFTERM[4]
AJ17 C228 VccCLKDMI 1.05 0.07
0.1U_0402_10V7K
PAD T48 @ +1.05VS_VCCAPLL_FDI BG6
VccAFDIPLL 2 +3VS VccSSC 1.05 0.095
1 R263 2 +1.05VS_VCCDPLL_FDI AP17 R399
+1.05VS VCCIO[27]
0_0603_5% V1 +3V_VCCPSPI 2 1 VccDIFFCLKN 1.05 0.055
FDI

10mA VCCSPI 0_0603_5%

+VCCP_VCCDMI AU20 1
VCCDMI[2]
VccALVDS 3.3 0.001
C230
B PANTHER-POINT_FCBGA989 1U_0402_6.3V6K B
2 VccTX_LVDS 1.8 0.04

+VCCAFDI_VRM
+1.5VS

R265 2 1 0_0603_5% +VCCAFDI_VRM

Intel recommand VCCVRM==>1.5V FOR MOBILE

stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 20 of 64
5 4 3 2 1
 5 4 3 2 1

Have internal VRM

+3VS +1.05VS R268 @ VCC3_3 = 266mA detal waiting for newest spec
0_0603_5%
2 1 +VCCACLK VCCDMI = 42mA detal waiting for newest spec
L3
0_0805_5%
+3VS_VCC_CLKF33 +3V_DSW R269
1 2
1 1 0_0603_5% U4J POWER +1.05VS

10U_0603_6.3V6M
C231

1U_0402_6.3V6K
C232
L3 For Deep S3 2 1 +VCCPDSW
1 AD49 N26 +1.05VS_VCCUSBCORE 2 R270 1
VCCACLK VCCIO[29] 0_0603_5%
2 2 1
@ C234 P26
0.1U_0402_10V7K VCCIO[30] C233
T16 VCCDSW3_3 1mA
D 2 P28 1U_0402_6.3V6K D
VCCIO[31] 2
10UH_LBR2012T100M_20%
2 1 +PCH_VCCDSW V12 T27
DCPSUSBYP VCCIO[32]
11/07 Change type to 0603
C235 @ T29
0.1U_0402_10V7K +3VS_VCC_CLKF33 VCCIO[33] +3V_PCH
T38 VCC3_3[5]

H ：On-Die PLL voltage regulator enable

On-Die PLL Voltage Regulator
T15 PAD +VCCAPLL_CPY_PCH BH23 VCCAPLLDMI2
228mA VCCSUS3_3[7]
T23 +3V_VCCPUSB 2 R272 1
0_0603_5%
+3V_PCH

0.1U_0402_10V7K
C236
T24 1
+VCCDPLL_CPY VCCSUS3_3[8] +5V_PCH +3V_PCH
VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 +1.05VS 2 R271 1 AL29 VCCIO[14]
0_0603_5% V23 +3V_VCCAUBG 2 R273 1
,VCCAPLLSATA VCCSUS3_3[9]

USB
1 0_0603_5%

2
+VCCSUS1 AL24 V24 2
DCPSUS[3] VCCSUS3_3[10]

1
1 C238 D1
P24 0.1U_0402_10V7K R275 CH751H-40PT_SOD323-2
@ C239 VCCSUS3_3[6] 2 +1.05VS 100_0402_5%
1U_0402_6.3V6K AA19

1
2 VCCASW[1] +1.05VS_VCCAUPLL +PCH_V5REF_SUS
T26 2 R276 1

2
+1.05VS VCCIO[34]
AA21
VCCASW[2]
903mA 0_0603_5% 1

1 R277 2 +1.05VM_VCCASW AA24 M26 +PCH_V5REF_SUS C240

0_0805_5% VCCASW[3] 1mA V5REF_SUS 0.1U_0402_25V6
1 1 2

22U_0805_6.3V6M
C241

22U_0805_6.3V6M
C242
AA26

Clock and Miscellaneous

VCCASW[4] +VCCA_USBSUS C243 @1
AN23 2 1U_0402_6.3V6K
DCPSUS[4]
AA27 VCCASW[5]
2 2 AN24 +3V_VCCPSUS
VCCSUS3_3[1]
AA29
VCCASW[6]
+1.05VS AA31 +5VS +3VS
VCCASW[7]
AC26 P34 +PCH_V5REF_RUN +3V_PCH
VCCASW[8] 1mA V5REF

2
C L5 10UH_LB2012T100MR_20% C
1 1 1

1U_0402_6.3V6K
C244

1U_0402_6.3V6K
C245

1U_0402_6.3V6K
C246
AC27 2 R278 1 R279 D2
+1.05VS_VCCA_A_DPL VCCASW[9] +3V_VCCPSUS 0_0603_5% 100_0402_5% CH751H-40PT_SOD323-2
1 2 N20 1
VCCSUS3_3[2]

PCI/GPIO/LPC
AC29 VCCASW[10]
1

2 2 2 N22 C247

1
R307 VCCSUS3_3[3] 1U_0402_6.3V +PCH_V5REF_RUN
AC31
VCCASW[11] 2 +3VS
0_0603_5% VCCSUS3_3[4] P20 1
AD29
+1.05VS_VCCA_B_DPL @ VCCASW[12]
1 2 P22 2 R281 1 C248
2

VCCSUS3_3[5] 0_0603_5% 1U_0603_10V6K

AD31 1
L6 10UH_LB2012T100MR_20% VCCASW[13] C249 2
W21 AA16 +3VS_VCCPCORE 0.1U_0402_10V7K
VCCASW[14] VCC3_3[1]
2 +3VS
22U_0805_6.3V6M
C229

220U_B2_2.5VM_R35
C250

1U_0402_6.3V6K
C251

22U_0805_6.3V6M
C237

220U_B2_2.5VM_R35
C252

1U_0402_6.3V6K
C253

@ 1 @ 1 W23 W16
VCCASW[15] VCC3_3[8]
1 1 1 1
+ + W24 T34 +3VS_VCCPPCI 2 R282 1
VCCASW[16] VCC3_3[4] 0_0603_5%
1
W26
2 2 2 2 2 2 VCCASW[17] C254
W29 +3VS 0.1U_0402_10V7K
VCCASW[18] 2
W31 AJ2 +VCC3_3_2 2 R283 1
VCCASW[19] VCC3_3[2] 0_0603_5% +1.05VS_SATA3 +1.05VS
1
W33
VCCASW[20]
AF13 2 R285 1
VCCIO[5] C255 0_0603_5%
2 0.1U_0402_10V7K 1
+VCCRTCEXT N16 DCPRTC C257
1 AH13
C258 VCCIO[12] 1U_0402_6.3V6K
0.1U_0402_10V7K +VCCAFDI_VRM Y49 AH14 +1.05VS_SATA3 2
VCCVRM[4] VCCIO[13]
2
B B
VCCIO[6] AF14
2 R274 1 +1.05VS_VCCA_A_DPL BD47

：On-Die PLL voltage regulator enable

+1.05VS VCCADPLLA 80mA

SATA
0_0603_5% AK1 +VCCSATAPLL PAD T16 On-Die PLL Voltage Regulator
+1.05VS_VCCA_B_DPL VCCAPLLSATA
1 BF47 H
C256 VCCADPLLB 80mA +VCCAFDI_VRM
1U_0402_6.3V6K AF11 +VCCAFDI_VRM VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2
+1.05VS_VCCDIFFCLKN +VCCDIFFCLK VCCVRM[1] +1.05VS_VCC_SATA +1.05VS
AF17
2 AF33
VCCIO[7] ,VCCAPLLSATA
VCCDIFFCLKN[1] +1.05VS_VCC_SATA
AF34 55mA
VCCDIFFCLKN[2] VCCIO[2]
AC16 2 R288 1
+1.05VS 2 R304 1 +1.05VS_VCCDIFFCLKN AG34 0_0603_5%
0_0603_5% VCCDIFFCLKN[3]
1 VCCIO[3] AC17 1
C261
C259 +1.05VS_SSCVCC AG33 AD17 1U_0402_6.3V6K
1U_0402_6.3V6K VCCSSC 95mA VCCIO[4]
2 2
+VCCSST V16 +1.05VS
DCPSST
1
+1.05VS 2 R284 1 C263
0_0603_5% 1 0.1U_0402_10V7K +1.05VM_VCCSUS T17 T21
DCPSUS[1] VCCASW[22]
V19
C262 2 DCPSUS[2]
MISC

1U_0402_6.3V6K +1.05VS V21

2 VCCASW[23]
CPU

@ R290 2 R286 1 +V_CPU_IO BJ8

0_0603_5% 0_0603_5% V_PROC_IO 1mA
T19
+1.05VM_VCCSUS VCCASW[21]
+1.05VS 2 1 1 1 1
+RTCVCC +3V_PCH
4.7U_0603_6.3V6K
C265

0.1U_0402_10V7K
C266

0.1U_0402_10V7K
C267

1
A22 P32 +VCCSUSHDA 2 R287 1
RTC

2 2 2 VCCRTC 10mA VCCSUSHDA

HDA

C264 @ @ 0_0603_5%
1U_0402_6.3V6K
C268

0.1U_0402_10V7K
C269

0.1U_0402_10V7K
C270

1U_0402_6.3V6K 1 1 1 1
2 PANTHER-POINT_FCBGA989 C271
A 0.1U_0402_16V4Z A
@
2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/07/21 2012/12/31 Title
Issued Date Deciphered Date PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 21 of 64
5 4 3 2 1
 5 4 3 2 1

U4I

AY4 VSS[159] VSS[259] H46

AY42 K18
VSS[160] VSS[260]
AY46 VSS[161] VSS[261] K26
AY8 K39
VSS[162] VSS[262]
B11 VSS[163] VSS[263] K46
D U4H D
B15 VSS[164] VSS[264] K7
H5 VSS[0] B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 AK38 B27 L20
VSS[1] VSS[80] VSS[167] VSS[267]
AA2 AK4 B31 L26
VSS[2] VSS[81] VSS[168] VSS[268]
AA3 VSS[3] VSS[82] AK42 B35 VSS[169] VSS[269] L28
AA33 AK46 B39 L36
VSS[4] VSS[83] VSS[170] VSS[270]
AA34 VSS[5] VSS[84] AK8 B7 VSS[171] VSS[271] L48
AB11 VSS[6] VSS[85] AL16 F45 VSS[172] VSS[272] M12
AB14 AL17 BB12 P16
VSS[7] VSS[86] VSS[173] VSS[273]
AB39 VSS[8] VSS[87] AL19 BB16 VSS[174] VSS[274] M18
AB4 AL2 BB20 M22
VSS[9] VSS[88] VSS[175] VSS[275]
AB43 VSS[10] VSS[89] AL21 BB22 VSS[176] VSS[276] M24
AB5 AL23 BB24 M30
VSS[11] VSS[90] VSS[177] VSS[277]
AB7 AL26 BB28 M32
VSS[12] VSS[91] VSS[178] VSS[278]
AC19 AL27 BB30 M34
VSS[13] VSS[92] VSS[179] VSS[279]
AC2 VSS[14] VSS[93] AL31 BB38 VSS[180] VSS[280] M38
AC21 AL33 BB4 M4
VSS[15] VSS[94] VSS[181] VSS[281]
AC24 VSS[16] VSS[95] AL34 BB46 VSS[182] VSS[282] M42
AC33 AL48 BC14 M46
VSS[17] VSS[96] VSS[183] VSS[283]
AC34 AM11 BC18 M8
VSS[18] VSS[97] VSS[184] VSS[284]
AC48 AM14 BC2 N18
VSS[19] VSS[98] VSS[185] VSS[285]
AD10 VSS[20] VSS[99] AM36 BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39 BC26 VSS[187] VSS[287] N47
AD12 AM43 BC32 P11
VSS[22] VSS[101] VSS[188] VSS[288]
AD13 VSS[23] VSS[102] AM45 BC34 VSS[189] VSS[289] P18
AD19 AM46 BC36 T33
VSS[24] VSS[103] VSS[190] VSS[290]
AD24 AM7 BC40 P40
VSS[25] VSS[104] VSS[191] VSS[291]
AD26 VSS[26] VSS[105] AN2 BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29 BC48 VSS[193] VSS[293] P47
AD33 AN3 BD46 P7
VSS[28] VSS[107] VSS[194] VSS[294]
AD34 AN31 BD5 R2
C VSS[29] VSS[108] VSS[195] VSS[295] C
AD36 VSS[30] VSS[109] AP12 BE22 VSS[196] VSS[296] R48
AD37 AP19 BE26 T12
VSS[31] VSS[110] VSS[197] VSS[297]
AD38 AP28 BE40 T31
VSS[32] VSS[111] VSS[198] VSS[298]
AD39 VSS[33] VSS[112] AP30 BF10 VSS[199] VSS[299] T37
AD4 VSS[34] VSS[113] AP32 BF12 VSS[200] VSS[300] T4
AD40 AP38 BF16 W34
VSS[35] VSS[114] VSS[201] VSS[301]
AD42 VSS[36] VSS[115] AP4 BF20 VSS[202] VSS[302] T46
AD43 AP42 BF22 T47
VSS[37] VSS[116] VSS[203] VSS[303]
AD45 VSS[38] VSS[117] AP46 BF24 VSS[204] VSS[304] T8
AD46 AP8 BF26 V11
VSS[39] VSS[118] VSS[205] VSS[305]
AD8 VSS[40] VSS[119] AR2 BF28 VSS[206] VSS[306] V17
AE2 AR48 BD3 V26
VSS[41] VSS[120] VSS[207] VSS[307]
AE3 VSS[42] VSS[121] AT11 BF30 VSS[208] VSS[308] V27
AF10 AT13 BF38 V29
VSS[43] VSS[122] VSS[209] VSS[309]
AF12 AT18 BF40 V31
VSS[44] VSS[123] VSS[210] VSS[310]
AD14 AT22 BF8 V36
VSS[45] VSS[124] VSS[211] VSS[311]
AD16 AT26 BG17 V39
VSS[46] VSS[125] VSS[212] VSS[312]
AF16 AT28 BG21 V43
VSS[47] VSS[126] VSS[213] VSS[313]
AF19 AT30 BG33 V7
VSS[48] VSS[127] VSS[214] VSS[314]
AF24 VSS[49] VSS[128] AT32 BG44 VSS[215] VSS[315] W17
AF26 AT34 BG8 W19
VSS[50] VSS[129] VSS[216] VSS[316]
AF27 AT39 BH11 W2
VSS[51] VSS[130] VSS[217] VSS[317]
AF29 AT42 BH15 W27
VSS[52] VSS[131] VSS[218] VSS[318]
AF31 AT46 BH17 W48
VSS[53] VSS[132] VSS[219] VSS[319]
AF38 AT7 BH19 Y12
VSS[54] VSS[133] VSS[220] VSS[320]
AF4 AU24 H10 Y38
VSS[55] VSS[134] VSS[221] VSS[321]
AF42 VSS[56] VSS[135] AU30 BH27 VSS[222] VSS[322] Y4
AF46 AV16 BH31 Y42
VSS[57] VSS[136] VSS[223] VSS[323]
AF5 AV20 BH33 Y46
VSS[58] VSS[137] VSS[224] VSS[324]
AF7 AV24 BH35 Y8
VSS[59] VSS[138] VSS[225] VSS[325]
AF8 AV30 BH39 BG29
VSS[60] VSS[139] VSS[226] VSS[328]
AG19 AV38 BH43 N24
B VSS[61] VSS[140] VSS[227] VSS[329] B
AG2 VSS[62] VSS[141] AV4 BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43 D3 VSS[229] VSS[331] AD47
AG48 AV8 D12 B43
VSS[64] VSS[143] VSS[230] VSS[333]
AH11 VSS[65] VSS[144] AW14 D16 VSS[231] VSS[334] BE10
AH3 AW18 D18 BG41
VSS[66] VSS[145] VSS[232] VSS[335]
AH36 AW2 D22 G14
VSS[67] VSS[146] VSS[233] VSS[337]
AH39 AW22 D24 H16
VSS[68] VSS[147] VSS[234] VSS[338]
AH40 AW26 D26 T36
VSS[69] VSS[148] VSS[235] VSS[340]
AH42 AW28 D30 BG22
VSS[70] VSS[149] VSS[236] VSS[342]
AH46 VSS[71] VSS[150] AW32 D32 VSS[237] VSS[343] BG24
AH7 VSS[72] VSS[151] AW34 D34 VSS[238] VSS[344] C22
AJ19 AW36 D38 AP13
VSS[73] VSS[152] VSS[239] VSS[345]
AJ21 VSS[74] VSS[153] AW40 D42 VSS[240] VSS[346] M14
AJ24 AW48 D8 AP3
VSS[75] VSS[154] VSS[241] VSS[347]
AJ33 VSS[76] VSS[155] AV11 E18 VSS[242] VSS[348] AP1
AJ34 AY12 E26 BE16
VSS[77] VSS[156] VSS[243] VSS[349]
AK12 AY22 G18 BC16
VSS[78] VSS[157] VSS[244] VSS[350]
AK3 AY28 G20 BG28
VSS[79] VSS[158] VSS[245] VSS[351]
G26 BJ28
PANTHER-POINT_FCBGA989 VSS[246] VSS[352]
G28
VSS[247]
G36
VSS[248]
G48 VSS[249]
H12
VSS[250]
H18 VSS[251]
H22
VSS[252]
H24
VSS[253]
H26 VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
A A

PANTHER-POINT_FCBGA989

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 22 of 64
5 4 3 2 1
 5 4 3 2 1

12/23 Change to +VDD33MISC for GTGE shutdown issue

UV1A
PCIE_CTX_GRX_N[0..15] +VDD33MISC
<5> PCIE_CTX_GRX_N[0..15] PCIE_CTX_GRX_P0 +VDD33MISC
AN12 Part 1 of 7
PCIE_CTX_GRX_P[0..15] PCIE_CTX_GRX_N0 PEX_RX0 GPU_VID4
<5> PCIE_CTX_GRX_P[0..15] AM12 P6 GPU_VID4 <56>
PCIE_CTX_GRX_P1 PEX_RX0_N GPIO0 GPU_VID3
AN14 M3 GPU_VID3 <56>
PEX_RX1 GPIO1

10K_0402_5%
PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N1 AM14 L6 PCH_THRMTRIP#_R
<5> PCIE_CRX_GTX_N[0..15] PEX_RX1_N GPIO2 PCH_THRMTRIP#_R <19>

1
PCIE_CTX_GRX_P2 AP14 P5
PEX_RX2 GPIO3

RV65
PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_N2 AP15 P7 RV208
<5> PCIE_CRX_GTX_P[0..15] PEX_RX2_N GPIO4

3
PCIE_CTX_GRX_P3 AN15 L7 GPU_VID1 10K_0402_5%
PCIE_CTX_GRX_N3 PEX_RX3 GPIO5 GPU_VID2 GPU_VID1 <56>
AM15 M7 @ OPT@ QV7B
PCIE_CTX_GRX_P4 PEX_RX3_N GPIO6 GPU_VID2 <56>
AN17 N8 DMN66D0LDW-7 2N_SOT363-6

2
PCIE_CTX_GRX_N4 PEX_RX4 GPIO7 OVERT#
AM17 M1 1 2 GC6_EVENT# <19> 5 OPT@
PCIE_CTX_GRX_P5 PEX_RX4_N GPIO8 GC6_EVENT#_R RV153 GC6@ 0_0402_5%
Under GPU(below 150mils) AP17
PEX_RX5 GPIO9
M2

6
D PCIE_CTX_GRX_N5 D
150mA AP18 L1

4
PCIE_CTX_GRX_P6 PEX_RX5_N GPIO10 GPU_VID0 MEM_VREF <28,29,30,31>
LV1 BLM18PG181SN1D_2P AN18 M5 QV7A

GPIO
+SP_PLLVDD PCIE_CTX_GRX_N6 PEX_RX6 GPIO11 GPU_VID0 <56> VGA_AC_DET_R
+1.05VS_VGA 1 2 AM18 N3 DMN66D0LDW-7 2N_SOT363-6
PEX_RX6_N GPIO12

10K_0402_5%
22U_0805_6.3V6M

4.7U_0402_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K
PCIE_CTX_GRX_P7 AN20 M4 GPU_VID5 OVERT# 2
PEX_RX7 GPIO13 GPU_VID5 <56> OPT@

1
OPT@ CV112

OPT@ CV113

CV4

CV5
180ohms (ESR=0.2) Bead 1 1 1 1 PCIE_CTX_GRX_N7 AM20 N4
PEX_RX7_N GPIO14

RV223
PCIE_CTX_GRX_P8 AP20 P2

1
PEX_RX8 GPIO15

OPT@
PCIE_CTX_GRX_N8 AP21 R8
PEX_RX8_N GPIO16 DPRSLPVR_VGA <56>

OPT@

OPT@
PCIE_CTX_GRX_P9 AN21 M6
2 2 2 2 PCIE_CTX_GRX_N9 PEX_RX9 GPIO17
AM21 R1

2
PCIE_CTX_GRX_P10 PEX_RX9_N GPIO18
AN23 P3
PCIE_CTX_GRX_N10 PEX_RX10 GPIO19
AM23 P4
PCIE_CTX_GRX_P11 PEX_RX10_N GPIO20
AP23 P1
PCIE_CTX_GRX_N11 PEX_RX11 GPIO21
AP24
PCIE_CTX_GRX_P12 PEX_RX11_N
AN24
PCIE_CTX_GRX_N12 PEX_RX12
AM24
+VDD33MISC PCIE_CTX_GRX_P13 PEX_RX12_N
PCIE_CTX_GRX_N13
AN26
PEX_RX13 Vendor recommand reserve PU/PD resistor +VDD33MISC
AM26
+VDD33MISC PCIE_CTX_GRX_P14 PEX_RX13_N
AP26
PCIE_CTX_GRX_N14 PEX_RX14
AP27
PEX_RX14_N
2

GL@ PCIE_CTX_GRX_P15 AN27 AK9 VGA_EDID_CLK 1 2

GL@ RV24 RV25 PCIE_CTX_GRX_N15 PEX_RX15 DACA_RED RV3 OPT@ 2.2K_0402_5%
AM27 AL10
2.2K_0402_5% 2.2K_0402_5% PEX_RX15_N DACA_GREEN VGA_EDID_DATA
DIS@ DACA_BLUE
AL9 For N13P-GT/N13E-GE 1 2
RV4 OPT@ 2.2K_0402_5%

DACs
5

GL@ PCIE_CRX_GTX_P0 CV6 OPT@1

OPT@ 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P0 AK14 VGA_CRT_DATA 1 2
1

QV1B PCIE_CRX_GTX_N0 CV7 OPT@

OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N0 PEX_TX0 RV10 OPT@ 2.2K_0402_5%
2 AJ14 AM9
VGA_SMB_CK2 PCIE_CRX_GTX_P1 PCIE_CRX_C_GTX_P1 PEX_TX0_N DACA_HSYNC VGA_CRT_CLK
4 3 EC_SMB_CK2 <15,39,42>
CV8 OPT@
OPT@1 2 0.22U_0402_10V6K AH14
PEX_TX1 DACA_VSYNC
AN9 12/23 Reserve for GTGE leakage issue 1 2
PCIE_CRX_GTX_N1 CV9 OPT@
OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N1 AG14 RV11 OPT@ 2.2K_0402_5%
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_P2 CV10 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_P2 PEX_TX1_N I2CB_SCL
2 AK15 1 2
PCIE_CRX_GTX_N2 CV11 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N2 PEX_TX2 +DACA_VDD 1 OPT@ 2 +3VS +VDD33MISC RV12 OPT@ 2.2K_0402_5%
1 2 2 AJ15 AG10
PEX_TX2_N DACA_VDD

PCI EXPRESS
RV126 0_0402_5% PCIE_CRX_GTX_P3 CV12 OPT@
OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P3 AL16 AP9 RV51 10K_0402_5% I2CB_SDA 1 2
GTGE@ PCIE_CRX_GTX_N3 CV13 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N3 PEX_TX3 DACA_VREF RV13 OPT@ 2.2K_0402_5%
2 AK16 AP8
PEX_TX3_N DACA_RSET

2
PCIE_CRX_GTX_P4 CV15 OPT@
OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P4 AK17
PEX_TX4
2

C GL@ PCIE_CRX_GTX_N4 CV17 OPT@

OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_N4 AJ17 RV14 RV2 OVERT# 1 2 C
QV1A PCIE_CRX_GTX_P5 CV19 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_P5 PEX_TX4_N RV1 OPT@ 10K_0402_5%
2 AH17 10K_0402_5% 10K_0402_5%
VGA_SMB_DA2 PCIE_CRX_GTX_N5 CV14 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N5 PEX_TX5
1 6 EC_SMB_DA2 <15,39,42> 2 AG17 @ OPT@
PCIE_CRX_GTX_P6 CV16 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_P6 PEX_TX5_N GC6_EVENT#_R
2 AK18 1 2

1
2N7002DW-T/R7_SOT363-6 PCIE_CRX_GTX_N6 CV18 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N6 PEX_TX6 RV49 10K_0402_5%
2 AJ18
PCIE_CRX_GTX_P7 PCIE_CRX_C_GTX_P7 PEX_TX6_N VGA_AC_DET_R
1 2 CV20 OPT@
OPT@1 2 0.22U_0402_10V6K AL19 2 1VGA_AC_DET VGA_AC_DET <42,56>
NOGC6@
RV137 0_0402_5% PCIE_CRX_GTX_N7 CV22 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N7 PEX_TX7 VGA_CRT_CLK RB751V_SOD323 DV3
2 AK19 R4
GTGE@ PCIE_CRX_GTX_P8 CV24 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_P8 PEX_TX7_N I2CA_SCL VGA_CRT_DATA
2 AK20 R5 OPT@
PCIE_CRX_GTX_N8 PCIE_CRX_C_GTX_N8 PEX_TX8 I2CA_SDA
PU AT EC SIDE, +3VS AND 4.7K CV26 OPT@
OPT@1 2 0.22U_0402_10V6K AJ20
PEX_TX8_N
PCIE_CRX_GTX_P9 CV21 OPT@
OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P9 AH20 R7 I2CB_SCL 1 2
PCIE_CRX_GTX_N9 CV23 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N9 PEX_TX9 I2CB_SCL I2CB_SDA RV111 0_0402_5%
2 AG20 R6
PCIE_CRX_GTX_P10 CV25 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_P10 PEX_TX9_N I2CB_SDA @

I2C
2 AK21
+3VS_VGA +3VS_VGA PCIE_CRX_GTX_N10 CV27 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N10 PEX_TX10 VGA_EDID_CLK
2 AJ21 R2
PCIE_CRX_GTX_P11 CV29 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_P11 PEX_TX10_N I2CC_SCL VGA_EDID_DATA
2 AL22 R3
PCIE_CRX_GTX_N11 CV31 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N11 PEX_TX11 I2CC_SDA
2 AK22
PCIE_CRX_GTX_P12 CV33 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_P12 PEX_TX11_N VGA_SMB_CK2
2 AK23 T4
PCIE_CRX_GTX_N12 CV28 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N12 PEX_TX12 I2CS_SCL VGA_SMB_DA2
2 AJ23 T3
PEX_TX12_N I2CS_SDA
2

@ PCIE_CRX_GTX_P13 CV30 OPT@

OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P13 AH23
RV105 PCIE_CRX_GTX_N13 CV32 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N13 PEX_TX13
2 AG23
10K_0402_5% PCIE_CRX_GTX_P14 CV36 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_P14 PEX_TX13_N
2 AK24
PCIE_CRX_GTX_N14 CV41 OPT@
OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N14 PEX_TX14
2 AJ24
PEX_TX14_N
5

UV2 PCIE_CRX_GTX_P15 CV34 OPT@

OPT@1 2 0.22U_0402_10V6K PCIE_CRX_C_GTX_P15 AL25 60mA
1

PLT_RST# PCIE_CRX_GTX_N15 CV35 OPT@

OPT@1 0.22U_0402_10V6K PCIE_CRX_C_GTX_N15 PEX_TX15 +PLLVDD
2 2 AK25
P

<18,36,37,42,46> PLT_RST# B PEX_TX15_N

4 PLT_RST_VGA#
DGPU_HOLD_RST# Y
<18> DGPU_HOLD_RST# 1 AD8 1 2
A PLLVDD
G

AJ11 45mA RV112 @ 0_0402_5%

PEX_WAKE_N
1

OPT@ AE8
3

RV18 CLK_PCIE_VGA SP_PLLVDD

<15> CLK_PCIE_VGA
CLK_PCIE_VGA#
AL13
PEX_REFCLK 45mA +SP_PLLVDD
NC7SZ08P5X_NL_SC70-5 10K_0402_5% <15> CLK_PCIE_VGA# AK13 AD7
CLK_REQ_GPU# PEX_REFCLK_N VID_PLLVDD
AK12

CLK
OPT@ PEX_CLKREQ_N
2

@ PEX_TSTCLK_OUT XTALIN
B Differential signal 1
RV20
2
200_0402_1% PEX_TSTCLK_OUT#
AJ26
AK26
PEX_TSTCLK_OUT XTAL_IN
H3
H2 XTAL_OUT B
PEX_TSTCLK_OUT_N XTAL_OUT
PLT_RST_VGA# AJ12 J4 XTALOUT
PEX_RST_N XTAL_OUTBUFF XTALSSIN 1
AP29 H1 2
PEX_TERMP XTAL_SSIN

1
1 2 PEX_TERMP 10K_0402_5% OPT@ RV26
RV22 OPT@ 2.49K_0402_1% RV27
1 2 10K_0402_5%
RV23 10M_0402_5% OPT@
OPT@

2
N13P-PES-A1_FCBGA908 Internal Thermal Sensor
YV1
XTALIN1 2XTAL_OUT UV1 GT@
27MHZ_16PF_X5H027000FG1H
CV37 OPT@ CV38
22P_0402_50V8J 22P_0402_50V8J
OPT@ OPT@ UV1
N13E-GE
9/20 For Crystal EA request GE@
30 ohms @100MHz (ESR=0.05)
N13P-GL
GL@ +PLLVDD 1 2 +1.05VS_VGA

22U_0805_6.3V6M
0.1U_0402_10V7K
LV7 0_0402_5%

OPT@ CV131
1 1
+3VS_VGA

OPT@CV40
<18,48> DGPU_PWR_EN
2

2 2
2

RV29
10K_0402_5% RV30
A OPT@ 10K_0402_5% A
1 2
G

OPT@
QV2 OPT@
Under GPU Near GPU
1

<15> CLK_REQ_VGA# 1 3 CLK_REQ_GPU#

D

2N7002H 1N_SOT23-3
@ RV32
@RV32
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
@
1 2 N13P-PCIE/DAC/GPIO
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RV110 0_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 23 of 64

5 4 3 2 1
 5 4 3 2 1

UV1D

Part 4 of 7
AM6 IFPA_TXC
AN6 IFPA_TXC_N NC P8
AP3 IFPA_TXD0 NC AC6
AN3 IFPA_TXD0_N NC AJ28
AN5 IFPA_TXD1 NC AJ4
AM5 IFPA_TXD1_N NC AJ5
AL6 IFPA_TXD2 NC AL11
AK6 IFPA_TXD2_N NC C15

NC
AJ6 IFPA_TXD3 NC D19
D
AH6 IFPA_TXD3_N NC D20 D
NC D23
NC D26
AJ9 IFPB_TXC NC H31
AH9 IFPB_TXC_N NC T8
AP6 IFPB_TXD4 NC V32
AP5 IFPB_TXD4_N
AM7 IFPB_TXD5
AL7 IFPB_TXD5_N
AN8 IFPB_TXD6
AM8 IFPB_TXD6_N
AK8 IFPB_TXD7
AL8 IFPB_TXD7_N
L4 VCCSENSE_VGA VCCSENSE_VGA <56>
VDD_SENSE
AK1 IFPC_L0
AJ1 IFPC_L0_N
AJ3 L5 VSSSENSE_VGA VSSSENSE_VGA <56>
IFPC_L1 GND_SENSE
AJ2 IFPC_L1_N
AH3 IFPC_L2 trace width: 16mils
AH4
AG5
IFPC_L2_N differential voltage sensing.
IFPC_L3
AG4 IFPC_L3_N differential signal routing.
TEST
AM1 AK11 TESTMODE
IFPD_L0 TESTMODE
AM2 IFPD_L0_N
AM3 IFPD_L1 JTAG_TCK AM10 TV2

1
AM4 IFPD_L1_N JTAG_TDI AM11 TV3
AL3 IFPD_L2 JTAG_TDO AP12 TV4
C AL4 AP11 10K_0402_5% C
IFPD_L2_N JTAG_TMS TV5
AK4 AN11 1 2 RV33
IFPD_L3 JTAG_TRST_N RV34 10K_0402_5% OPT@
AK5

2
IFPD_L3_N

LVDS/TMDS
OPT@

AD2 IFPE_L0
AD3 IFPE_L0_N
AD1
AC1
IFPE_L1 SERIAL
IFPE_L1_N ROM_CS
AC2 IFPE_L2 ROM_CS_N H6
AC3 H4 ROM_SCLK ROM_SCLK <32>
IFPE_L2_N ROM_SCLK ROM_SI
AC4 IFPE_L3 ROM_SI H5 ROM_SI <32>
AC5 H7 ROM_SO ROM_SO <32>
IFPE_L3_N ROM_SO

AE3 IFPF_L0
AE4 IFPF_L0_N
AF4 IFPF_L1
AF5 IFPF_L1_N GENERAL
AD4 RV35 OPT@ 10K_0402_5%
IFPF_L2
AD5 IFPF_L2_N BUFRST_N L2 2 1
AG1 IFPF_L3
AF1 IFPF_L3_N CEC L3 1 2 +3VS_VGA
RV56 GL@ 10K_0402_5%
MULTI_STRAP_REF0_GND J1 1 2
RV38 OPT@ 40.2K_0402_1%
AG3 IFPC_AUX_I2CW _SCL
AG2 IFPC_AUX_I2CW _SDA_N
J2 STRAP0 STRAP0 <32>
STRAP0 STRAP1
B STRAP1 J7 STRAP1 <32> B
AK3 J6 STRAP2 STRAP2 <32>
IFPD_AUX_I2CX_SCL STRAP2 STRAP3
AK2 IFPD_AUX_I2CX_SDA_N STRAP3 J5 STRAP3 <32>
J3 STRAP4 STRAP4 <32>
STRAP4
AB3 IFPE_AUX_I2CY_SCL
AB4 IFPE_AUX_I2CY_SDA_N
THERMDP K3
THERMDN K4
AF3 IFPF_AUX_I2CZ_SCL
AF2 IFPF_AUX_I2CZ_SDA_N
Reserve 1MB SPI ROM FOR VBIOS ROM
+3VS_VGA
CV295
N13P-PES-A1_FCBGA908
2 1
20mils

1
0.1U_0402_16V4Z
@ RV229 @ @ RV225
10K_0402_5% 10K_0402_5%

2
@ RV224
@RV224 0_0402_5% UV15
ROM_CS 1 2 ROM_CS_R 1 8
ROM_SO ROM_SO_R CS# VCC ROM_HOLD#
1 2 2 DO HOLD# 7
@RV226
@ RV226 0_0402_5% 3 6
W P# CLK @ RV228 0_0402_5%
4 GND DIO 5
ROM_SCLK_R 1 2 ROM_SCLK
A MX25L1005AMC-12G SOP ROM_SI_R 1 2 ROM_SI A
@ @ RV227 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-LVDS/HDMI/DP/THM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 24 of 64
5 4 3 2 1
 5 4 3 2 1

UV1E
Near GPU
+1.5VS_VGA
For GDDR5 setting. Near GPU Part 5 of 7 2000mA +1.05VS_VGA
3.5A
AA27 FBVDDQ_0 PEX_IOVDD_0 AG19

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
OPT@ CV273

OPT@ CV274

OPT@ CV275

CV276

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AA30 AG21
FBVDDQ_1 PEX_IOVDD_1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
OPT@ CV263

OPT@ CV264

OPT@ CV265

OPT@ CV266

OPT@ CV267

OPT@ CV268

OPT@ CV269

OPT@ CV270

OPT@ CV271

OPT@ CV272

OPT@ CV43

OPT@ CV44

OPT@ CV45

OPT@ CV46

OPT@ CV47

OPT@ CV48

OPT@ CV49

OPT@ CV50

OPT@ CV51

OPT@ CV52
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 1 1 2 2 2 2 1 1 1 1 AB27 AG22 1 1 1 1 1 1 2 2 2 2
FBVDDQ_2 PEX_IOVDD_2
AB33 AG24
FBVDDQ_3 PEX_IOVDD_3
AC27 AH21
FBVDDQ_4 PEX_IOVDD_4

OPT@
AD27 AH25
2 2 2 2 2 2 1 1 1 1 2 2 2 2 FBVDDQ_5 PEX_IOVDD_5 2 2 2 2 2 2 1 1 1 1
AE27
FBVDDQ_6
AF27
FBVDDQ_7
AG27 FBVDDQ_8 PEX_IOVDDQ_0 AG13
B13
FBVDDQ_9 PEX_IOVDDQ_1
AG15 Under GPU(below 150mils) +1.05VS_VGA For N13P-GT/N13E-GE
D B16 FBVDDQ_10 PEX_IOVDDQ_2 AG16 D

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
+1.5VS_VGA
Under GPU(below 150mils) B19 FBVDDQ_11 PEX_IOVDDQ_3 AG18

OPT@ CV54

OPT@ CV53

OPT@ CV56

OPT@ CV55
E13 FBVDDQ_12 PEX_IOVDDQ_4 AG25 1 1 1 1
E16 FBVDDQ_13 PEX_IOVDDQ_5 AH15 <48,53> DGPU_PWR_EN#

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
E19 FBVDDQ_14 PEX_IOVDDQ_6 AH18
+3VS_VGA
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
OPT@ CV277

OPT@ CV281

OPT@ CV282

OPT@ CV278

OPT@ CV279

OPT@ CV280

OPT@ CV292

OPT@ CV287

OPT@ CV294

OPT@ CV284

OPT@ CV285

OPT@ CV286
1 1 1 1 1 1 1 1 1 1 1 1 H10 FBVDDQ_15 PEX_IOVDDQ_7 AH26

2
2 2 2 2

G
H11 AH27 AO3413_SOT23 QV8
FBVDDQ_16 PEX_IOVDDQ_8
H12 FBVDDQ_17 PEX_IOVDDQ_9 AJ27
H13 AK27 +VDD33MISC 3 1
2 2 2 2 2 2 2 2 2 2 2 2 FBVDDQ_18 PEX_IOVDDQ_10

0.1U_0402_10V7K

0.1U_0402_10V7K

D
H14 AL27

POWER
FBVDDQ_19 PEX_IOVDDQ_11

CV72

CV105
H15 AM28 1 1 GTGE@
FBVDDQ_20 PEX_IOVDDQ_12
H16 FBVDDQ_21 PEX_IOVDDQ_13 AN28
H18 For N13P-GT/N13E-GE GL@
FBVDDQ_22 +3VS_VGA
H19 FBVDDQ_23 1 2
GTGE@ GTGE@ 2 2 RV140 0_0402_5%
H20
FBVDDQ_24 +PEX_PLLHVDD GTGE@ +3VS
H21 AH12 1 2
FBVDDQ_25 PEX_PLL_HVDD

0.1U_0402_10V7K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
H22 RV138 0_0402_5%
FBVDDQ_26

OPT@ CV70

OPT@ CV74

OPT@ CV73
H23 1 1 1 1 2
FBVDDQ_27 RV154 @ 0_0402_5%
H24
FBVDDQ_28 +PEX_SVDD3V3
H8 AG12
FBVDDQ_29 PEX_SVDD_3V3
H9
FBVDDQ_30 2 2 2
L27
FBVDDQ_31
M27
FBVDDQ_32 +PEX_PLLVDD
N27 AG26
FBVDDQ_33 PEX_PLLVDD
P27 FBVDDQ_34 +VDD33MISC
R27 FBVDDQ_35 Under GPU(below 150mils)
T27
FBVDDQ_36
T30 J8
FBVDDQ_37 VDD33_0 +3VS_VGA
T33
FBVDDQ_38 VDD33_1
K8 Place near balls Place near GPU
V27 L8 0_0603_5%
FBVDDQ_39 VDD33_2 +VDD33
W27 M8 2 1
FBVDDQ_40 VDD33_3

0.1U_0402_10V7K

0.1U_0402_10V7K

4.7U_0603_6.3V6K
W30 FBVDDQ_41

1U_0402_6.3V6K
OPT@ CV109

OPT@ CV111

OPT@ CV293

OPT@ CV75
W33 1 1 1 1 RV5 OPT@
FBVDDQ_42 10K_0402_5% RV52
Y27 FBVDDQ_43
AH8 +IFPAB_PLLVDD 1 OPT@ 2
C IFPAB_PLLVDD C
AJ8 2 1
OPT@ 1 FB_VDDQ_SENSE IFPAB_RSET 1K_0402_1% RV40 2 2 2 2
<53> VDDQ_SENSE 2
RV141 0_0402_5% AG8 +IFPAB_IOVDD 1 OPT@ 2 @
IFPA_IOVDD 10K_0402_5% RV53
IFPB_IOVDD AG9
OPT@ 1 2 FB_VSS_SENSE F1
RV142 0_0402_5% FB_VDDQ_SENSE
AF7 +IFPC_PLLVDD 1 OPT@ 2
+1.5VS_VGA IFPC_PLLVDD 10K_0402_5% RV42 2
F2 AF8 1
FB_GND_SENSE IFPC_RSET 1K_0402_1% RV43
AF6 +IFPC_IOVDD 1 OPT@ 2 @
IFPC_IOVDD 10K_0402_5% RV44
1 2 J27
RV6 40.2_0402_1% FB_CAL_PD_VDDQ
CALIBRATION PIN GDDR5 OPT@ AG7 +IFPD_PLLVDD 1 OPT@ 2
IFPD_PLLVDD 10K_0402_5% RV45 2
1 2 H27 AN2 1
RV8 40.2_0402_1% FB_CAL_PU_GND IFPD_RSET 1K_0402_1% RV46
FB_CAL_x_PD_VDDQ 40.2Ohm OPT@ AG6 +IFPD_IOVDD 1 OPT@ 2 @
IFPD_IOVDD 10K_0402_5% RV47
1 2 H25
RV9 60.4_0402_1% FB_CAL_TERM_GND LV2
FB_CAL_x_PU_GND 40.2Ohm OPT@ AB8 +IFPEF_PLLVDD 1 OPT@ 2
IFPEF_PLVDD 10K_0402_5% RV55 2
AD6 1
IFPEF_RSET 1K_0402_1% RV50
FB_CAL_xTERM_GND 60.4Ohm AC7 +IFPE_IOVDD 1 OPT@ 2 @
IFPE_IOVDD 10K_0402_5% RV54 GTGE@
Place near balls IFPF_IOVDD
AC8
0_0603_5%
+1.05VS_VGA
120mA GL@ LV2
+PEX_PLLVDD 2 1

1U_0603_10V6K

4.7U_0805_25V6-K
0.1U_0402_10V7K
N13P-PES-A1_FCBGA908

OPT@ CV65

CV3

OPT@ CV66
1 1 1 BLM18PG121SN1D_0603
120ohms @100MHz (ESR=0.18)

OPT@
2 2 2
B B

Place near balls

A A

Security Classification
2011/07/21
Compal Secret Data
2012/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-POWER
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 25 of 64
5 4 3 2 1
 5 4 3 2 1

UV1F

Part 6 of 7
A2 D2
GND_0 GND_100
AA17 D31
GND_1 GND_101
AA18 D33
GND_2 GND_102
AA20 E10
GND_3 GND_103
AA22 E22
UV1G +VGA_CORE GND_4 GND_104
AB12 E25
+VGA_CORE GND_5 GND_105
AB14 E5
GND_6 GND_106
AB16 E7
Part 7 of 7 GND_7 GND_107
V17 AB19 F28
VDD_56 GND_8 GND_108
AA12 V18 AB2 F7
VDD_0 VDD_57 GND_9 GND_109
AA14 V20 AB21 G10
D VDD_1 VDD_58 GND_10 GND_110 D
AA16 V22 A33 G13
VDD_2 VDD_59 GND_11 GND_111
AA19 W12 AB23 G16
VDD_3 VDD_60 GND_12 GND_112
AA21 W14 AB28 G19
VDD_4 VDD_61 GND_13 GND_113
AA23 W16 AB30 G2
VDD_5 VDD_62 GND_14 GND_114
AB13 W19 AB32 G22
VDD_6 VDD_63 GND_15 GND_115
AB15 W21 AB5 G25
VDD_7 VDD_64 GND_16 GND_116
AB17 W23 AB7 G28
VDD_8 VDD_65 GND_17 GND_117
AB18 Y13 AC13 G3
VDD_9 VDD_66 GND_18 GND_118
AB20 Y15 AC15 G30
VDD_10 VDD_67 GND_19 GND_119
AB22 Y17 AC17 G32
VDD_11 VDD_68 GND_20 GND_120
AC12 Y18 AC18 G33
VDD_12 VDD_69 GND_21 GND_121
AC14 Y20 AA13 G5
VDD_13 VDD_70 GND_22 GND_122
AC16 Y22 AC20 G7
VDD_14 VDD_71 GND_23 GND_123
AC19 AC22 K2
VDD_15 GND_24 GND_124
AC21 AE2 K28
VDD_16 GND_25 GND_125
AC23 U1 AE28 K30
VDD_17 XVDD_1 GND_26 GND_126
M12 U2 AE30 K32
VDD_18 XVDD_2 GND_27 GND_127
M14 U3 AE32 K33
VDD_19 XVDD_3 GND_28 GND_128
POWER
M16 U4 AE33 K5
VDD_20 XVDD_4 GND_29 GND_129
M19 U5 AE5 K7
VDD_21 XVDD_5 GND_30 GND_130
M21 U6 AE7 M13
VDD_22 XVDD_6 GND_31 GND_131
M23 U7 AH10 M15
VDD_23 XVDD_7 GND_32 GND_132
N13 U8 AA15 M17
VDD_24 XVDD_8 GND_33 GND_133
N15 AH13 M18
VDD_25 GND_34 GND_134
N17 AH16 M20
VDD_26 GND_35 GND_135
N18 V1 AH19 M22
VDD_27 XVDD_9 GND_36 GND_136
N20 V2 AH2 N12
VDD_28 XVDD_10 GND_37 GND_137
N22 V3 AH22 N14
VDD_29 XVDD_11 GND_38 GND_138
P12 V4 AH24 N16
VDD_30 XVDD_12 GND_39 GND_139
C P14 V5 AH28 N19 C
VDD_31 XVDD_13 GND_40 GND_140
P16 V6 AH29 N2
VDD_32 XVDD_14 GND_41 GND_141
P19 V7 AH30 N21
VDD_33 XVDD_15 GND_42 GND_142

GND
P21 V8 AH32 N23
VDD_34 XVDD_16 GND_43 GND_143
P23 AH33 N28
VDD_35 GND_44 GND_144
R13 AH5 N30
VDD_36 GND_45 GND_145
R15 W2 AH7 N32
VDD_37 XVDD_17 GND_46 GND_146
R17 W3 AJ7 N33
VDD_38 XVDD_18 GND_47 GND_147
R18 W4 AK10 N5
VDD_39 XVDD_19 GND_48 GND_148
R20 W5 AK7 N7
VDD_40 XVDD_20 GND_49 GND_149
R22 W7 AL12 P13
VDD_41 XVDD_21 GND_50 GND_150
T12 W8 AL14 P15
VDD_42 XVDD_22 GND_51 GND_151
T14 AL15 P17
VDD_43 GND_52 GND_152
T16 AL17 P18
VDD_44 GND_53 GND_153
T19 Y1 AL18 P20
VDD_45 XVDD_23 GND_54 GND_154
T21 Y2 AL2 P22
VDD_46 XVDD_24 GND_55 GND_155
T23 Y3 AL20 R12
VDD_47 XVDD_25 GND_56 GND_156
U13 Y4 AL21 R14
VDD_48 XVDD_26 GND_57 GND_157
U15 Y5 AL23 R16
VDD_49 XVDD_27 GND_58 GND_158
U17 Y6 AL24 R19
VDD_50 XVDD_28 GND_59 GND_159
U18 Y7 AL26 R21
VDD_51 XVDD_29 GND_60 GND_160
U20 Y8 AL28 R23
VDD_52 XVDD_30 GND_61 GND_161
U22 AL30 T13
VDD_53 GND_62 GND_162
V13 AL32 T15
VDD_54 GND_63 GND_163
V15 AA1 AL33 T17
VDD_55 XVDD_31 GND_64 GND_164
AA2 AL5 T18
XVDD_32 GND_65 GND_165
AA3 AM13 T2
XVDD_33 GND_66 GND_166
AA4 AM16 T20
XVDD_34 GND_67 GND_167
AA5 AM19 T22
XVDD_35 GND_68 GND_168
AA6 AM22 AG11
B XVDD_36 GND_69 GND_169 B
AA7 AM25 T28
XVDD_37 GND_70 GND_170
AA8 AN1 T32
XVDD_38 GND_71 GND_171
AN10 T5
GND_72 GND_172
AN13 T7
GND_73 GND_173
AN16 U12
GND_74 GND_174
AN19 U14
N13P-PES-A1_FCBGA908 GND_75 GND_175
AN22 U16
GND_76 GND_176
AN25 U19
GND_77 GND_177
AN30 U21
GND_78 GND_178
AN34 U23
GND_79 GND_179
AN4 V12
GND_80 GND_180
AN7 V14
GND_81 GND_181
AP2 V16
GND_82 GND_182
AP33 V19
GND_83 GND_183
B1 V21
GND_84 GND_184
B10 V23
GND_85 GND_185
B22 W13
GND_86 GND_186
B25 W15
GND_87 GND_187
B28 W17
GND_88 GND_188
B31 W18
GND_89 GND_189
B34 W20
GND_90 GND_190
B4 W22
GND_91 GND_191
B7 W28
GND_92 GND_192
C10 Y12
GND_93 GND_193
C13 Y14
GND_94 GND_194
C19 Y16
GND_95 GND_195
C22 Y19
GND_96 GND_196
C25 Y21
GND_97 GND_197
C28 Y23
GND_98 GND_198
A C7 AH11 A
GND_99 GND_199
C16
GND_OPT
W32
GND_OPT

Security Classification Compal Secret Data N13P-PES-A1_FCBGA908 Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-VGA CORE, GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 26 of 64
5 4 3 2 1
 5 4 3 2 1

FBC_D[0..63]
FBA_D[0..63] <30,31> FBC_D[0..63]
<28,29> FBA_D[0..63]

30ohms (ESR=0.01) Bead

UV1B PU for X16 mode PU for X16 mode
P/N;SM010007W00 UV1C
Part 2 of 7
+1.05VS_VGA +FB_PLLAVDD FBA_D0 L28 U30 FBA_CS#_L Part 3 of 7
FBA_D1 FBA_D0 FBA_CMD0 FBA_MA3_BA3_L FBA_CS#_L <28> FBC_D0 FBC_CS#_L
200mA FBA_D2
M29
FBA_D1 FBA_CMD1
T31
FBA_MA2_BA0_L FBA_MA3_BA3_L <28> FBC_D1
G9
FBB_D0 FBB_CMD0
D13
FBC_MA3_BA3_L FBC_CS#_L <30>
FBMA-L11-160808300LMA25T_2P
1 2 +FB_PLLAVDD FBA_D3
L29
M28
FBA_D2
FBA_D3
FBA_CMD2
FBA_CMD3
U29
R34 FBA_MA4_BA2_L FBA_MA2_BA0_L <28>
FBA_MA4_BA2_L <28>
FBC_D2
E9
G8
FBB_D1
FBB_D2
FBB_CMD1
FBB_CMD2
E14
F14 FBC_MA2_BA0_L FBC_MA3_BA3_L <30>
FBC_MA2_BA0_L <30>
GDDR5
D FBA_D4 N31 R33 FBA_MA5_BA1_L FBC_D3 F9 A12 FBC_MA4_BA2_L D
LV3 OPT@ FBA_D5 P29
FBA_D4
FBA_D5
FBA_CMD4
FBA_CMD5
U32 FBA_WE#_L FBA_MA5_BA1_L <28> +1.5VS_VGA
FBA_WE#_L <28>
FBC_D4 F11
FBB_D3
FBB_D4
FBB_CMD3
FBB_CMD4
B12 FBC_MA5_BA1_L FBC_MA4_BA2_L <30>
FBC_MA5_BA1_L <30> +1.5VS_VGA
Mode H - Mirror Mode Mapping
Place close to BGA FBA_D6 R29
FBA_D6 FBA_CMD6
U33 FBA_MA7_MA8_L
FBA_MA7_MA8_L <28>
FBC_D5 G11
FBB_D5 FBB_CMD5
C14 FBC_WE#_L
FBC_WE#_L <30>
FBA_D7 P28 U28 FBA_MA6_MA11_L FBC_D6 F12 B14 FBC_MA7_MA8_L
FBA_D7 FBA_CMD7 FBA_MA6_MA11_L <28> FBB_D6 FBB_CMD6 FBC_MA7_MA8_L <30>

1
FBA_D8 J28 V28 FBA_ABI#_L FBC_D7 G12 G15 FBC_MA6_MA11_L DATA Bus
FBA_D8 FBA_CMD8 FBA_ABI#_L <28> FBB_D7 FBB_CMD7 FBC_MA6_MA11_L <30>

1
FBA_D9 H29 V29 FBA_MA12_RFU_L RV209 FBC_D8 G6 F15 FBC_ABI#_L
FBA_D10 FBA_D9 FBA_CMD9 FBA_MA0_MA10_L FBA_MA12_RFU_L <28> FBC_D9 FBB_D8 FBB_CMD8 FBC_MA12_RFU_L FBC_ABI#_L <30>
J29
FBA_D10 FBA_CMD10
V30 FBA_MA0_MA10_L <28> 10K_0402_5% F5
FBB_D9 FBB_CMD9
E15 FBC_MA12_RFU_L <30>
RV210 Address 0..31 32..63
FBA_D11 H28 U34 FBA_MA1_MA9_L FBC_D10 E6 D15 FBC_MA0_MA10_L 10K_0402_5%
FBA_D11 FBA_CMD11 FBA_MA1_MA9_L <28> OPT@ FBB_D10 FBB_CMD10 FBC_MA0_MA10_L <30>
FBA_D12 G29 U31 FBA_RAS#_L FBC_D11 F6 A14 FBC_MA1_MA9_L FBx_CMD0 CS#
OPT@

2
FBA_D13 FBA_D12 FBA_CMD12 FBA_RST#_L FBA_RAS#_L <28> FBC_D12 FBB_D11 FBB_CMD11 FBC_RAS#_L FBC_MA1_MA9_L <30>
E31 V34 F4 D14

2
FBA_D14 FBA_D13 FBA_CMD13 FBA_CKE_L FBA_RST#_L <28> FBC_D13 FBB_D12 FBB_CMD12 FBC_RST#_L FBC_RAS#_L <30>
E32
FBA_D14 FBA_CMD14
V33 FBA_CKE_L <28> G4
FBB_D13 FBB_CMD13
A15 FBC_RST#_L <30> FBx_CMD1 A3_BA3
FBA_D15 F30 Y32 FBA_CAS#_L FBC_D14 E2 B15 FBC_CKE_L
FBA_D16 FBA_D15 FBA_CMD15 FBA_CS#_H FBA_CAS#_L <28> FBC_D15 FBB_D14 FBB_CMD14 FBC_CAS#_L FBC_CKE_L <30>
C34
FBA_D16 FBA_CMD16
AA31 FBA_CS#_H <29> F3
FBB_D15 FBB_CMD15
C17 FBC_CAS#_L <30> FBx_CMD2 A2_BA0
FBA_D17 D32 AA29 FBA_MA3_BA3_H FBC_D16 C2 D18 FBC_CS#_H
FBA_D18 FBA_D17 FBA_CMD17 FBA_MA2_BA0_H FBA_MA3_BA3_H <29> FBC_D17 FBB_D16 FBB_CMD16 FBC_MA3_BA3_H FBC_CS#_H <31>
B33
FBA_D18 FBA_CMD18
AA28 FBA_MA2_BA0_H <29> D4
FBB_D17 FBB_CMD17
E18 FBC_MA3_BA3_H <31> FBx_CMD3 A4_BA2
FBA_D19 C33 AC34 FBA_MA4_BA2_H FBC_D18 D3 F18 FBC_MA2_BA0_H
FBA_D20 FBA_D19 FBA_CMD19 FBA_MA5_BA1_H FBA_MA4_BA2_H <29> FBC_D19 FBB_D18 FBB_CMD18 FBC_MA4_BA2_H FBC_MA2_BA0_H <31>
F33
FBA_D20 FBA_CMD20
AC33 FBA_MA5_BA1_H <29>+1.5VS_VGA C1
FBB_D19 FBB_CMD19
A20 FBC_MA4_BA2_H <31> FBx_CMD4 A5_BA1
FBA_D21 F32 AA32 FBA_WE#_H FBC_D20 B3 B20 FBC_MA5_BA1_H
FBA_D22 FBA_D21 FBA_CMD21 FBA_MA7_MA8_H FBA_WE#_H <29> FBC_D21 FBB_D20 FBB_CMD20 FBC_WE#_H FBC_MA5_BA1_H <31>+1.5VS_VGA
H33
FBA_D22 FBA_CMD22
AA33 FBA_MA7_MA8_H <29> C4
FBB_D21 FBB_CMD21
C18 FBC_WE#_H <31> FBx_CMD5 WE#
FBA_D23 H32 Y28 FBA_MA6_MA11_H FBC_D22 B5 B18 FBC_MA7_MA8_H
FBA_D23 FBA_CMD23 FBA_MA6_MA11_H <29> FBB_D22 FBB_CMD22 FBC_MA7_MA8_H <31>

1
FBA_D24 P34 Y29 FBA_ABI#_H FBC_D23 C5 G18 FBC_MA6_MA11_H FBx_CMD6 A7_A8

MEMORY INTERFACE
FBA_D24 FBA_CMD24 FBA_ABI#_H <29> FBB_D23 FBB_CMD23 FBC_MA6_MA11_H <31>

1
FBA_D25 P32 W31 FBA_MA12_RFU_H RV221 FBC_D24 A11 G17 FBC_ABI#_H
FBA_D26 FBA_D25 FBA_CMD25 FBA_MA0_MA10_H FBA_MA12_RFU_H <29> FBC_D25 FBB_D24 FBB_CMD24 FBC_MA12_RFU_H FBC_ABI#_H <31>
P31
FBA_D26 FBA_CMD26
Y30 FBA_MA0_MA10_H <29> 10K_0402_5% C11
FBB_D25 FBB_CMD25
F17 FBC_MA12_RFU_H <31>
RV222 FBx_CMD7 A6_A11
FBA_D27 FBA_MA1_MA9_H FBC_D26 FBC_MA0_MA10_H

MEMORY INTERFACE B
P33 AA34 FBA_MA1_MA9_H <29> OPT@ D11 D16 FBC_MA0_MA10_H <31> 10K_0402_5%
FBA_D28 FBA_D27 FBA_CMD27 FBA_RAS#_H FBC_D27 FBB_D26 FBB_CMD26 FBC_MA1_MA9_H
L31 Y31 B11 A18 OPT@ FBx_CMD8 ABI#

2
FBA_D29 FBA_D28 FBA_CMD28 FBA_RST#_H FBA_RAS#_H <29> FBC_D28 FBB_D27 FBB_CMD27 FBC_RAS#_H FBC_MA1_MA9_H <31>
L34 Y34 D8 D17

2
FBA_D30 FBA_D29 FBA_CMD29 FBA_CKE_H FBA_RST#_H <29> FBC_D29 FBB_D28 FBB_CMD28 FBC_RST#_H FBC_RAS#_H <31>
L32
FBA_D30 FBA_CMD30
Y33 FBA_CKE_H <29> A8
FBB_D29 FBB_CMD29
A17 FBC_RST#_H <31> FBx_CMD9 A12_RFU
FBA_D31 L33 V31 FBA_CAS#_H FBC_D30 C8 B17 FBC_CKE_H
FBA_D32 FBA_D31 FBA_CMD31 FBA_CAS#_H <29> FBC_D31 FBB_D30 FBB_CMD30 FBC_CAS#_H FBC_CKE_H <31>
AG28
FBA_D32
B8
FBB_D31 FBB_CMD31
E17 FBC_CAS#_H <31> FBx_CMD10 A0_A10
FBA_D33 AF29 FBC_D32 F24
FBA_D34 FBA_D33 FBC_D33 FBB_D32
AG29
FBA_D34
G23
FBB_D33 FBx_CMD11 A1_A9
FBA_D35 AF28 R32 FBC_D34 E24
C FBA_D36 FBA_D35 FBA_CMD_RFU0 FBC_D35 FBB_D34 C
AD30
FBA_D36 FBA_CMD_RFU1
AC32 G24
FBB_D35 FBB_CMD_RFU0
C12 FBx_CMD12 RAS#
FBA_D37 AD29 FBC_D36 D21 C20
FBA_D38 FBA_D37 FBC_D37 FBB_D36 FBB_CMD_RFU1
AC29
FBA_D38
E21
FBB_D37 FBx_CMD13 RST#
FBA_D39 AD28 @ FBC_D38 G21
FBA_D39 FBB_D38

A
FBA_D40 AJ29 R28 60.4_0402_1%
1 2RV58 FBC_D39 F21 @ FBx_CMD14 CKE#
FBA_D40 FBA_DEBUG0 +1.5VS_VGA FBB_D39
FBA_D41 AK29 AC28 60.4_0402_1%
1 2RV59 FBC_D40 G27 G14 60.4_0402_1%
1 2RV60
FBA_D41 FBA_DEBUG1 FBB_D40 FBB_DEBUG0 +1.5VS_VGA
FBA_D42 AJ30 @ FBC_D41 D27 G20 60.4_0402_1%
1 2RV61 FBx_CMD15 CAS#
FBA_D43 FBA_D42 FBC_D42 FBB_D41 FBB_DEBUG1 @
AK28 G26
FBA_D44 FBA_D43 FBC_D43 FBB_D42
AM29
FBA_D44
E27
FBB_D43 FBx_CMD16 CS#
FBA_D45 AM31 R30 FBA_CLK0 FBC_D44 E29
FBA_D46 FBA_D45 FBA_CLK0 FBA_CLK0# FBA_CLK0 <28> FBC_D45 FBB_D44 FBC_CLK0
AN29
FBA_D46 FBA_CLK0_N
R31 FBA_CLK0# <28> F29
FBB_D45 FBB_CLK0
D12 FBC_CLK0 <30> FBx_CMD17 A3_BA3
FBA_D47 AM30 AB31 FBA_CLK1 FBC_D46 E30 E12 FBC_CLK0#
FBA_D48 FBA_D47 FBA_CLK1 FBA_CLK1# FBA_CLK1 <29> FBC_D47 FBB_D46 FBB_CLK0_N FBC_CLK1 FBC_CLK0# <30>
AN31
FBA_D48 FBA_CLK1_N
AC31 FBA_CLK1# <29> D30
FBB_D47 FBB_CLK1
E20 FBC_CLK1 <31> FBx_CMD18 A2_BA0
FBA_D49 AN32 FBC_D48 A32 F20 FBC_CLK1#
FBA_D50 FBA_D49 FBC_D49 FBB_D48 FBB_CLK1_N FBC_CLK1# <31>
AP30
FBA_D50
C31
FBB_D49 FBx_CMD19 A4_BA2
FBA_D51 AP32 FBC_D50 C32
FBA_D52 FBA_D51 FBA_WCK0 FBC_D51 FBB_D50
AM33
FBA_D52 FBA_WCK01
K31 FBA_WCK0 <28> B32
FBB_D51 FBx_CMD20 A5_BA1
FBA_D53 AL31 L30 FBA_WCK0_N FBC_D52 D29 F8 FBC_WCK0
FBA_D54 FBA_D53 FBA_WCK01_N FBA_WCK1 FBA_WCK0_N <28> FBC_D53 FBB_D52 FBB_WCK01 FBC_WCK0_N FBC_WCK0 <30>
AK33
FBA_D54 FBA_WCK23
H34 FBA_WCK1 <28> A29
FBB_D53 FBB_WCK01_N
E8 FBC_WCK0_N <30> FBx_CMD21 WE#
FBA_D55 AK32 J34 FBA_WCK1_N FBC_D54 C29 A5 FBC_WCK1
FBA_D56 FBA_D55 FBA_WCK23_N FBA_WCK2 FBA_WCK1_N <28> FBC_D55 FBB_D54 FBB_WCK23 FBC_WCK1_N FBC_WCK1 <30>
AD34
FBA_D56 FBA_WCK45
AG30 FBA_WCK2 <29> B29
FBB_D55 FBB_WCK23_N
A6 FBC_WCK1_N <30> FBx_CMD22 A7_A8
FBA_D57 AD32 AG31 FBA_WCK2_N FBC_D56 B21 D24 FBC_WCK2
FBA_D58 FBA_D57 FBA_WCK45_N FBA_WCK3 FBA_WCK2_N <29> FBC_D57 FBB_D56 FBB_WCK45 FBC_WCK2_N FBC_WCK2 <31>
AC30
FBA_D58 FBA_WCK67
AJ34 FBA_WCK3 <29> C23
FBB_D57 FBB_WCK45_N
D25 FBC_WCK2_N <31> FBx_CMD23 A6_A11
FBA_D59 AD33 AK34 FBA_WCK3_N FBC_D58 A21 B27 FBC_WCK3
FBA_D60 FBA_D59 FBA_WCK67_N FBA_WCK3_N <29> FBC_D59 FBB_D58 FBB_WCK67 FBC_WCK3_N FBC_WCK3 <31>
AF31
FBA_D60
C21
FBB_D59 FBB_WCK67_N
C27 FBC_WCK3_N <31> FBx_CMD24 ABI#
FBA_D61 AG34 FBC_D60 B24
FBA_D62 FBA_D61 FBC_D61 FBB_D60
AG32
FBA_D62
C24
FBB_D61 FBx_CMD25 A12_RFU
FBA_D63 AG33 J30 FBC_D62 B26
FBA_D63 FBA_WCKB01 FBC_D63 FBB_D62
FBA_WCKB01_N
J31 C26
FBB_D63 FBB_WCKB01
D6 FBx_CMD26 A0_A10
FBA_DBI0# P30 J32 D7
<28> FBA_DBI0# FBA_DBI1# FBA_DQM0 FBA_WCKB23 FBC_DBI0# FBB_WCKB01_N
<28> FBA_DBI1# F31
FBA_DQM1 FBA_WCKB23_N
J33 <30> FBC_DBI0# E11
FBB_DQM0 FBB_WCKB23
C6 FBx_CMD27 A1_A9
FBA_DBI2# F34 AH31 FBC_DBI1# E3 B6
B <28> FBA_DBI2# FBA_DBI3# FBA_DQM2 FBA_WCKB45 <30> FBC_DBI1# FBC_DBI2# FBB_DQM1 FBB_WCKB23_N B
<28> FBA_DBI3# M32
FBA_DQM3 FBA_WCKB45_N
AJ31 <30> FBC_DBI2# A3
FBB_DQM2 FBB_WCKB45
F26 FBx_CMD28 RAS#
FBA_DBI4# AD31 AJ32 FBC_DBI3# C9 E26
<29> FBA_DBI4# FBA_DBI5# FBA_DQM4 FBA_WCKB67 <30> FBC_DBI3# FBC_DBI4# FBB_DQM3 FBB_WCKB45_N
<29> FBA_DBI5# AL29
FBA_DQM5 FBA_WCKB67_N
AJ33 <31> FBC_DBI4# F23
FBB_DQM4 FBB_WCKB67
A26 FBx_CMD29 RST#
FBA_DBI6# AM32 FB_CLAMP FBC_DBI5# F27 A27
<29> FBA_DBI6# FBA_DBI7# FBA_DQM6 <31> FBC_DBI5# FBC_DBI6# FBB_DQM5 FBB_WCKB67_N
<29> FBA_DBI7# AF34
FBA_DQM7 <31> FBC_DBI6# C30
FBB_DQM6 FBx_CMD30 CKE#
RV66 NOGC6@ 10K_0402_5% FBC_DBI7# A24
FBA_EDC0 <31> FBC_DBI7# FBB_DQM7
M31
FBA_DQS_WP0 FB_CLAMP
E1 2 1 FBx_CMD31 CAS#
FBA_EDC1 G31 FBC_EDC0 D10
<28> FBA_EDC[3..0] FBA_DQS_WP1 +FB_PLLAVDD FBB_DQS_WP0
FBA_EDC2 E33 FBC_EDC1 D5
FBA_EDC3 FBA_DQS_WP2 CV106 0.1U_0402_10V7K FBC_EDC2 FBB_DQS_WP1
<29> FBA_EDC[7..4] M33 C3
FBA_EDC4 FBA_DQS_WP3 FBC_EDC3 FBB_DQS_WP2
AE31 K27 1 2 B9
FBA_EDC5 FBA_DQS_WP4 FB_DLL_AVDD OPT@ FBC_EDC4 FBB_DQS_WP3
AK30 E23 H17 +FB_PLLAVDD
FBA_DQS_WP5 FBB_DQS_WP4 FBB_PLL_AVDD

0.1U_0402_10V7K
FBA_EDC6 AN33 Place close to ball FBC_EDC5 E28
FBA_DQS_WP6 FBB_DQS_WP5

OPT@ CV108
FBA_EDC7 AF33 FBC_EDC6 B30 1
FBA_DQS_WP7 FBC_EDC7 FBB_DQS_WP6
U27 +FB_PLLAVDD A23
FBA_PLL_AVDD FBB_DQS_WP7

22U_0805_6.3V6M
0.1U_0402_10V7K

M30
FBA_DQS_RN0
OPT@ CV107

OPT@ CV110
1U_0402_6.3V6K

H30 1 1 1 <30> FBC_EDC[3..0] D9

FBA_DQS_RN1 FBB_DQS_RN0 2

OPT@CV39
E34 E4
FBA_DQS_RN2 FBB_DQS_RN1
M34 H26 <31> FBC_EDC[7..4] B2
FBA_DQS_RN3 FB_VREF FBB_DQS_RN2
AF30 A9
FBA_DQS_RN4 2 2 2 FBB_DQS_RN3
AK31 D22
FBA_DQS_RN5 FBB_DQS_RN4
AM34
FBA_DQS_RN6
D28
FBB_DQS_RN5
Place close to ball
AF32 A30
FBA_DQS_RN7 FBB_DQS_RN6 FBC_RST#_L
B23
FBB_DQS_RN7
Place close to ball Place close to BGA FBC_RST#_H
For N13P-GT/N13E-GE GC6 support

1
N13P-PES-A1_FCBGA908
GC6@ +3VS N13P-PES-A1_FCBGA908 RV74 RV73
FBA_RST#_L 10K_0402_5% 10K_0402_5%
1

RV157 D FBA_RST#_H
OPT@ OPT@
1 2 2 QV3

2
A <18> DGPU_GC6_EN A
G 2N7002_SOT23
1

0_0402_5% S DV2
3

GC6@ RV71 RV72

GC6@ DAN202UT106_SC70-3 10K_0402_5% 10K_0402_5%
FB_CLAMP 1 2 GC6_EN 2 OPT@ OPT@
1K_0402_1% RV7 1
2

FBVDDQ_PWR_EN <53>
2 1 3
10K_0402_5% RV67
Security Classification Compal Secret Data Compal Electronics, Inc.
1

GC6@ GC6@
RV19 2011/07/21 2012/12/31 Title
Issued Date Deciphered Date
200K_0402_5%
<19,53,56> DGPU_PWROK 1 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-MEM Interface
RV156 0_0402_5% GC6@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2

1.0
NOGC6@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 27 of 64
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits UV3 UV4

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBA_D0 A4 FBA_D24
FBA_EDC0 DQ24 DQ0 FBA_D1 FBA_EDC3 DQ24 DQ0 FBA_D25
C2 A2 C2 A2
EDC0 EDC3 DQ25 DQ1 FBA_D2 EDC0 EDC3 DQ25 DQ1 FBA_D26
C13 B4 C13 B4
EDC1 EDC2 DQ26 DQ2 EDC1 EDC2 DQ26 DQ2
<27> FBA_D[0..31]
FBA_EDC2 R13
EDC2 EDC1 DQ27 DQ3
B2 FBA_D3 BYTE0 FBA_EDC1 R13
EDC2 EDC1 DQ27 DQ3
B2 FBA_D27
R2 E4 FBA_D4 R2 E4 FBA_D28 BYTE3
EDC3 EDC0 DQ28 DQ4 FBA_D5 EDC3 EDC0 DQ28 DQ4 FBA_D29
E2 E2
DQ29 DQ5 FBA_D6 DQ29 DQ5 FBA_D30
<27> FBA_EDC[3..0] F4 F4
FBA_DBI0# DQ30 DQ6 FBA_D7 FBA_DBI3# DQ30 DQ6 FBA_D31
<27> FBA_DBI0# D2 F2 <27> FBA_DBI3# D2 F2
DBI0# DBI3# DQ31 DQ7 DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
FBA_DBI2# DBI1# DBI2# DQ16 DQ8 FBA_DBI1# DBI1# DBI2# DQ16 DQ8
<27> FBA_DBI2# P13 A13 <27> FBA_DBI1# P13 A13
DBI2# DBI1# DQ17 DQ9 DBI2# DBI1# DQ17 DQ9
D P2 B11 P2 B11 D
DBI3# DBI0# DQ18 DQ10 DBI3# DBI0# DQ18 DQ10
B13 B13
FBA_CLK0 DQ19 DQ11 FBA_CLK0 DQ19 DQ11
<27> FBA_CLK0 J12 E11 <27> FBA_CLK0 J12 E11
FBA_CLK0# CK DQ20 DQ12 FBA_CLK0# CK DQ20 DQ12
<27> FBA_CLK0# J11 E13 <27> FBA_CLK0# J11 E13
FBA_CKE_L CK# DQ21 DQ13 FBA_CKE_L CK# DQ21 DQ13
<27> FBA_CKE_L J3
CKE# DQ22
DQ23
DQ14
DQ15
F11
F13
<27> FBA_CKE_L J3
CKE# DQ22
DQ23
DQ14
DQ15
F11
F13 GDDR5
U11 FBA_D16 U11 FBA_D8
<27> FBA_MA2_BA0_L
FBA_MA2_BA0_L H11
BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13 FBA_D17
<27> FBA_MA4_BA2_L
FBA_MA4_BA2_L H11
BA0/A2 BA2/A4
DQ8
DQ9
DQ16
DQ17
U13 FBA_D9 Mode H - Mirror Mode Mapping
FBA_MA5_BA1_L K10 T11 FBA_D18 FBA_MA3_BA3_L K10 T11 FBA_D10
<27> FBA_MA5_BA1_L BA1/A5 BA3/A3 DQ10 DQ18 <27> FBA_MA3_BA3_L BA1/A5 BA3/A3 DQ10 DQ18
FBA_MA4_BA2_L K11 T13 FBA_D19 FBA_MA2_BA0_L K11 T13 FBA_D11 BYTE1
<27> FBA_MA4_BA2_L BA2/A4 BA0/A2 DQ11 DQ19 <27> FBA_MA2_BA0_L BA2/A4 BA0/A2 DQ11 DQ19
<27> FBA_MA3_BA3_L
FBA_MA3_BA3_L H10
BA3/A3 BA1/A5 DQ12 DQ20
N11 FBA_D20 BYTE2 <27> FBA_MA5_BA1_L
FBA_MA5_BA1_L H10
BA3/A3 BA1/A5 DQ12 DQ20
N11 FBA_D12 DATA Bus
N13 FBA_D21 N13 FBA_D13
DQ13 DQ21 DQ13 DQ21 Address
DQ14 DQ22
M11 FBA_D22
DQ14 DQ22
M11 FBA_D14 0..31 32..63
FBA_MA7_MA8_L K4 M13 FBA_D23 FBA_MA0_MA10_L K4 M13 FBA_D15
<27> FBA_MA7_MA8_L A8/A7 A10/A0 DQ15 DQ23 <27> FBA_MA0_MA10_L A8/A7 A10/A0 DQ15 DQ23
FBA_MA1_MA9_L H5 U4 FBA_MA6_MA11_L H5 U4 FBx_CMD0 CS#
<27> FBA_MA1_MA9_L A9/A1 A11/A6 DQ0 DQ24 <27> FBA_MA6_MA11_L A9/A1 A11/A6 DQ0 DQ24
FBA_MA0_MA10_L H4 U2 FBA_MA7_MA8_L H4 U2
<27> FBA_MA0_MA10_L A10/A0 A8/A7 DQ1 DQ25 <27> FBA_MA7_MA8_L A10/A0 A8/A7 DQ1 DQ25
<27> FBA_MA6_MA11_L
FBA_MA6_MA11_L K5
A11/A6 A9/A1 DQ2 DQ26
T4 <27> FBA_MA1_MA9_L
FBA_MA1_MA9_L K5
A11/A6 A9/A1 DQ2 DQ26
T4 FBx_CMD1 A3_BA3
FBA_MA12_RFU_L J5 T2 FBA_MA12_RFU_L J5 T2
<27> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27 <27> FBA_MA12_RFU_L A12/RFU/NC DQ3 DQ27
DQ4 DQ28
N4
DQ4 DQ28
N4 FBx_CMD2 A2_BA0
A5 N2 A5 N2
VPP/NC DQ5 DQ29 +1.5VS_VGA VPP/NC DQ5 DQ29
U5
VPP/NC DQ6 DQ30
M4 U5
VPP/NC DQ6 DQ30
M4 FBx_CMD3 A4_BA2
2 RV115 1 M2 2 RV116 1 M2
DQ7 DQ31 DQ7 DQ31
OPT@ 1K_0402_1%
+1.5VS_VGA
OPT@ 1K_0402_1%
+1.5VS_VGA
FBx_CMD4 A5_BA1
J1 J1
MF MF
2 RV117 1 J10
SEN
2 RV118 1 J10
SEN FBx_CMD5 WE#
2 RV119 1 OPT@ 1K_0402_1% J13 B1 2 RV120 1 OPT@ 1K_0402_1% J13 B1
ZQ VDDQ ZQ VDDQ
OPT@ 121_0402_1%
VDDQ
D1 OPT@ 121_0402_1%
VDDQ
D1 FBx_CMD6 A7_A8
F1 F1
VDDQ VDDQ
Follow DG <27> FBA_ABI#_L
FBA_ABI#_L J4
ABI# VDDQ
M1 <27> FBA_ABI#_L
FBA_ABI#_L J4
ABI# VDDQ
M1 FBx_CMD7 A6_A11
FBA_RAS#_L G3 P1 FBA_CAS#_L G3 P1
<27> FBA_RAS#_L RAS# CAS# VDDQ <27> FBA_CAS#_L RAS# CAS# VDDQ
<27> FBA_CS#_L
FBA_CS#_L G12
CS# WE# VDDQ
T1 <27> FBA_WE#_L
FBA_WE#_L G12
CS# WE# VDDQ
T1 FBx_CMD8 ABI#
FBA_CLK0 1 2 FBA_CAS#_L L3 G2 FBA_RAS#_L L3 G2
<27> FBA_CAS#_L CAS# RAS# VDDQ <27> FBA_RAS#_L CAS# RAS# VDDQ
RV21 40.2_0402_1%
<27> FBA_WE#_L
FBA_WE#_L L12
WE# CS# VDDQ
L2 <27> FBA_CS#_L
FBA_CS#_L L12
WE# CS# VDDQ
L2 FBx_CMD9 A12_RFU
OPT@ B3 B3
2

VDDQ VDDQ
VDDQ
D3
VDDQ
D3 FBx_CMD10 A0_A10
RV123 F3 F3
VDDQ VDDQ
160_0402_1% <27> FBA_WCK0_N
FBA_WCK0_N D5
WCK01# WCK23# VDDQ
H3 <27> FBA_WCK1_N
FBA_WCK1_N D5
WCK01# WCK23# VDDQ
H3 FBx_CMD11 A1_A9
C @ FBA_WCK0 D4 K3 FBA_WCK1 D4 K3 C
<27> FBA_WCK0 WCK01 WCK23 VDDQ <27> FBA_WCK1 WCK01 WCK23 VDDQ
M3 M3 FBx_CMD12 RAS#
1

FBA_CLK0# FBA_WCK1_N VDDQ FBA_WCK0_N VDDQ

1 2 <27> FBA_WCK1_N P5 P3 <27> FBA_WCK0_N P5 P3
WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ
RV28 40.2_0402_1%
<27> FBA_WCK1
FBA_WCK1 P4
WCK23 WCK01 VDDQ
T3 <27> FBA_WCK0
FBA_WCK0 P4
WCK23 WCK01 VDDQ
T3 FBx_CMD13 RST#
OPT@ E5 E5
VDDQ VDDQ
VDDQ
N5
VDDQ
N5 FBx_CMD14 CKE#
OPT@ CV155

+FBA_VREFD_L A10 E10 +FBA_VREFD_L A10 E10

0.01U_0402_25V7K

1 VREFD VDDQ VREFD VDDQ

U10
VREFD VDDQ
N10 U10
VREFD VDDQ
N10 FBx_CMD15 CAS#
+FBA_VREFC0 J14 B12 +FBA_VREFC0 J14 B12
VREFC VDDQ VREFC VDDQ
2 VDDQ
D12
VDDQ
D12 FBx_CMD16 CS#
F12 F12
VDDQ VDDQ
VDDQ
H12
VDDQ
H12 FBx_CMD17 A3_BA3
FBA_RST#_L J2 K12 FBA_RST#_L J2 K12
<27> FBA_RST#_L RESET# VDDQ <27> FBA_RST#_L RESET# VDDQ
VDDQ
M12
VDDQ
M12 FBx_CMD18 A2_BA0
P12 P12
VDDQ VDDQ
+1.5VS_VGA VDDQ
T12
VDDQ
T12 FBx_CMD19 A4_BA2
G13 G13
VDDQ VDDQ
H1
VSS VDDQ
L13 H1
VSS VDDQ
L13 FBx_CMD20 A5_BA1
K1 B14 K1 B14
VSS VDDQ VSS VDDQ
1

B5
VSS VDDQ
D14 B5
VSS VDDQ
D14 FBx_CMD21 WE#
RV127 G5 F14 G5 F14
VSS VDDQ VSS VDDQ
549_0402_1% L5
VSS VDDQ
M14 L5
VSS VDDQ
M14 FBx_CMD22 A7_A8
OPT@ T5 P14 T5 P14
RV212 VSS VDDQ VSS VDDQ
B10 T14 B10 T14 FBx_CMD23 A6_A11
2

+FBA_VREFC0 VSS VDDQ VSS VDDQ

1 2 D10 D10
VSS VSS
931_0402_1% FBx_CMD24 ABI#
820P_0402_25V7

G10 G10
VSS VSS
1

OPT@ CV42

OPT@ 1 16 mil L10

VSS VSSQ
A1 L10
VSS VSSQ
A1
RV128 P10
VSS VSSQ
C1 P10
VSS VSSQ
C1 FBx_CMD25 A12_RFU
1.33K_0402_1% T10 E1 T10 E1
VSS VSSQ VSS VSSQ
OPT@
2
H14
VSS VSSQ
N1 H14
VSS VSSQ
N1 FBx_CMD26 A0_A10
K14 R1 K14 R1
2

+1.5VS_VGA VSS VSSQ +1.5VS_VGA VSS VSSQ

VSSQ
U1
VSSQ
U1 FBx_CMD27 A1_A9
H2 H2
VSSQ VSSQ
G1
VDD VSSQ
K2 G1
VDD VSSQ
K2 FBx_CMD28 RAS#
L1 A3 L1 A3
VDD VSSQ VDD VSSQ
G4
VDD VSSQ
C3 G4
VDD VSSQ
C3 FBx_CMD29 RST#
L4 E3 L4 E3
VDD VSSQ VDD VSSQ
B
+1.5VS_VGA
C5
VDD VSSQ
N3 C5
VDD VSSQ
N3 FBx_CMD30 CKE# B
R5 R3 R5 R3
VDD VSSQ VDD VSSQ
C10
VDD VSSQ
U3 C10
VDD VSSQ
U3 FBx_CMD31 CAS#
R10 C4 R10 C4
VDD VSSQ VDD VSSQ
1

D11 R4 D11 R4
RV129 VDD VSSQ VDD VSSQ
G11 F5 G11 F5
549_0402_1% VDD VSSQ VDD VSSQ
L11 M5 L11 M5
OPT@ VDD VSSQ VDD VSSQ
RV213 P11 F10 P11 F10
VDD VSSQ VDD VSSQ
G14 M10 G14 M10
2

+FBA_VREFD_L VDD VSSQ VDD VSSQ

1 2 L14 C11 L14 C11
931_0402_1% VDD VSSQ VDD VSSQ
820P_0402_25V7

R11 R11
VSSQ VSSQ
1

OPT@ CV58

OPT@ 1 A12 A12

RV130 VSSQ VSSQ
C12 C12
VSSQ VSSQ
1

D 1.33K_0402_1% E12 E12

OPT@ OPT@ VSSQ VSSQ
2 N12 N12
<23,29,30,31> MEM_VREF G 2 VSSQ VSSQ
R12 R12
2

QV9 170-BALL VSSQ 170-BALL VSSQ

S U12 U12
3

2N7002W-T/R7_SOT323-3 VSSQ VSSQ

H13 H13
SGRAM GDDR5 VSSQ SGRAM GDDR5 VSSQ
K13 K13
VSSQ VSSQ
A14 A14
VSSQ VSSQ
C14 C14
VSSQ VSSQ
E14 E14
VSSQ VSSQ
N14 N14
VSSQ VSSQ
R14 R14
VSSQ VSSQ
U14 U14
VSSQ VSSQ
X76@ X76@

H5GQ1H24AFR-T2L_BGA170 H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV3 SIDE +1.5VS_VGA UV4 SIDE
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
OPT@ CV68

OPT@ CV69

OPT@ CV77

OPT@ CV78

OPT@ CV71

OPT@ CV76

OPT@ CV79

OPT@ CV80
OPT@ CV166

OPT@ CV129

OPT@ CV132

OPT@ CV133

OPT@ CV174

OPT@ CV134

OPT@ CV135

OPT@ CV136
2 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1

1 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-VRAM A Lower
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 28 of 64
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits UV6

UV5
MF=0 MF=1 MF=1 MF=0
MF=0 MF=1 MF=1 MF=0
A4 FBA_D56
FBA_D32 FBA_EDC7 DQ24 DQ0 FBA_D57
A4 C2 A2
FBA_EDC4 DQ24 DQ0 FBA_D33 EDC0 EDC3 DQ25 DQ1 FBA_D58
C2 A2 C13 B4
EDC0 EDC3 DQ25 DQ1 FBA_D34 FBA_EDC5 EDC1 EDC2 DQ26 DQ2 FBA_D59
C13 B4 R13 B2
FBA_EDC6 EDC1 EDC2 DQ26 DQ2 FBA_D35 EDC2 EDC1 DQ27 DQ3 FBA_D60
<27> FBA_D[63..32] R13
EDC2 EDC1 DQ27 DQ3
B2 BYTE4 R2
EDC3 EDC0 DQ28 DQ4
E4 BYTE7
R2 E4 FBA_D36 E2 FBA_D61
EDC3 EDC0 DQ28 DQ4 FBA_D37 DQ29 DQ5 FBA_D62
E2 F4
DQ29 DQ5 FBA_D38 FBA_DBI7# DQ30 DQ6 FBA_D63
<27> FBA_EDC[7..4] F4 <27> FBA_DBI7# D2 F2
FBA_DBI4# DQ30 DQ6 FBA_D39 DBI0# DBI3# DQ31 DQ7
<27> FBA_DBI4# D2 F2 D13 A11
DBI0# DBI3# DQ31 DQ7 FBA_DBI5# DBI1# DBI2# DQ16 DQ8
D13 A11 <27> FBA_DBI5# P13 A13
FBA_DBI6# DBI1# DBI2# DQ16 DQ8 DBI2# DBI1# DQ17 DQ9
D <27> FBA_DBI6# P13 A13 P2 B11 D
DBI2# DBI1# DQ17 DQ9 DBI3# DBI0# DQ18 DQ10
P2 B11 B13
DBI3# DBI0# DQ18 DQ10 FBA_CLK1 DQ19 DQ11
B13 <27> FBA_CLK1 J12 E11
FBA_CLK1 DQ19 DQ11 FBA_CLK1# CK DQ20 DQ12
<27> FBA_CLK1 J12 E11 <27> FBA_CLK1# J11 E13
FBA_CLK1# CK DQ20 DQ12 FBA_CKE_H CK# DQ21 DQ13
<27> FBA_CLK1# J11 E13 <27> FBA_CKE_H J3 F11
FBA_CKE_H CK# DQ21 DQ13 CKE# DQ22 DQ14
<27> FBA_CKE_H J3 F11 F13
CKE# DQ22 DQ14 DQ23 DQ15 FBA_D40
F13 U11
DQ23 DQ15 FBA_D48 FBA_MA4_BA2_H DQ8 DQ16 FBA_D41
U11 <27> FBA_MA4_BA2_H H11 U13
FBA_MA2_BA0_H DQ8 DQ16 FBA_D49 FBA_MA3_BA3_H BA0/A2 BA2/A4 DQ9 DQ17 FBA_D42
<27> FBA_MA2_BA0_H H11 U13 <27> FBA_MA3_BA3_H K10 T11
FBA_MA5_BA1_H BA0/A2 BA2/A4 DQ9 DQ17 FBA_D50 FBA_MA2_BA0_H BA1/A5 BA3/A3 DQ10 DQ18 FBA_D43
<27> FBA_MA5_BA1_H K10
BA1/A5 BA3/A3 DQ10 DQ18
T11 <27> FBA_MA2_BA0_H K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 BYTE5
FBA_MA4_BA2_H FBA_D51 FBA_MA5_BA1_H FBA_D44
<27>
<27>
FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA3_BA3_H
K11
H10
BA2/A4
BA3/A3
BA0/A2
BA1/A5
DQ11
DQ12
DQ19
DQ20
T13
N11 FBA_D52 BYTE6
<27> FBA_MA5_BA1_H H10
BA3/A3 BA1/A5 DQ12
DQ13
DQ20
DQ21
N11
N13 FBA_D45 GDDR5
N13 FBA_D53 M11 FBA_D46
DQ13
DQ14
DQ21
DQ22
M11 FBA_D54
<27> FBA_MA0_MA10_H
FBA_MA0_MA10_H K4
A8/A7 A10/A0
DQ14
DQ15
DQ22
DQ23
M13 FBA_D47 Mode H - Mirror Mode Mapping
FBA_MA7_MA8_H K4 M13 FBA_D55 FBA_MA6_MA11_H H5 U4
<27> FBA_MA7_MA8_H A8/A7 A10/A0 DQ15 DQ23 <27> FBA_MA6_MA11_H A9/A1 A11/A6 DQ0 DQ24
FBA_MA1_MA9_H H5 U4 FBA_MA7_MA8_H H4 U2
<27> FBA_MA1_MA9_H A9/A1 A11/A6 DQ0 DQ24 <27> FBA_MA7_MA8_H A10/A0 A8/A7 DQ1 DQ25
<27> FBA_MA0_MA10_H
FBA_MA0_MA10_H H4
A10/A0 A8/A7 DQ1 DQ25
U2 <27> FBA_MA1_MA9_H
FBA_MA1_MA9_H K5
A11/A6 A9/A1 DQ2 DQ26
T4 DATA Bus
FBA_MA6_MA11_H K5 T4 FBA_MA12_RFU_H J5 T2
<27> FBA_MA6_MA11_H A11/A6 A9/A1 DQ2 DQ26 <27> FBA_MA12_RFU_H A12/RFU/NC DQ3 DQ27
<27> FBA_MA12_RFU_H
FBA_MA12_RFU_H J5 T2 N4 Address 0..31 32..63
A12/RFU/NC DQ3 DQ27 DQ4 DQ28
N4 A5 N2
DQ4 DQ28 +1.5VS_VGA VPP/NC DQ5 DQ29
A5
VPP/NC DQ5 DQ29
N2 U5
VPP/NC DQ6 DQ30
M4 FBx_CMD0 CS#
U5 M4 2 RV132 1 M2
VPP/NC DQ6 DQ30 DQ7 DQ31
2 RV131 1
DQ7 DQ31
M2 OPT@ 1K_0402_1%
+1.5VS_VGA
FBx_CMD1 A3_BA3
OPT@ 1K_0402_1% J1
+1.5VS_VGA MF
J1
MF
2 RV134 1 J10
SEN FBx_CMD2 A2_BA0
2 RV133 1 J10 2 RV136 1 OPT@ 1K_0402_1% J13 B1
SEN ZQ VDDQ
2 RV135 1 OPT@ 1K_0402_1% J13
ZQ VDDQ
B1 OPT@ 121_0402_1%
VDDQ
D1 FBx_CMD3 A4_BA2
OPT@ 121_0402_1% D1 F1
VDDQ VDDQ
Follow DG VDDQ
F1 <27> FBA_ABI#_H
FBA_ABI#_H J4
ABI# VDDQ
M1 FBx_CMD4 A5_BA1
FBA_ABI#_H J4 M1 FBA_CAS#_H G3 P1
<27> FBA_ABI#_H ABI# VDDQ <27> FBA_CAS#_H RAS# CAS# VDDQ
<27> FBA_RAS#_H
FBA_RAS#_H G3
RAS# CAS# VDDQ
P1 <27> FBA_WE#_H
FBA_WE#_H G12
CS# WE# VDDQ
T1 FBx_CMD5 WE#
FBA_CS#_H G12 T1 FBA_RAS#_H L3 G2
<27> FBA_CS#_H CS# WE# VDDQ <27> FBA_RAS#_H CAS# RAS# VDDQ
FBA_CLK1 1 2 <27> FBA_CAS#_H
FBA_CAS#_H L3
CAS# RAS# VDDQ
G2 <27> FBA_CS#_H
FBA_CS#_H L12
WE# CS# VDDQ
L2 FBx_CMD6 A7_A8
RV31 40.2_0402_1% FBA_WE#_H L12 L2 B3
<27> FBA_WE#_H WE# CS# VDDQ VDDQ
OPT@
VDDQ
B3
VDDQ
D3 FBx_CMD7 A6_A11
2

D3 F3
VDDQ VDDQ
RV139
VDDQ
F3 <27> FBA_WCK3_N
FBA_WCK3_N D5
WCK01# WCK23# VDDQ
H3 FBx_CMD8 ABI#
C 160_0402_1% FBA_WCK2_N D5 H3 FBA_WCK3 D4 K3 C
<27> FBA_WCK2_N WCK01# WCK23# VDDQ <27> FBA_WCK3 WCK01 WCK23 VDDQ
@
<27> FBA_WCK2
FBA_WCK2 D4
WCK01 WCK23 VDDQ
K3
VDDQ
M3 FBx_CMD9 A12_RFU
M3 FBA_WCK2_N P5 P3
<27> FBA_WCK2_N
1

VDDQ WCK23# WCK01# VDDQ

FBA_CLK1# 1 2 <27> FBA_WCK3_N
FBA_WCK3_N P5
WCK23# WCK01# VDDQ
P3 <27> FBA_WCK2
FBA_WCK2 P4
WCK23 WCK01 VDDQ
T3 FBx_CMD10 A0_A10
RV36 40.2_0402_1% FBA_WCK3 P4 T3 E5
<27> FBA_WCK3 WCK23 WCK01 VDDQ VDDQ
OPT@
VDDQ
E5
VDDQ
N5 FBx_CMD11 A1_A9
N5 +FBA_VREFD_H A10 E10
VDDQ VREFD VDDQ
OPT@ CV175

+FBA_VREFD_H A10 E10 U10 N10 FBx_CMD12 RAS#

0.01U_0402_25V7K

1 VREFD VDDQ VREFD VDDQ

U10 N10 +FBA_VREFC1 J14 B12
VREFD VDDQ VREFC VDDQ
+FBA_VREFC1 J14
VREFC VDDQ
B12
VDDQ
D12 FBx_CMD13 RST#
D12 F12
2 VDDQ VDDQ
VDDQ
F12
VDDQ
H12 FBx_CMD14 CKE#
H12 FBA_RST#_H J2 K12
VDDQ <27> FBA_RST#_H RESET# VDDQ
<27> FBA_RST#_H
FBA_RST#_H J2
RESET# VDDQ
K12
VDDQ
M12 FBx_CMD15 CAS#
M12 P12
VDDQ VDDQ
VDDQ
P12
VDDQ
T12 FBx_CMD16 CS#
T12 G13
VDDQ VDDQ
VDDQ
G13 H1
VSS VDDQ
L13 FBx_CMD17 A3_BA3
H1 L13 K1 B14
+1.5VS_VGA VSS VDDQ VSS VDDQ
K1
VSS VDDQ
B14 B5
VSS VDDQ
D14 FBx_CMD18 A2_BA0
B5 D14 G5 F14
VSS VDDQ VSS VDDQ
G5 F14 L5 M14 FBx_CMD19 A4_BA2
1

VSS VDDQ VSS VDDQ

L5 M14 T5 P14
VSS VDDQ VSS VDDQ
RV143 T5
VSS VDDQ
P14 B10
VSS VDDQ
T14 FBx_CMD20 A5_BA1
549_0402_1% B10 T14 D10
VSS VDDQ VSS
RV214
OPT@ D10
VSS
G10
VSS FBx_CMD21 WE#
G10 L10 A1
2

+FBA_VREFC1 VSS VSS VSSQ

1 2 L10
VSS VSSQ
A1 P10
VSS VSSQ
C1 FBx_CMD22 A7_A8
931_0402_1% 16 mil
820P_0402_25V7

P10 C1 T10 E1
VSS VSSQ VSS VSSQ
1

OPT@ CV59

OPT@ 1 T10
VSS VSSQ
E1 H14
VSS VSSQ
N1 FBx_CMD23 A6_A11
RV144 H14 N1 K14 R1
VSS VSSQ +1.5VS_VGA VSS VSSQ
1.33K_0402_1%
+1.5VS_VGA
K14
VSS VSSQ
R1
VSSQ
U1 FBx_CMD24 ABI#
OPT@ U1 H2
2 VSSQ VSSQ
H2 G1 K2 FBx_CMD25 A12_RFU
2

VSSQ VDD VSSQ

G1 K2 L1 A3
VDD VSSQ VDD VSSQ
L1
VDD VSSQ
A3 G4
VDD VSSQ
C3 FBx_CMD26 A0_A10
G4 C3 L4 E3
VDD VSSQ VDD VSSQ
B L4
VDD VSSQ
E3 C5
VDD VSSQ
N3 FBx_CMD27 A1_A9 B
C5 N3 R5 R3
VDD VSSQ VDD VSSQ
R5
VDD VSSQ
R3 C10
VDD VSSQ
U3 FBx_CMD28 RAS#
C10 U3 R10 C4
VDD VSSQ VDD VSSQ
+1.5VS_VGA
R10
VDD VSSQ
C4 D11
VDD VSSQ
R4 FBx_CMD29 RST#
D11 R4 G11 F5
VDD VSSQ VDD VSSQ
G11
VDD VSSQ
F5 L11
VDD VSSQ
M5 FBx_CMD30 CKE#
L11 M5 P11 F10
VDD VSSQ VDD VSSQ
1

P11
VDD VSSQ
F10 G14
VDD VSSQ
M10 FBx_CMD31 CAS#
RV145 G14 M10 L14 C11
549_0402_1% VDD VSSQ VDD VSSQ
L14 C11 R11
OPT@ VDD VSSQ VSSQ
RV215 R11 A12
VSSQ VSSQ
A12 C12
2

+FBA_VREFD_H VSSQ VSSQ

1 2 C12 E12
931_0402_1% VSSQ VSSQ
820P_0402_25V7

E12 N12
1

VSSQ VSSQ
OPT@ CV60

OPT@ 1 N12 R12

RV146 VSSQ 170-BALL VSSQ
R12 U12
VSSQ VSSQ
1

D 1.33K_0402_1% 170-BALL U12 H13

OPT@ OPT@ VSSQ SGRAM GDDR5 VSSQ
2 H13 K13
<23,28,30,31> MEM_VREF G 2 SGRAM GDDR5 VSSQ VSSQ
K13 A14
2

QV11 VSSQ VSSQ

S A14 C14
3

2N7002W-T/R7_SOT323-3 VSSQ VSSQ

C14 E14
VSSQ VSSQ
E14 N14
VSSQ VSSQ
N14 R14
VSSQ VSSQ
R14 U14
VSSQ VSSQ
U14
VSSQ X76@
X76@
+1.5VS_VGA UV5 SIDE H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
+1.5VS_VGA UV6 SIDE
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
OPT@ CV84

OPT@ CV81

OPT@ CV82

OPT@ CV83
OPT@ CV179

OPT@ CV138

OPT@ CV142

OPT@ CV137

2 1 1 1 1 1 1 1
1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6
10U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
OPT@ CV187

OPT@ CV87

OPT@ CV88

OPT@ CV85

OPT@ CV86

OPT@ CV145

OPT@ CV143

OPT@ CV144
2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2
A A
1 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-VRAM A Upper
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 29 of 64
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits

UV7 UV8

MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 FBC_D0 A4 FBC_D24
FBC_EDC0 DQ24 DQ0 FBC_D1 FBC_EDC3 DQ24 DQ0 FBC_D25
C2 A2 C2 A2
EDC0 EDC3 DQ25 DQ1 FBC_D2 EDC0 EDC3 DQ25 DQ1 FBC_D26
C13 B4 C13 B4
FBC_EDC2 EDC1 EDC2 DQ26 DQ2 FBC_D3 FBC_EDC1 EDC1 EDC2 DQ26 DQ2 FBC_D27
<27> FBC_D[0..31] R13
EDC2 EDC1 DQ27 DQ3
B2 BYTE0 R13
EDC2 EDC1 DQ27 DQ3
B2
R2 E4 FBC_D4 R2 E4 FBC_D28 BYTE3
EDC3 EDC0 DQ28 DQ4 FBC_D5 EDC3 EDC0 DQ28 DQ4 FBC_D29
E2 E2
DQ29 DQ5 FBC_D6 DQ29 DQ5 FBC_D30
<27> FBC_EDC[3..0] F4 F4
FBC_DBI0# DQ30 DQ6 FBC_D7 FBC_DBI3# DQ30 DQ6 FBC_D31
D <27> FBC_DBI0# D2 F2 <27> FBC_DBI3# D2 F2 D
DBI0# DBI3# DQ31 DQ7 DBI0# DBI3# DQ31 DQ7
D13 A11 D13 A11
FBC_DBI2# DBI1# DBI2# DQ16 DQ8 FBC_DBI1# DBI1# DBI2# DQ16 DQ8
<27> FBC_DBI2# P13 A13 <27> FBC_DBI1# P13 A13
DBI2# DBI1# DQ17 DQ9 DBI2# DBI1# DQ17 DQ9
P2 B11 P2 B11
DBI3# DBI0# DQ18 DQ10 DBI3# DBI0# DQ18 DQ10
B13 B13
FBC_CLK0 DQ19 DQ11 FBC_CLK0 DQ19 DQ11
<27> FBC_CLK0 J12 E11 <27> FBC_CLK0 J12 E11
FBC_CLK0# CK DQ20 DQ12 FBC_CLK0# CK DQ20 DQ12
<27> FBC_CLK0#
<27> FBC_CKE_L
FBC_CKE_L
J11
J3
CK#
CKE#
DQ21
DQ22
DQ13
DQ14
E13
F11
<27> FBC_CLK0#
<27> FBC_CKE_L
FBC_CKE_L
J11
J3
CK#
CKE#
DQ21
DQ22
DQ13
DQ14
E13
F11 GDDR5
F13 F13

FBC_MA2_BA0_L
DQ23
DQ8
DQ15
DQ16
U11 FBC_D16
FBC_D17 FBC_MA4_BA2_L
DQ23
DQ8
DQ15
DQ16
U11 FBC_D8
FBC_D9
Mode H - Mirror Mode Mapping
<27> FBC_MA2_BA0_L H11 U13 <27> FBC_MA4_BA2_L H11 U13
FBC_MA5_BA1_L BA0/A2 BA2/A4 DQ9 DQ17 FBC_D18 FBC_MA3_BA3_L BA0/A2 BA2/A4 DQ9 DQ17 FBC_D10
<27> FBC_MA5_BA1_L K10 T11 <27> FBC_MA3_BA3_L K10 T11
FBC_MA4_BA2_L BA1/A5 BA3/A3 DQ10 DQ18 FBC_D19 FBC_MA2_BA0_L BA1/A5 BA3/A3 DQ10 DQ18 FBC_D11
<27> FBC_MA4_BA2_L K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 <27> FBC_MA2_BA0_L K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 BYTE1 DATA Bus
FBC_MA3_BA3_L H10 N11 FBC_D20 BYTE2 FBC_MA5_BA1_L H10 N11 FBC_D12
<27> FBC_MA3_BA3_L BA3/A3 BA1/A5 DQ12 DQ20 FBC_D21 <27> FBC_MA5_BA1_L BA3/A3 BA1/A5 DQ12 DQ20 FBC_D13
DQ13 DQ21
N13
DQ13 DQ21
N13 Address 0..31 32..63
M11 FBC_D22 M11 FBC_D14
FBC_MA7_MA8_L DQ14 DQ22 FBC_D23 FBC_MA0_MA10_L DQ14 DQ22 FBC_D15
<27> FBC_MA7_MA8_L K4
A8/A7 A10/A0 DQ15 DQ23
M13 <27> FBC_MA0_MA10_L K4
A8/A7 A10/A0 DQ15 DQ23
M13 FBx_CMD0 CS#
FBC_MA1_MA9_L H5 U4 FBC_MA6_MA11_L H5 U4
<27> FBC_MA1_MA9_L FBC_MA0_MA10_L A9/A1 A11/A6 DQ0 DQ24 <27> FBC_MA6_MA11_L FBC_MA7_MA8_L A9/A1 A11/A6 DQ0 DQ24
<27> FBC_MA0_MA10_L H4
A10/A0 A8/A7 DQ1 DQ25
U2 <27> FBC_MA7_MA8_L H4
A10/A0 A8/A7 DQ1 DQ25
U2 FBx_CMD1 A3_BA3
FBC_MA6_MA11_L K5 T4 FBC_MA1_MA9_L K5 T4
<27> FBC_MA6_MA11_L FBC_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26 <27> FBC_MA1_MA9_L FBC_MA12_RFU_L A11/A6 A9/A1 DQ2 DQ26
<27> FBC_MA12_RFU_L J5
A12/RFU/NC DQ3 DQ27
T2 <27> FBC_MA12_RFU_L J5
A12/RFU/NC DQ3 DQ27
T2 FBx_CMD2 A2_BA0
N4 N4
DQ4 DQ28 DQ4 DQ28
A5
VPP/NC DQ5 DQ29
N2
+1.5VS_VGA
A5
VPP/NC DQ5 DQ29
N2 FBx_CMD3 A4_BA2
U5 M4 U5 M4
VPP/NC DQ6 DQ30 VPP/NC DQ6 DQ30
2 RV147 1
DQ7 DQ31
M2 2 RV148 1
DQ7 DQ31
M2 FBx_CMD4 A5_BA1
OPT@ 1K_0402_1% OPT@ 1K_0402_1%
J1 +1.5VS_VGA J1 +1.5VS_VGA FBx_CMD5 WE#
MF MF
2 RV149 1 J10 2 RV150 1 J10
SEN SEN
2 RV151 1 OPT@ 1K_0402_1% J13
ZQ VDDQ
B1 2 RV152 1 OPT@ 1K_0402_1% J13
ZQ VDDQ
B1 FBx_CMD6 A7_A8
OPT@ 121_0402_1% D1 OPT@ 121_0402_1% D1
VDDQ VDDQ
VDDQ
F1
VDDQ
F1 FBx_CMD7 A6_A11
Follow DG FBC_ABI#_L J4 M1 FBC_ABI#_L J4 M1
<27> FBC_ABI#_L FBC_RAS#_L ABI# VDDQ <27> FBC_ABI#_L FBC_CAS#_L ABI# VDDQ
<27> FBC_RAS#_L G3
RAS# CAS# VDDQ
P1 <27> FBC_CAS#_L G3
RAS# CAS# VDDQ
P1 FBx_CMD8 ABI#
FBC_CS#_L G12 T1 FBC_WE#_L G12 T1
FBC_CLK0 <27> FBC_CS#_L FBC_CAS#_L CS# WE# VDDQ <27> FBC_WE#_L FBC_RAS#_L CS# WE# VDDQ
1 2 <27> FBC_CAS#_L L3
CAS# RAS# VDDQ
G2 <27> FBC_RAS#_L L3
CAS# RAS# VDDQ
G2 FBx_CMD9 A12_RFU
RV37 40.2_0402_1% FBC_WE#_L L12 L2 FBC_CS#_L L12 L2
<27> FBC_WE#_L WE# CS# VDDQ <27> FBC_CS#_L WE# CS# VDDQ
OPT@
VDDQ
B3
VDDQ
B3 FBx_CMD10 A0_A10
2

C D3 D3 C
VDDQ VDDQ
RV155
VDDQ
F3
VDDQ
F3 FBx_CMD11 A1_A9
160_0402_1% FBC_WCK0_N D5 H3 FBC_WCK1_N D5 H3
<27> FBC_WCK0_N FBC_WCK0 WCK01# WCK23# VDDQ <27> FBC_WCK1_N FBC_WCK1 WCK01# WCK23# VDDQ
@
<27> FBC_WCK0 D4
WCK01 WCK23 VDDQ
K3 <27> FBC_WCK1 D4
WCK01 WCK23 VDDQ
K3 FBx_CMD12 RAS#
M3 M3
1

FBC_CLK0# FBC_WCK1_N VDDQ FBC_WCK0_N VDDQ

1 2 <27> FBC_WCK1_N P5
WCK23# WCK01# VDDQ
P3 <27> FBC_WCK0_N P5
WCK23# WCK01# VDDQ
P3 FBx_CMD13 RST#
RV39 40.2_0402_1% FBC_WCK1 P4 T3 FBC_WCK0 P4 T3
<27> FBC_WCK1 WCK23 WCK01 VDDQ <27> FBC_WCK0 WCK23 WCK01 VDDQ
OPT@
VDDQ
E5
VDDQ
E5 FBx_CMD14 CKE#
N5 N5
VDDQ VDDQ
OPT@ CV195
0.01U_0402_25V7K

1 +FBC_VREFD_L A10 E10 +FBC_VREFD_L A10 E10 FBx_CMD15 CAS#

VREFD VDDQ VREFD VDDQ
U10 N10 U10 N10
+FBC_VREFC0 VREFD VDDQ +FBC_VREFC0 VREFD VDDQ
J14
VREFC VDDQ
B12 J14
VREFC VDDQ
B12 FBx_CMD16 CS#
D12 D12
2 VDDQ VDDQ
VDDQ
F12
VDDQ
F12 FBx_CMD17 A3_BA3
H12 H12
FBC_RST#_L VDDQ FBC_RST#_L VDDQ
<27> FBC_RST#_L J2
RESET# VDDQ
K12 <27> FBC_RST#_L J2
RESET# VDDQ
K12 FBx_CMD18 A2_BA0
M12 M12
VDDQ VDDQ
VDDQ
P12
VDDQ
P12 FBx_CMD19 A4_BA2
T12 T12
+1.5VS_VGA VDDQ VDDQ
VDDQ
G13
VDDQ
G13 FBx_CMD20 A5_BA1
H1 L13 H1 L13
VSS VDDQ VSS VDDQ
K1
VSS VDDQ
B14 K1
VSS VDDQ
B14 FBx_CMD21 WE#
1

B5 D14 B5 D14
VSS VDDQ VSS VDDQ
RV159 G5
VSS VDDQ
F14 G5
VSS VDDQ
F14 FBx_CMD22 A7_A8
549_0402_1% L5 M14 L5 M14
VSS VDDQ VSS VDDQ
RV216
OPT@ T5
VSS VDDQ
P14 T5
VSS VDDQ
P14 FBx_CMD23 A6_A11
B10 T14 B10 T14
2

+FBC_VREFC0 VSS VDDQ VSS VDDQ

1 2 D10
VSS
D10
VSS FBx_CMD24 ABI#
820P_0402_25V7

931_0402_1% G10 G10

VSS VSS
1

OPT@ CV61

OPT@ 1 L10
VSS VSSQ
A1 L10
VSS VSSQ
A1 FBx_CMD25 A12_RFU
RV160 P10 C1 P10 C1
VSS VSSQ VSS VSSQ
1.33K_0402_1% T10
VSS VSSQ
E1 T10
VSS VSSQ
E1 FBx_CMD26 A0_A10
OPT@ H14 N1 H14 N1
2 VSS VSSQ VSS VSSQ
K14 R1 K14 R1 FBx_CMD27 A1_A9
2

+1.5VS_VGA VSS VSSQ +1.5VS_VGA VSS VSSQ

U1 U1
VSSQ VSSQ
VSSQ
H2
VSSQ
H2 FBx_CMD28 RAS#
G1 K2 G1 K2
VDD VSSQ VDD VSSQ
B L1
VDD VSSQ
A3 L1
VDD VSSQ
A3 FBx_CMD29 RST# B
G4 C3 G4 C3
VDD VSSQ VDD VSSQ
L4
VDD VSSQ
E3 L4
VDD VSSQ
E3 FBx_CMD30 CKE#
C5 N3 C5 N3
VDD VSSQ VDD VSSQ
+1.5VS_VGA
R5
VDD VSSQ
R3 R5
VDD VSSQ
R3 FBx_CMD31 CAS#
C10 U3 C10 U3
VDD VSSQ VDD VSSQ
R10 C4 R10 C4
VDD VSSQ VDD VSSQ
D11 R4 D11 R4
VDD VSSQ VDD VSSQ
1

G11 F5 G11 F5
RV161 VDD VSSQ VDD VSSQ
L11 M5 L11 M5
549_0402_1% VDD VSSQ VDD VSSQ
P11 F10 P11 F10
OPT@ VDD VSSQ VDD VSSQ
RV217 G14 M10 G14 M10
VDD VSSQ VDD VSSQ
L14 C11 L14 C11
2

+FBC_VREFD_L VDD VSSQ VDD VSSQ

1 2 R11 R11
VSSQ VSSQ
820P_0402_25V7

931_0402_1% A12 A12

VSSQ VSSQ
1

OPT@ CV62

OPT@ 1 C12 C12

RV162 VSSQ VSSQ
E12 E12
1.33K_0402_1% VSSQ VSSQ
N12 N12
OPT@ VSSQ VSSQ
R12 R12
VSSQ VSSQ
1

D 2 170-BALL 170-BALL
U12 U12
2

OPT@ VSSQ VSSQ

2 H13 H13
<23,28,29,31> MEM_VREF G SGRAM GDDR5 VSSQ SGRAM GDDR5 VSSQ
K13 K13
QV13 VSSQ VSSQ
S A14 A14
3

2N7002W-T/R7_SOT323-3 VSSQ VSSQ

C14 C14
VSSQ VSSQ
E14 E14
VSSQ VSSQ
N14 N14
VSSQ VSSQ
R14 R14
VSSQ +1.5VS_VGA VSSQ
VSSQ
U14 UV8 SIDE VSSQ
U14

X76@ X76@
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
+1.5VS_VGA UV7 SIDE
OPT@ CV207

OPT@ CV95

OPT@ CV96

OPT@ CV93

OPT@ CV94

OPT@ CV163

OPT@ CV161

OPT@ CV162
H5GQ1H24AFR-T2L_BGA170 2 1 1 1 1 1 1 1 H5GQ1H24AFR-T2L_BGA170
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
OPT@ CV199

OPT@ CV91

OPT@ CV92

OPT@ CV89

OPT@ CV90

OPT@ CV160

OPT@ CV157

OPT@ CV159

2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2

A A
1 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-VRAM C Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 30 of 64
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits

UV9

MF=0 MF=1 MF=1 MF=0 UV10

A4 FBC_D32 MF=0 MF=1 MF=1 MF=0

FBC_EDC4 DQ24 DQ0 FBC_D33
C2 A2
EDC0 EDC3 DQ25 DQ1 FBC_D34 FBC_D56
C13 B4 A4
FBC_EDC6 EDC1 EDC2 DQ26 DQ2 FBC_D35 FBC_EDC7 DQ24 DQ0 FBC_D57
<27> FBC_D[63..32] R13
EDC2 EDC1 DQ27 DQ3
B2 BYTE4 C2
EDC0 EDC3 DQ25 DQ1
A2
R2 E4 FBC_D36 C13 B4 FBC_D58
EDC3 EDC0 DQ28 DQ4 FBC_D37 FBC_EDC5 EDC1 EDC2 DQ26 DQ2 FBC_D59
E2 R13 B2
DQ29 DQ5 FBC_D38 EDC2 EDC1 DQ27 DQ3 FBC_D60
<27> FBC_EDC[7..4] DQ30 DQ6
F4 R2
EDC3 EDC0 DQ28 DQ4
E4 BYTE7
FBC_DBI4# D2 F2 FBC_D39 E2 FBC_D61
<27> FBC_DBI4# DBI0# DBI3# DQ31 DQ7 DQ29 DQ5 FBC_D62
D D13 A11 F4 D
FBC_DBI6# DBI1# DBI2# DQ16 DQ8 FBC_DBI7# DQ30 DQ6 FBC_D63
<27> FBC_DBI6# P13
P2
DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
A13
B11
<27> FBC_DBI7# D2
D13
DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
F2
A11 GDDR5
B13 FBC_DBI5# P13 A13
<27> FBC_CLK1
FBC_CLK1
FBC_CLK1#
J12
CK
DQ19
DQ20
DQ11
DQ12
E11
<27> FBC_DBI5#
P2
DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
B11 Mode H - Mirror Mode Mapping
<27> FBC_CLK1# J11 E13 B13
FBC_CKE_H CK# DQ21 DQ13 FBC_CLK1 DQ19 DQ11
<27> FBC_CKE_H J3 F11 <27> FBC_CLK1 J12 E11
CKE# DQ22 DQ14 FBC_CLK1# CK DQ20 DQ12
DQ23 DQ15
F13 <27> FBC_CLK1# J11
CK# DQ21 DQ13
E13 DATA Bus
U11 FBC_D48 FBC_CKE_H J3 F11
FBC_MA2_BA0_H DQ8 DQ16 FBC_D49 <27> FBC_CKE_H CKE# DQ22 DQ14
<27> FBC_MA2_BA0_H H11
BA0/A2 BA2/A4 DQ9 DQ17
U13
DQ23 DQ15
F13 Address 0..31 32..63
FBC_MA5_BA1_H K10 T11 FBC_D50 U11 FBC_D40
<27> FBC_MA5_BA1_H FBC_MA4_BA2_H BA1/A5 BA3/A3 DQ10 DQ18 FBC_D51 FBC_MA4_BA2_H DQ8 DQ16 FBC_D41
<27> FBC_MA4_BA2_H K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 <27> FBC_MA4_BA2_H H11
BA0/A2 BA2/A4 DQ9 DQ17
U13 FBx_CMD0 CS#
FBC_MA3_BA3_H H10 N11 FBC_D52 BYTE6 FBC_MA3_BA3_H K10 T11 FBC_D42
<27> FBC_MA3_BA3_H BA3/A3 BA1/A5 DQ12 DQ20 FBC_D53 <27> FBC_MA3_BA3_H FBC_MA2_BA0_H BA1/A5 BA3/A3 DQ10 DQ18 FBC_D43
DQ13 DQ21
N13 <27> FBC_MA2_BA0_H K11
BA2/A4 BA0/A2 DQ11 DQ19
T13 BYTE5 FBx_CMD1 A3_BA3
M11 FBC_D54 FBC_MA5_BA1_H H10 N11 FBC_D44
FBC_MA7_MA8_H DQ14 DQ22 FBC_D55 <27> FBC_MA5_BA1_H BA3/A3 BA1/A5 DQ12 DQ20 FBC_D45
<27> FBC_MA7_MA8_H K4
A8/A7 A10/A0 DQ15 DQ23
M13
DQ13 DQ21
N13 FBx_CMD2 A2_BA0
FBC_MA1_MA9_H H5 U4 M11 FBC_D46
<27> FBC_MA1_MA9_H FBC_MA0_MA10_H A9/A1 A11/A6 DQ0 DQ24 FBC_MA0_MA10_H DQ14 DQ22 FBC_D47
<27> FBC_MA0_MA10_H H4
A10/A0 A8/A7 DQ1 DQ25
U2 <27> FBC_MA0_MA10_H K4
A8/A7 A10/A0 DQ15 DQ23
M13 FBx_CMD3 A4_BA2
FBC_MA6_MA11_H K5 T4 FBC_MA6_MA11_H H5 U4
<27> FBC_MA6_MA11_H FBC_MA12_RFU_H A11/A6 A9/A1 DQ2 DQ26 <27> FBC_MA6_MA11_H FBC_MA7_MA8_H A9/A1 A11/A6 DQ0 DQ24
<27> FBC_MA12_RFU_H J5
A12/RFU/NC DQ3 DQ27
T2 <27> FBC_MA7_MA8_H H4
A10/A0 A8/A7 DQ1 DQ25
U2 FBx_CMD4 A5_BA1
N4 FBC_MA1_MA9_H K5 T4
DQ4 DQ28 <27> FBC_MA1_MA9_H FBC_MA12_RFU_H A11/A6 A9/A1 DQ2 DQ26
A5
VPP/NC DQ5 DQ29
N2 <27> FBC_MA12_RFU_H J5
A12/RFU/NC DQ3 DQ27
T2 FBx_CMD5 WE#
U5 M4 N4
VPP/NC DQ6 DQ30 DQ4 DQ28
2 RV163 1
DQ7 DQ31
M2
+1.5VS_VGA
A5
VPP/NC DQ5 DQ29
N2 FBx_CMD6 A7_A8
OPT@ 1K_0402_1% U5 M4
+1.5VS_VGA VPP/NC DQ6 DQ30
J1
MF
2 RV164 1
DQ7 DQ31
M2 FBx_CMD7 A6_A11
2 RV165 1 J10 OPT@ 1K_0402_1%
SEN +1.5VS_VGA
2 RV167 1 OPT@ 1K_0402_1% J13
ZQ VDDQ
B1 J1
MF FBx_CMD8 ABI#
OPT@ 121_0402_1% D1 2 RV166 1 J10
VDDQ SEN
VDDQ
F1 2 RV168 1 OPT@ 1K_0402_1% J13
ZQ VDDQ
B1 FBx_CMD9 A12_RFU
Follow DG FBC_ABI#_H J4 M1 OPT@ 121_0402_1% D1
<27> FBC_ABI#_H FBC_RAS#_H ABI# VDDQ VDDQ
<27> FBC_RAS#_H G3
RAS# CAS# VDDQ
P1
VDDQ
F1 FBx_CMD10 A0_A10
FBC_CS#_H G12 T1 FBC_ABI#_H J4 M1
FBC_CLK1 <27> FBC_CS#_H FBC_CAS#_H CS# WE# VDDQ <27> FBC_ABI#_H FBC_CAS#_H ABI# VDDQ
1 2 <27> FBC_CAS#_H L3
CAS# RAS# VDDQ
G2 <27> FBC_CAS#_H G3
RAS# CAS# VDDQ
P1 FBx_CMD11 A1_A9
RV41 40.2_0402_1% FBC_WE#_H L12 L2 FBC_WE#_H G12 T1
<27> FBC_WE#_H WE# CS# VDDQ <27> FBC_WE#_H FBC_RAS#_H CS# WE# VDDQ
OPT@
VDDQ
B3 <27> FBC_RAS#_H L3
CAS# RAS# VDDQ
G2 FBx_CMD12 RAS#
2

D3 FBC_CS#_H L12 L2
VDDQ <27> FBC_CS#_H WE# CS# VDDQ
C RV171
VDDQ
F3
VDDQ
B3 FBx_CMD13 RST# C
160_0402_1% FBC_WCK2_N D5 H3 D3
<27> FBC_WCK2_N FBC_WCK2 WCK01# WCK23# VDDQ VDDQ
@
<27> FBC_WCK2 D4
WCK01 WCK23 VDDQ
K3
VDDQ
F3 FBx_CMD14 CKE#
M3 FBC_WCK3_N D5 H3
1

FBC_CLK1# FBC_WCK3_N VDDQ <27> FBC_WCK3_N FBC_WCK3 WCK01# WCK23# VDDQ

1 2 <27> FBC_WCK3_N P5
WCK23# WCK01# VDDQ
P3 <27> FBC_WCK3 D4
WCK01 WCK23 VDDQ
K3 FBx_CMD15 CAS#
RV48 40.2_0402_1% FBC_WCK3 P4 T3 M3
<27> FBC_WCK3 WCK23 WCK01 VDDQ FBC_WCK2_N VDDQ
OPT@
VDDQ
E5 <27> FBC_WCK2_N P5
WCK23# WCK01# VDDQ
P3 FBx_CMD16 CS#
N5 FBC_WCK2 P4 T3
VDDQ <27> FBC_WCK2 WCK23 WCK01 VDDQ
OPT@ CV215
0.01U_0402_25V7K

1 +FBC_VREFD_H A10 E10 E5 FBx_CMD17 A3_BA3

VREFD VDDQ VDDQ
U10 N10 N5
+FBC_VREFC1 VREFD VDDQ +FBC_VREFD_H VDDQ
J14
VREFC VDDQ
B12 A10
VREFD VDDQ
E10 FBx_CMD18 A2_BA0
D12 U10 N10
2 VDDQ +FBC_VREFC1 VREFD VDDQ
VDDQ
F12 J14
VREFC VDDQ
B12 FBx_CMD19 A4_BA2
H12 D12
FBC_RST#_H VDDQ VDDQ
<27> FBC_RST#_H J2
RESET# VDDQ
K12
VDDQ
F12 FBx_CMD20 A5_BA1
M12 H12
VDDQ FBC_RST#_H VDDQ
VDDQ
P12 <27> FBC_RST#_H J2
RESET# VDDQ
K12 FBx_CMD21 WE#
T12 M12
+1.5VS_VGA VDDQ VDDQ
VDDQ
G13
VDDQ
P12 FBx_CMD22 A7_A8
H1 L13 T12
VSS VDDQ VDDQ
K1
VSS VDDQ
B14
VDDQ
G13 FBx_CMD23 A6_A11
1

B5 D14 H1 L13
VSS VDDQ VSS VDDQ
RV175 G5
VSS VDDQ
F14 K1
VSS VDDQ
B14 FBx_CMD24 ABI#
549_0402_1% L5 M14 B5 D14
VSS VDDQ VSS VDDQ
RV218
OPT@ T5
VSS VDDQ
P14 G5
VSS VDDQ
F14 FBx_CMD25 A12_RFU
B10 T14 L5 M14
2

+FBC_VREFC1 VSS VDDQ VSS VDDQ

1 2 D10
VSS
T5
VSS VDDQ
P14 FBx_CMD26 A0_A10
820P_0402_25V7

931_0402_1% G10 B10 T14

VSS VSS VDDQ
1

OPT@ CV63

OPT@ 1 L10
VSS VSSQ
A1 D10
VSS FBx_CMD27 A1_A9
RV176 P10 C1 G10
VSS VSSQ VSS
1.33K_0402_1% T10
VSS VSSQ
E1 L10
VSS VSSQ
A1 FBx_CMD28 RAS#
OPT@ H14 N1 P10 C1
2 VSS VSSQ VSS VSSQ
K14 R1 T10 E1 FBx_CMD29 RST#
2

+1.5VS_VGA VSS VSSQ VSS VSSQ

U1 H14 N1
VSSQ VSS VSSQ
VSSQ
H2
+1.5VS_VGA
K14
VSS VSSQ
R1 FBx_CMD30 CKE#
G1 K2 U1
VDD VSSQ VSSQ
L1
VDD VSSQ
A3
VSSQ
H2 FBx_CMD31 CAS#
B G4 C3 G1 K2 B
VDD VSSQ VDD VSSQ
L4 E3 L1 A3
VDD VSSQ VDD VSSQ
C5 N3 G4 C3
+1.5VS_VGA VDD VSSQ VDD VSSQ
R5 R3 L4 E3
VDD VSSQ VDD VSSQ
C10 U3 C5 N3
VDD VSSQ VDD VSSQ
R10 C4 R5 R3
VDD VSSQ VDD VSSQ
1

D11 R4 C10 U3
RV177 VDD VSSQ VDD VSSQ
G11 F5 R10 C4
549_0402_1% VDD VSSQ VDD VSSQ
L11 M5 D11 R4
OPT@ VDD VSSQ VDD VSSQ
RV219 P11 F10 G11 F5
VDD VSSQ VDD VSSQ
G14 M10 L11 M5
2

+FBC_VREFD_H VDD VSSQ VDD VSSQ

1 2 L14 C11 P11 F10
VDD VSSQ VDD VSSQ
820P_0402_25V7

931_0402_1% R11 G14 M10

VSSQ VDD VSSQ
1

OPT@ CV64

OPT@ 1 A12 L14 C11

RV178 VSSQ VDD VSSQ
C12 R11
1.33K_0402_1% VSSQ VSSQ
E12 A12
OPT@ VSSQ VSSQ
N12 C12
VSSQ VSSQ
1

D 2 R12 E12
2

OPT@ 170-BALL VSSQ VSSQ

2 U12 N12
<23,28,29,30> MEM_VREF G VSSQ VSSQ
H13 R12
QV15 SGRAM GDDR5 VSSQ 170-BALL VSSQ
S K13 U12
3

2N7002W-T/R7_SOT323-3 VSSQ VSSQ

A14 H13
VSSQ SGRAM GDDR5 VSSQ
C14 K13
VSSQ VSSQ
E14 A14
VSSQ VSSQ
N14 C14
VSSQ VSSQ
R14 E14
VSSQ VSSQ
U14 N14
VSSQ +1.5VS_VGA VSSQ
UV10 SIDE VSSQ
R14
X76@ U14
+1.5VS_VGA VSSQ
UV9 SIDE
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
H5GQ1H24AFR-T2L_BGA170 X76@
OPT@ CV227

OPT@ CV103

OPT@ CV104

OPT@ CV101

OPT@ CV102

OPT@ CV170

OPT@ CV168

OPT@ CV169
2 1 1 1 1 1 1 1
10U_0603_6.3V6M

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

1U_0603_25V6

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

H5GQ1H24AFR-T2L_BGA170
OPT@ CV245

OPT@ CV99

OPT@ CV100

OPT@ CV97

OPT@ CV98

OPT@ CV167

OPT@ CV164

OPT@ CV165

2 1 1 1 1 1 1 1
1 2 2 2 2 2 2 2

1 2 2 2 2 2 2 2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P-VRAM C Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 31 of 64
5 4 3 2 1
 5 4 3 2 1

+3VS_VGA
Physical Logical Logical Logical Logical
Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
ROM_SCLK +3VS_VGA PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE

2
GL@
RV92 RV93 RV94 RV121 RV122 STRAP0 +3VS_VGA USER[3] USER[2] USER[1] USER[0]
45.3K_0402_1% 34.8K_0402_1% 10K_0402_1% 20K_0402_1% 20K_0402_1%
OPT@ @ @ @ STRAP1 +3VS_VGA 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
D D

1
STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
<24> STRAP0 STRAP0
<24> STRAP1 STRAP1 STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
<24> STRAP2 STRAP2
<24> STRAP3 STRAP3 STRAP4 +3VS_VGA RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
STRAP4
<24> STRAP4 CHANGE_GEN3

Pull-up to
2

2
GTGE@ GT@ GTGE@ Resistor Values Pull-down to Gnd
@ RV95 RV96 RV97 RV124 RV125 +3VS_VGA
45.3K_0402_1% 34.8K_0402_1% 10K_0402_1% 4.99K_0402_1% 45.3K_0402_1% 5K 1000 0000
GTGE@
10K 1001 0001
1

1
15K 1010 0010
RV96 RV97 11/07 Follow NV request change to 45K for GTGE
20K 1011 0011
25K 1100 0100
30K 1101 0101
45.3K_0402_1% 24.9K_0402_1%
GL@ GE@ 35K 1110 0110

+3VS_VGA
45K 1111 0111
C C

3GIO_PADCFG XCLK_417
2

GTGE@
RV98 RV99 RV100 3GIO_PADCFG[3:0] 0 277MHz (Default)
4.99K_0402_1% 10K_0402_1% 4.99K_0402_1%
@ GTGE@
0110 Notebook Default 1 Reserved
1

<24> ROM_SI ROM_SI SLOT_CLK_CFG

<24> ROM_SO ROM_SO
<24> ROM_SCLK ROM_SCLK 0 GPU and MCH don't share a common reference clock
2

1 GPU and MCH share a common reference clock (Default)

2

RV101 GL@
X76 20K_0402_1% RV102 RV103
X76@ 10K_0402_1% 15K_0402_1%
GL@ SMBUS_ALT_ADDR VGA_DEVICE
1

0 0x9E (Default) 0 3D Device (Class Code 302h)

B B
1 0x9C (Multi-GPU usage) 1 VGA Device (Default)

USER Straps
SUB_VENDOR
User[3:0]
0 No VBIOS ROM
1000-1100 Customer defined
1 BIOS ROM is present (Default)
PEX_PLL_EN_TERM
FB_0_BAR_SIZE
0 Disable (Default)
0 Reserved
1 Enable
1 Reserved

2 256MB (Default)
PCIE_MAX_SPEED
0 Limit to PCIE Gen1
3 Reserved
A A
1 PCIE Gen 2/3 Capable

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N13P_MISC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 32 of 64
5 4 3 2 1
 5 4 3 2 1

+LEDVDD
(60 MIL) +LEDVDD CPU_B+

+LCDVDD_CONN 1 R813 2 0_0805_5%

1 1
C523
CMOS JLVDS1 470P_0603_50V8J C524
1 2 4.7U_0805_25V6-K
+CMOS_PW 1 2 2 2
W=40mils <18> USB20_N5 USB20_N5 3 4 W=60mils 9/23 EMI Request
USB20_P5 3 4
<18> USB20_P5 5 5 6 6
7 7 8 8
LVDS_A0# 9 10 +3VS
<17> LVDS_A0# 9 10
LVDS_A0 11 12 +3VS
<17> LVDS_A0 11 12
LVDS_A1# 13 14 DMIC_DATA <41> 1
D <17> LVDS_A1# 13 14 D
LVDS_A1 15 16 @
<17> LVDS_A1 15 16 DMIC_CLK <41>
LVDS_A2# 17 18 680P_0402_50V7K
<17> LVDS_A2# 17 18
LVDS_A2 19 20 C528
<17> LVDS_A2 19 20 2
21 21 22 22
LVDS_ACLK# 23 24 DISPOFF#
<17> LVDS_ACLK# 23 24
LVDS_ACLK 25 26 INVPWM
<17> LVDS_ACLK 25 26
27 28 EDID_DATA_CONN
27 28 EDID_CLK_CONN
<42> ECR_EN 29 29 30 30
USB20_P5 DMIC_DATA
9/18 Remove CE_EN 31 GND GND 32
USB20_N5 DMIC_CLK
ACES_87142-3041-BS

2
PJDLC05_SOT23-3

PJDLC05_SOT23-3
@ D52 D55
2 1 R828 @ @
EC_INVT_PWM <42>
0_0402_5%
INVPWM 2 1 R824
PCH_PWM <17>
0_0402_5%

1
+3VS

R823 R826
2.2K_0402_5%
2.2K_0402_5% ESD request
<17> EDID_CLK EDID_CLK R1199 1 2 0_0402_5% EDID_CLK_CONN

C C

<17> EDID_DATA EDID_DATA R1200 1 2 0_0402_5% EDID_DATA_CONN INVPWM

470P_0402_50V7K

470P_0402_50V7K
DISPOFF#
C525
1 @ 1 @
C527
+3VS

2 2

1
R891 1 2 @
0_0402_5% For EMI
R822
4.7K_0402_5%
D30

2
BKOFF# 1 2 DISPOFF# DMIC_CLK
<42> BKOFF#

100P_0402_50V8J
RB751V-40 SOD-323 1

1
@

C934
@
R890
10K_0402_5% 2

2
For EMI

+LCDVDD R1201 1 0_0402_5%

<17> PCH_ENBKL 2 ENBKL <42>
+5VALW
+3VS
W=60mils

2
1

R816 R817 R827

B 150_0603_1% 100K_0402_5% 100K_0402_1% B
1
C529
4.7U_0805_10V4Z

1
2
1

D R820 220K_0402_5%
S 2
G
2 LCD_ENVDD# 1 2 2
Q67 G
2N7002_SOT23 S 1
D AO3413_SOT23-3
3

1
1

DTC124EK C530 Q68

W=60mils
OUT

0.1U_0402_16V4Z

2
2 +LCDVDD
L15
+LCDVDD_CONN CMOS Camera
<17> PCH_ENVDD IN
1 2 (40 MIL)
GND

Q69 FBMA-L11-201209-221LMA30T_0805 Q94 AO3413_SOT23-3 R432 +CMOS_PW

1

DTC124EKAT146_SC59-3 1 1 (40 MIL) 0_0603_5%

3

D
C531 C532 +3VS 3 1 +CMOS_PW_R 1 2
R821 @ 1 CMOS@ 1
100K_0402_5% 4.7U_0805_10V4Z 0.1U_0402_16V4Z CMOS@ CMOS@ CMOS@
2 2 +3VALW C518 C519

G
2

2
0.1U_0402_16V4Z 10U_0603_6.3V6M
2 2
1
@
C521
0.1U_0402_16V4Z 11/07 Change type to 0603
2

<42> CMOS_ON#
1
R435 CMOS@
150K_0402_5% C520
CMOS@ 0.1U_0402_16V4Z
A 2 A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS/CAMERA
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 33 of 64
5 4 3 2 1
 A B C D E

+5VS +5VS +5VS

3 3 3

1 BLUE 1 GREEN 1 RED

2 2 2 BAT54S-7-F_SOT23-3
@ @ @
D31 D32 D33
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

1
+5VS
D36
+CRT_VCC
CRT Connector
F1
1

2 1 1 2 +CRT_VCC_CONN
1
RB491D_SC59-3
1.1A_6V_SMD1812P110TF C536

FCM1608CF-121T03 0603 W=40mils 2

0.1U_0402_16V4Z

DAC_RED 1 2 RED
<17> DAC_RED
L16
FCM1608CF-121T03 0603
DAC_GRN 1 2 GREEN
<17> DAC_GRN
L17
FCM1608CF-121T03 0603 JCRT1
DAC_BLU 1 2 BLUE 6
<17> DAC_BLU
L18 T75 PAD CRT_TEST 11

1
1 1 1 1 1 1 RED 1
7
R830 R831 R832 C537 C538 C539 C540 C542 C541 CRT_DDC_DAT_CONN 12
150_0402_1% 150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J GREEN 2
2 2 2 2 2 2
8

2
JVGA_HS 13
10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J BLUE 3
CLOSE TO CONN 9
JVGA_VS 14 G 16
4 G 17
10
CRT_DDC_CLK_CONN 15
2 5 2
+CRT_VCC 1
R833
C543 TYCO_1775763-1
1 2 ME@
1 100P_0402_50V8J
2
C544 1K_0402_5%
0.1U_0402_16V4Z
2

1
OE#
P
CRT_HSYNC 2 4 CRT_HSYNC_1 1 2 JVGA_HS
<17> CRT_HSYNC A Y L19

G
FCM1608CF-121T03 0603 U24
SN74AHCT1G125DCKR_SC70-5 1

3
@
D8
C545 @
10P_0402_50V8J JVGA_VS 3 6 JVGA_HS
+CRT_VCC 2 I/O2 I/O4
R834
1 2
1 2 GND VDD 5 +5VS
C546 1K_0402_5%
0.1U_0402_16V4Z
2 CRT_DDC_CLK_CONN CRT_DDC_DAT_CONN
1 I/O1 I/O3 4
5

1
OE#
P
CRT_VSYNC CRT_VSYNC_1 JVGA_VS AZC099-04S.R7G_SOT23-6
<17> CRT_VSYNC 2 4 1 2
3 FCM1608CF-121T03 0603 A Y L20 3
G

U25 1
SN74AHCT1G125DCKR_SC70-5
3

@ C547
+3VS 10P_0402_50V8J
+3VS +CRT_VCC 2
1

R835 R836
2.2K_0402_5% 2.2K_0402_5% R837 R838
5

2.2K_0402_5% 2.2K_0402_5%
2

<17> CRT_DDC_DATA CRT_DDC_DATA 4 3 CRT_DDC_DAT_CONN

DMN66D0LDW -7 2N_SOT363-6
2

Q73B

<17> CRT_DDC_CLK CRT_DDC_CLK 1 6 CRT_DDC_CLK_CONN

1 1
DMN66D0LDW -7 2N_SOT363-6 @ @
Q73A C548 C549
100P_0402_50V8J 68P_0402_50V8K
2 2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 34 of 64
A B C D E
 5 4 3 2 1

L23
HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN 1 2
1 2 C1016 3.3P_0402_50V8C
@
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN 1 2
4 3 C1015 3.3P_0402_50V8C
W CM-2012-900T_4P
HDMI@ @
L24 <17> HDMI_CLK+_CK HDMI_CLK+_CK R865 1 @ 2 0_0402_5% HDMI_CLK+_CONN
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN 1 2 <17> HDMI_CLK-_CK HDMI_CLK-_CK R866 1 @ 2 0_0402_5% HDMI_CLK-_CONN
1 2 C1018 3.3P_0402_50V8C HDMI_TX0+_CK R867 @ 0_0402_5% HDMI_TX0+_CONN
D <17> HDMI_TX0+_CK 1 2 D
@ <17> HDMI_TX0-_CK HDMI_TX0-_CK R868 1 @ 2 0_0402_5% HDMI_TX0-_CONN
HDMI_TX0-_CK 4 HDMI_TX0-_CONN HDMI_TX1+_CK R869 @ 0_0402_5% HDMI_TX1+_CONN
4
HDMI@ 3 3 1
C1017
2
3.3P_0402_50V8C
<17> HDMI_TX1+_CK
HDMI_TX1-_CK R870
1
@
2
0_0402_5% HDMI_TX1-_CONN
<17> HDMI_TX1-_CK 1 2
W CM-2012-900T_4P @ <17> HDMI_TX2+_CK HDMI_TX2+_CK R871 1 @ 2 0_0402_5% HDMI_TX2+_CONN
<17> HDMI_TX2-_CK HDMI_TX2-_CK R872 1 @ 2 0_0402_5% HDMI_TX2-_CONN
L26
HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN 1 2
1 2 C1020 3.3P_0402_50V8C
@
HDMI_TX1-_CK 4 HDMI_TX1-_CONN
4
HDMI@ 3 3 1
C1019
2
3.3P_0402_50V8C
W CM-2012-900T_4P @
L27
HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN 1 2
1 2 C1022 3.3P_0402_50V8C
@
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN 1 2
4
HDMI@ 3 C1021 3.3P_0402_50V8C +3VS
W CM-2012-900T_4P @

2
HDMI@
<17> HDMICLK HDMICLK 1 6 HDMICLK_R

DMN66D0LDW -7 2N_SOT363-6

5
Q80A
C HDMI@ C
RP5 <17> HDMIDAT HDMIDAT 4 3 HDMIDAT_R

HDMI_CLK-_CONN 1 8 DMN66D0LDW -7 2N_SOT363-6

HDMI_CLK+_CONN 2 7 Q80B
HDMI_TX1-_CONN 3 6
HDMI_TX1+_CONN 4 5
+5VS
680_8P4R_5%
HDMI@
RP6

2
HDMI_TX0-_CONN 1 8 +5VS_HDMI_F
HDMI_TX0+_CONN 2 7 HDMI@
HDMI_TX2-_CONN 3 6 D37
HDMI_TX2+_CONN 4 5 RB491D_SC59-3

1
680_8P4R_5%
HDMI@ R857 @
D
1

2
0_0805_5%
+3VS 2 Q114 F2
G 2N7002H 1N_SOT23-3 +5VS 1.1A_6V_SMD1812P110TF
S HDMI@ +3VS
3

1 @ 2 HDMI@

1
3

2
R1142 100K_0402_5%
+5VS_HDMI

2
R859 1 C561
1M_0402_5% 0.1U_0402_16V4Z

2
B HDMI@ @ HDMI@ B

1
2
G
Q85 D38

1
HDMI@ BAT54S-7-F_SOT23-3 R860 R861 2

<17> TMDS_B_HPD 3 1 HDMI_DET_UMA 2.2K_0402_5% 2.2K_0402_5%

HDMI@ HDMI@

1
2N7002_SOT23

2
R864
20K_0402_5%
HDMI@ JHDMI1
19

1
HP_DET
18 +5V
17 DDC/CEC_GND
HDMIDAT_R 16
HDMICLK_R SDA
15 SCL
14 Reserved
13 CEC
HDMI_CLK-_CONN 12 20
CK- G1
11 CK_shield G2 21
HDMIDAT_R HDMI_CLK+_CONN 10 22
HDMICLK_R HDMI_TX0-_CONN CK+ G3
9 D0- G4 23

2
8 D0_shield
D57 HDMI_TX0+_CONN 7
HDMI_TX1-_CONN D0+
PJSOT24C 3P C/A SOT-23 6 D1-
@ 5
HDMI_TX1+_CONN D1_shield
4 D1+
HDMI_TX2-_CONN 3

1
D2-
2 D2_shield
A
HDMI_TX2+_CONN 1 A
D2+
SUYIN_100042GR019M23DZL

ME@

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 35 of 64
5 4 3 2 1
 A B C D E

+3VS +3VS_WLAN

Mini-Express Card for WLAN/WiMAX(Half) 1

J3

1 2
2
Reserve for SW mini-pcie debug card.
1 1
Mini-Express Card for SSD(Full) JUMP_43X79 C563
@
C570 Series resistors closed to KBC side.

@
0.1U_0402_16V4Z 10U_0603_6.3V6M
2 2 LPC_FRAME#_R R873 1 @ 2 0_0402_5% LPC_FRAME#
LPC_FRAME# <14,42>
11/08 Reserve LPC_AD3_R R874 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 <14,42>
LPC_AD2_R R875 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 <14,42>
LPC_AD1_R R876 1 @ 2 0_0402_5% LPC_AD1
+1.5VS LPC_AD1 <14,42>
LPC_AD0_R R878 1 @ 2 0_0402_5% LPC_AD0
LPC_AD0 <14,42>
9/18 JP1 Pin2,24,52 contact to +3VS_WLAN for AOAC function PCI_RST#_R R879 1 @ 2 0_0402_5% PLT_RST#
+1.5VS CLK_PCI_DB CLK_PCI_DB <18>
+3VS_WLAN_AOAC
Mini-Express Card(WLAN/WiMAX)

1
1 1 1 1
R289
0_0603_5% C564 C565
0.1U_0402_16V4Z 0.1U_0402_16V4Z
JP1 2 2

2
<16,19,37> PCIE_WAKE# PCIE_WAKE# 1 2
@ BT_ACTIVE R877 1 WAKE# 3.3V
<44> BT_ACTIVE 2 @ 0_0402_5% 3 4
R892 1 0_0402_5% BT_DISABLE_R NC GND +1.5VS_WLAN
<19,44> PCH_BT_ON# 2 5 6
WLAN_CLKREQ1# NC 1.5V LPC_FRAME#_R
<15> WLAN_CLKREQ1# 7 8
R897 1 0_0402_5% CLKREQ# NC LPC_AD3_R
<19> BT_DISABLE 2 9 10
GND NC LPC_AD2_R
<15> CLK_PCIE_WLAN1# 11 12
REFCLK- NC LPC_AD1_R
<15> CLK_PCIE_WLAN1 13 14
REFCLK+ NC LPC_AD0_R
15 16
PCI_RST#_R GND NC
17 18
CLK_PCI_DB NC GND R880 1 0_0402_5%
19 20 2 PCH_WL_OFF# <18>
NC NC WL_RST#
21 22 2 1 PLT_RST# PLT_RST# <18,23,37,42,46>
GND PERST# R881 1
<15> PCIE_PRX_DTX_N2 23 24 2 @ 0_0402_5% +3VALW 0_0402_5% R1343
PERn0 +3.3Vaux R882 1 0_0402_5%
<15> PCIE_PRX_DTX_P2 25 26 2 +3VS_WLAN_AOAC
PERp0 GND
27 28
GND +1.5V R883 1
29 30 2 @ 0_0402_5% SMB_CLK_S3 <12,13,15>
GND SMB_CLK R884 1
<15> PCIE_PTX_C_DRX_N2 31 32 2 @ 0_0402_5% SMB_DATA_S3 <12,13,15>
PETn0 SMB_DATA
<15> PCIE_PTX_C_DRX_P2 33 34
PETp0 GND
35 36 USB20_N10 <18>
+3VS_WLAN GND USB_D-
37 38 USB20_P10 <18>
NC USB_D+
39 40
NC GND
41 42
NC LED_WWAN#
43 44
100_0402_1% NC LED_WLAN#
45 46
R887 NC LED_WPAN#
47 48
EC_TX NC +1.5V
<42,43> EC_TX 1 2 49 50
EC_RX NC GND +3VS_WLAN +3VS_WLAN_AOAC
<42,43> EC_RX 1 2 51 52
R888 NC +3.3V
100_0402_1% 53 54
GND GND R267 2 1 0_0603_5%

TAITW_PFPET0-AFGLBG1ZZ4N0

2
For EC to detect +3VALW
R889
2
debug card insert. 100K_0402_5%
ME@
Q104 AO3413_SOT23-3 2

D
3 1 1

1
AOAC@
AOAC@ C533
0.1U_0402_16V4Z

G
2
2
<42> AOAC_ON#
1
R436 AOAC@
150K_0402_5% C526
AOAC@ 0.1U_0402_16V4Z
2

9/18 Increase for Intel AOAC function

Mini-Express Card(SSD) SSD Active:4.5W(1.5A)
+3VS_SSD +3VS +3VS_SSD
J5
0.1U_0402_16V4Z 10U_0603_6.3V6M
1 2
1 2
1 1 1 1
@
C566 C567 C568 C569 JUMP_43X79
@
2 2 2 2 JP3
1 2
0.01U_0402_25V7K 10U_0603_6.3V6M WAKE# 3.3V
3 4
NC GND
11/07 Change type to 0603 5
NC 1.5V
6
7 8
CLKREQ# NC
9 10
GND NC
11 12
REFCLK- NC
13 14
REFCLK+ NC
15 16
3 GND NC 3
17 18
NC GND
19 20
0.01U_0402_16V7K NC NC
21 22
SATA_DTX_C_IRX_P0 2 GND PERST#
1 C572 SATA_DTX_IRX_P0 23 24
<14> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_N0 2 PERn0 +3.3Vaux
1 C573 SATA_DTX_IRX_N0 25 26
<14> SATA_DTX_C_IRX_N0 PERp0 GND
27 28
0.01U_0402_16V7K GND +1.5V
29 30
SATA_ITX_DRX_N0 GND SMB_CLK
<14> SATA_ITX_DRX_N0 31 32
SATA_ITX_DRX_P0 PETn0 SMB_DATA
<14> SATA_ITX_DRX_P0 33 34
PETp0 GND
35 36
GND USB_D-
37 38
+3VS_SSD NC USB_D+
39 40
NC GND
41 42
NC LED_WWAN#
43 44
NC LED_WLAN#
45 46
100_0402_1% NC LED_WPAN#
47 48
EC_TX R893 1 NC +1.5V
<42,43> EC_TX 2 @ 49 50
EC_RX NC GND
<42,43> EC_RX 1 2 @ 51 52
NC +3.3V
R894
100_0402_1% 53 54
GND GND

TAITW_PFPET0-AFGLBG1ZZ4N0
SATA_DET#
<14> SATA_DET#
ME@
For SSD use:

4 4

Security Classification
2011/07/21
Compal Secret Data
2012/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 36 of 64
A B C D E
 5 4 3 2 1

+LX
LX Voltage Configure
+3VALW +3V_LAN
<Pin 40>

@
Close together
J18 +1.7V
+1.7_VDDCT AR8151 R1356,C955
R1356 8151@ 0_0402_5% L74
<VDDCT>
1 1 2 2
1 2 +LX_R 1 2 +LX +1.1V

1000P_0402_50V7K

10U_0603_6.3V6M
4.7UH_SIA4012-4R7M_20% AR8161 R1357,R1372,L76

0.1U_0402_16V4Z
JUMP_43X79 <DVDDL,AVDDL>

@ C935

C936

C937
R1357 8161@ 0_0402_5% 1 1
AO3413_SOT23 +1.1_DVDDL 1 2
Note: Place Close to LAN chip L75 L76

D
3 1 L39 DCR< 0.15 ohm
2 2 FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
D Rate current > 1A +1.1_AVDDL_L 1 2 +1.1_AVDDL 1 2 +1.1_DVDDL D
R145
Q150

0.1U_0402_16V4Z

1U_0402_6.3V4Z

4.7U_0603_6.3V6K
G
2
LAN_PWR_ON# 2 1 8161@
<42> LAN_PWR_ON#

C967

C980

C278
2 11/07 Change type to 0603 1 1 1
10K_0402_5% C976
0.1U_0402_16V7K
1 2 2 2
Close to
Pin40

Layout Notice : Place as close

11/08 Increase for LAN S5 power saving chip as possible. Place close to Pin34

Vendor recommand reseve the

PU resistor close LAN chip

+3V_LAN R345 1 2 4.7K_0402_5%

@
PLT_RST#
<18,23,36,42,46> PLT_RST#
H --> Overclocking mode
2 @ 1
U63 R31 10K_0402_5%
L --> Not overclocking mode
Place Close to Chip
C C946 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_N1 29 38 ACTIVITY C
<15> PCIE_PRX_DTX_N1 TX_N LED_0 ACTIVITY <38>
LAN_LINK#
C947 1 2 0.1U_0402_16V7K PCIE_PRX_C_DTX_P1 30
Atheros LED_1 39
23
LAN_LINK# <38>
<15> PCIE_PRX_DTX_P1 TX_P LED_2
AR8151/AR8161
<15> PCIE_PTX_C_DRX_N1 36 RX_N
12 MDI0-
TRXN0 MDI0- <38>
MDI0+
<15> PCIE_PTX_C_DRX_P1 35 RX_P TRXP0 11
15 MDI1-
MDI0+ <38> Place Close to LAN chip
TRXN1 MDI1- <38>
32 14 MDI1+
<15> CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ <38>
33 18 MDI2- 8151@ 49.9_0402_1%
<15> CLK_PCIE_LAN REFCLK_P TRXN2 MDI2- <38>
17 MDI2+ MDI0+ R1358 1 2 1@ 2 C938 1000P_0402_50V7K
TRXP2 MDI2+ <38>
PLT_RST# 2 21 MDI3- 8151@ 49.9_0402_1% 8151@
PERST# TRXN3 MDI3- <38>
@ MDI3+ MDI0- R1359 1 2 C939 0.1U_0402_16V4Z
R1369 1 2 0_0402_5% PCIE_WAKE#_R 3
TRXP3 20 MDI3+ <38> Place Close to PIN1 2
8151@ 49.9_0402_1%
1
<16,19,36> PCIE_WAKE# W AKE#
R1370 1 2 0_0402_5% MDI1+ R1360 1 2 1@ 2 C940 1000P_0402_50V7K
<42> LAN_WAKE# +3V_LAN
25 10 LAN_RBIAS 1 2 8151@ 49.9_0402_1% 8151@
R343 1 BOM Structure SMCLK RBIAS MDI1-
+3V_LAN 2 4.7K_0402_5%
= CD4@ 26 SMDATA
R1371 2.37K_0402_1% R1361 1 2 1 2 C941 0.1U_0402_16V4Z
Place Close to PIN1 8151@ 49.9_0402_1%
@ 28 1 +3V_LAN MDI2+ R1362 1 2 1@ 2 C942 1000P_0402_50V7K
NC VDD33

1000P_0402_50V7K

10U_0603_6.3V6M

10U_0603_6.3V6M
Vendor recommand reseve the 8151@ 49.9_0402_1% 8151@

0.1U_0402_16V4Z

1U_0402_6.3V4Z
27 TESTMODE 1 1 1 1

@
@ MDI2- R1363 1 2 1 2 C943 0.1U_0402_16V4Z
PU resistor close LAN chip +LX R1372 8161@ 30K_0402_5% 8151@ 49.9_0402_1%
LX 40 +LX

C950

C951

C952

C953

C954
LAN_XTALO 7 1 2 MDI3+ R1364 1 2 1@ 2 C944 1000P_0402_50V7K
+3VS

1
@ LAN_XTALI XTLO 8151@ 2 2 2 2 8151@ 49.9_0402_1% 8151@
8 XTLI
R344 1 2 4.7K_0402_5% 5 +1.7_VDDCT 1 2 MDI3- R1365 1 2 1 2 C945 0.1U_0402_16V4Z
+3V_LAN VDDCT/ISOLAN C955 0.1U_0402_16V4Z
<15> CLKREQ_LAN# 4 CLKREQ# Note : C938, C940, C942, 944, reserved for EMI.
24 +1.1_DVDDL_R R1366 1 2 0_0402_5% +1.1_DVDDL
DVDDL/PPS
DVDDL_REG/DVDDL 37
+1.1_AVDDL 13 +1.1_DVDDL 8151@
B
+1.1_AVDDL AVDDL B
19 AVDDL 11/07 Change type to 0603 For AR8151: Stuff 49.9K and 0.1u
+1.1_AVDDL 31 16 +AVDDH_AVDD3.3
+1.1_AVDDL_L AVDDL AVDDH/AVDD33 +2.7_AVDDH For AR8161: NC
34 AVDDL AVDDH 22
+1.1_AVDDL 6 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C956

C957

C958

C959

C960
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1U_0402_6.3V4Z
1 1 1 1 1
C961

C962

C963

C966
41 GND 1 1 1 2
+3V_LAN

C964

C965
1 1
AR8161-AL3A-R_QFN40_5X5 8151@
2 2 2 2 2 8161@ +2.7_AVDDH
U63 2 2 2 1 R1367 1 2 0_0402_5%
8161@ 2 2
8151@
For AR8151: Stuff C966,R1366 +AVDDH_AVDD3.3 R1368 1 2 0_0402_5% +2.7_AVDDH
For AR8161: NC
Near
Near Near Near Near SA00003LE20 Near Near Near

1U_0402_6.3V4Z
0.1U_0402_16V4Z
Pin9
Pin13 Pin19 Pin31 Pin6 Pin22 Pin37 Pin24

C948

C949
8151@ 1 1
8161@
C981 3.3P_0402_50V8
1 2 LAN_XTALI 2 2
<15> PCH_LAN_48M
@ Y6 LAN_XTALO
Place Close to C968 4 NC OSC 3
Place close to Pin16
33P_0402_50V8J

1 OSC NC 2
33P_0402_50V8J

A 1 25MHZ_12PF_X3G025000DC1H~D 1 For AR8151: Stuff R1368 for +AVDD3.3 A

C968

C969

For AR8161: Stuff R1367,C949 for +AVDDH

2 2

9/20 For Crystal EA request Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-AR8151/8161
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom QIWY3 LA-8001P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 37 of 64
5 4 3 2 1
 5 4 3 2 1

C970 C972 C974 C975

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 11/25 Change T1,T2 P/N to SP050007K00

8161S@ 8161S@ 8161S@ 8161S@

+1.7_VDDCT T76
D 8151@ D
2
C970 MDI3+ 1 16 MDO3+
<37> MDI3+ TD+ TX+
R1373 8151@ 0.1U_0402_16V4Z MDI3- 2 15 MDO3- R1374
<37> MDI3- TD- TX-
2 1 3 14 MCT3 2 1
0_0603_5% 1 CT CT 0_0402_5%
4 NC NC 13
1 5 12 R1375
C971 NC NC MCT2
1 6 CT CT 11 2 1
8151@ MDI2+ 7 10 MDO2+ 0_0402_5%
<37> MDI2+ RD+ RX+
8151@ C972 MDI2- 8 9 MDO2-
2 <37> MDI2- RD- RX-
1U_0402_6.3V4Z
2
0.1U_0402_16V4Z 11/20 For LAN SURGE CO-LAY
BOTHHAND_NS0013LF

6/23 update 1 R90 2 1 2

75_0603_5% C973
T77 10P_0603_50V8-J
2
C974 MDI0+ 1 16 MDO0+
<37> MDI0+ TD+ TX+
Place Close to T76 8151@ 0.1U_0402_16V4Z MDI0- 2 15 MDO0- R1376
<37> MDI0- TD- TX-
3 14 MCT0 2 1
MDI3- 1 CT CT 0_0402_5%
4 NC NC 13
5 12 R1377
NC NC MCT1
C 1 6 CT CT 11 2 1 C
MDI3+ MDI1+ 7 10 MDO1+ 0_0402_5%
<37> MDI1+ RD+ RX+
D68 8151@ C975 MDI1- 8 9 MDO1-
<37> MDI1- RD- RX-
0.1U_0402_16V4Z
TCLAMP3302N.TCT_SLP2626P10-10 2
BOTHHAND_NS0013LF
10
6
7
8
9
6
7
8
9
10

11 R02
GND
5
4
3
2
1

11/20 Atheros request

5
4
3
2
1

220_0402_5% JRJ1
LAN_LINK# 2 1 9
<37> LAN_LINK# Green LED-
1 R1380 Place Close to T76,T77
MDI2- @ +3V_LAN R1378 2 1 0_0402_5%
10
C978 Green LED+ MCT3
MDI2+ 470P_0402_50V7K MDO0+ 1
2 PR1+ MCT2
MDO0- 2
8151S@ PR1- MCT1
MDO1+ 3 PR2+ MCT0
Place Close to T77
B MDO2+ 4 B
PR3+

LSE-200NX3216TRLF_1206-2

LSE-200NX3216TRLF_1206-2

LSE-200NX3216TRLF_1206-2

LSE-200NX3216TRLF_1206-2
MDI1-
MDO2- 5 PR3-

2
MDI1+ MDO1- 6 PR2-

F6

F3

F4

F5
D67
MDO3+ 7 14
TCLAMP3302N.TCT_SLP2626P10-10 PR4+ G2
MDO3-
10

8 PR4- G1 13
6
7
8
9

R1448 220_0402_5% SURGE@ @ @ @

1
2 1 11
6
7
8
9
10

R02 Yellow LED-

11 GND ACTIVITY R1379 2 1 220_0402_5% 12
<37> ACTIVITY Yellow LED+
@
2

0_0402_5%
5
4
3
2
1

1 SANTA_130452-D
R1446

@ R1442
5
4
3
2
1

C979 +3V_LAN 2 1 @ ME@ Reserve for EMI go rural solution

470P_0402_50V7K
2 0_0402_5%
1

MDI0-

MDI0+

A 8151S@ A

Reserve D67,D68 for EMI go rural solution

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B QIWY3 LA-8001P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 38 of 64
5 4 3 2 1
 5 4 3 2 1

R431 1403@

1403:
@C982/@C984=100p
0_0402_5%

D D
+3VS +3VS +3VS +3VS +3VS +3VS +3VS

SMSC thermal sensor Under VRAM

1
2103@ 2103@ 2103@ 2103@ REMOTE1+

1
2103@ 2103@ R460 R462 R440
placed near by VRAM R461 R441 1

1
R431 R459 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @ C
68_0402_5% 6.8K_0402_5% @ C982 2 Q137
U20 2103@ 100P_0402_50V8J B MMST3904-7-F_SOT323-3

2
2 E
1 2

3
+VDD DN1 DP1 REMOTE1-
3 VDD GPIO1 4
5 6 ALERT#
GPIO2 ALERT# EC_SMB_DA2
7 SYS_SHDN# SMDATA 8 EC_SMB_DA2 <15,23,42>
2 EC_SMB_CK2 9 10 TACH
<15,23,42> EC_SMB_CK2 SMCLK TACH
FAN_PW M 11 12
C443 SHDN_SEL PWM GND TRIP_SET
0.1U_0402_16V4Z
13
15
SHDN_SEL TRIP_SET 14
16 REMOTE2+
Close to SSD side
1 DN2 / DP3 DP2 / DN3 REMOTE2+
GPAD 17
1

1
REMOTE2- @ C
EMC2103-2-AP-TR_QFN16_4X4 R439 C984 2 Q138
100P_0402_50V8J B MMST3904-7-F_SOT323-3
FAN_PWM & TACH 1.5K_0402_1%
@ 2 E
Address 0101_110xb

3
for PWM FAN REMOTE2-

1
REMOTE2+/-:
internal pull up 1.2K to 1.5V
C
Trace width/space:10/10 mil C
R for initial thermal
Trace length:<8"
shutdown temp

Close U20 2103@

REMOTE1+ REMOTE2+ 1 2 REMOTE1-
1 R622 0_0402_5%
1403@ 2103@
C449 REMOTE2- 1 2 REMOTE1+
2200P_0402_50V7K R623 0_0402_5%
2 REMOTE1-

REMOTE2+
B +3VS B
1
C658
FAN1 Conn
1
2200P_0402_50V7K
2 REMOTE2- R624
10K_0402_5%
@
U29 1403@
2

+5VS
R309
+VDD 1 10 EC_SMB_CK2
VDD SMCLK
Shutdown TRIP_SET REMOTE1+ 2 9 EC_SMB_DA2 2
1 2
DP1 SMDATA
Temp R1387(1%) REMOTE1- ALERT# C986 0_0603_5% JP22
3 DN1 ALERT# 8
93 953ohm REMOTE2+ 4 7
1
10U_0603_6.3V6M 1
2
1
DP2 THERM# <42> EC_TACH 2
94 1020ohm 11/07 Change type to 0603 <42> EC_FAN_PW M 3 3
REMOTE2- 5 6 4
DN2 GND 4
95 1100ohm 5
6
G5
G6
96 1150ohm EMC1403-2-AIZL-TR_MSOP10 ACES_85205-04001
ME@
97 1240ohm
Address 1001_101xb
98 1330ohm
99 1400ohm
A A
100 1500ohm
101 1580ohm
102 1690ohm
103 1820ohm
Security Classification Compal Secret Data Compal Electronics,Ltd.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
104 1960ohm EMC1403/2103_Thermal sensor/FAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
105 2050ohm AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 39 of 64
5 4 3 2 1
 A B C D E F G H

1 1

SATA HDD Conn.

JHDD1
2 2
1 GND
SATA_ITX_DRX_P1 2
<14> SATA_ITX_DRX_P1
<14> SATA_ITX_DRX_N1
SATA_ITX_DRX_N1 3
A+
A-
SATA ODD Conn.
4 GND
SATA_DTX_C_IRX_N1 C627 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N1 5
<14> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 C628 1 SATA_DTX_IRX_P1 B-
2 0.01U_0402_16V7K 6
<14> SATA_DTX_C_IRX_P1 B+
7 GND
JODD1
1
@ J13 SATA_ITX_DRX_P2_CONN GND
8 VCC3.3 <14> SATA_ITX_DRX_P2_CONN 2 RX+
1 2 +3VS_HDD 9 SATA_ITX_DRX_N2_CONN 3
+3VS 1 2 VCC3.3 <14> SATA_ITX_DRX_N2_CONN RX-
10 VCC3.3 4 GND
11 SATA_DTX_C_IRX_N2 C629 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N2 5
JUMP_43X79 GND <14> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C630 1 SATA_DTX_IRX_P2 TX-
12 2 0.01U_0402_16V7K 6
GND <14> SATA_DTX_C_IRX_P2 TX+
13 7
@ J12 GND @ GND
14
+5VS_HDD VCC5 R921 R710 1
+5VS 1 2 15 2 0_0402_5% 8
1 2 VCC5 DP
16 +3VS 1 2 +5V_ODD 9
VCC5 10K_0402_5% +5V
17 GND 10 +5V
JUMP_43X79 ODD_DA#
18 1 2 11
RESERVED <18,42> ODD_DA# R922 0_0402_5% MD
19 12 14
GND GND GND1
20 23 13 15
+5VS +3VS VCC12 G1 GND GND2
21 24
VCC12 G2 TYCO_2-1759838-8~D
22
VCC12 ME@
1 1 1 1 1 1
@ FOX_LD2822F-SAQL6
C631 C632 C633 C634 C635 C636
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z ME@
2 2 2 2 2 2

3 ODD Power Control 3

11/07 Change type to 0603

@ J6
1 2
1 2
+5VS
JUMP_43X79 +5V_ODD
+5VALW Q88

D
3 1
1

1
AO3413_SOT23-3
C637

G
2
R923 0.1U_0402_16V4Z
10K_0402_5% 2
1

2
R1110 C638 0.1U_0402_10V7K
1 2 1 2 C639
10U_0603_6.3V6M

1
200K_0402_5% 2
11/07 Change type to 0603

OUT
11/07 Change for soft star
<19> ODD_EN 2
IN GND

Q89
DTC124EKAT146_SC59-3
3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 40 of 64
A B C D E F G H
 5 4 3 2 1

600ohms @100MHz 1A +3VS +3VDD_CODEC +IOVDD_CODEC +3VDD_CODEC

P/N: SM01000BU00
+5VS +5VDDA_CODEC +5VDDA_CODEC R1355
0_0402_5% R927
L10 1 2 1 2

1U_0603_10V4Z

10U_0603_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1 2
0_0603_5% 1 1 1 1 P/N: SM01000DI00
FBMA-L11160808601LMA10T_2P

C644

C693

C654

C655
0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
1 1 1 2 @ @

4.7U_0805_10V4Z
2 2 2 2

C646

C648
11/07 Change type to 0603

C295

C293
2 2 2 1
Place near Pin1 Place near Pin9
600ohms @100MHz 2A
P/N: SM01000EE00
D +MIC1_VREFO_L D
R70 Place near Pin25 Place near Pin38
0_0805_5%
+5VS 1 2 +5VS_PVDD

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.7U_0603_6.3V6K
2 1 1 +3VDD_CODEC

C657

C656

2
C294
+IOVDD_CODEC D22
1 2 2 D23
RB751V_SOD323
RB751V_SOD323

1
U8

39

46

25

38

9
Power down (PD#) power stage for save power

2
Vendor recommend. 2.2K

PVDD1

PVDD2

AVDD1

AVDD2

DVDD1

DVDD-IO
0V: Power down power stage R931 R930
3.3V: Power up power stage 2.2K_0402_5% 2.2K_0402_5%
@
<42> EAPD 1 2 EAPD_R 47 24 Vendor recommend. 2.2u

1
R941 0_0402_5% DAPD/COMB_JACK LINE1-R(PORT-C-R)
12/26 modify for MIC R/L reverse issue
EC_MUTE# 1 2 EC_MUTE#_R 4 23
<42> EC_MUTE# PD# LINE1-L(PORT-C-L)
R943 0_0402_5% C675 2.2U_0603_6.3V6K
HDA_SDOUT_AUDIO 5 22 MIC_EXTR_C 2 1 2 1
+3VS <14> HDA_SDOUT_AUDIO SDATA-OUT MIC1-R(PORT-B-R) EXT_MIC_R <46>
R933 1K_0402_5% external MIC
HDA_BITCLK_AUDIO 6 21 MIC_EXTL_C 2 1 2 1
<14> HDA_BITCLK_AUDIO BIT-CLK MIC1-L(PORT-B-L) EXT_MIC_L <46>
R935 1K_0402_5%
2

HDA_SDIN0 2 1 SDATA_IN 8 17 C689 2.2U_0603_6.3V6K

<14> HDA_SDIN0 SDATA-IN MIC2-R(PORT-F-R)
R341 22_0402_5% R938
4.7K_0402_5% 16
MIC2-L(PORT-F-L)
@
<14> HDA_SYNC_AUDIO 10 15
1

SYNC LINE2-R(PORT-E-R)
HDA_RST_AUDIO# 11 14
<14> HDA_RST_AUDIO# RESET# LINE2-L(PORT-E-L)
PC_BEEP 12
PCBEEP
1

R331 40 SPK_L2+ 12/26 modify for MIC R/L reverse issue

JDREF SPK-OUT-L+
4.7K_0402_5% 2 1 19
20K_0402_1% R942 JDREF SPK_L1-
C @ 41 C
SPK-OUT-L-
20 Internal Speaker
2

MONO-OUT(PORT-H) SPK_R1-
44
SENSEA SPK-OUT-R-
<46> MIC_JD 2 1 13
20K_0402_1% R939 Sense A SPK_R2+
SPK-OUT-R+
45 12/26 modify for HP R/L reverse issue
<46> PLUG_IN 2 1 18
39.2K_0402_1% R940 Sense-B
MIC Sense CBN 35
CBN HPOUT-R(PORT-A-R)
33 HPOUT_R
75_0402_5%
2 1
R936
HP_OUTR <46>
R939 place near pin13 CBP HPOUT_L
Headphone
2 1 36 32 2 1 HP_OUTL <46>
2.2U_0603_6.3V6K C666 CBP HPOUT-L(PORT-A-L) 75_0402_5% R934
Capless HP Sense 2 1 34 48 SPDIF 1 2 SPDIF
CPVEE SPDIF-OUT SPDIF_OUT <46>
2.2U_0603_6.3V6K C673 FBMA-10-100505-301T_2P R932
R940 place near pin34 2 1 28 9/23 EMI Request
4.7U_0603_6.3V6K C291 LDO-CAP DMIC_CLK_R
3 1 2 DMIC_CLK <33>
GPIO1/DMIC-CLK FBMA-10-100505-301T_2P R937
EAPD 1 2 29 2 DMIC_DATA_R 2 1 DMIC_DATA <33>
R9451 MIC2-VREFO GPIO0/DMIC-DATA
2 0_0402_5% 0_0402_5% R944
11/11 Reserve for MUTE_LED issue R481 10K_0402_5% 30
MIC1-VREFO-R
31
MIC1-VREFO-L

+MIC1_VREFO_L
42
PVSS1 VREF
27 Place next to pin 27

1U_0603_10V4Z

0.1U_0402_16V4Z
43 26 1 1
PVSS2 AVSS1

C659
C674
7 37
DVSS AVSS2
49 2 2
Thermal PAD

ALC269Q-VC2-GR_QFN48_6X6

R946
B
1 2 B
0_0402_5%
R947 HDA_RST_AUDIO#
Pin Assignment Location Function 1 2
0_0402_5% HDA_SYNC_AUDIO
EMI
R948
SPK-OUT (Pin40/41/44/45) Internal Int Speaker 1 2 HDA_SDOUT_AUDIO
@ 0_0402_5%
R949 1 2 HDA_BITCLK_AUDIO
Capless HP-OUT (Pin32/33) External Headphone out 1 2
@ 0_0402_5% R928 @ 27_0402_5%
R950 1 1 1 1
MIC1(Pin21/22) External Mic in 1 2
@ 0_0402_5% C1014

C650

C651

C652
22P_0402_50V8J

22P_0402_50V8J

22P_0402_50V8J
R951 @ 33P_0402_50V8J
1 2 2 2 2 2
wide 25MIL JSPK1
@ 0_0402_5% @ @ @

SPK_R1- 1 R1280 2 0_0805_5% SPK_R1-_CONN 1

SPK_R2+ R1281 0_0805_5% SPK_R2+_CONN 1
SPK_L1-
1
R1282
2
0_0805_5% SPK_L1-_CONN
2
2 GND GNDA
1 2 3
SPK_L2+ R1283 0_0805_5% SPK_L2+_CONN 3
1 2 4
4
1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1 1 1 1 5
GND1
11/15 For EMI request change to SM010024230
C678

C679

C680

C681

6
GND2

@ 2 @ 2 @ 2 @ 2 ACES_88231-04001
PC Beep
ME@

EC Beep <42> BEEP# 1 2

C619 0.1U_0402_16V4Z

SPK_R1-_CONN SPK_L1-_CONN R492

PCH Beep <14> HDA_SPKR 1 2PC_BEEP1 1 2 PC_BEEP
SPK_R2+_CONN SPK_L2+_CONN C612 0.1U_0402_16V4Z 33_0402_5%

1
A A
3

@
R480
@ @ 10K_0402_5%

2
D59 D60
PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3
1

Security Classification Compal Secret Data Compal Electronics,Ltd.

2011/07/21 2012/12/31
Reserve for ESD request. Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec_ALC269Q-VC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 41 of 64
5 4 3 2 1
 +3VALW

+EC_VCCA

+3VLP

L77
FBM-11-160808-601-T_0603 1 1 1 1 1 1 R1401

0.1U_0402_16V4Z
C990

0.1U_0402_16V4Z
C991

0.1U_0402_16V4Z
C992

0.1U_0402_16V4Z
C993

1000P_0402_50V7K
C997

1000P_0402_50V7K
C994
1 2 +3VLP_R 2 1
+3VALW +EC_VCCA
1 1 0_0402_5%
C996
C995 2 2 2 2 2 2

111
125
0.1U_0402_16V4Z 1000P_0402_50V7K U70

22
33
96

67
9
1 2 2 ECAGND 2
L78

EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
FBM-11-160808-601-T_0603
KBL@
R1443 0_0402_5%
1 21 LED_KB_PWM 2 1
<19> GATEA20 GATEA20/GPIO00 GPIO0F LED_KB_PWM_R <47>
KBRST# 2 23 BEEP#
<19> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# <41>
3 26 NOVO#
<14> SERIRQ SERIRQ GPIO12 NOVO# <47>
4 27 ACOFF +3VS +3VALW
<14,36> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF <51>
LPC_AD3 5
<14,36> LPC_AD3 LPC_AD3

2
LPC_AD2 7 PWM Output
<14,36> LPC_AD2 LPC_AD2

1
LPC_AD1 8 63 BATT_TEMP
<14,36> LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 BATT_TEMP <50> R1.0
LPC_AD0 10 LPC & MISC 64 R1405
<14,36> LPC_AD0 LPC_AD0 GPIO39 VGA_IMVP_IMON <56>
2 1 2 1 65 R1402 100K_0402_1%
ADP_I/GPIO3A ADP_I <50,51>
@ C998 22P_0402_50V8J @ R1403 10_0402_5% 12 AD Input 66 10K_0402_5%
<18> CLK_PCI_EC MUTE_BTN# <47>

1
CLK_PCI_EC GPIO3B BRDID @ BRDID
<18,23,36,37,46> PLT_RST# 13 75

2
EC_RST# PCIRST#/GPIO05 GPIO42 EC_FAN_PWM
+3VALW 1 2 37 76 IMVP_IMON <57>
EC_RST# IMON/GPIO43

1
R1404 47K_0402_5% EC_SCI# 20
<19> EC_SCI# EC_SCII#/GPIO0E
2 BATT_LEN# 38 R1406
<50> BATT_LEN# GPIO1D
68 33K_0402_5%
DAC_BRIG/GPIO3C ECR_EN <33>
C999 70
EN_DFAN1/GPIO3D CHG_ON# <46>
0.1U_0402_16V4Z DA Output 71 PM_SLP_SUS# <16>

2
1 KSI0 IREF/GPIO3E +5VALW
55 72 SUSWARN# <16>
KSI1 KSI0/GPIO30 CHGVADJ/GPIO3F
56
KSI2 KSI1/GPIO31 EC_MUTE# +5VS
57 1 R1407 2 10K_0402_5% +3VALW
KSO[0..15] KSI3 KSI2/GPIO32 @
58 83 EC_MUTE# <41>
<43> KSO[0..15] KSI4 KSI3/GPIO33 EC_MUTE#/GPIO4A USB_ON# TP_CLK R1410 1
59 84 USB_ON# <45,46> 2 4.7K_0402_5%
KSI[0..7] KSI5 KSI4/GPIO34 USB_EN#/GPIO4B R1409
60 85 MUTE_LED# <47>
<43> KSI[0..7] KSI6 KSI5/GPIO35 CAP_INT#/GPIO4C USB_ON# 1 TP_DATAR1412 1
61 PS2 Interface 86 EAPD <41> 2 2 4.7K_0402_5%
KSI7 KSI6/GPIO36 EAPD/GPIO4D TP_CLK @
62 87 TP_CLK <43>
+3VALW @ KSO0 KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA 10K_0402_5% +3VS
39 88 TP_DATA <43>
KSO0/GPIO20 TP_DATA/GPIO4F
R1411 1 2 47K_0402_5% KSO1 KSO1 40
KSO2 KSO1/GPIO21 TP_CLK R1415 1
41 2 2.2K_0402_5%
KSO2/GPIO22
R1413 1 2 47K_0402_5% KSO2 KSO3 42 97 CPU1.5V_S3_GATE
CPU1.5V_S3_GATE <10,48,55>
KSO4 KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 TP_DATAR1419 1
43 98 VGA_AC_DET <23,56> 2 2.2K_0402_5%
@ KSO5 KSO4/GPIO24 WOL_EN/GPXIOA01
KSO5/GPIO25 Int. K/B
44 99 ME_FLASH <14>
KSO6 HDA_SDO/GPXIOA02 NTC_V_R
45 109 2 1
KSO7 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 R1414 0_0402_5%
NTC_V <50>
46
KSO7/GPIO27 SPI Device Interface 12/23 Follow T/P power to PU +3VS
+3VS +3VALW KSO8 47 @
R1417 KSO9 KSO8/GPIO28 PCH_PWR_EN BATT_TEMP
48 119 1 2
EC_SMB_CK1 KSO10 KSO9/GPIO29 SPIDI/GPIO5B BM#_R @ 1 BM# C1000 100P_0402_50V8J
1 2 49 120 2 BM# <51>
2.2K_0402_5% KSO11 KSO10/GPIO2A SPIDO/GPIO5C R1432 0_0402_5% ACIN
50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
126 AOAC_ON# <36> 1 2
R1424 KSO12 51 128 C1001 100P_0402_50V8J
KSO12/GPIO2C SPICS#/GPIO5A SUSACK# <16>
R1422 R1423 1 2 EC_SMB_DA1 KSO13 52 1 2
KSO13/GPIO2D ENBKL <33>
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% KSO14 53 R1416 @ 4.7K_0402_5%
KSO15 KSO14/GPIO2E R1444
54 73
KSO15/GPIO2F ENBKL/GPIO40 ONEKEY_BTN#_R
81 74 2 1 0_0402_5% ONEKEY_BTN# <47>
EC_SMB_CK2 KSO16/GPIO48 PECI_KB930/GPIO41
82 89 LAN_PWR_ON# <37>
EC_SMB_DA2 KSO17/GPIO49 FSTCHG/GPIO50 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52
90 BATT_CHG_LED# <44> 11/08 Increase for LAN S5 power saving
1 1 91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# <44>
@ @ EC_SMB_CK1 77 GPIO 92
<50,51> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <44,47> +3VLP
C1002 C1003 EC_SMB_DA1 78 93 BATT_LOW_LED#
<50,51> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# <44>
100P_0402_50V8J 100P_0402_50V8J EC_SMB_CK2 79 SM Bus 95 SYSON
2 2 <15,23,39> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <48,53>
EC_SMB_DA2 80 121
<15,23,39> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <57>

1
127 PM_SLP_S4# <16>
PM_SLP_S4#/GPIO59 R1426
@ 47K_0402_5% VR_HOT# 1 R1427 2 H_PROCHOT# <6,50>
<57> VR_HOT#
6 100 0_0402_5%
<16> PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# <16>
+3VS 14 101 EC_LID_OUT#
<16> PM_SLP_S5# EC_LID_OUT# <19>

2
PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04

1
EC_SMI# Turbo_V_R R1428 2 D
<19> EC_SMI# 15 102 1 0_0402_5% Turbo_V <50>
EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 H_PROCHOT#_EC R1429 2 @ 1 0_0402_5% H_PROCHOT#_EC
<33> CMOS_ON# 16 103 PROCHOT <50> 2 1
GPIO0A H_PROCHOT#_EC/GPXIOA06
1

17 104 MAINPWON_R R1430 2 @ 1 0_0402_5% G

<44> TP_LED# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <50,52>
18 GPO 105 BKOFF# @ Q141 S C1004
<7> DRAMRST_CNTRL_EC BKOFF# <33>

3
R1431 ODD_DA# GPIO0C BKOFF#/GPXIOA08 PBTN_OUT# 2N7002H_SOT23-3 47P_0402_50V8J
<18,40> ODD_DA# 19
GPIO0D GPIO PBTN_OUT#/GPXIOA09
106 PBTN_OUT# <16> 2
10K_0402_5% EC_INVT_PWM 25 107 PCH_APWROK <16>
<33> EC_INVT_PWM EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10
EC_TACH 28 108 SA_PGOOD <54>
<39> EC_TACH
2

EC_TACH EC_PME# FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11

29
EC_TX EC_PME#/GPIO15
<36,43> EC_TX 30
EC_RX EC_TX/GPIO16 ACIN
<36,43> EC_RX 31 110 ACIN <16,51>
PCH_PWROK EC_RX/GPIO17 AC_IN/GPXIOD01 EC_ON +3VALW
<16> PCH_PWROK 32 112 EC_ON <47,52>
EC_FAN_PWM PCH_PWROK/GPIO18 EC_ON/GPXIOD02
<39> EC_FAN_PWM 34 114 ON/OFF <47>
SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 LID_SW#
<44> NUM_LED# 36
NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04
115 LID_SW# <43>

2
2 1 116 SUSP#
SUSP#/GPXIOD05 SUSP# <10,48,53,55,56>
@ R1433 117 PCH_HOT#_R R1445 2 @ 1 0_0402_5% PCH_HOT# <15>
10K_0402_5% GPXIOD06 PECI_KB9012 R1434
118
PECI_KB9012/GPXIOD07
AGND/AGND

R1436 EC_RTCX1 122 R1435 1 2 43_0402_1% H_PECI 10K_0402_5%

XCLKI/GPIO5D H_PECI <6,19>
SUSCLK_R +V18R
GND/GND
GND/GND
GND/GND
GND/GND

<16> SUSCLK 2 1 123 124

1
XCLKO/GPIO5E V18R
0_0402_5% 1 Please place R1435 close to EC with in 750mil
GND0
1

C1005
1

4.7U_0805_10V4Z 2 R1439 1
R1438 C1006 2 0_0402_5% LAN_WAKE# <37>
11
24
35
94
113

69

100K_0402_5% 20P_0402_50V8
2

2 R1440 1
2

KB9012QF-A2_LQFP128_14X14 EMC Request 0_0402_5% @

ECAGND

EC_RTCX1 SYSON EC_PME# 1 3

S
PCI_PME# <18>
SUSCLK_R Q142 @

C1007
1 2

0.1U_0402_10V6K
R1441 @ 2N7002_SOT23

G
2
10M_0402_5% 1 +3VALW
@
Y3
1 2
2
18P_0402_50V8J

32.768KHZ_12.5PF_CM31532768DZFT

+5VALW
1 @ 1
C1008 C1009 @
@ 18P_0402_50V8J

1
2 2

100K_0402_5%
@ R1111

2
PCH_PWR_EN#
<48> PCH_PWR_EN#

1
D
2 Q117
<50> PCH_PWR_EN
8/23 change to reserved G 2N7002_SOT23

1
S

3
@
@ 100K_0402_5%
R1114

2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 42 of 64
 5 4 3 2 1

INT_KBD Conn. EC DEBUG PORT

KSI[0..7]
KSI[0..7] <42>
D KSO[0..15] D
KSO[0..15] <42>
JP5 JP6
KSI1 1 +3VALW 1
KSO2 C734 1 1 1
2 @ 100P_0402_50V8J KSO1 C735 1 2 @ 100P_0402_50V8J KSI7 2 2 <36,42> EC_TX
EC_TX 2 2
KSI6 3 EC_RX 3
3 <36,42> EC_RX 3
KSO15 C736 1 2 @ 100P_0402_50V8J KSO7 C737 1 2 @ 100P_0402_50V8J KSO9 4 4
KSI4 4 4
5 5
KSO6 C738 1 2 @ 100P_0402_50V8J KSI2 C739 1 2 @ 100P_0402_50V8J KSI5 6 ACES_85205-0400
KSO0 6
7 7 ME@
KSO8 C740 1 2 @ 100P_0402_50V8J KSO5 C741 1 2 @ 100P_0402_50V8J KSI2 8
KSI3 8
9 9
KSO13 C742 1 2 @ 100P_0402_50V8J KSI3 C743 1 2 @ 100P_0402_50V8J KSO5 10
KSO1 10
11 11
KSO12 C744 1 2 @ 100P_0402_50V8J KSO14 C745 1 2 @ 100P_0402_50V8J KSI0 12
KSO2 12
13 13
KSO11 C746 1 2 @ 100P_0402_50V8J KSI7 C747 1 2 @ 100P_0402_50V8J KSO4 14
KSO7 14
15 15
KSO10 C748 1 2 @ 100P_0402_50V8J KSI6 C749 1 2 @ 100P_0402_50V8J KSO8 16
KSO6 16
17 17
KSO3 C750 1 2 @ 100P_0402_50V8J KSI5 C751 1 2 @ 100P_0402_50V8J KSO3 18

KSO4 C752 1 2 @ 100P_0402_50V8J KSI4 C753 1 2 @ 100P_0402_50V8J

KSO12
KSO13
19
20
18
19 Lid Switch
KSO14 20
21 21
KSI0 C754 1 2 @ 100P_0402_50V8J KSO9 C755 1 2 @ 100P_0402_50V8J KSO11 22
KSO10 22
23 23
KSO0 C756 1 2 @ 100P_0402_50V8J KSI1 C757 1 2 @ 100P_0402_50V8J KSO15 24 24 +VCC_LID R1003 1
25 G1 +3VALW 1 2 2 100K_0402_5%
26 R1002 0_0402_5%
C G2 C
CONN PIN define need double check

2
ACES_85202-24051 5711ACDL-M3T1S SOT-23

VDD
ME@
1
OUTPUT 3 LID_SW # <42>
C758
To TP/B Conn. 0.1U_0402_16V4Z 2

GND
2
C759
U37 10P_0402_50V8J
JP24

1
1
8 GND
7 GND
6 6
5 5
4 4
TP_DATA 3
<42> TP_DATA 3
TP_CLK 2
<42> TP_CLK 2
1 1 +3VS 1 1
@ @
C761 C762 C760
100P_0402_50V8J 100P_0402_50V8J ACES_88514-00601-071
2 2 0.1U_0402_16V4Z
3

ME@
@
B D58 B
PACDN042Y3R_SOT23-3
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB /SW /LPC Debug Conn.
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 43 of 64
5 4 3 2 1
 LED
LED1
<42> TP_LED# 1 2 2 1 +5VS
300_0402_5% R1010
12-21SYGCS530-E1S155TR8_W

White
Amber LED2
BATT_LOW_LED# 3 FD1 FD2 FD3 FD4
<42> BATT_LOW_LED#
1 1 1 1
1 2 1 +5VALW
470_0402_5% R1012
<42> BATT_CHG_LED# 2 D:H_2P8 X 10
BATT_CHG_LED#
White
H1 H2 H3 H4 H5 H6 H7 H8 H9 H19
12-22-S2ST3D-C30-2C_WHI-ORG HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
LED3
<42,47> PWR_LED# 1 2 2 1 +5VALW
300_0402_5% R1013

1
12-21SYGCS530-E1S155TR8_W

White

LED4
1 2 2 1
A:H_3P9 X 3 B:H_3P8 X 2
<42> CAPS_LED# +5VS
300_0402_5% R1014 H10 H11 H12 H13 H15
12-21SYGCS530-E1S155TR8_W HOLEA HOLEA HOLEA HOLEA HOLEA

White

1
LED5
<42> NUM_LED# 1 2 2 1 +5VS
300_0402_5% R1026
12-21SYGCS530-E1S155TR8_W
H_3P3 H_3P2 H_6P0X3P0N H_4P5X3P0N
White
H16 H18 H20 H21
HOLEA HOLEA HOLEA HOLEA

1
BT MODULE CONN

+3VS +3VS_BT

+3VALW
Q93 AO3413_SOT23-3
11/30 change to 200K for soft star 1 30mils
S

@ 3 1
C522 1
0.1U_0402_16V4Z BT@ 0.1U_0402_16V4Z
R1025 2 C776
G
2

2 1 BT@
<19,36> PCH_BT_ON# 2
200K_0402_5% BT@ JP8
1 1
1
2
C775 USB20_P13 2
<18> USB20_P13 3
USB20_N13 3
0.1U_0402_16V4Z <18> USB20_N13 4 4
2 5 7
BT@ 5 G1
<36> BT_ACTIVE BT_ACTIVE 6 8
6 G2
ACES_87213-0600G
ME@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/EC SPI ROM/BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 44 of 64
 A B C D E

LEFT SIDE USB3.0 PORT X2

11/07 Change source to SA00004KB00
+5VALW +USB_VCCA
U39
1 GND VOUT 8
1 C767 0.1U_0402_16V4Z 2 7 1
VIN VOUT
2 1 3 VIN VOUT 6
<42,46> USB_ON# USB_ON# 4 5 USB_OC1#
EN FLG USB_OC1# <18>
SY6288DCAC_MSOP8 1
C904
Low Active 2A @ 1000P_0402_50V7K
2 +USB_VCCA
C814 220U_6.3V_M
1 2

+
For EMI request 1 2
C816 470P_0402_50V7K
USB2.0 choke --> SM070000I00
USB3.0 Choke --> SM070001U00
JUSB1
USB30_TX_P3 C299 1 2 0.1U_0402_10V6K USB30_TX_C_P3 R1157 1 2 0_0402_5% USB30_TX_R_P3 9
<18> USB30_TX_P3 SSTX+
1 VBUS
L68 USB30_TX_N3 C300 1 2 0.1U_0402_10V6K USB30_TX_C_N3 R1156 1 @ 2 0_0402_5% USB30_TX_R_N3 8
<18> USB30_TX_N3 SSTX-
USB30_RX_N3 2 1 USB30_RX_R_N3 USB20_N2 R1162 1 2 0_0402_5% USB20_N2_R 2
2 1 <18> USB20_N2 D-
@ 7 GND
USB20_P2 R1163 1 @ 2 0_0402_5% USB20_P2_R 3 10
<18> USB20_P2 D+ GND
USB30_RX_P3 3 4 USB30_RX_R_P3 USB30_RX_P3 R1155 1 2 0_0402_5% USB30_RX_R_P3 6 11
3 4 <18> USB30_RX_P3 SSRX+ GND
2 @ 4 GND GND 12 2
WCM-2012-900T_4P USB30_RX_N3 R1154 1 @ 2 0_0402_5% USB30_RX_R_N3 5 13
<18> USB30_RX_N3 SSRX- GND
L70 @ OCTEK_USB-09EAEB
USB30_TX_C_N3 2 1 USB30_TX_R_N3
2 1
For ESD request ME@
USB30_TX_C_P3 3 4 USB30_TX_R_P3
3 4 D27 D24
@ @
WCM-2012-900T_4P USB30_RX_R_N3 9 10 1 1USB30_RX_R_N3 USB20_N2_R 3 6
I/O2 I/O4
L72 USB30_RX_R_P3 8 9 2 2 USB30_RX_R_P3
USB20_N2 2 1 USB20_N2_R
2 1 USB30_TX_R_N3 7 7 4 4 USB30_TX_R_N3 2 GND VDD 5 +5VALW
USB20_P2 3 4 USB20_P2_R USB30_TX_R_P3 6 6 5 5 USB30_TX_R_P3
3 4
WCM-2012-900T_4P 3 3 1 4 USB20_P2_R +USB_VCCA
I/O1 I/O3
8 1 2
AZC099-04S.R7G_SOT23-6 C825 470P_0402_50V7K

L69 YSCLAMP0524P_SLP2510P8-10-9
USB30_RX_N4 2 1 USB30_RX_R_N4
2 1

USB30_RX_P4 3 4 USB30_RX_R_P4 JUSB2

3 4 USB30_TX_P4 C292 1
3 <18> USB30_TX_P4 2 0.1U_0402_10V6K USB30_TX_C_P4 R1161 1 2 0_0402_5% USB30_TX_R_P4 9 SSTX+ 3
WCM-2012-900T_4P 1
USB30_TX_N4 C296 1 VBUS
<18> USB30_TX_N4 2 0.1U_0402_10V6K USB30_TX_C_N4 R1160 1 @ 2 0_0402_5% USB30_TX_R_N4 8 SSTX-
L71 USB20_N3 R1164 1 2 0_0402_5% USB20_N3_R 2
<18> USB20_N3 D-
USB30_TX_C_N4 2 1 USB30_TX_R_N4 @ 7
2 1 USB20_P3 R1165 1 @ GND
<18> USB20_P3 2 0_0402_5% USB20_P3_R 3 D+ GND 10
USB30_RX_P4 R1159 1 2 0_0402_5% USB30_RX_R_P4 6 11
<18> USB30_RX_P4 SSRX+ GND
USB30_TX_C_P4 3 4 USB30_TX_R_P4 @ 4 12
3 4 USB30_RX_N4 R1158 1 @ GND GND
<18> USB30_RX_N4 2 0_0402_5% USB30_RX_R_N4 5 SSRX- GND 13
WCM-2012-900T_4P
@ OCTEK_USB-09EAEB
L73
USB20_N3 2 1 USB20_N3_R ME@
2 1
For ESD request
USB20_P3 3 4 USB20_P3_R
3 4 D39 D40
@ @
WCM-2012-900T_4P USB30_RX_R_N4 9 10 1 1 USB30_RX_R_N4 USB20_P3_R 3 6
I/O2 I/O4
USB30_RX_R_P4 8 9 2 2 USB30_RX_R_P4
USB30_TX_R_N4 7 7 4 4 USB30_TX_R_N4 2 5 +5VALW
GND VDD
USB30_TX_R_P4 6 6 5 5 USB30_TX_R_P4

3 3 1 4 USB20_N3_R
I/O1 I/O3
8
4 AZC099-04S.R7G_SOT23-6 4

YSCLAMP0524P_SLP2510P8-10-9

Security Classification Compal Secret Data For EMI request Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title
USB3.0 ports
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 45 of 64
A B C D E
 5 4 3 2 1

+5VS +5V_CHGUSB
Right side USB Charger +3VS

U68 ACES_88514-3001
PWRSHARE_EN# 1 8 CHG_ON# 30 32
CEN# CB CHG_ON# <42> 30 GND
29 29 GND 31

1
USB20_N0_C 2 7 28
DM TDM USB20_N0 <18> 28

SLG55566
R1394 27
USB20_P0_C 100K_0402_5% 27
3 DP TDP 6 USB20_P0 <18> 26 26
CHG@ 25
PLT_RST# 25
4 5 +5VALW 24

2
GND VDD <18,23,36,37,42> PLT_RST# 24
D 23 23
D
9 CLK_PCIE_CARD_PCH# 22
Thermal Pad <15> CLK_PCIE_CARD_PCH# 22

2
CLK_PCIE_CARD_PCH 21
C987 <15> CLK_PCIE_CARD_PCH 21
SLG55566VTR_TDFN8_2X2 20
CHG@ 0.1U_0402_16V4Z PCIE_PTX_C_DRX_N4 20
<15> PCIE_PTX_C_DRX_N4 19

1
CHG@ PCIE_PTX_C_DRX_P4 19
<15> PCIE_PTX_C_DRX_P4 18 18
17 17
11/07 Change source to SA00004KB00 PCIE_PRX_DTX_N4 16
<15> PCIE_PRX_DTX_N4 16
PCIE_PRX_DTX_P4 15
+5VALW +5V_CHGUSB <15> PCIE_PRX_DTX_P4 15
14 14
U69 USB20_P0_C 13
USB20_N0_C 13
1 GND VOUT 8 12 12
C988 0.1U_0402_16V4Z 2 7 11
VIN VOUT 11
2 1 3 VIN VOUT 6 <15> CPPE# 10 10
<42,45> USB_ON# USB_ON# 4 5 USB_OC0# 9
EN FLG EXT_MIC_L 9
<41> EXT_MIC_L 8 8
SY6288DCAC_MSOP8 1 EXT_MIC_R 7
<41> EXT_MIC_R 7
C989 <41> MIC_JD MIC_JD 6
@ 1000P_0402_50V7K HP_OUTR 6
<41> HP_OUTR 5 5
Low Active 2A HP_OUTL 4
2 <41> HP_OUTL 4
SPDIF_OUT 3
<41> SPDIF_OUT 3
<41> PLUG_IN PLUG_IN 2 2
1 1
+5VALW +5V_CHGUSB NOCHG@ JP21
C C
USB20_N0 R1167 1 2 0_0402_5% USB20_N0_C ME@
1

USB20_P0 R1166 1 2 0_0402_5% USB20_P0_C

R1395 NOCHG@
10K_0402_5% R1396 12/23 Change to SP010011A00 for ASSY issue
@ 470_0603_5% CB Function
@
2

1 2

D L auto detection charger identification active

PWRSHARE_EN# 2 PWRSHARE_EN# H DP/DM=TDP/TDM
G
S Q140
3
1

2N7002_SOT23 USB2.0/3.0 choke and ESD diode at sub-B.

R1397 @
10K_0402_5%

CHG@
Right USB Conn.(Cable)
2

+USB_VCCB
W=80mils JUSB3
1 1
150U_B2_6.3VM_R35M 1 R1109 1 2 0_0402_5% USB20_N9_R 2
<18> USB20_N9 2
C911 1 R1108 1 2 0_0402_5% USB20_P9_R 3
+ <18> USB20_P9 3
4 4
C766 5 G5

2
470P_0402_50V7K WCM-2012-900T_4P

PJDLC05_SOT23-3
B 6 B
Right side USB3.0 port (Option) 2 2 USB20_N9 4 4 3 3 USB20_N9_R D49
@
G6
ACES_85205-04001
ME@
AC CAP reserve on SUB/B USB20_P9 1 2 USB20_P9_R
JP23 1 2
1 L64
1
<18> USB30_TX_P1 2 2
3 @

1
3
<18> USB30_TX_N1 4 4
5 5 11/07 Change source to SA00004KB00
6 6
7 +5VALW +USB_VCCB
<18> USB30_RX_P1 7
8 U40
8
<18> USB30_RX_N1 9 9 1 GND VOUT 8
10 C768 0.1U_0402_16V4Z 2 7
10 VIN VOUT
11 GND 2 1 3 VIN VOUT 6
12 <42,45> USB_ON# USB_ON# 4 5 USB_OC4#
GND EN FLG USB_OC4# <18>
SY6288DCAC_MSOP8 1
ACES_50463-0104A-001 C909
@ 1000P_0402_50V7K
Low Active 2A 2
ME@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio B Conn/USB charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 46 of 64
5 4 3 2 1
ON/OFF switchSW 2 Power Button/B link to Function/B Conn. 10pin KB Lighting CONN.4pin
1 3 +3VLP +3VALW

Power Button 2 4 JP12

2
SMT1-05_4P @ +VCC_KB_LED 1
100K_0402_5% 100K_0402_5% 1
2

0.1U_0402_10V6K
6
5
+3VALW +5VALW +5VS 2

C905
R1116 R1115 2 3 3
4
TOP Side @ J7 4

1
1 2 R60 0_0402_5% @ 5
1 GND
1 2 6 GND

2
SHORT PADS
Bottom Side @ JOINT_F1017W R-S-04P
D53 JP10
R1398 R1399 ME@
3 ON/OFF 100K_0402_5% 100K_0402_5% 1
ON/OFF <42> 1 +5VS
ON/OFFBTN# 1 2

1
@ 51_ON# 2
2 51_ON# <49> 3 3
4 +5VALW
<42> MUTE_BTN# 4 +VCC_KB_LED
DAN202UT106_SC70-3 <42> MUTE_LED# 5 5 Q121
<42> ONEKEY_BTN# 6 6

1
D 7 7

D
NOVO_BTN# 8 8 11/07 change to +5VALW 3 1
EC_ON 2 <42,44> PW R_LED# 9 R1229
<42,52> EC_ON 9
G ON/OFFBTN# 10 10K_0402_5% AO3413_SOT23-3
10 KBL@

C906
Q95 S @ 11 13 KBL@ KBL@

G
1

10U_0603_6.3V6M
2

2
11 GND
2

2N7002_SOT23-3 9/23 ESD Request 12 12 GND 14

R1112 1 R1232 2 C908
1
@ 10K_0402_5% C551 E-T_6712K-F12N-02L 100K_0402_5% 0.1U_0402_16V4Z
2 1

KBL@
ME@ KBL@ 1 KBL@
100P_0402_50V8J
1

2 C907
+3VLP +3VALW NOVO_BTN# ON/OFFBTN# 0.01U_0402_16V7K
2

1
2

D54

OUT
100K_0402_5% R1118 PJSOT24C 3P C/A SOT-23 11/07 Change type to 0603
R1117 100K_0402_5% @
@ <42> LED_KB_PW M_R 2
D56 IN

GND
1

1
NOVO# 2
<42> NOVO#
1 NOVO_BTN# Q122
51_ON# 1 @ 2 3 DTC124EKAT146_SC59-3
<49> 51_ON#

3
R14 0_0402_5% KBL@
R19 0_0402_5% EMI REQUEST 1ST = SCA00000E00
ON/OFF 1 DAN202UT106_SC70-3
2
2ST = SCA00000R00

Security Classification Compal Secret Data Compal Electronics,Ltd.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
other IO connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 47 of 64
 A B C D E

7/26 change SI4800 to SI2301

+5VALW TO +5VS +3VALW TO +3VS +1.5V to +1.5VS
11/07 Change type to 0603 11/07 Change type to 0603 +1.5V +1.5VS
11/07 Change type to 0603
+5VALW

S
+5VS +3VALW +3VS

D
3 1
U46 U47 1 1 1

1
8 1 8 D 1 Q120
D S S C856 C857 C835

G
1 7 2 1 1 1 7 D S 2 1 1

2
D S

1
6 3 6 D 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V4Z R1119
C836 D S C837 C838 C839 S 3 C840 C841 2 2 2 470_0603_5%
5 D G 4 5 D G 4
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V4Z R1113 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V4Z R1084 SI2301BDS-T1-E3_SOT23-3 @

2
1 2 2 2 2 1
DMN3030LSS-13_SOP8L-8 470_0603_5% DMN3030LSS-13_SOP8L-8 2 2 470_0603_5%
@ @

1 2

1 2

1
+VSB +VSB +3VALW D
D D
2 SUSP
2 SUSP 2 SUSP G

1
G G S Q98

3
S Q96 S Q97 2N7002_SOT23

3
R1085 2N7002_SOT23 R1086 2N7002_SOT23 100K_0402_5% @
150K_0402_5% @ 470K_0402_5% @ R1087

2
5VS_GATE2 R1088 15VS_GATE_R 2 R1090 1 1.5VS_GATE

2
1 1 Q101 0_0402_5% 1 1
1

1
D 82K_0402_5% D R1089 D C844 C845
SUSP 2 Q99 C842 SUSP 2 Q100 0_0402_5% C843 SUSP# 2
G 2N7002_SOT23 0.01U_0603_50V7K G 2N7002_SOT23 0.01U_0603_50V7K G 0.1U_0402_25V6 0.1U_0402_25V6
S 2 S @ 2 2N7002_SOT23S 2 2
3

3
+RTCVCC +5VALW
J20 +5VALW
+3VALW TO +3V_DSW +3VALW 1 1 2 2 +3V_DSW
+3V_DSW to +3V_PCH +5VALW to +5V_PCH

1
11/07 Change type to 0603

1
@
+3VALW +3V_DSW JUMP_43X79 R1096 R1097 @
@

U48 220K_0402_5% 100K_0402_5% R1098

2 8 1 +3V_DSW +3V_PCH +5VALW +5V_PCH 100K_0402_5% 2
J11 J14

2
D S
10U_0603_6.3V6M

7 D SUSP
1 S 2 1 1 <10,53,55> SUSP

2
1
1U_0603_10V4Z

6 D SYSON#
S 3
1 2 1 2
1 2 1 2
C848

C846

C847 5 4 Q107 Q108

10U_0603_6.3V6M D G

1
R1100

@
DTC124EKAT146_SC59-3 DTC124EKAT146_SC59-3
2 DMN3030LSS-13_SOP8L-8 2 2 470_0603_5% JUMP_43X79 JUMP_43X79 @

OUT

OUT
@
1 2

@+VSB @ @ AO3413_SOT23 AO3413_SOT23

D SYSON
<10,42,53,55,56> SUSP# 2 IN <42,53> SYSON 2 IN

D
@ 2 PCH_PWR_EN# 3 1 3 1

GND

GND
1

1
G 1 1
S Q110
3

R1106 2N7002_SOT23 Q148 DS3@ C38 Q149 DS3@ C39 R1101

G
2

3
47K_0402_5% @ 10U_0603_6.3V6M 10U_0603_6.3V6M @ 100K_0402_5%
2 2
DS3@ DS3@
2

2
2

@ 1
1

D R1107
PCH_PWR_EN# 2 Q116 C851
G
0_0402_5%
2
0.1U_0402_25V6
<42> PCH_PWR_EN# <16> PM_SLP_SUS
+3VS to +3VS_VGA
@ S 2N7002_SOT23 @ @
3

+3VS +3VS_VGA
J10

09/05 add for Deep S3 1 1 2 2

@
+5VALW JUMP_43X79
3 +1.5V +1.05VS +3VALW 3

AO3413_SOT23 OPT@

1
1

D
3 1 2 1

1
R1449

1
R1092 R1095 R6 47K_0402_5% C37 10U_0603_6.3V6M
470_0603_5% 470_0603_5% @ OPT@ OPT@ Q145 OPT@

G
100K_0402_5%

2
@ @ R1451 R1450
<25,53> DGPU_PWR_EN#
1 2

1 2

1 2 470_0603_5%

2
D D R1452 10K_0402_5% @
<55> 0.75VR_EN#

1 2
1
D

C1011
2 SYSON# 2 SUSP 0_0402_5% @

DMN66D0LDW-7 2N_SOT363-6
3 1 D
Q143B

0.1U_0402_10V7K
G G 2 1 2 Q146 R1453
<18,23> DGPU_PWR_EN
S Q103 S Q106 G 2N7002_SOT23 2 2 1 DGPU_PWR_EN#
3

2N7002_SOT23 2N7002_SOT23 S OPT@ G 10K_0402_5%

3
2
@ @ <54,55> +V1.05S_VCCP_PWRGOOD 2 10.75VR_EN 5 S Q147

3
1

OPT@
2N7002_SOT23
R8 @ @
DMN66D0LDW-7 2N_SOT363-6

100K_0402_5% R1454
+1.8VS +0.75VS

@ C1012
@ 100K_0402_5% 1
6

0.1U_0402_10V7K
OPT@

2
@
1

SUSP 2
2
R1091 R1094
Q144A

470_0603_5% 22_0603_5%
1

@
1 2

1 2

2 1 CPU1.5V_S3_GATE <10,42,55>
D D @ R91 0_0402_5%
4 4
2 SUSP 2 2 1 SUSP
G G R92 0_0402_5%
S Q102 S Q105
3

2N7002_SOT23 2N7002_SOT23
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
For Intel S3 Power Reduction. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 48 of 64
A B C D E
 5 4 3 2 1

DC030006J00 VIN

PF101 PL101
12A_65V_451012MRL SMB3025500YA_2P
4 APDIN 1 2 APDIN1 1 2
4
3
3

1000P_0402_50V7K

1000P_0402_50V7K
100P_0402_50V8J

100P_0402_50V8J
2
2

1
D D
1 1

2
@ 4602-Q04C-09R 4P P2.5

PC101

PC102

PC103

PC104
JDCIN1

VIN

LL4148_LL34-2
2
PD103 @
PD104 @

1
C LL4148_LL34-2 PJ101 51ON-1 C

BATT+ 2 1 @ JUMP_43X39

1
68_1206_5%

68_1206_5%
1 1
2 2

PR118 @

PR119 @
PQ104 @
PR125 @ TP0610K-T1-E3_SOT23-3

2
200_0402_1%
1 2 51ON-2 3 1
VS
0.22U_0603_25V7K
1

100K_0402_1%
PR123 @

PC112 @

@ 0.1U_0603_25V7K
2

PC113
1

PR124 @ 2
2

22K_0402_1%
1 2 51ON-3

+3VLP
<47> 51_ON#
- JRTC1 + PR129
560_0603_5%
PR130
560_0603_5%
PD107
2 1 1 2 1 2 2 1 +RTCBATT

RB751V-40_SOD323-2
2

0_0402_5%

@ MAXEL_ML1220T10 1 2 +CHGRTC
+CHGRTC
PR126

PD108
@ PU101 PR128 RB751V-40_SOD323-2
@ 200_0603_5%
RTC Battery
1

APL5156-33DI-TRL_SOT89-3
3.3V
2

3 2 CHGRTCIN
B VOUT VIN B
1

GND PC115
PC114 1U_0805_25V6K
10U_0603_6.3V6M 1
@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/30 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3
Date: Monday, January 16, 2012 Sheet 49 of 64
5 4 3 2 1
 5 4 3 2 1

VMB2 VMB
PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
1 1 1 2 1 2 BATT+
2
2 EC_SMCA
3 3
4 EC_SMDA
4
5 5

1
D D
6 6

1
7 PC201 PC202
7

100_0402_1%

100_0402_1%
8 1000P_0402_50V7K 0.01U_0402_25V7K

2
GND
9
GND PR201

PR202
@ SUYIN_200082GR007M229ZR
2

PH201 under CPU botten side :

EC_SMB_CK1 <42,51> CPU thermal protection at 92+-3 degree C
Recovery at 56 +-3 degree C
EC_SMB_DA1 <42,51>

1 2 +3VALW
VL
PR203 +3VLP

0.1U_0603_25V7K
6.49K_0402_1%
<42,51> ADP_I

21.5K_0402_1%
PR205

1
9.1K_0402_1%

13.7K_0402_1%
PC203

1
PR206 @

PR207
1 2 BATT_TEMP <42> A/D 4.42K:90W

PR205
PR204

2
10K_0402_5% 9.1K:120W
+3VS

2
PU201

2
1 8 NTC_V-1
VCC TMSNS1

100K_0402_1%
C OTP_N_002 C
2 GND RHYST1 7 2 1
PR208

PR209
3 6 Turbo_V-1 10K_0402_1%
<6,42> H_PROCHOT# OT1 TMSNS2

2
0_0402_5%

0_0402_5%
PR230 @

PR231 @
ADP_OCP_2 1

100K_0402_1%_NCP15WF104F03RC
4 5 2

1
OT2 RHYST2

PH201
1

2
D

10K_0402_1%
G718TM1U_SOT23-8 PR210

PR211
PQ201 2 ADP_OCP_1
PR210 82.5K_0402_1% +3VALW

OTP_N_003
2N7002KW_SOT323-3 G +3VALW PR233 @

1
S 27.4K:90W

2
47K_0402_1%

1
PR212 @
0_0402_5% PR213
82.5K:120W 2 1 PR232
2 1
<42> PROCHOT 1 2 2 1 PR234
MAINPWON <42,52>
0_0402_5% 47K_0402_1%
0_0402_5% 2 1
+3VLP
+3VLP PR235 @
PR236 @
47K_0402_1%
47K_0402_1% 2 1
2 1

<42>
Turbo_V

<42>
NTC_V
B B

P2
PQ202
+3VLP +3VALW
0.01U_0402_25V7K

TP0610K-T1-E3_SOT23-3
1

100K_0402_1%

100K_0402_1%
PC204

B+ 3 1 +VSBP
2

VMB2

100K_0402_1%
PR214

PR215

0.22U_0603_25V7K
2

1
PR216

PC205
PR217 PR218
2

768K_0402_1% 10M_0402_5% PC206

1

1 2 0.1U_0603_25V7K
BATT_OUT <51>

2
PR219 PQ203

2
10K_0402_1% 2N7002KW_SOT323-3 PR220
8

1 2 VL 22K_0402_1%
1

D
3 1 2
P

+
1 2
O
2

PR221 2 G
-
G
2

221K_0402_1% PU202A S PR222 @

3

AS393MTR-E1 SO 8P OP 100K_0402_1%
4

+3VLP PR228 @ PR224 PQ205

1

0_0402_5% 1K_0402_1% D PJ201

1

2N7002KW_SOT323-3 @ JUMP_43X39
<52> SPOK 1 2 1 2 2
100K_0402_1%

2 1 G 1 1
+CHGRTC +VSBP 2 2 +VSB
2

1U_0402_6.3V6K

PR229 S
3
1
PR226

PC207

PR223 @ 0_0402_5%
10K_0402_1% 1 2
<42> PCH_PWR_EN
2

2 1 2VREF_8205
1

A PQ204 A
PR227
1

PR225 D 2N7002KW_SOT323-3
10K_0402_1% 2 1 2
<42> BATT_LEN#
G
10K_0402_1% S
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/06/30 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3
Date: Monday, January 16, 2012 Sheet 50 of 64
5 4 3 2 1
 5 4 3 2 1

P3
B+
P2

PQ301 PQ302
SI4459_SO8 SI4459_SO8
PR301
VIN 8
7
1
2
1
2
8
7 0.01_1206_1% PL301 CHG_B+
6 3 3 6 FBMA-L11-201209-121LMA50T_0805
5 5 1 4 1 2 PQ303
SI4459_SO8

1000P_0603_50V7K
2 3 1 8

4
D D
2 7

2
PC323
PC301

1000P_0603_50V7K
3 6

2200P_0402_50V7K
PQ304 5600P_0402_25V7K 5

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
47K_0402_5%

1 2

1
1

2
PC302
200K_0402_1%
0.1U_0603_25V7K

PC307

4
1
PR302

PC304

PC305

PC306
DTA144EUA_SC70-3 DISCHG_G
3

PC303

PR303
1 2

1
PR304
PC322 @ 47K_0402_1%
2

2
2 0.1U_0603_25V7K 1 2

2
ACN VIN

2ACOFF-1

1SS355_SOD323-2
2
1

ACP PR305

1DISCHG_G-1
10K_0402_1%
1

2
PD302
P2-1 PR306

0.1U_0603_25V7K

1
2 200K_0402_1%
PQ305 PQ306

1
PC308 PC309 DTC115EUA_SC70-3

1
DTC115EUA_SC70-3 +3VALW P
PR307 <52> ACPRN PD303
1 2 2 1
3

20K_0402_1% 1SS355_SOD323-2
0.1U_0603_25V7K

100K_0402_1%
2 1 2
1 2
6

@ 10K_0603_1%
PQ308
1

1
D

PR309 @
2N7002KW _SOT323-3 PC310 PQ309
150K_0402_1%

2
PR308

PR310
PQ307A 2 2N7002KW _SOT323-3
BATT_OUT <50>
2 2N7002KDW -2N_SOT363-6 G 0.1U_0603_25V7K

1
D

0.1U_0603_25V7K
S
3

2 1 2 PACIN
1

1
PC311
VIN PR311 @ PR312 @ G

1
C C
2 1 1 2 S

3
4.7M_0603_1% P2
390K_0603_1%

2
1
P2-2

39.2K_0402_1% PQ310

5
6
7
8
PR313
2N7002KDW-2N_SOT363-6

1
PR328

TPC8037-H 1N SO8
3
PQ307B

10_1206_5%

ACOK

CMPIN

CMPOUT

ACP

ACN
PR316 PR317 <42,50> ADP_I 1 2
2

47K_0402_1% 64.9K_0603_1% 21
PACIN TP
PACIN 1 2 5 1 2 6 ACDET PC313 4

PC321 @ .1U_0603_25V7K PC312 20 1 2

4

VCC PL302
ACON 2 1 1 2 7 IOUT
PR329 PR318

3
2
1
1U_0603_25V6
1

PQ311 0_0402_5% 100P_0603_50V8 19 4.7UH_PCMB104E-4R7MS_10A_20% 0.01_1206_1%

PHASE
DTC115EUA_SC70-3 <42,50> EC_SMB_DA1 1 2 8 SDA
PU301 BATT+
PR330 BQ24737RGRR_VQFN20_3P5X3P5 LX_CHG 1 2 CHG
1 4
PR319 0_0402_5% 18 DH_CHG
HIDRV

5
6
7
8
1 2ACOFF-12 <42,50> EC_SMB_CK1 1 2 9 2 3
<42> ACOFF SCL

1
10K_0402_5% PR322 PC314 PQ312

4.7_1206_5%
PR320
PR321 2.2_0603_5% 0.047U_0603_50V7
1

BST_CHG

10U_0805_25V6K

10U_0805_25V6K
1 2 10 17 1 2 2 1

TPC8A03-H 1N SO8
+3VALW P ILIM BTST
1

16251_SN
PR323 147K_0402_1% PD301
3

RB751V-40_SOD323-2

LODRV
0_0402_5% 4

1
PC315

PC316
PR324 16 2 1

GND
SRN

SRP
REGN
BM
100K_0402_1%
2N7002KW_SOT323-3
2

2
PQ313

680P_0603_50V7K
BQ24737_VDD
11

1 12

1 13

14

15

3
2
1
1

PC318
6.8_0603_5%

2
1
10_0603_5%
<50> BATT_OUT 2
<42> BM#
PR326

PR325
G PC317
10K_0402_5%

S 1U_0603_25V6
3

2
2
PR327 @

B B
2

PC319 DL_CHG
0.1U_0603_25V7K
2 1
1

+3VS PC320
0.1U_0603_25V7K
2

BQ24737_VDD

PR337
10K_0402_1%
1

1
1 2 ACIN <16,42>
PR336
PR335 10K_0402_1%
47K_0402_1%
PACIN
2

2N7002KW_SOT323-3

1
PQ316
1

ACPRN <52> D PR339

2
G 12K_0402_1%
S 2
3

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/06/30 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 51 of 64

5 4 3 2 1
 5 4 3 2 1

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205 PJ402
+3VALW P 2 2 1 1 +3VALW
@ JUMP_43X118

1U_0603_10V6K
D D

1
PJ403

PC401
+5VALW P 2 1 +5VALW

2
2 1
@ JUMP_43X118

PR401 PR402
13K_0402_1% 30K_0402_1%
1 2 1 2

PR403 PR404
RT8205_B+ 20K_0402_1% 20K_0402_1% RT8205_B+
1 2 1 2
PJ401 Typ: 175mA
B+ 2 1 +3VLP
0.1U_0603_25V7K

2 1

ENTRIP2

ENTRIP1
@ JUMP_43X118 PR405 PR406
PC402

2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0603_25V7K

0.1U_0603_25V7K
4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

154K_0402_1% 88.7K_0402_1%
PC403

PC410
1 2 1 2

4.7U_0805_10V6K
1

1
PC404

PC405

PC406

PC407

PC408

PC409
2

8
7
6
5

5
6
7
8
PU401 PQ402
2

2
TPC8037-H 1N SO8

PC411

ENTRIP2

FB2

TONSEL

FB1

ENTRIP1
REF
1
C PQ401 C
25 P PAD
AO4466L_SO8

2
4 4
7 VO2 VO1 24
SPOK <50>
8 23 PR408 PC413
PR407 VREG3 PGOOD 2.2_0603_5% 0.1U_0603_25V7K
1
2
3

3
2
1
1 2 1 2 BST_3V 9 BOOT2 BOOT1 22 BST_5V 1 2 1 2
2.2_0603_5%
PL401 PC412 UG_3V 10
VFB=2.0V 21 UG_5V PL402
3.3UH +-20% PCMC063T-3R3MN 6A 0.1U_0603_25V7K UGATE2 UGATE1 4.7UH_VMPI1004AR-4R7M-Z01_10A_20% +5VALWP
1 2 LX_3V 11 20 LX_5V 1 2
+3VALWP PHASE2 PHASE1
1

8
7
6
5

1
LG_3V LG_5V
4.7_1206_5%

12 19

4.7_1206_5%
LGATE2 LGATE1

5
6
7
8
PQ403
PR409

PR410
SKIPSEL
AO4712_SO8

VREG5
PQ404

GND

150U_B2_6.3VM_R45M

150U_B2_6.3VM_R45M
VIN
RT8205LZQW _W QFN24_4X4

NC
EN
1 1
150U_B2_6.3VM_R45M

2
4

@ 1U_0603_10V6K
1

1
+ +

PC417

PC415

PC418
4

13

14

15

16

17

18
1

1
+ PR411
PC414

PC416
680P_0603_50V7K

499K_0402_1% TPC8A03-H 1N SO8

680P_0603_50V7K

2
2 2

PC419
1 2
2

1
2
3

2
2
B+

3
2
1
1
100K_0402_1%

1U_0603_10V6K
VL

1
PC420

1
PR412

PC421
Typ: 175mA

4.7U_0805_10V6K
B B

2
ENTRIP1 ENTRIP2
2

2
PQ405B RT8205_B+
6

2N7002KDW -2N_SOT363-6
PR419
PQ405A 0_0402_5% RT8205

0.1U_0603_25V7K
2N7002KDW -2N_SOT363-6 2 5 2 1
2VREF_8205 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)

PC422
PR420 @ (2)SMPS2=375KHZ(+3VALWP)
1

PR413 0_0402_5% TPS51125A

2
0_0402_5% 2 1 TONSEL=VREF (1)SMPS1=245KHZ (+5VALWP)
<42,50> MAINPW ON 2 1
VL
PR421 @ (2)SMPS2=305KHZ(+3VALWP)
PR414 0_0402_5%
PR418 100K_0402_1% 2 1
<42,47> EC_ON 2.2K_0402_5% 2 1
2 1
VL

+3.3VALWP Imax=7.5A ; Ipeak=9A +5VALWP Imax=11.1A ; Ipeak=13.32A

1/2 Delta I=1.113A (F=375K Hz) 1/2 Delta I=1.33A (F=300K Hz)
1

Vtrip=0.169V Vtrip=0.098V
PQ407 @
PR415 @ 2N7002KW _SOT323-3
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Rds(on)=7.0m ohm(max) ; Rds(on)=5.1m ohm(typical)
D
1

200K_0402_1% Ilimit_min=0.169/18m=9.388A Ilimit_min=0.098/7m=14.03A

> ACPRN PQ406
2 1 2
G VS 1 2 2
DTC115EUA_SC70-3
Ilimit_max=0.169/15=11.26A Ilimit_max=0.098/5.1m=19.21A
S PR416 @ Iocp=Ilimit+1/2Delta I=10.5A~12.373A Iocp=Ilimit+1/2Delta I=15.36A ~ 20.54A
402K_0402_1%

4.7U_0603_10V6K
3

A A
1
PR417 @

100K_0402_1%
1

PC423

3
2

42,47> EC_ON
2

2
PQ408
@ DTC115EUA_SC70-3
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/12/31 Title

3VALWP/5VALWP
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3
Date: Monday, January 16, 2012 Sheet 52 of 64
5 4 3 2 1
 A B C D

PJ501
1.5V_B+ 2 2 1 1 B+
Freq= 266~314KHz , 290KHz(typ)

470P_0603_50V7K
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
5
6
7
8
PQ501 @ JUMP_43X118

1
PC502

PC503

PC504

PC505

PC526
TPC8037-H 1N SO8 PL503
Iocp=13.58A~23.10A 1 2

2
FBMA-L11-160808-121LMA30T_0603
4
PR501
0_0402_5%
1 2
<42,48> SYSON

3
2
1
2
47K_0402_5%
PR503 PC506 PL501

.1U_0402_16V7K
1 1

PC501 @
PR502
PU501 2.2_0603_5% 0.22U_0603_16V7K 1UH +-20% PCMB104T-1R0MH 18A
+1.5VP

1
1 10 BST_1.5V 1 2BST_1.5V-1 1 2 1 2
PGOOD VBST
2 9 DH_1.5V

2
TRIP DRVH
LX_1.5V

4.7_1206_5%
3 EN SW 8

PR504 @
1

5
6
7
8
PQ502

220U_6.3V_M
4 VFB V5IN 7 +5VALW +

PC508
1
5 6 DL_1.5V TPC8A03-H 1N SO8
RF DRVL PC507

84.5K_0402_1%

2
1
1U_0603_10V6K 2

470K_0402_1%
11

2
TP

2
PR505

1000P_0603_50V7K
4

PC510 @
TPS51212DSCR_SON10_3X3 PJ502 +1.5V

1
PR506
VFB=0.7V +1.5VP 2 2 1 1

2
@ JUMP_43X118

3
2
1

2
PR507
1 2 PL504
FBMA-L11-201209-121LMA50T_0805
11.5K_0402_1%
1.5VSP_VGA_B+ 1 2 B+
1

PQ503

470P_0603_50V7K
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
5

1
PC511

PC512

PC513

PC514

PC527
PR509

TPCA8065-H_PPAK56-8-5
PR522 10K_0402_1% +5VS
2
0_0402_5% 2
2

2
7> FBVDDQ_PWR_EN 1 2

100K_0402_1%
4
1.5V_VGA_PWROK

PR510 1
PR523

@ 0_0402_5%
1 2
10,42,48,55,56> SUSP#

3
2
1
2
2
PR512 @
47K_0402_5%

PR511 PC516 PL502

.1U_0402_16V7K
PC515 @

PU502 2.2_0603_5% 0.22U_0603_16V7K 1UH_PCMC063T-1R0MN_11A_20%

+1.5VSP_VGA
1

1 10 BST_1.5VSP_VGA
1 2BST_1.5VSP_VGA-1
1 2 1 2
PGOOD VBST
2 9 DH_1.5VSP_VGA
1

TRIP DRVH PQ504

LX_1.5VSP_VGA

4.7_1206_5%
3 EN SW 8

PR513 @

220U_D2_4VY_R15M
1

0.1U_0402_10V7K
4 7 +5VALW

TPCA8057-H 1N PPAK56-8
VFB V5IN

2
+

PC518
5 6 DL_1.5VSP_VGA
RF DRVL

PC519
75K_0402_1%

PC517

1
1

1U_0603_10V6K 2
470K_0402_1%

11

2
TP
2
PR514

1000P_0603_50V7K
PC520 @
TPS51212DSCR_SON10_3X3 4 PJ504 +1.5VS_VGA

1
PR515

VFB=0.7V +1.5VSP_VGA 2 2 1 1
2

@ JUMP_43X118
1

2
3
2
1
PR517
PR516
0_0402_5%
1 2 2 1 VDDQ_SENSE <25>
1

3 3

11.5K_0402_1%
Freq= 266~314KHz , 290KHz(typ) PR518
10K_0402_1% PJ505
+1.05VS 2 1 +1.05VS_VGA
2

Iocp=12.25A~20.77A 2 1
@ JUMP_43X118
+1.05VS +1.05VS_VGA
PQ505
TPC8A03-H 1N SO8

10U_0805_25V6K
8 1
+5VALW

@ 470K_0603_5%
1U_0603_10V6K
10U_0805_25V6K

7 2

2
+5VALW 6 3
1
PC521

PC522

PC523

PR521
5
1

2
1

PR526

1
10K_0402_1% PR519
100K_0402_1% PR527 PQ507 @
2

1
@ 0_0402_5% D
PR520
2

2N7002KW _SOT323-3
1 2 2
PR524 1 2 <10,48,55> SUSP G
PQ506A

0_0402_5% S
2N7002KDW-2N_SOT363-6

2N7002KDW-2N_SOT363-6

3
1

<19,27,56> DGPU_PWROK 1 2 100K_0402_1%

PR528
6

3
PQ506B

PC524 @ 0_0402_5%
PR525 0.01u_0603_10V6K 1 2
2

@ 0_0402_5%
1 2 2 5
<10,42,48,55,56> SUSP# <25,48> DGPU_PWR_EN#
1

4
@ 1U_0603_10V6K
1
PC525

4 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/06/30 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP/1.5VSP_VGA/1.05VSP_VGA
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3
Date: Monday, January 16, 2012 Sheet 53 of 64
A B C D
 5 4 3 2 1

+3VS PR601
1K_0402_1%
2 1
VID [0] VID[1] VCCSA Vout PJ602
+VCC_SAP

100K_0402_5%
0 0 0.9V H_VCCSA_VID1 <10> +VCCSAP 1 2 +VCCSA

1
TDC 4.2A
0 1 0.8V PAD-OPEN 4x4m

PR602
Peak Current 6A
1 0 0.725V OCP current 7.2A

2 +VCCSA_PWRGD
H_VCCSA_VID0 <10>
1 1 0.675V
PR603
<42> SA_PGOOD
1K_0402_1%
output voltage adjustable network 2 1
D D
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that

+VCCSA_VID0
+VCCSA_VID1
+5VALW

+VCCSA_PWRGD
VCCSA VID is 00 prior to VCCIO stability.

1U_0603_10V6K
2

PC601
PR604 PR605
10_0402_1% 0_0402_5%

1
2 1 +VCCSA_EN 1 2 +V1.05S_VCCP_PWRGOOD <48,55>
PC602
2.2U_0603_10V7K
1 2

18

17

16

15

14

13
PU601
PR606 PC603

VID1

VID0
PGOOD

EN
V5FILT
V5DRV
2.2_0603_5% 0.22U_0603_16V7K
12 +VCCSA_BT 1 2+VCCSA_BT_1 1 2
BST PL601
19
PGND 0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
SW
11 +VCCSA_PHASE 1 2 +VCCSAP
20
PGND

22U_0805_6.3V6M

22U_0805_6.3V6M

0.1U_0402_10V7K
1
10

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
2200P_0402_50V7K
SW
2200P_0402_50V7K

21 PR607 @ @ @ @
0.1U_0603_25V7K

PGND

2
10U_0805_6.3V6M

10U_0805_6.3V6M
4.7_1206_5%

PC605

PC606

PC608

PC609

PC611

PC612
TPS51461RGER_QFN24_4X4

PC607

PC610
9
SW
22
PC614

1 2 2

1
VIN
2
PC613

PC615

PC616

8
SW

1
23 PC604
1

2 1 1 VIN 1000P_0603_50V7K
PJ601 7
+3VALW

2
SW
2 1 +VCCSA_PWR_SRC +VCCSA_PWR_SRC 24
2 1 VIN
C @ JUMP_43X118 25 C

COMP

MODE
TP

SLEW

VOUT
VREF
GND
1

6
@ PR608
2 1

33K_0402_5%
PC617 PR609
2 1 100_0402_5%
2 1
0.22U_0402_10V6K

0.01U_0402_25V7K
2
2 1 2 1
PR611

PC619
PC618 PR610 0_0402_5%

1
3300P_0402_50V7K 4.99K_0402_1% 2 1 +VCCSA_SENSE <10>

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/30 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VCCSAP/1.05S_VCCPP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3
Date: Monday, January 16, 2012 Sheet 54 of 64
5 4 3 2 1
 5 4 3 2 1

PJ707
2 2 1 1

@ JUMP_43X118
PL701 @ PU701 SY8033BDBC_DFN10_3X3 PL702

4
HCB1608KF-121T30_0603 1UH_PH041H-1R0MS_3.8A_20%
1 2 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+5VALW

PG
PVIN LX +1.8VSP
9 3

68P_0402_50V8J
PVIN LX

1
680P_0603_50V7K 4.7_1206_5%
1

1
PC701

PC702
8 SVIN
22U_0805_6.3VAM PR703

PR702
D D
6 20K_0402_1%

2
FB
5

22U_0805_6.3VAM

22U_0805_6.3VAM
1 2

2
EN

1
PJ701

NC

NC
TP
FB=0.6Volt +1.8VSP +1.8VS

PC704

PC705
2 2 1 1
<10,42,48,53,56> SUSP# PR701

PC703
11

2
1 2 EN_1.8VSP @ JUMP_43X118

2
0_0402_5%
+1.5V

0.1U_0402_10V7K
2

PC706 @
1.8VSP_FB PJ702

1
PR704 +0.75VSP 2 1 +0.75VS
2 1

1
1M_0402_5%

1
@ JUMP_43X118

2
PJ703 PR705

1
1
JUMP_43X118 10K_0402_1%
@ PJ704

2
2
2 2 1 1

2
PU702 @ JUMP_43X118
1 VIN NC 8 +3VALW +1.05VS_VCCPP PJ705 +1.05VS
PR724 @ 2 2
0_0402_5% PC707 1 1
2 GND NC 7

1
<10,42,48> CPU1.5V_S3_GATE 1 2 4.7U_0805_6.3V6K @ JUMP_43X118

1
3 6 PC708
PR706 VREF VCNTL

2
PR707 1K_0402_1% 4 5 1U_0603_10V6K
@ 0_0402_5% VOUT NC B+
<48> 0.75VR_EN# 1 2 9

2
TP

68U_25V_M_R0.36
C APL5336KAI-TRL_SOP8P8 1 C

PC709 @
PR708 +

0.1U_0402_16V7K
D
+0.75VSP

1
33K_0402_1% PQ701

10U_0603_6.3V6M
<10,48,53> SUSP 2N7002KW _SOT323-3

PC712
1K_0402_1%
1 2 2

10U_0603_6.3V6M
1

1
2

PR709

PC710

PC711
G

2
S
0.1U_0402_10V7K

2
1
PC713

PR710
<10,42,48,53,56> SUSP# 0_0402_5%
1 2
@ 10K_0402_1%

+3VS
2

+1.05VS_VCCPP OCP(min)=22.38A
@.1U_0402_16V7K
1
PR711

PC714

100K_0402_1%
2

PJ706
1

1.05VS_B+
PR712

100K_0402_1%

2 1

2200P_0402_50V7K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 1
B+
2

220P_0402_50V7K

0.1U_0402_25V6
@ JUMP_43X118
PR713

1
PR722 PQ702

PC716

PC717
1

5
0_0402_5% PR714 PC718

PC722

PC719

PC715
1 2 2.2_0603_5% 0.1U_0603_25V7K
<48,54> +V1.05S_VCCP_PWRGOOD
1

2
BST_1.05VS_VCCP
1 2 1 2
B B
17

16

15

14

13

PU703 4
10.7K_0402_1%

PAD

PGOOD

EN
MODE

BST
2

TPCA8065-H_PPAK56-8-5
PR715

1 12 LX_1.05VS_VCCP PL703
0.1U_0402_25V6

3
2
1
VREF SW 1UH +-20% PCMB104T-1R0MH 18A
+1.05VS_VCCPP
1

2 1
1
PC720

2 11 DH_1.05VS_VCCP
2

REFIN DH
2

1
PQ703
PR716

1000P_0603_50V7K 4.7_1206_5%
5
PC721
12K_0402_1%

TPCA8057-H 1N PPAK56-8
TPS51219RTER_QFN16_3X3

PR717
0.01U_0402_25V7K 1
1

330U_D2_2VM_R6M
PR723 3 10 DL_1.05VS_VCCP
GSNS DL

PC66
0_0402_5% +
1

2
<9> VSSIO_SENSE 1 2
4
2 3
4 VSNS V5 9 +5VALW
COMP

1
PGND

PC723
TRIP

GND

3
2
1

2
5

PC724
1

PR718
1 2 PC725
54.9K_0402_1%
2 PR719 1

<9> VCCIO_SENSE 1 2 1U_0603_10V6K

2
2
PR720 @

0.01U_0402_25V7K
0_0402_5%

A A
10_0402_1%
1000P_0402_50V7K
2
PC726

PR721
1

1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/06/30 Deciphered Date 2012/12/31 Title
2

10_0402_1%
PC727
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8VSP/0.75VSP/1.05VS_VCCPP
1000P_0402_50V7K Size Document Number Rev
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3
Date: Monday, January 16, 2012 Sheet 55 of 64
5 4 3 2 1
 A B C D

+VDD33MISC
PJ801 @
JUMP_43X118

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
1 2
1 2

2
GL1:0.9V(110000) +VGA_B+ PL801
GT:0.975V(101010) HCB4532KF-800T90_1812

PR851

PR852

PR853

PR854

PR855

PR856

PR857

PR858

PR859

PR860

PR861

PR862
1 2 B+

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

2200P_0402_50V7K
GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0

GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0
PQ801@GL1

1
PC801

PC803

PC804
PQ802@GL1

PC802
1 1

2
5

5
PQ807 PQ801

2
PR802 PR801 TPCA8065-H_PPAK56-8-5
0_0402_5% 0_0402_5%
1 2VRON_VGA 4 4

GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1

GPU_VID0
<23>

<23>

<23>

<23>

<23>

<23>
<18> NVDD_PWR_EN

1
PR803 @
0_0402_5% PR804 PC805
1 2 2.2_0603_5% 0.22U_0603_10V7K TPCA8065-H_PPAK56-8-5

3
2
1

3
2
1
<10,42,48,53,55> SUSP# BOOT2_VGA 2 1 BOOT2_2_VGA 1 2
PR815 @ 1 2 PL803
<23> DPRSLPVR_VGA 1 2 UGATE2_VGA 0.36UH_VMPI1004AR-R36M-Z03_30A_20% +VGA_CORE
PC806 @ .1U_0402_16V7K
0_0402_5% PHASE2_VGA 1 4
PR805
1 2 DPRSLPVR_VGA-1 PQ802 LF2_VGA 2 3 V2N_VGA

3.65K_0402_1%
2

1
2.2K_0402_1% PQ803

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

4.7_1206_5%

10K_0402_1%
TPCA8057-H 1N PPAK56-8

PR807 @
+3VS PR806 @ PR810

PR842

PR843

PR844

PR845

PR846

PR847

PR808
1 1 1

470U_D2_2VM_R9M
GPU_VID6

470U_D2_2VY_R9M

470U_D2_2VY_R9M
TPCA8057-H 1N PPAK56-8
1.91K_0402_1% 1_0402_1%

PR809
CLK_ENABLE#_VGA + + +

PC807

PC808

PC867
1 2
LGATE2_VGA 4 4
1.91K_0402_1%

2
1

2 2 2

SNUB2_VGA
PR811

PR814 PD801 @ VSUM-_VGA

3
2
1

3
2
1
0_0402_5% RB751V-40_SOD323-2
2

1 2 PR812 2 1 VSUM+_VGA ISEN2_VGA

2.2K_0402_1%
+3VS 1 2

680P_0402_50V7K
3> DGPU_PWROK

PC809 @

1
1 PR838 2
<23> DPRSLPVR_VGA 0_0402_5%

2
PR813 +VGA_CORE Under VGA Core
PSI#_VGA

2 2

147K_0402_1%
2 1 +VGA_CORE Near VGA Core
PC810
PR865 1U_0603_10V6K
40
39
38
37
36
35
34
33
32
31

@ 100K_0402_5% PU801 1 2
1 2
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

+3VS

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
RBIAS_VGA

22U_0805_6.3V6M

47U_0805_6.3V6M

4.7U_0805_6.3V6K
1

1
PC811

PC812

PC813

PC814

PC815

PC816

PC817

PC818
1 2 30 1 1

22U_0805_6.3V6M
<23,42> VGA_AC_DET BOOT2

1
PC819

PC820

PC821

PC822
29
PR864 @ UGATE2
1 28

2
0_0402_5% PGOOD PHASE2
2 27

2
PR863 470K_0402_5%_TSM0B474J4702RE PSI# VSSP2 2 2
3 26
RBIAS LGATE2
1 2 1 2 4 25
VR_TT# VCCP
5 24 +5VS
4.02K_0402_1% PH802 VW_VGA NTC PWM3
6 23
COMP_VGA VW LGATE1
7 22
FB_VGA COMP VSSP1
8 21

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K
FB PHASE1
1 2ISEN3_VGA 9
ISEN3
1

1
UGATE1

PC824

PC825

PC826

PC827

PC828

PC829

PC830

PC831

PC832

PC833

PC834

PC835
10
BOOT1
ISUM+

ISEN2
ISEN1

ISUM-
VSEN

IMON

PC823 1U_0603_10V6K
8.06K_0402_1%

VDD
1000P_0402_50V7K

RTN

VIN

22P_0402_50V8J 41
249K_0402_1%

2
AGND
2

1
PR816 @

PC836

ISL62883CHRTZ-T_TQFN40_5X5
PR817

11
12
13
14
15
16
17
18
19
20

PR818
2

499_0402_1% PC837
2FB1_VGA1
ISUM-_VGA

1 2
1

VDD_VGA
RTN_VGA

390P_0402_50V7K
PC838 PR820 PR819 @ 0_0402_5%

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K
33P_0402_50V8J 1.69K_0402_1% 1 2 +5VS PC818

1
VSEN_VGA

PC839

PC840

PC841

PC842

PC843

PC844

PC845

PC846
1 2 1 2
PR821 0_0402_5% PC825,PC827,PC828,PC829
11K_0402_1%
0.047U_0402_16V7-K
2

VIN_VGA 1 2 VGA_IMVP_IMON <42>

2
PC839,PC841,PC844,PC845
1
PC874

PR850

ISEN2_VGA +VGA_B+
1 2FB2_VGA1 2 PR823
ISEN1_VGA 1_0402_5%
2

3
PC847 PR822 1 2 +VGA_B+ 3
0.22U_0402_10V6K

0.22U_0402_10V6K

1
1

150P_0402_50V8J 267K_0402_1% +5VS

1

1
PC848

PC849

PC850

PC851
1U_0603_10V6K

0.22U_0603_25V7K

PR824 VSSSENSE_VGA <24>

30K_0402_1%
PQ806@GL1

2200P_0402_50V7K
2

PQ804
BOOT1_VGA

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
2

5
PQ808@GL1 PQ808

1
PC852

PC853

PC854

PC855
TPCA8065-H_PPAK56-8-5

2
VSUM+_VGA UGATE1_VGA 4 4
VSUM-_VGA
1 2
82.5_0402_5%

+VGA_CORE
PR826 @

PR827 PC856
1

PR825 2.2_0603_5% 0.22U_0603_10V7K

3
2
1

3
2
1
1

10_0402_1% 2 1 BOOT1_1_VGA 1 2 TPCA8065-H_PPAK56-8-5

2.61K_0402_1%

PL804
PR828

0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<24> VCCSENSE_VGA 1 2
2

PHASE1_VGA 1 4 +VGA_CORE
2

PR829
VSUM_VGA_N001

0.22U_0603_10V7K

0.033U_0603_25V7K
1

0_0402_5% PQ805 LF1_VGA 2 3 V1N_VGA

5
NTC_VGA

PC857 PQ806
1

1
330P_0402_50V7K
PC858

PC859

10K_0402_1%
3.65K_0402_1%
2

1
TPCA8057-H 1N PPAK56-8

PR831

1_0402_1%
1 1

4.7_1206_5%

470U_D2_2VM_R9M

470U_D2_2VM_R9M
PR830 @

PR833
2

TPCA8057-H 1N PPAK56-8
+ +

PR832

PC860

PC861
0.01U_0402_25V7K
PC864 @

LGATE1_VGA 4 4
330P_0402_50V7K

2
1

1
PC863 @

11K_0402_1%

2
1

PC862 PH801 2 2
PR834

PR835 1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ

1 SNUB1_VGA
0_0402_5%
2

3
2
1

3
2
1
1 2 VSUM-_VGA
<24> VSSSENSE_VGA
2

Layout Note: VSUM+_VGA

PR836 PR837 Place near Phase1 Choke ISEN1_VGA

680P_0402_50V7K
PC865 @
10_0402_1% 1.43K_0402_1%
4 4
1 2 1 2 VSUM-_VGA

2
1

PC866
0.1U_0402_16V7K
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/30 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS QIWY3 LA-8001P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 56 of 64
A B C D
 5 4 3 2 1

PR901 PC901
10_0402_1% 0.033u_0402_16V7K PC902

1200P_0402_50V7K
1 2 FBA3 1 2 1 2

330P_0402_50V8J
D PUT COLSE D

75K_0402_1%
.1U_0402_16V7K
TO GT

1
PR902 PR903 1 PR904 2

PC903

PC904

PR905
TRBSTA# 1 2 FBA1 1 2 PH901 Inductor

0.033u_0402_16V7K
2P: 24K 24K_0402_1% PR906 PC906

1
1
8.06K_0402_1% 806_0402_1% 220K_0402_5%_ERTJ0EV224J CSCOMPA 1 2 DROOPA 1 2 CSREFA
1P: 24.9K

PC905

2
PR908 PC907 PC908 2 PR907 1 NTC_PH203 1.65K_0402_1% 1000P_0402_50V7K

2
1 2 FBA2 1 2 1 2 165K_0402_1%
10_0402_1% 2P: 1.65K
560P_0402_50V7K PR910 10P_0402_50V8J PC909 2P: install
1 PR909 2 1 2 COMPA1 1 2 1 PR911 2 SWN2A 1P: 1K
1P: @
1K_0402_1% 5.11K_0402_1% 2200P_0402_50V7K 91K_0603_1% CSREFA
PC910 TSENSEA

2
1 PR912 2 SWN1A 0.047U_0402_16V7K

2P: 21.5K 91K_0603_1% PR913 5.49K_0402_1%

1
CSP1A 1 2
1P: 15.8K SWN1A <58>

2
21.5K_0402_1%
CSCOMPA
PC911
<10> VCC_AXG_SENSE

2
8.25K_0402_1%
1PR914
1000P_0402_50V7K CSREFA

1
PC912 2P: install PH902

PR915
1000P_0402_50V7K
CSREFA <58> 1P: @

1
PC913 100K_0402_1%_TSM0B104F4251RZ
<10> VSS_AXG_SENSE 0.047U_0402_16V7K
PC914

1
+3VS

CSP2A
CSP1A
1 2 CSP2A 1 2 SWN2A <58>

TRBSTA#

DROOPA

CSSUMA
PR916

TSENSEA
COMPA
IMONA
FBA
.1U_0402_16V7K 5.49K_0402_1%

DIFFA

ILIMA
1

PR917
10K_0402_1% PR918 2P: 36K
1 2
1P: 26.1K PUT COLSE
36K_0402_1%

61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
TO V_GT
2

+5VS 1 PR919 2 PU901

C VR_RDYA C
2_0603_5% HOT SPOT

VSNA
VSPA
DIFFA

FBA
COMPA
IOUTA
ILIMA
DROOPA
CSCOMPA
CSSUMA
CSREFA
CSP2A
CSP1A
TSNSA
PAD

TRBSTA#
+1.05VS 6132_PWMA <58>
PC915
1 2 6132_VCC
.1U_0402_16V7K

.1U_0402_16V7K

1 45 PR921 PC918
2.2U_0603_10V7K VCC PWMA BSTA1
2 44 1 2 BSTA1_12 1
VDDBP BSTA +5VS
130_0402_1%

54.9_0402_1%

PR920 VR_RDYA 3 43 2.2_0603_5%

VRDYA HGA HG1A <58>
1

PR922 2

1 2VR_ON_CPU 4 42 0.22U_0603_10V7K
<42> VR_ON EN SWA SW1A <58>
PR923

PC916 PC917 0_0402_5% VR_SVID_DAT1 5 41 PC919

SDIO LGA LG1A <58>
VR_SVID_ALRT# 6 40 BST2 1 PR924 2 BST2_1 2 1 2Phase: @
2

PR927 PR925 VR_SVID_CLK ALERT# BST2 4.7_0603_5%

7 39 HG2 <58>
SCLK HG2 1Phase: install

0_0402_5%
PR928 @
0_0402_5% 95.3K_0402_1% 1 2 VBOOT 8 38 0.22U_0603_10V7K Option for
SW2 <58>
1

VBOOT SW2
<9> VR_SVID_DAT 1 PR926 2VR_SVID_DAT1 1 2 10K_0402_1% ROSC_CPU 9 NCP6132AMNR2G_QFN60_7X7 37 LG2 <58> 1 phase GFX
VRMP ROSC LG2 6132P_VCCP PR930 2
<9> VR_SVID_ALRT# CPU_B+ 1 2 10
VRMP PVCC
36 1 2 1
VR_HOT# 11 35 0_0402_5%
<9> VR_SVID_CLK VRHOT# PGND
0.01U_0402_25V7K

PR929 1K_0402_1% VGATE 12 34 PC920

LG1 <58> +5VS

2
VRDY LG1
1

13 33 2.2U_0603_10V7K CSP2A
+1.05VS VSN SW1 SW1 <58>
PC921 14 32
+3VS VSP HG1 HG1 <58>
DIFF_CPU 15 31 BST1 1 PR931 2 BST1_1 2 1

CSCOMP
2

DIFF BST1

TRBST#
4.7_0603_5%

DROOP

CSSUM

DRVEN
CSREF
1

COMP
75_0402_1%

TSNS
PC922

CSP3
CSP2
CSP1

PWM
IOUT
ILIM
1
PR932

0.22U_0603_10V7K

FB
PR933 +5VS
PC972 @ 10K_0402_5%

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
43P_0402_50V7K 3P: 73.2K
2

1 2 1 PR934 2
<42> VR_HOT# 2P: 41.2K
2

COMP_CPU

0_0402_5%
PR935 @
FB_CPU 73.2K_0402_1% Option for 3Phase: @
TRBST#
<16> VGATE
PR936 2 phase CPU

DROOP

TSENSE
ILIM_CPU
1 2 VSN 3P: 22p CSP3 1 PR9372 2Phase: install
<9> VSSSENSE 6132_PWM <58> SWN3 <58>
1

20K_0402_1%
0_0402_5% 6.98K_0402_1%
2P: 10p

1
PR974 @
PC923
DRVEN <58>

2
1
PR938 1000P_0402_50V7K 3P: install CSP3
2

1 2 VSP PC924 PC925

<9> VCCSENSE 0.047U_0402_16V7K2P: @
2
21K_0402_1%

0_0402_5% 1 2

2
.1U_0402_16V7K

2
B CSREF B
PC926 CSP1 TSENSE
1 PR940 2 2 1 CSP2 CSP2 1 PR9412
SWN2 <58>
1

20K_0402_1%
1K_0402_1% CSP3 6.98K_0402_1%

1
PR975 @
22P_0402_50V8J

1
PR939

PR942 PC928 PR943 PC929 3P: 21K PC927

1 2FB_CPU1 1 2 2 1COMP_CPU1 2 1 0.047U_0402_16V7K
2P: 12.4K

2
PR944 PC930 49.9_0402_1% 6.04K_0402_1%

8.25K_0402_1%
1 2FB_CPU3 1 2 470P_0402_50V7K 2200P_0402_50V7K CSREF

PR946 1

2
10_0402_1% CSP1 1 PR9452
CSREF <58> SWN1 <58>
CSCOMP

20K_0402_1%
0.033u_0402_16V7K 6.98K_0402_1% PH903

1
PR976 @
PR947 PR948 PC932

1
TRBST# 1 2 FB_CPU2 1 2 1000P_0402_50V7K 3P: 1500p 100K_0402_1%_TSM0B104F4251RZ
1
0.033u_0402_16V7K

PC931
2P: 1200p

1
1

8.06K_0402_1% 806_0402_1% 0.047U_0402_16V7K

2
PC933

2
CSSUM CSREF
2

PC934
1 2 1 PR949 2 SWN1
23.7K_0402_1%

1500P_0402_50V7K 130K_0603_1% PUT COLSE

2

.1U_0402_16V7K

PC969@QC TO VCORE
PC935

3P: 23.7K 1 PR951 2 SWN2

PR950

2P: 24.9K 1 2 PC969 130K_0603_1% HOT SPOT

1

330P_0402_50V7K
1 PR954 2 SWN3
1

130K_0603_1%
PR955 PC937 1 2 PC936
CSCOMP 1 2 DROOP 1 2 CSREF 330P_0402_50V7K 3P: install
PUT COLSE 2P: @
806_0402_1% 1000P_0402_50V7K PR952 PR953
3P: 806 <42> IMVP_IMON TO VCORE 1 NTC_PH201
2 1 2
2P: 1K Phase 1 75K_0402_1%
165K_0402_1%
A Inductor PH904 A

2 1

220K_0402_5%_ERTJ0EV224J

Security Classification
2011/06/30
Compal Secret Data
2012/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom QIWY3 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 57 of 64
5 4 3 2 1
 5 4 3 2 1

CPU_B+ CPU_B+

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
PQ901 B+ PQ902

0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_25V7K

2200P_0402_25V7K
5

5
PL901

TPCA8065-H_PPAK56-8-5

TPCA8065-H_PPAK56-8-5
HCB4532KF-800T90_1812

1
PC938

PC939

PC940

PC941

PC942

PC943

PC944

PC946
1 2 CPU_B+

220U_25V_M
1 1

470P_0603_50V7K

470P_0603_50V7K
1000P_0603_50V7K
100U_25V_M_R0.36
2

2
<57> HG1 4 <57> HG2 4

1
+ +

PC970

PC973

PC947

PC971
+VCC_CORE +VCC_CORE

PC945
2

2
PL902 2 2

3
2
1

3
2
1
D D
0.36UH_VMPI1004AR-R36M-Z03_30A_20% PL903
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
<57> SW1 1 4 <57> SW2 1 4

1
PQ903 2 3 PQ904 2 3

5
TPCA8057-H 1N PPAK56-8

TPCA8057-H 1N PPAK56-8
PR956 PR957
4.7_1206_5% 4.7_1206_5%

2
PR958
4 V1N_CPU2 1 4 V2N_CPU 2 PR959 1 CSREF
<57> LG1 CSREF <57> <57> LG2

1SNUB_CPU1

SNUB_CPU2
10_0402_1%
10_0402_1%

SWN1 <57> SWN2 <57>

3
2
1

3
2
1
PC948
680P_0402_50V7K

1
PC949

2
680P_0402_50V7K

2
CPU_B+
PR960
BST3 1 2 BST3_1

10U_0805_25V6K

10U_0805_25V6K
4.7_0603_5%

0.1U_0402_25V6

2200P_0402_25V7K
PQ905

5
2

1
TPCA8065-H_PPAK56-8-5

PC951

PC952

PC953

PC954
PC950
0.22U_0603_10V7K
1

2
4
PU902 +VCC_CORE
1 9
BST FLAG
C C
2 8 HG3 PL904
<57> 6132_PWM
3
2
1

PWM DRVH
QC 45W CPU DC 35W CPU
<57> DRVEN 2 PR961 1EN_CPU3 3 7 SW3 1 4
2K_0402_1% EN SW VID1=0.9V VID1=1.05V

1
+5VS 2 1VCC_CPU3 4 6 2 3 IccMax=94A IccMax=53A
VCC GND
5

TPCA8057-H 1N PPAK56-8

PR962 PQ906 0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1

0_0402_5%
DRVL
5 LG3 PR963 Icc_Dyn=66A Icc_Dyn=43A
4.7_1206_5%
PC955 NCP5911MNTBG_DFN8_2X2
Icc_TDC=52A Icc_TDC=36A
2

2.2U_0603_10V7K R_LL=1.9m ohm R_LL=1.9m ohm

4 V3N_CPU 2 PR964 1 CSREF
OCP~110A OCP~65A
SNUB_CPU3

10_0402_1%

SWN3 <57>
3
2
1

PC956
680P_0402_50V7K
3Phase: install
2

2Phase:: @

CPU_B+ CPU_B+

2Phase: install
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

0.1U_0402_25V6
2200P_0402_25V7K

2200P_0402_25V7K
B 1Phase:: @ B
1

1
PC957

PC958

PC959

PC960

PC961

PC962

PC963

PC964
PQ907
PQ908
2

2
5

5
TPCA8065-H_PPAK56-8-5

TPCA8065-H_PPAK56-8-5
BSTA2 1 PR965 2 BSTA2_1

2
2.2_0603_5%
PC965
0.22U_0603_10V7K

1
<57> HG1A 4 4

PU903
1 9
+VCC_GFXCORE_AXG BST FLAG
3
2
1

3
2
1
PL905 2 8 HG2A PL907
<57> 6132_PWMA PWM DRVH
0.36UH 20% PDME064T-R36MS1R405 24A 0.36UH 20% PDME064T-R36MS1R405 24A
1 2 DRVEN 2 PR966 1EN_GFX2 3 7 SW2A 1 2 +VCC_GFXCORE_AXG
<57> SW1A EN SW
2K_0402_1%
1

PQ909 +5VS 2 1VCC_GFX2 4 6

@ 4.7_1206_5%

VCC GND
5

5
TPCA8057-H 1N PPAK56-8

PR968
PR967

1
TPCA8057-H 1N PPAK56-8
0_0402_5% 5 PQ910

0_0402_5%
DRVL

PR973
1
NCP5911MNTBG_DFN8_2X2 PR969 @
2

PC966 4.7_1206_5% PR970

0_0402_5%

2.2U_0603_10V7K LG2A CSREFA

PR972

<57> LG1A 4 2 4 2 1

2
10_0402_1%
SNUB_GFX1

SNUB_GFX2
2

2 PR971 1
CSREFA <57>
3
2
1

3
2
1
@ 680P_0402_50V7K

SWN2A <57>
10_0402_1%
1

1
PC967 @
PC968

SWN1A <57>
2

680P_0402_50V7K

2
A A

QC 45W GT2 DC 35W GT2

VID1=1.23V VID1=1.23V
IccMax=46A IccMax=33A
Icc_Dyn=37A Icc_Dyn=20.2A Security Classification Compal Secret Data Compal Electronics, Inc.
Icc_TDC=38A Icc_TDC=21.5A Issued Date 2011/06/30 Deciphered Date 2012/12/31 Title

R_LL=3.9m ohm R_LL=3.9m ohm THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
Size Document Number Rev
OCP~55A OCP~40A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS QIWY3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 58 of 64
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

+CPU_CORE +VCC_GFXCORE_AXG
1 1 1 1 1
5 x 22 µF (0805)
PC1
PC2 PC3 PC4 PC5
Socket Bottom 5 x (0805) no-stuff
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM
2
10U_0805_6.3VAM +VCC_GFXCORE_AXG sites

D
7 x 22 µF (0805) D
Socket Top 2 x (0805) no-stuff
sites

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1

PC12

PC13

PC14

PC15

PC16

PC17

PC18

PC19
PC6 PC7 PC8 PC9 PC10 PC11
10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM 10U_0805_6.3VAM
2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.05VS
+VCC_CORE +1.05VS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1

PC25

PC26

PC27

PC28

PC29

PC30

PC31

PC32

PC33

PC34

PC35
PC20 PC21 PC22 PC23 PC24
2 2 2 2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 1 1 1 1 1 1
2 2 2 2 2

PC36

PC37

PC38

PC39

PC40

PC41

PC42

PC43
2 2 2 2 2 2 2 2

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1 1 1 1 1 1 1 1
1 1 1 1 1

PC49

PC50

PC51

PC52

PC53

PC54

PC55

PC56
PC44 PC45 PC46 PC47 PC48
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2 2 2 2 2 2
2 2 2 2 2
1 1 1

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M
PC57

PC58

PC59
+ + +
C C
PC59@DC
2 3 2 3 2 3
1 1

330U_D2_2VM_R6M

330U_D2_2VM_R6M
1 1 1 1 1

PC67

PC68
+ +
PC61 PC62 PC63 PC64 PC65
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2 2 2 3 2 3

1 1 1 1
PC69 PC70 PC71 PC72
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 2 2
PC32,PC49,PC54,PC55,PC56
+VCC_CORE
PC8,PC21,PC22,PC63
PC38,PC39,PC40,PC41
330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M

330U_D2_2VM_R9M
PC75@DC

1 1 1 1 1 1
470U_D2_2VM_R9M
PC77 @

+ + + + + +
PC73

PC74

PC76

PC78

B 2 3 2 3 2 3 2 3 2 3 2 B

DC:PC73,PC74,PC76(330uF/9m)+PC78(330uF/6m)
QC:PC73,PC74,PC75,PC76(330uF/9m)+PC78(470uF/9m)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/30 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR DECOUPLING
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS QIWY3 LA-8001P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, January 16, 2012 Sheet 59 of 64
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Reason for change PG# Modify List Date Phase

2011/09/27
1 Reserve 0.1uF for Charger IC 51 Reserve PC321 B test
D
change PR322,PR407,PR408,PR503,PR511,PR606,PR804,PR827 to 2.2 ohm D

2 EMI Request 2011/09/27

add PC526,PC527,PC970,PC971(470pF) B test
Remove one power rail +V1.05S_VCCPP
3 Combine 1.05V 51 2011/09/27 B test
Pop PR722,PR712,PR718

4 Discharge for +1.05VS_VGA by NV Request 53 Reserve PR528 2011/09/27 B test

unpop PR806
5 Set VGA_CORE VBOOT voltage 56 2011/09/27
change PR813 to 147K ohm B test
6
For VGA_CORE power saving by NV Request 56 add PR838 0ohm 2011/09/27 B test

7 for CPU_CORE load line adjust 57 add PC969 2011/09/27 B test

8 to prevent MOS over temperature 55/58 change PQ702,PQ901,PQ902,PQ905 TPCA8065 2011/09/27 B test
C C
9 for CPU_CORE test 59 Reserve PC77,PC78 2011/09/27 B test

10 for debug 51 add PR329,PR330 2011/11/30 C test

11 for VCCIO remote sense 55 add PR723 2011/11/30 C test

12 RC filter to reduce noise 55 add PR721,PC727 2011/11/30 C test

pop PC203,PQ201,PR209,PU201,PR213
13 G718 for adapter and OTP 50 2011/11/30 C test
unpop PR206

14 58 change PR911,PR912 to 91K 2011/11/30 C test

for CPU transient
add PL301,PC503,PL504,PL801
15 for EMI Request 2011/11/30 C test
add PC302,PC323,PC424,PC526,PC722,PC970,PC974
B 50 reserve connect PCH_PWR_EN for power sequence B
16 HW reqeust 2011/11/30 C test
55 reserve connect CPU1.5V_S3_GATE for power sequence

17 for thermal request to reduce temperature 53 change PQ503,PQ504 2011/11/30 C test

18 adjust 1.5VSP_VGA OCP 53 change PR514 to 49.9K 2011/11/30 C test

change PR222,PR228 to NA
19 For HW power sequence adjustment 50 2011/12/02 C test
change PR229 to 0 ohm

20 To adjust +5VALW by HW request 52 change PR404 to 19.6K 2011/12/16 C test

Using G718 to replace KB9012 function need to add Add PR232 and reserve PR233 pull high to +3VALW
50
21 or reserve resistor Add PR234 pull down 2011/12/28 Pre MP

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/30 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3
Date: Monday, January 16, 2012 Sheet 60 of 64
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 2

for PWR
Item Reason for change PG# Modify List Date Phase

2011/12/28 Pre MP
22 TI 's suggestion that snubber should be first at R than C 54 change PR607 and PC604 order
D D

23 Reserve resistor for adjust current balance 57 Reserve PR974,PR975,PR976 2011/12/28 Pre MP

24 To reduce noise 58 change PC945 to 220uF 2011/12/28 Pre MP

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/30 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3
Date: Monday, January 16, 2012 Sheet 61 of 64
5 4 3 2 1
 5 4 3 2 1

QIWY3 HW PIR List

NO DATE PAGE MODIFICATION LIST PURPOSE
EVT TO DVT
1 P7 Reserve R64 Reserve EC DRAMRST control pin for Deep S3
2 P16 Reserve R1457,R1455,R1447 Reserve SUSACK#,SUSWARN#,SLP_SUS# control signal for Deep S3
D 3 P16 Reserve Q118,R1120,R1121 Reverse SLP_SUS# to control +3V_PCH&+5V_PCH D

4 P16 Change AC_PRESENT Pull high source to +3V_DSW For Deep S3 function
5 P21 Remove R289 +5V_PCH control circuit change for Deep S3
6 P36 Reserve J8,Q104,C533,C526,R436 Reserve for AOAC function
7 P36 Change JP1 pin2,24,52 power source to +3VS_WLAN_AOAC Reserve for AOAC function
8 P42 Change EC GPIO pin setting (Impact pin 18,71,72,126,128) For DeepS3/AOAC function
9 P48 Reserve J11,J14,Q148,Q149,C38,C39 +3V_PCH&+5V_PCH control circuit for Deep S3
10 P45 change U49 symbol (without GND pad) For DFx issue
11 P46 change U40,U69 symbol (without GND pad) For DFx issue
12 P47 change JP10 type to SP01001B800 For DFx issue
13 P19 Reserve R207,R224 to contact WLAN wake even Reserve for AOAC function
14 P41 Change JSPK1 type to SP02000H700 For DFx issue
14 P19 Reserve R704 and R706 for GPIO69 PU&PD For SKU ID
15 P23 Change CV37,CV38 to 22P For Crystal EA request
16 P37 Change C968,C969 to 33P For Crystal EA request
DVT TO PVT
1 P14 Change power source to +5VS (Q10 pin 2) Follow intel Design Guide
C C

2 P16 Reserve R257 PU 10K to +3V_DSW For Deep S3 function

3 P40 Change R1110 to 200K,C638 to 0.1u For ODD soft star
4 P10 Change C124,C125,C126,C127,C130 to 0603 type For commond design
5 P20 Change C215,C221,C395 to 0603 type For commond design
6 P21 Change C231 to 0603 type For commond design
7 P33 Change C519 to 0603 type For commond design
8 P36 Change C568,C569 to 0603 type For commond design
9 P37 Change C937,C954,C953 to 0603 type For commond design
10 P39 Change C986 to 0603 type For commond design
11 P40 Change C634,C635,C639 to 0603 type For commond design
12 P41 Change C655 to 0603 type For commond design
13 P48 Change C836,C837,C839,C840,C847 For commond design
C848,C856,C857 to 0603 type
14 P47 Change C906 to 0603 type For commond design
B
15 P47 Modify gate powr rail of MOS to +5VALW Avoid leakage issue. B

16 P45 Change U39 source to SA00004KB00 For main source issue

17 P46 Change U40,U69 source to SA00004KB00 For main source issue
18 P37 Add Q150,R145,C976 For LAN power control
19 P42 Reserve LAN_PWR_ON# net on EC pin 89 For LAN power control
20 P41 Stuff R945,R481 for EAPD contact U8 pin29 For MUTE_LED issue
21 P38 Add R90 For LAN SURGE CO-LAY
22 P38 Add R1380 Atheros request

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (HW)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6882P
Date: Monday, January 16, 2012 Sheet 62 of 64
5 4 3 2 1
 5 4 3 2 1

QIWY3 HW PIR List

NO DATE PAGE MODIFICATION LIST PURPOSE
PVT TO SVT
1 P46 change JP21 type (SP010011A00) For ASSY issue
2 P23 RV208 change to contact +VDD33MISC For N13P-GT/N13E-GE shutdown issue
D 3 P23 Reserve RV14 For N13P-GT/N13E-GE +VDD33MISC leakage issue D

4 P41 Swap HP R/L For HP R/L reverse issue

5 P42 Add R1415,R1419 T/P SM BUS pull high voltage change

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (HW)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6881P
Date: Monday, January 16, 2012 Sheet 63 of 64
5 4 3 2 1
 5 4 3 2 1

D D

PCH_PWR_EN# 2
U14,+3VALW_PCH

V
AC A1
MODE VIN QH4,+5VALW_PCH

V V
A2 A3 B5

VV
PU2 A5 2

V
PU3

V
B+ +3VALW_PCH
+3VALW B7 2 3
BATT V +5VALW_PCH
BATT
MODE
B1
B2
B+ B4 V
V

V
EC 4 SYS_PWROK
13
PQ2 PCH_RSMRST# PM_DRAM_PWRGD

V
V V PCH
B3 A5 B7 5 14
PBTN_OUT# H_CPUPWRGD
CPU

V V
V
51ON# EC_ON
PM_SLP_S3#
PM_SLP_S4# PLT_RST# 15
C C
PM_SLP_S5#
A4 B6 PM_SLP_A# 6
PM_SLP_SUS#

V
V
ON/OFF V
SYSON 7 SYSON# +1.5V

V
PU5
DGPU_PWR_EN 8a (DIS) VGA_ON
+3VSDGPU

V
8
Q6 11
SUSP#,SUSP U49

V
VGATE
+5VS

V
+1.5VSDGPU
U40

V
U20

V
+3VS +1.8VSDGPU VGA
U37
B B

V
U13

V
+1.5VS +1.0VSDGPU
PU28

V
PU8

V
+0.75V +VGA_CORE
VCCPPWRGOOD
PU998
V

V
PU9 PU7
+1.05VS_VCCP +VCCSA 8b (DIS)
VGA_PWROK

U47
CK505
VR_ON 9 PU1000
V
10
V

+CPU_CORE

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/07/21 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QIWY3 LA-8001P
Date: Monday, January 16, 2012 Sheet 64 of 64
5 4 3 2 1