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TPS54240
SLVSAA6B – APRIL 2010 – REVISED NOVEMBER 2014
TPS54240 3.5-V to 42-V Step-Down DC - DC Converter With Eco-Mode™

1 Features 3 Description
•
1 3.5-V to 42-V Input Voltage Range The TPS54240 device is a 42-V, 2.5-A, step-down
regulator with an integrated high-side MOSFET.
• 200-mΩ High-Side MOSFET Current mode control provides simple external
• High Efficiency at Light Loads With a Pulse compensation and flexible component selection. A
Skipping Eco-Mode™ low-ripple, pulse skip mode reduces the no load,
• 138-μA Operating Quiescent Current regulated output supply current to 138 μA. Using the
enable pin, shutdown supply current is reduced to 1.3
• 1.3-μA Shutdown Current
μA, when the enable pin is low.
• 100-kHz to 2.5-MHz Switching Frequency
Undervoltage lockout is internally set at 2.5 V, but it
• Synchronizes to External Clock can be increased using the enable pin. The output
• Adjustable Slow Start and Sequencing voltage startup ramp is controlled by the slow-start
• UV and OV Power Good Output pin that can also be configured for sequencing and
• Adjustable UVLO Voltage and Hysteresis tracking. An open-drain power good signal indicates
the output is within 94% to 107% of its nominal
• 0.8-V Internal Voltage Reference voltage.
• 10-Pin HVSSOP and 10-Pin 3-mm x 3-mm VSON
A wide switching frequency range allows efficiency
Packages with PowerPAD™ and optimization of external component size.
• Supported by WEBENCH® Software Tool Frequency foldback and thermal shutdown protects
the part during an overload condition.
2 Applications The TPS54240 is available in 10-pin, thermally-
• 12-V and 24-V Industrial and Commercial Low- enhanced HVSSOP and 10-pin 3-mm x 3-mm
Power Systems PowerPAD package.
• GSM, GPRS Modules in Fleet Management,
Device Information(1)
eMeters, and Security Systems
PART NUMBER PACKAGE BODY SIZE (NOM)
HVSSOP (10)
TPS54240 3.00 mm x 3.00 mm
VSON (10)
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Simplified Schematic Efficiency vs Load Current

100
VIN VIN PWRGD
90
80
TPS54240
70
BOOT
EN
Efficiency - %
60
50
SS /TR PH V OUT
40
RT /CLK
30
VIN=12V
COMP 20 VOUT=3.3V
VSENSE fsw=300kHz
10
0
GND 0 0.5 1.0 1.5 2.0 2.5 3.0
IO - Output Current - A
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS54240
SLVSAA6B – APRIL 2010 – REVISED NOVEMBER 2014 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes ....................................... 30
2 Applications ........................................................... 1 8 Application and Implementation ........................ 30
3 Description ............................................................. 1 8.1 Application Information .......................................... 30
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 31
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 42
6 Specifications......................................................... 4 10 Layout................................................................... 42
6.1 Absolute Maximum Ratings ..................................... 4 10.1 Layout Guidelines ................................................. 42
6.2 Handling Ratings....................................................... 4 10.2 Layout Example .................................................... 42
6.3 Recommended Operating Conditions....................... 4 10.3 Estimated Circuit Area .......................................... 43
6.4 Thermal Information .................................................. 5 11 Device and Documentation Support ................. 43
6.5 Electrical Characteristics........................................... 6 11.1 Device Support .................................................... 43
6.6 Typical Characteristics .............................................. 8 11.2 Documentation Support ........................................ 43
7 Detailed Description ............................................ 12 11.3 Trademarks ........................................................... 43
7.1 Overview ................................................................. 12 11.4 Electrostatic Discharge Caution ............................ 43
7.2 Functional Block Diagram ....................................... 13 11.5 Glossary ................................................................ 43
7.3 Feature Description................................................. 13 12 Mechanical, Packaging, and Orderable
Information ........................................................... 43
4 Revision History
NOTE: Page numbers of current version may differ from previous versions.
Changes from Revision A (April 2010) to Revision B Page
• Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ................................................................................................................................................................................... 1
• Changed the Start Input Voltage value in Design Requirements from 6.0 V to 6.25 V ....................................................... 31
• Changed the Stop Input Voltage value in Design Requirements from 5.5 V to 5.9 V ........................................................ 31
• Changed the value 6.0 V to 6.25 V ...................................................................................................................................... 36
• Changed the value 5.5 V to 5.9 V ........................................................................................................................................ 36
• Changed the value 6.0 V to 6.25 V ...................................................................................................................................... 36
• Changed the value 5.5 V to 5.9 V ........................................................................................................................................ 36
Changes from Original (April 2010) to Revision A Page
• Added 10-Pin 3mm x 3mm SON to Features......................................................................................................................... 1

• Added Thermal Information table and deleted Package Dissipation Ratings table ............................................................... 4
2 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated
Product Folder Links: TPS54240

TPS54240
www.ti.com SLVSAA6B – APRIL 2010 – REVISED NOVEMBER 2014
5 Pin Configuration and Functions

DGQ PACKAGE DRC PACKAGE
(TOP VIEW) (TOP VIEW)
BOOT 1 10 PH BOOT 1 10 PH
VIN 2 Thermal 9 GND VIN 2 Thermal 9 GND
EN 3 Pad 8 COMP EN 3 Pad 8 COMP
(11) (11)
SS/TR 4 7 VSENSE SS/TR 4 7 VSENSE
RT/CLK 5 6 PWRGD RT/CLK 5 6 PWRGD
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the
BOOT 1 O
minimum required by the output device, the output is forced to switch off until the capacitor is refreshed.
Error amplifier output, and input to the output switch current comparator. Connect frequency compensation
COMP 8 O
components to this pin.
Enable pin, internal pullup current source. Pull below 1.2 V to disable. Float to enable. Adjust the input
EN 3 I
undervoltage lockout with two resistors.
GND 9 – Ground
PH 10 I The source of the internal high-side power MOSFET.
POWERPAD 11 – GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation.
An open-drain output, asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage or
PWRGD 6 O
EN shut down.
Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an
external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold,
RT/CLK 5 I a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and
the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-
enabled and the mode returns to a resistor set function.
Slow-Start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the
SS/TR 4 I
voltage on this pin overrides the internal reference, it can be used for tracking and sequencing.
VIN 2 I Input supply voltage, 3.5 V to 42 V.
VSENSE 7 I Inverting node of the transconductance (gm) error amplifier.
Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 3

TPS54240
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN –0.3 47
EN –0.3 5
VSENSE –0.3 3
Input voltage COMP –0.3 3 V
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
BOOT-PH 8
Output voltage PH –0.6 47 V
PH, 10-ns Transient –2 47
Voltage difference PAD to GND ±200 mV
EN 100 μA
BOOT 100 mA
Source current VSENSE 10 μA
PH Current Limit A
RT/CLK 100 μA
VIN Current Limit A
COMP 100 μA
Sink current
PWRGD 10 mA
SS/TR 200 μA
Operating junction temperature –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all -2 2
kV
pins (1)
V(ESD) Electrostatic discharge
Charged device model (CDM), per JEDEC specification -500 500
V
JESD22-C101, all pins (2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Operating Input Voltage on (VIN pin) 3.5 42 V
Operating junction temperature, TJ -40 150 °C

TPS54240
6.4 Thermal Information

TPS54240
THERMAL METRIC (1) (2) (2) DGQ DRC UNIT
10 PINS 10 PINS
θJA Junction-to-ambient thermal resistance (standard board) 62.5 40
ψJT Junction-to-top characterization parameter 1.7 0.6
ψJB Junction-to-board characterization parameter 20.1 7.5
°C/W
θJCtop Junction-to-case(top) thermal resistance 83 65
θJCbot Junction-to-case(bottom) thermal resistance 21 7.8
θJB Junction-to-board thermal resistance 28 8
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
distortion starts to substantially increase. See power dissipation estimate in application section of this data sheet for more information.

TPS54240
6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 42 V
Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 42 V 1.3 4
μA
Operating : nonswitching supply current VSENSE = 0.83 V, VIN = 12 V, 25°C 138 200
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling, 25°C 1.15 1.25 1.36 V
Enable threshold +50 mV –3.8
Input current μA
Enable threshold –50 mV –0.9
Hysteresis current –2.9 μA
VOLTAGE REFERENCE
TJ = 25°C 0.792 0.8 0.808
Voltage reference V
0.784 0.8 0.816
HIGH-SIDE MOSFET
VIN = 3.5 V, BOOT-PH = 3 V 300
On-resistance mΩ
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER (EA)
Input current 50 nA
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V 310 μS
Error amplifier transconductance (gM) –2 μA < ICOMP < 2 μA, VCOMP = 1 V,
70 μS
during slow start VVSENSE = 0.4 V
Error amplifier dc gain VVSENSE = 0.8 V 10,000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±27 μA
COMP to switch current
10.5 A/V
transconductance

TPS54240
Electrical Characteristics (continued)

TJ = –40°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT LIMIT
Current limit threshold VIN = 12 V, TJ = 25°C 3.5 6.1 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK
(RT/CLK PIN)
Switching Frequency Range using RT
100 2500 kHz
mode
fSW Switching frequency RT = 200 kΩ 450 581 720 kHz
Switching Frequency Range using CLK
300 2200 kHz
mode
Minimum CLK input pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising edge
Measured at 500 kHz with RT resistor in series 60 ns
delay
PLL lock in time Measured at 500 kHz 100 μs
SLOW-START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.15 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 382 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWERGOOD (PWRGD PIN)
VSENSE falling 92%
VVSEN VSENSE rising 94%
VSENSE threshold
SE VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, I(PWRGD) = 100 μA 0.95 1.5 V

TPS54240
6.6 Typical Characteristics
500 0.816
Static Drain-Source On-State Resistance (mW)
375 BOOT-PH = 3 V 0.808
Voltage Reference (V)

250 0.800
BOOT-PH = 6 V
125 0.792
0 0.784
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
Junction Temperature (°C) C001
VI = 12 V
Figure 1. On Resistance vs Junction Temperature Figure 2. Voltage Reference vs Junction Temperature

7.0 610
VI = 12 V
600
Switching Frequency (kHz)
6.5
590
Switch Current - A
580
6.0
570
5.5 560
550
–50 –25 0 25 50 75 100 125 150
5.0 Junction Temperature (°C) C004
-50 -25 0 25 50 75 100 125 150
VI = 12 V RT = 200 kΩ
TJ - Junction Temperature - °C
Figure 3. Switch Current Limit vs Junction Temperature Figure 4. Switching Frequency vs Junction Temperature
2500 500
2000 400
1500 300
1000 200
500 100
0 0
0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200
RT/CLK Resistance (kW) C005 RT/CLK Resistance (kW) C006
VI = 12 V TJ = 25°C VI = 12 V TJ = 25°C
Figure 5. Switching Frequency vs RT/CLK Resistance High Figure 6. Switching Frequency vs RT/CLK Resistance Low
Frequency Range Frequency Range

TPS54240
Typical Characteristics (continued)

120 500
VI = 12 V VI = 12 V
450
100
400
80
gm - mA/V
gm - mA/V
350
60
300
40 250
20 200
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TJ - Junction Temperature - °C TJ - Junction Temperature - °C
Figure 7. EA Transconductance during Slow Start vs Figure 8. EA Transconductance vs Junction Temperature

Junction Temperature
1.40 –3.25
–3.5
EN Threshold (V)
1.30
I(EN) (μA)
–3.75
1.20
–4
–4.25
1.10 –50 –25 0 25 50 75 100 125 150
–50 –25 0 25 50 75 100 125 150 Junction Temperature (°C) C010
VI = 12 V VI(EN) = Threshold
VI = 12 V +50 mV
Figure 9. EN Pin Voltage vs Junction Temperature Figure 10. EN Pin Current vs Junction Temperature
–0.8 –1
–0.85 –1.5
I(EN) (μA)
I(SS/TR) (μA)
–0.9
–2
–0.95
–2.5
–1
–50 –25 0 25 50 75 100 125 150 –3
Junction Temperature (°C) –50 –25 0 25 50 75 100 125 150
C011
Junction Temperature (°C)
VI = 12 V VI(EN) = Threshold C012
+50 mV VI = 12 V
Figure 11. EN Pin Current vs Junction Temperature Figure 12. SS/TR Charge Current vs Junction Temperature

TPS54240

575 100
VI = 12 V
500 80
% of Nominal fsw
425 60
II(SS/TR) - mA
350 40
275 20
200 0
-50 0 50 100 150 0 0.2 0.4 0.6 0.8
TJ - Junction Temperature - °C VSENSE (V) C014
VI = 12 V TJ = 25°C
Figure 13. SS/TR Discharge Current vs Junction Figure 14. Switching Frequency vs VSENSE
Temperature
2 2
TJ = 25°C
1.5 1.5
I(VIN) (μA)
I(VIN) - mA
1 1
0.5 0.5
0 0
–50 –25 0 25 50 75 100 125 150 0 10 20 30 40
VI - Input Voltage - V
VI = 12 V
Figure 15. Shutdown Supply Current vs Junction Figure 16. Shutdown Supply Current vs Input Voltage (VIN)
Temperature
210 170
VI = 12 V, o
TJ = 25 C,
VI(VSENSE) = 0.83 V
190 VI(VSENSE) = 0.83 V
170
150
I(VIN) - mA
150
I(VIN) - mA
130
130
110
90
70 110
-50 0 50 100 150 0 10 20 30 40
TJ - Junction Temperature - °C VI - Input Voltage - V
Figure 17. VIN Supply Current vs Junction Temperature Figure 18. VIN Supply Current vs Input Voltage

TPS54240

100 115
VSENSE Rising
80 110
PWRGD Threshold (% of Vref)

105 VSENSE Falling
RDSON (W)
60
100
40
VSENSE Rising
95
20
90 VSENSE Falling
0 85
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
VI = 12 V VI = 12 V
Figure 19. PWRGD on Resistance vs Junction Temperature Figure 20. PWRGD Threshold vs Junction Temperature
2.5 3
2.3 2.75
VI(BOOT-PH) (V)
VI(VIN) (V)
2 2.50
1.8 2.25
1.5 2
–50 –25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) C021 Junction Temperature (°C) C022
Figure 21. BOOT-PH UVLO vs Junction Temperature Figure 22. Input Voltage UVLO vs Junction Temperature
600 60
V(SS/TR) = 0.4 V
VI = 12 V,
500 o 50 VI = 12 V
TJ = 25 C
400 40
Offset - mV
Offset - mV
300 30
200 20
100 10
0 0
0 100 200 300 400 500 600 700 800 -50 -25 0 25 50 75 100 125 150
VSENSE - mV TJ - Junction Temperature - °C
Figure 23. SS/TR to VSENSE Offset vs Vsense Figure 24. SS/TR to VSENSE Offset vs Temperature

TPS54240
7 Detailed Description
7.1 Overview
The TPS54240 device is a 42-V, 2.5-A, step-down (buck) regulator with an integrated high-side n-channel
MOSFET. To improve performance during line and load transients, the device implements a constant-frequency,
current mode control which reduces output capacitance and simplifies external frequency compensation design.
The wide-switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting
the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin.
The device has an internal phase-lock loop (PLL) on the RT/CLK pin that is used to synchronize the power
switch turn on to a falling edge of an external system clock.
The TPS54240 has a default startup voltage of approximately 2.5 V. The EN pin has an internal pullup current
source that can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external
resistors. In addition, the pullup current provides a default condition. When the EN pin is floating, the device will
operate. The operating current is 138 μA when not switching and under no load. When the device is disabled,
the supply current is 1.3 μA.
The integrated 200-mΩ high-side MOSFET allows for high-efficiency power supply designs capable of delivering
2.5 amperes of continuous current to a load. The TPS54240 reduces the external component count by
integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a
capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the
high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS54240 can operate at high
duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V
reference.
The TPS54240 has a power good comparator (PWRGD) which asserts when the regulated output voltage is less
than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which
deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the
pin to transition high when a pullup resistor is used.
The TPS54240 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV
powergood comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked
from turning on until the output voltage is lower than 107%.
The SS/TR (slow-start / tracking) pin is used to minimize inrush currents or provide power supply sequencing
during power-up. A small value capacitor should be coupled to the pin to adjust the slow-start time. A resistor
divider can be coupled to the pin for critical power supply sequencing requirements. The SS/TR pin is discharged
before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault,
UVLO fault or a disabled condition.
The TPS54240, also, discharges the slow-start capacitor during overload conditions with an overload recovery
circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation
voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during
startup and overcurrent fault conditions to help control the inductor current.

TPS54240
7.2 Functional Block Diagram

PWRGD EN VIN
6 3 2
Shutdown Thermal
Shutdown UVLO
Enable
UV Logic Comparator
Shutdown
Shutdown
Logic
OV
Enable
Threshold
Boot
Charge
Voltage
Minimum Boot
Reference Current
Clamp UVLO
Pulse Sense
ERROR Skip
AMPLIFIER
PWM
VSENSE 7 Comparator 1 BOOT
Logic
SS/TR 4
And
PWM Latch
Shutdown
Slope
Compensation
COMP 8 10 PH
Frequency 11 POWERPAD
Shift
Overload Maximum
Recovery Clamp 9 GND
Oscillator TPS54240 Block Diagram
with PLL
5
RT/CLK
7.3 Feature Description

7.3.1 Fixed Frequency PWM Control
The TPS54240 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared
through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives
the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output
is compared to the high-side power switch current. When the power switch current reaches the level set by the
COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output
current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a
maximum level. The Eco-Mode is implemented with a minimum clamp on the COMP pin.
7.3.2 Slope Compensation Output Current

The TPS54240 adds a compensating ramp to the switch current signal. This slope compensation prevents sub-
harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
7.3.3 Pulse Skip Eco-Mode

The TPS54240 operates in a pulse skip Eco-Mode at light load currents to improve efficiency by reducing
switching and gate drive losses. The TPS54240 is designed so that if the output voltage is within regulation and
the peak switch current at the end of any switching cycle is below the pulse-skipping current threshold, the
device enters Eco-Mode. This current threshold is the current level corresponding to a nominal COMP voltage or
500 mV.

TPS54240
Feature Description (continued)

When in Eco-Mode, the COMP pin voltage is clamped at 500 mV and the high-side MOSFET is inhibited. Further
decreases in load current or in output voltage cannot drive the COMP pin below this clamp voltage level.
Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates
for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side MOSFET is enabled
and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The
output voltage re-charges the regulated value, then the peak switch current starts to decrease, and eventually
falls below the Eco-Mode threshold at which time the device again enters Eco-Mode.
For Eco-Mode operation, the TPS54240 senses peak current, not average or load current, so the load current
where the device enters Eco-Mode is dependent on the output inductor value. For example, the circuit in
Figure 49 enters Eco-Mode at about 5 mA of output current. When the load current is low and the output voltage
is within regulation, the device enters a sleep mode and draws only 138-μA input quiescent current. The internal
PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip mode, the
switching transitions occur synchronously with the external clock signal.
7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)

The TPS54240 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and
PH pins to provide the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the low-side diode conducts. The value of this ceramic capacitor should be 0.1 μF.
A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended
because of the stable characteristics overtemperature and voltage.
To improve drop out, the TPS54240 is designed to operate at 100% duty cycle as long as the BOOT to PH pin
voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V, the high-side MOSFET is
turned off using an UVLO circuit which allows the low-side diode to conduct and refresh the charge on the BOOT
capacitor. Since the supply current sourced from the BOOT capacitor is low, the high-side MOSFET can remain
on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the
switching regulator is high.
The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the
power MOSFET, inductor resistance, low-side diode and printed circuit board resistance. During operating
conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the
high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH
voltage falls below 2.1 V.
Take care of maximum duty cycle applications which experience extended time periods with light loads or no
load. When the voltage across the BOOT capacitor falls below the 2.1-V UVLO threshold, the high-side MOSFET
is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the BOOT
capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT
capacitor is less than 2.1 V. The output capacitor then decays until the difference in the input voltage and output
voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts
switching again until the desired output voltage is reached. This operating condition persists until the input
voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater than the
BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with
resistors on the EN pin.
The start and stop voltages for typical 3.3-V and 5-V output applications are shown in Figure 25 and Figure 26.
The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate
the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops
switching.
During high-duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being
recharged resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot
capacitor being longer than the typical high-side off-time when switching occurs every cycle.

TPS54240

4 5.6
3.8 5.4
Input Voltage (V)

Input Voltage (V)
3.6 5.2
Start Start
3.4 Stop 5
Stop
3.2 4.8
3 4.6
0 0.05 0.10 0.15 0.20 0 0.05 0.10 0.15 0.20
Output Current (A) C025
Output Current (A) C026
VO = 3.3 V VO = 5 V
Figure 25. 3.3 V Start / Stop Voltage Figure 26. 5.0 V Start / Stop Voltage
7.3.5 Error Amplifier

The TPS54240 has a transconductance amplifier for the error amplifier. The error amplifier compares the
VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The
transconductance (gM) of the error amplifier is 310 μA/V during normal operation. During the slow-start operation,
the transconductance is a fraction of the normal operating gm. When the voltage of the VSENSE pin is below 0.8
V and the device is regulating using the SS/TR voltage, the gm is 70 μA/V.
The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin
to ground.
7.3.6 Voltage Reference

The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output
of a temperature stable bandgap circuit.
7.3.7 Adjusting The Output Voltage

The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends using
1% tolerance or better divider resistors. Start with a 10-kΩ for the R2 resistor and use the Equation 1 to calculate
R1. To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the
regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be noticeable.
æ Vout - 0.8V ö
R1 = R2 ´ ç ÷
è 0.8 V ø (1)
7.3.8 Enable And Adjusting Undervoltage Lockout

The TPS54240 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher
undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using
the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation it is highly
recommended to provide consistent power-up behavior. The EN pin has an internal pullup current source, I1, of
0.9 μA that provides the default condition of the TPS54240 operating when the EN pin floats. Once the EN pin
voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, Ihys, is added. This additional current facilitates input
voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to set the
input start voltage.
spacer

TPS54240
TPS54240
VIN
Ihys
I1
R1 2.9 mA
0.9 mA
+
R2 EN 1.25 V -
Figure 27. Adjustable Undervoltage Lockout (UVLO)
V - VSTOP
R1 = START
IHYS
(2)
VENA
R2 =
VSTART - VENA
+ I1
R1 (3)
Another technique to add input voltage hysteresis is shown in Figure 28. This method may be used, if the
resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3
sources additional hysteresis current into the EN pin.
spacer
TPS54240
VIN
Ihys
R1 I1
2.9 mA
0.9 mA
+
R2 EN 1.25 V -
VOUT
R3
Figure 28. Adding Additional Hysteresis
VSTART - VSTOP
R1 =
V
IHYS + OUT
R3 (4)
VENA
R2 =
VSTART - VENA V
+ I1 - ENA
R1 R3 (5)

TPS54240

7.3.9 Slow-Start / Tracking Pin (SS/TR)
The TPS54240 effectively uses the lower voltage of the internal voltage reference, or the SS/TR pin voltage as
the power supply's reference voltage, and regulates the output accordingly. A capacitor on the SS/TR pin-to-
ground implements a slow start time. The TPS54240 has an internal pullup current source of 2 μA that charges
the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in Equation 6.
The voltage reference (VREF) is 0.8 V and the slow start current (ISS) is 2 μA. The slow-start capacitor should
remain lower than 0.47 μF and greater than 0.47 nF.
Tss(ms) ´ Iss(m A)
Css(nF) =
Vref (V) ´ 0.8 (6)
At power-up, the TPS54240 will not start switching until the slow-start pin is discharged to less than 40 mV. To
ensure a proper power up, see Figure 29.
Also, during normal operation, the TPS54240 will stop switching and the SS/TR must be discharged to 40 mV.
When the VIN UVLO is exceeded, the EN pin must be pulled below 1.25 V, or a thermal shutdown event occurs.
The VSENSE voltage will follow the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage
reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as
the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see
Figure 23). The SS/TR voltage will ramp linearly until clamped at 1.7 V.
spacer
EN
SS/TR
VSENSE
VOUT
Figure 29. Operation of SS/TR Pin When Starting
7.3.10 Overload Recovery Circuit

The TPS54240 has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the
overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit will
discharge the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pulldown of
382 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is
removed, the output will slow start from the fault voltage to nominal output voltage.

TPS54240

7.3.11 Sequencing
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins. The sequential method can be implemented using an open-drain output of a power on reset pin of another
device. The sequential method is illustrated in Figure 30 using two TPS54240 devices. The powergood is
coupled to the EN pin on the TPS54240, which will enable the second power supply once the primary supply
reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply will provide a
1-ms startup delay. Figure 31 shows the results of Figure 30.
TPS54240
PWRGD
EN EN
SS /TR SS /TR
PWRGD
Figure 30. Schematic for Sequential Startup Sequence
EN1
PWRGD1
VOUT1
VOUT2
Figure 31. Sequential Startup Using EN and PWRGD

TPS54240
TPS54160
TPS54240
3 EN
4 SS/TR
6 PWRGD
TPS54240
TPS54160
3 EN
4 SS/TR
6 PWRGD
Figure 32. Schematic for Ratio-metric Startup Sequence
EN1, EN2
VOUT1
VOUT2
Figure 33. Ratio-metric Startup Using Coupled SS/TR Pins
Figure 32 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The
regulator outputs will ramp up and reach regulation at the same time. When calculating the slow-start time, the
pullup current source must be doubled in Equation 6. Figure 33 shows the results of Figure 32.

TPS54240
TPS54240
EN VOUT 1
SS/TR
PWRGD
TPS54240
EN VOUT 2
R1
SS/ TR
R2
PWRGD
R3
R4
Figure 34. Schematic for Ratio-metric and Simultaneous Startup Sequence
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
of R1 and R2 shown in Figure 34 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation 7 and Equation 8, the tracking resistors can be calculated to initiate the Vout2
slightly before, after, or at the same time as Vout1. Equation 9 is the voltage difference between Vout1 and
Vout2 at the 95% of nominal output regulation.
The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
VSENSE, offset (Vssoffset) in the slow-start circuit and the offset created by the pullup current source (ISS) and
tracking resistors, the Vssoffset and Iss are included as variables in the equations.
To design a ratio-metric startup in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2
reaches regulation, use a negative number in Equation 7 through Equation 9 for deltaV. Equation 9 will result in a
positive number for applications which the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.
Since the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown fault,
careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the
calculated R1 value from Equation 7 is greater than the value calculated in Equation 10 to ensure the device can
recover from a fault.
As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger
as the slow-start circuits gradually hands off the regulation reference to the internal voltage reference. The
SS/TR pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as
shown in Figure 23.
Vout2 + deltaV Vssoffset
R1 = ´
VREF Iss (7)
VREF ´ R1
R2 =
Vout2 + deltaV - VREF (8)
deltaV = Vout1 - Vout2 (9)
R1 > 2800 ´ Vout1 - 180 ´ deltaV (10)

TPS54240
EN EN
VOUT1 VOUT1
VOUT2 VOUT2
Figure 35. Ratio-metric Startup With Tracking Resistors Figure 36. Ratio-metric Startup With Tracking Resistors
EN
VOUT1
VOUT2
Figure 37. Simultaneous Startup With Tracking Resistor

TPS54240

7.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
The switching frequency of the TPS54240 is adjustable over a wide range from approximately 100 kHz to 2500
kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor-
to-ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use
Equation 11 or the curves in Figure 38 or Figure 39. To reduce the solution size, one would typically set the
switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and
minimum controllable on time should be considered.
The minimum controllable on time is typically 135 ns and limits the maximum operating input voltage.
The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of
the maximum switching frequency is located below.
206033
RT (kOhm ) =
¦ sw (kHz )1.0888 (11)
2500 500
VI = 12 V,
TJ = 25°C
2000 400
fs - Switching Frequency - kHz

1500 300
200
1000
100
500
0
0
0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200
RT/CLK - Clock Resistance - kW RT/CLK Resistance (kW) C006
VI = 12 V TJ = 25°C
Figure 38. High Range RT Figure 39. Low Range RT
7.3.13 Overcurrent Protection and Frequency Shift

The TPS54240 implements current mode control which uses the COMP pin voltage to turn off the high-side
MOSFET on a cycle-by-cycle basis. Each cycle the switch current and COMP pin voltage are compared, when
the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent
conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high,
increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current
limit.
To increase the maximum operating switching frequency at high-input voltages, the TPS54240 implements a
frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on
VSENSE pin.
The device implements a digital frequency shift to enable synchronizing to an external clock during normal
startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum
input voltage limit in which the device operates and still have frequency shift protection.
During short-circuit events (particularly with high-input voltage applications), the control loop has a finite minimum
controllable on time and the output has a low voltage. During the switch-on time, the inductor current ramps to
the peak current limit because of the high-input voltage and minimum on time. During the switch-off time, the
inductor would normally not have enough off-time and output voltage for the inductor to ramp down by the ramp-
up amount. The frequency shift effectively increases the off-time allowing the current to ramp down.

TPS54240

7.3.14 Selecting the Switching Frequency
The switching frequency that is selected should be the lower value of the two equations, Equation 12 and
Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on-time.
Setting the switching frequency above this value will cause the regulator to skip-switching pulses.
Equation 13 is the maximum switching frequency limit set by the frequency shift protection. To have adequate
output short circuit protection at high-input voltages, the switching frequency should be set to be less than the
fSW(maxshift) frequency. In Equation 13, to calculate the maximum switching frequency one must take into account
that the output voltage decreases from the nominal voltage to 0 volts, the fdiv integer increases from 1 to 8,
corresponding to the frequency shift.
In Figure 40, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the
output voltage is zero volts, and the resistance of the inductor is 0.130-Ω, MOSFET on resistance of 0.2 Ω and
the diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping.
Enter these equations in a spreadsheet, or use the WEBENCH design software to determine the switching
frequency.
æ 1 ö æ (IL ´ Rdc + VOUT + Vd) ö
fSW (max skip ) = ç ÷ ´ çç ÷
è tON ø è (VIN - IL ´ Rhs + Vd) ø
÷
(12)
fdiv æ (IL ´ Rdc + VOUTSC + Vd) ö
fSW (shift ) = ´ç ÷
tON çè (VIN - IL x Rhs + Vd) ÷ø
(13)
IL inductor current
Rdc inductor resistance
VIN maximum input voltage
VOUT output voltage
VOUTSC output voltage during short
Vd diode voltage drop
RDS(on) switch on resistance
tON controllable on time
ƒDIV frequency divide equals (1, 2, 4, or 8)
2500
VO = 3.3 V
fs - Switching Frequency - kHz
2000
Shift
1500
Skip
1000
500
0
10 20 30 40
VI - Input Voltage - V
Figure 40. Maximum Switching Frequency vs. Input Voltage

TPS54240

7.3.15 How to Interface to RT/CLK Pin
The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the
synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in
Figure 41. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin
and have an on-time greater than 40 nS and an off-time greater than 40 ns. The synchronization frequency
range is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin
signal. The external synchronization circuit should be designed in such a way that the device will have the default
frequency set resistor connected from the RT/CLK pin-to-ground should the synchronization signal turn-off. It is
recommended to use a frequency set resistor connected as shown in Figure 41 through a 50-Ω resistor-to-
ground. The resistor should set the switching frequency close to the external CLK frequency. TI recommends
AC-coupling the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin and a 4-kΩ series
resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock
and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the
CLK threshold, the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage
source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal.
Since there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with
the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or
decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds.
When the device transitions from the PLL to resistor mode, the switching frequency will slow down from the CLK
frequency to 150 kHz, then reapply the 0.5-V voltage and the resistor will then set the switching frequency. The
switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The
device implements a digital frequency shift to enable synchronizing to an external clock during normal startup
and fault conditions. Figure 42, Figure 43 and Figure 44 show the device synchronized to an external system
clock in continuous conduction mode (CCM) discontinuous conduction (DCM) and pulse skip mode (PSM).
TPS54240
10 pF 4 kW
PLL
Rfset
EXT RT/CLK
Clock 50 W
Source
Figure 41. Synchronizing to a System Clock

TPS54240
PH
PH
EXT EXT
IL
IL
Figure 42. Plot of Synchronizing in CCM Figure 43. Plot of Synchronizing in DCM
PH
EXT
IL
Figure 44. Plot of Synchronizing in PSM
7.3.16 Powergood (PWRGD Pin)

The PWRGD pin is an open-drain output. Once the VSENSE pin is between 94% and 107% of the internal
voltage reference, the PWRGD pin is de-asserted and the pin floats. TI recommends using a pullup resistor
between the values of 10 and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state
once the VIN input voltage is greater than 1.5 V but with reduced current sinking capability. The PWRGD will
achieve full current sinking capability as VIN input voltage approaches 3 V.

TPS54240

The PWRGD pin is pulled low when the VSENSE is lower than 92% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin
pulled low.
7.3.17 Overvoltage Transient Protection

The TPS54240 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot
when recovering from output fault conditions or strong unload transients on power supply designs with low-value
output capacitance. For example, when the power supply output is overloaded the error amplifier compares the
actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal
reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error
amplifier output to a high voltage, thus requesting the maximum output current. Once the condition is removed,
the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some
applications, the power supply output voltage can respond faster than the error amplifier output can respond, this
actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when
using a low-value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP
threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP
threshold, the high-side MOSFET is disabled, preventing current from flowing to the output and minimizing output
overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed
to turn on at the next clock cycle.
7.3.18 Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal
trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power-up sequence
by discharging the SS/TR pin.
7.3.19 Small Signal Model for Loop Response

Figure 45 shows an equivalent model for the TPS54240 control loop which can be modeled in a circuit simulation
program to check frequency response and dynamic load response. The error amplifier is a transconductance
amplifier with a gmEA of 310 μA/V. The error amplifier can be modeled using an ideal voltage controlled current
source. The resistor Ro and capacitor Co model the open-loop gain and frequency response of the amplifier. The
1-mV AC voltage source between the nodes A and B effectively breaks the control loop for the frequency
response measurements. Plotting C/A shows the small signal response of the frequency compensation. Plotting
A/B shows the small signal response of the overall loop. The dynamic loop response can be checked by
replacing RL with a current source with the appropriate load step amplitude and ste- rate in a time domain
analysis. This equivalent model is only valid for continuous conduction mode designs.

TPS54240
PH
VO
Power Stage
gmps 10.5 A/V
a
R1 RESR
COMP RL
c
VSENSE COUT
0.8 V
R3 CO RO
gmea
C2
350 mA/V R2
C1
Figure 45. Small Signal Model for Loop Response
7.3.20 Simple Small Signal Model for Peak Current Mode Control
Figure 46 describes a simple small signal model that can be used to understand how to design the frequency
compensation. The TPS54240 power stage can be approximated to a voltage-controlled current source (duty
cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer
function is shown in Equation 14 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient
of the change in switch current and the change in COMP pin voltage (node C in Figure 45) is the power stage
transconductance. The gmPS for the TPS54240 is 10.5 A/V. The low-frequency gain of the power stage
frequency response is the product of the transconductance and the load resistance as shown in Equation 15.
As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This
variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the
load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of
Figure 46. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB
crossover frequency the same for the varying load conditions which makes it easier to design the frequency
compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on
the frequency compensation design. Using high-ESR aluminum electrolytic capacitors may reduce the number
frequency compensation components needed to stabilize the overall loop because the phase margin increases
from the ESR zero at the lower frequencies (see Equation 17).

TPS54240
VO
VC Adc
RESR
fp
RL
gmps
COUT
fz
Figure 46. Simple Small Signal Model and Frequency Response for Peak Current Mode Control
æ s ö
ç1 + ÷
VOUT 2p ´ fZ ø
= Adc ´ è
VC æ s ö
ç1 + ÷
è 2 p ´ fP ø (14)
Adc = gmps ´ RL
(15)
1
fP =
COUT ´ RL ´ 2p (16)
1
fZ =
COUT ´ RESR ´ 2p (17)
7.3.21 Small Signal Model for Frequency Compensation

The TPS54240 uses a transconductance amplifier for the error amplifier and readily supports three of the
commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are
shown in Figure 47. Type 2 circuits most likely implemented in high-bandwidth, power supply designs using low-
ESR output capacitors. The Type 1 circuit is used with power supply designs with high-ESR aluminum
electrolytic or tantalum capacitors.. Equation 18 and Equation 19 show how to relate the frequency response of
the amplifier to the small signal model in Figure 47. The open-loop gain and bandwidth are modeled using the RO
and CO shown in Figure 47. See Application Information for a design example using a Type 2A network with a
low-ESR output capacitor.
Equation 18 through Equation 27 are provided as a reference for those who prefer to compensate using the
preferred methods. Those who prefer to use prescribed method use the method outlined in the Application
Information and Implementation section or use switched information.

TPS54240
VO
R1
VSENSE
gmea Type 2A Type 2B Type 1
COMP
Vref
R3 C2 R3
R2 RO CO C2
C1 C1
Figure 47. Types of Frequency Compensation
Aol
A0 P1
Z1 P2
A1
BW
Figure 48. Frequency Response of the Type 2A and Type 2B Frequency Compensation
Aol(V/V)
Ro =
gmea (18)
gmea
CO =
2p ´ BW (Hz) (19)
æ s ö
ç1 + ÷
è 2p ´ fZ1 ø
EA = A0 ´
æ s ö æ s ö
ç1 + ÷ ´ ç1 + ÷
è 2p ´ fP1 ø è 2p ´ fP2 ø
(20)
R2
A0 = gmea ´ Ro ´
R1 + R2 (21)
R2
A1 = gmea ´ Ro| | R3 ´
R1 + R2 (22)
1
P1 =
2p ´ Ro ´ C1 (23)

TPS54240

1
Z1 =
2p ´ R3 ´ C1 (24)
1
P2 = type 2a
2p ´ R3 | | RO ´ (C2 + CO ) (25)
1
P2 = type 2b
2p ´ R3 | | RO ´ CO (26)
1
P2 = type 1
2p ´ R O ´ (C2 + C O ) (27)
7.4 Device Functional Modes

7.4.1 Operation Near Minimum VIN (V(VIN) = < 3.5 V)
The TPS54240 is designed to operate with input voltage above 3.5 V. The typical VIN UVLO threshold is 2.5 V
and the device may operate at input voltages down to the UVLO voltage. At input voltages below the UVLO
voltage, the device does not switch. If an external resistor divider pulls the EN pin up to VIN or the EN pin is
floating, when VIN passes the UVLO threshold the device becomes active. When the device is active, switching
begins and the soft-start sequence initiates. The TPS54240 ramps up the output voltage at the soft-start time
determined by the external capacitance on the SS/TR pin.
7.4.2 Operation With EN Control

The enabled threshold voltage is 1.2 V typical. With EN held below the threshold voltage the device is shut down
and switching is inhibited even if the VIN voltage is above its UVLO threshold. The IC quiescent current
decreases to a minimum in this state. If the EN pin voltage is increased above its threshold while the VIN voltage
is also above its UVLO threshold, the device becomes active. When the device is active, switching begins and
the soft-start sequence initiates. The TPS54240 ramps up the output voltage at the soft-start time determined by
the external capacitance on the SS/TR pin.
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

The TPS54240 device is a 42-V, 2.5-A, step-down regulator with an integrated high-side MOSFET. This device
typically converts a higher DC voltage to a lower DC voltage with a maximum available output current of 2.5 A.
Example applications are 12-V and 24-V industrial, automotive and communication power systems. Use the
following design procedure to select component values for the TPS54240 device. This procedure illustrates the
design of a high-frequency switching regulator using ceramic output capacitors. The Excel™ spreadsheet
(SLVC432) located on the product page can help on all calculations. Alternatively, use the WEBENCH software
to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a
comprehensive database of components when generating a design.

TPS54240
8.2 Typical Application

8.2.1 TPS54240 3.3-V Output Design
TPS54240DGQ
Figure 49. 3.3-V Output TPS54240 Design Example
8.2.1.1 Design Requirements

This example details the design of a high-frequency switching regulator design using ceramic output capacitors.
A few parameters must be known in order to start the design process. These parameters are typically determined
at the system level. For this example, we will start with the following known parameters:
DESIGN PARAMETERS VALUE

Output Voltage 3.3 V
Transient Response 0 to 1.5-A load step ΔVout = 3 %
Maximum Output Current 2.5 A
Input Voltage 12 V nom. 10.8 V to 13.2 V
Output Voltage Ripple 1% of Vout
Start Input Voltage (rising VIN) 6.25 V
Stop Input Voltage (falling VIN) 5.9 V
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Selecting the Switching Frequency

The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the
highest switching frequency possible since this will produce the smallest solution size. The high-switching
frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that
switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of
the internal power switch, the input voltage and the output voltage and the frequency shift limitation.
Equation 12 and Equation 13 must be used to find the maximum switching frequency for the regulator, choose
the lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping
or the lack of overcurrent protection during a short circuit.

TPS54240
The typical minimum on time, tonmin, is 135 ns for the TPS54240. For this example, the output voltage is 3.3 V
and the maximum input voltage is 13.2 V, which allows for a maximum switch frequency up to 2247 kHz when
including the inductor resistance, on resistance output current and diode voltage in Equation 12. To ensure
overcurrent runaway is not a concern during short circuits in your design use Equation 13 or the solid curve in
Figure 40 to determine the maximum switching frequency. With a maximum input voltage of 13.2 V, assuming a
diode voltage of 0.7 V, inductor resistance of 26 mΩ, switch resistance of 200 mΩ, a current limit value of 3.5 A
and a short circuit output voltage of 0.2 V. The maximum switching frequency is approximately 4449 kHz.
For this design, a much lower switching frequency of 300 kHz is used. To determine the timing resistance for a
given switching frequency, use Equation 11 or the curve in Figure 39.
The switching frequency is set by resistor R3 shown in Figure 49 For 300-kHz operation a 412-kΩ resistor is
required.
8.2.1.2.2 Output Inductor Selection (LO)

To calculate the minimum value of the output inductor, use Equation 28.
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high-inductor ripple
currents will impact the selection of the output capacitor since the output capacitor must have a ripple current
rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion
of the designer; however, the following guidelines may be used.
For designs using low ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used.
When using higher ESR output capacitors, KIND = 0.2 yields better results. Since the inductor ripple current is
part of the PWM control system, the inductor ripple current should always be greater than 150 mA for
dependable operation. In a wide-input voltage regulator, it is best to choose an inductor ripple current on the
larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its
minimum.
For this design example, use KIND = 0.3 and the minimum inductor value is calculated to be 11 μH. For this
design, a nearest standard value was chosen: 10 μH. For the output filter inductor, it is important that the RMS
current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from
Equation 30 and Equation 31.
For this design, the RMS inductor current is 2.51 A and the peak inductor current is 2.913 A. The chosen
inductor is a Coilcraft MSS1038-103NLB . It has a saturation current rating of 4.52 A and an RMS current rating
of 4.05 A.
As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but
will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of
the regulator but allow for a lower inductance value.
The current flowing through the inductor is the inductor ripple current plus the output current. During power-up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.
Vinmax - Vout Vout
Lo min = ´
Io ´ KIND Vinmax ´ ƒsw (28)
IRIPPLE =
VOUT ´ (Vin max - VOUT )
Vin max ´ L O ´ fSW (29)
2
1 æ VOUT ´ (Vinmax- VOUT ) ö
IL(rms) = (IO )2 + 12 ´ çç Vinmax ´ LO ´ fSW
÷
÷
è ø (30)
Iripple
ILpeak = Iout +
2 (31)

TPS54240
8.2.1.2.3 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor will
determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in
load current. The output capacitance needs to be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator also will temporarily not be able to
supply sufficient output current if there is a large, fast increase in the current needs of the load such as
transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop
to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for two clock cycles while only
allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance
necessary to accomplish this.
Where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the
allowable change in the output voltage. For this example, the transient load response is specified as a 3%
change in Vout for a load step from 1.5 A to 2.5 A (full load). For this example, ΔIout = 2.5-1.5 = 1.0 A and ΔVout
= 0.03 × 3.3 = 0.099 V. Using these numbers gives a minimum capacitance of 67 μF. This value does not take
the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is
usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher
ESR that should be taken into account.
The catch diode of the regulator cannot sink current so any stored energy in the inductor will produce an output
voltage overshoot when the load current rapidly decreases, see Figure 50. The output capacitor must also be
sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current.
The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The
capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33 is
used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is
the value of the inductor, IOH is the output current under heavy load, IOL is the output under light load, Vf is the
final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be
from 2.5 A to 1.5 A. The output voltage will increase during this load transition and the stated maximum in our
specification is 3 % of the output voltage. This will make Vf = 1.03 × 3.3 = 3.399 V. Vi is the initial capacitor
voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum
capacitance of 60 μF.
Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Iripple is the
inductor ripple current. Equation 34 yields 12 μF.
Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 35 indicates the ESR should be less than 36 mΩ.
The most stringent criteria for the output capacitor is 67 μF of capacitance to keep the output voltage in
regulation during an load transient.
Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which will increase
this minimum value. For this example, 2 x 47-μF, 10-V ceramic capacitors with 3 mΩ of ESR will be used. The
derated capacitance is 72.4 µF, above the minimum required capacitance of 67 µF.
Capacitors generally have limits to the amount of ripple current they can handle without failing or producing
excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor
data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 36 can be used
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields
238 mA.
2 ´ DIout
Cout >
¦ sw ´ DVout (32)

TPS54240
Cout > Lo ´
(Ioh2
- Iol2)
(V ¦ 2
- Vi )2
(33)
1 1
Cout > ´
8 ´ ¦ sw VORIPPLE
IRIPPLE (34)
V
RESR < ORIPPLE
IRIPPLE
(35)
Vout ´ (Vin max - Vout)
Icorms =
12 ´ Vin max ´ Lo ´ ¦ sw (36)
8.2.1.2.4 Catch Diode

The TPS54240 requires an external catch diode between the PH pin and GND. The selected diode must have a
reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than
the maximum inductor current. The diode should also have a low-forward voltage. Schottky diodes are typically a
good choice for the catch diode due to their low-forward voltage. The lower the forward voltage of the diode, the
higher the efficiency of the regulator.
Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be.
Although the design example has an input voltage up to 13.2 V, a diode with a minimum of 60-V reverse voltage
is selected.
For the example design, the B360B-13-F Schottky diode is selected for its lower-forward voltage and it comes in
a larger package size which has good thermal characteristics over small devices. The typical forward voltage of
the B360B-13-F is 0.70 volts.
The diode must also be selected with an appropriate power rating. The diode conducts the output current during
the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input
voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by
the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies,
the AC losses of the diode need to be taken into account. The AC losses of the diode are due to the charging
and discharging of the junction capacitance and reverse recovery. Equation 37 is used to calculate the total
power dissipation, conduction losses plus SC losses, of the diode.
The B360B-13-F has a junction capacitance of 200 pF. Using Equation 37, the selected diode will dissipate 1.32
Watts.
If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a
diode which has a low leakage current and slightly higher-forward voltage drop.
2
(Vin max - Vout) ´ Iout ´ Vƒd Cj ´ ƒsw ´ (Vin + Vƒd)
Pd = +
Vin max 2 (37)
8.2.1.2.5 Input Capacitor

The TPS54240 requires a high-quality ceramic, type X5R or X7R, input-decoupling capacitor of at least 3 μF of
effective capacitance, and in some applications, a bulk capacitance. The effective capacitance includes any DC
bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The
capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54240.
The input ripple current can be calculated using Equation 38.
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the
capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that
is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power-regulator capacitors
because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output
capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases.

TPS54240
For this example design, a ceramic capacitor with at least a 60-V voltage rating is required to support the
maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25
V, 50 V or 100 V, so a 100-V capacitor should be selected. For this example, two 2.2-μF, 100-V capacitors in
parallel have been selected. Table 1 shows a selection of high voltage capacitors. The input capacitance value
determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 39.
Using the design example values, Ioutmax = 2.5 A, Cin = 4.4 μF, ƒsw = 300 kHz, yields an input voltage ripple of
206 mV and a rms input ripple current of 1.15 A.
Vout (Vin min - Vout )
Icirms = Iout ´ ´
Vin min Vin min (38)
Iout max ´ 0.25
ΔVin =
Cin ´ ¦ sw (39)
Table 1. Capacitor Types

VENDOR VALUE (μF) EIA Size VOLTAGE DIALECTRIC COMMENTS
1.0 to 2.2 100 V
1210 GRM32 series
1.0 to 4.7 50 V
Murata
1.0 100 V
1206 GRM31 series
1.0 to 2.2 50 V
1.0 10 1.8 50 V
2220
1.0 to 1.2 100 V
Vishay VJ X7R series
1.0 to 3.9 50 V
2225
1.0 to 1.8 100 V
X7R
1.0 to 2.2 100 V
1812 C series C4532
1.5 to 6.8 50 V
TDK
1.0. to 2.2 100 V
1210 C series C3225
1.0 to 3.3 50 V
1.0 to 4.7 50 V
1210
1.0 100 V
AVX X7R dielectric series
1.0 to 4.7 50 V
1812
1.0 to 2.2 100 V
8.2.1.2.6 Slow-Start Capacitor

The slow-start capacitor determines the minimum amount of time it will take for the output voltage to reach its
nominal programmed value during power-up. This is useful if a load requires a controlled voltage slew rate. This
is also used if the output capacitance is large and would require large amounts of current to quickly charge the
capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the
TPS54240 reach the current limit or excessive current draw from the input power supply may cause the input
voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.
The slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output
voltage without drawing excessive current. Equation 40 can be used to find the minimum slow-start time, tss,
necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average
slow-start current of Issavg. In the example, to charge the effective output capacitance of 72.4 µF up to 3.3 V
while only allowing the average output current to be 1 A would require a 0.19-ms slow-start time.
Once the slow-start time is known, the slow-start capacitor value can be calculated using Equation 6. For the
example circuit, the slow-start time is not too critical since the output capacitor value is 2 x 47 μF which does not
require much current to charge to 3.3 V. The example circuit has the slow start-time set to an arbitrary value of
3.5 ms which requires a 8.75 nF slow-start capacitor. For this design, the next larger standard value of 10 nF is
used.
Cout ´ Vout ´ 0.8
tss >
Issavg (40)

TPS54240
8.2.1.2.7 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI
recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or
higher voltage rating.
8.2.1.2.8 Undervoltage Lock Out Set Point

The Undervoltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54240. The UVLO has two thresholds, one for power-up when the input voltage is rising, and one for power-
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 6.25 V (enabled). After the regulator starts switching, it should
continue to do so until the input voltage falls below 5.9 V (UVLO stop).
The programmable UVLO and enable voltages are set using the resistor divider of R1 and R2 between Vin and
ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary.
For the example application, a 124 kΩ between Vin and EN (R1) and a 30.1 kΩ between EN and ground (R2)
are required to produce the 6.25 and 5.9 volt start and stop voltages.
8.2.1.2.9 Output Voltage And Feedback Resistors Selection

The voltage divider of R5 and R6 is used to set the output voltage. For the example design, 10.0 kΩ was
selected for R6. Using Equation 1, R5 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ.
Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater
than 1 μA to maintain the output voltage accuracy. This requirement makes the maximum value of R2 equal to
800 kΩ. Choosing higher resistor values will decrease quiescent current and improve efficiency at low-output
currents but may introduce noise immunity problems.
8.2.1.2.10 Compensation
There are several methods used to compensate DC - DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope
compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency
used in the calculations. This method assumes the cross-over frequency is between the modulator pole and the
ESR zero and the ESR zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more
accurate design.
To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using Equation 41 and
Equation 42. For Cout, use a derated value of 40 μF. Use equations Equation 43 and Equation 44, to estimate a
starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is
1206 Hz and fzmod is 530.5 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and
Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 25.3 kHz and
Equation 44 gives 13.4 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency.
For this example, a higher fco is desired to improve transient response. the target fco is 35.0 kHz. Next, the
compensation components are calculated. A resistor-in-series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole.
Ioutmax
¦p mod =
2 × p × Vout × Cout (41)
1
¦ z mod =
2 ´ p ´ Resr × Cout (42)
fco = f p mod ´ f z mod
(43)
f sw
fco = f p mod ´
2 (44)
To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance,
gmps, is 10.5 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are
3.3 V, 0.8 V and 310 μA/V, respectively. R4 is calculated to be 20.2 kΩ, use the nearest standard value of 20.0
kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 4740 pF
for compensating capacitor C5, a 4700 pF is used for this design.

TPS54240
æ 2 ´ p ´ fco ´ Cout ö æ Vout ö

R4 = ç ÷´ç ÷
è gmps V
ø è ref ´ gmea ø (45)
1
C5 =
2 ´ p ´ R4 ´ fpmod
(46)
A compensation pole can be implemented if desired using an additional capacitor C8 in parallel with the series
combination of R4 and C5. Use the larger value of Equation 47 and Equation 48 to calculate the C8, to set the
compensation pole. C8 is not used for this design example.
C ´ Re sr
C8 = o
R4 (47)
1
C8 =
R4 ´ f sw ´ p (48)
8.2.1.2.11 Discontinuous Mode And Eco-Mode Boundary

With an input voltage of 12 V, the power supply enters discontinuous mode when the output current is less than
337 mA. The power supply enters Eco-Mode when the output current is lower than 5 mA.
The input current draw at no load is 392 μA.
8.2.1.2.12 Power Dissipation Estimate

The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM)
operation. These equations should not be used if the device is working in discontinuous conduction mode (DCM).
The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and
supply current (Pq).
Vout
Pcon = Io2 ´ RDS(on) ´
Vin (49)
Psw = Vin 2 ´ ¦ sw ´ lo ´ 0.25 ´ 10-9 (50)
-9
Pgd = Vin ´ 3 ´ 10 ´ ¦ sw (51)
-6
Pq = 116 ´ 10 ´ Vin (52)
Where:
Iout is the output current (A).
RDS(on) is the on-resistance of the high-side MOSFET (Ω).
Vout is the output voltage (V).
Vin is the input voltage (V).
fsw is the switching frequency (Hz).
So
Ptot = Pcon + Psw + Pgd + Pq (53)
For given TA,
TJ = TA + Rth ´ Ptot (54)
For given TJMAX = 150°C
TAmax = TJmax - Rth ´ Ptot (55)
Where:
Ptot is the total device power dissipation (W).
TA is the ambient temperature (°C).
TJ is the junction temperature (°C).
Rth is the thermal resistance of the package (°C/W).
TJMAX is maximum junction temperature (°C).
TAMAX is maximum ambient temperature (°C).

TPS54240
There will be additional power losses in the regulator circuit due to the inductor AC and DC losses, the catch
diode and trace resistance that will impact the overall efficiency of the regulator.
8.2.1.3 Application Curves
Vout = 50 mv / div (ac coupled) Vin = 10 V / div
Vout = 2 V / div
Output Current = 1 A / div (Load Step 1.5 A to 2.5 A)
EN = 2 V / div
SS/TR = 2 V / div
Time = 200 usec / div Time = 5 msec / div
Figure 50. Load Transient Figure 51. Startup With VIN
Vout = 20 mV / div (ac coupled) Vout = 20 mV / div (ac coupled)
PH = 5 V / div PH = 5 V / div
Time = 2 usec / div Time = 2 usec / div

Figure 52. Output Ripple, CCM Figure 53. Output Ripple, DCM
Vin = 200 mV / div (ac coupled)

Vout = 20 mV / div (ac coupled)
PH = 5 V / div
PH = 5 V / div
Time = 10 usec / div Time = 2 usec / div
Figure 54. Output Ripple, PSM Figure 55. Input Ripple, CCM
100
90
Vin = 50 mV / div (ac coupled)
80
70
Efficiency - %
60
50
PH = 5 V / div 40
30
VIN=12V
20 VOUT=3.3V
fsw=300kHz
10
0
0 0.5 1.0 1.5 2.0 2.5 3.0
Time = 2 usec / div IO - Output Current - A
Figure 56. Input Ripple, DCM Figure 57. Efficiency vs Load Current

TPS54240
100 60 180
90
40 120
80
Phase
70
20 60
Efficiency - %
60 Gain
Phase - o
Gain - dB
50 0 0
40
-20 -60
30
VIN=12V
20 VOUT=3.3V VIN=12 V
fsw=300kHz -40 VOUT=3.3V -120
10 IOUT=2.5A
0 -60 -180
0.001 0.01 0.1 10 100 1-103 1-104 1-105 1-106
IO - Output Current - A f - Frequency - Hz
Figure 58. Light Load Efficiency Figure 59. Overall Loop Frequency Response
3.4 3.4
3.38 3.38
VO - Output Voltage - V
VO - Output Voltage - V
3.36 3.36
3.34 3.34
VIN=12V
3.32 3.32 VOUT=3.3V
VIN=12V fsw=300kHz
VOUT=3.3V
fsw=300kHz
IOUT=1.5A
3.3 3.3
0 0.5 1.0 1.5 2.0 2.5 3.0 10.8 11.2 11.6 12 12.4 12.8 13.2
IO - Output Current - A IO - Output Current - A
Figure 60. Regulation vs Load Current Figure 61. Regulation vs Input Voltage
8.2.2 TPS54240 Inverting Power Supply

This application circuit shows how to use the TPS54240 to convert a positive-input voltage to a negative-output
voltage. Ideal applications are amplifiers requiring a negative power supply. For a more-detailed example, see
Create an Inverting Power Supply From a Step-Down Regulator, application report SLVA317.
VIN +
Cin
Cboot
Lo
VIN BOOT PH GND
Cd R1
GND +
R2 Co
TPS54240
VOUT
VSENSE
EN
SS/TR COMP
RT/CLK Rcomp
Czero Cpole
Css RT
Figure 62. TPS54240 Inverting Power Supply

TPS54240
8.2.3 TPS54240 Split Rail Power Supply

This application circuit shows how to use the TPS54240 to convert a positive-input voltage to a split-rail positive-
and negative-output voltage by using a coupled inductor. Ideal applications are amplifiers requiring a split-rail
positive- and negative-voltage power supply. For a more-detailed example, see Creating a Split-Rail Power
Supply With a Wide Input Voltage Buck Regulator, application report SLVA369.
VOPOS
+
VIN + Copos
Cin
Cboot
PH
GND
VIN BOOT
Lo
Cd R1
+
GND Coneg
TPS54240 R2
VSENSE VONEG
EN
SS/TR COMP
RT/CLK Rcomp
Czero Cpole
Css RT
Figure 63. TPS54240 Split Rail Power Supply
8.2.4 12-V To 3.8-V GSM Power Supply

This application circuit is designed with TPS54240 device to power GSM-GPRS modules. GSM-GPRS modules
typically require a power supply that can support large output current transients. For a more-detailed example,
see Creating GSM-GPRS Power Supply, application report SLVA412.
TPS54240DGQ
Figure 64. 12-V to 3.8-V GSM Power Supply

TPS54240
8.2.5 24-V to 4.2-V GSM Power Supply

This application circuit is also designed to power GSM-GPRS modules. For a more-detailed example, see
Creating GSM-GPRS Power Supply, application report SLVA412.
TPS54240DGQ
Figure 65. 24-V to 4.2-V GSM Power Supply

TPS54240
9 Power Supply Recommendations

The design of the device is for operation from an input voltage supply range between 3.5 V and 42 V. Good
regulation of this input supply is essential. If the input supply is more distant than a few inches from the
TPS54240 converter, the circuit may require additional bulk capacitance in addition to the ceramic bypass
capacitors. An electrolytic capacitor with a value of 100 µF is a typical choice.
10 Layout
10.1 Layout Guidelines

Layout is a critical portion of good power supply design. There are several signal paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed
to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop
area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 66
for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power
pad.
The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC.
The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH
connection is the switching node, the catch diode and output inductor should be located close to the PH pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated
load, the top-side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise
so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The
additional external components can be placed approximately as shown. It may be possible to obtain acceptable
performance with alternate PCB layouts, however this layout has been shown to produce good results and is
meant as a guideline.
10.2 Layout Example

Vout
Output
Capacitor Output
Topside Inductor
Ground Route Boot Capacitor
Area Catch
Trace on another layer to
provide wide path for Diode
topside ground
Input
Bypass
Capacitor BOOT PH
Vin
VIN GND
EN COMP
UVLO
SS/TR VSENSE Compensation
Adjust
Resistor
Resistors Network
RT/CLK PWRGD Divider
Slow Start
Frequency Thermal VIA
Capacitor
Set Resistor
Signal VIA
Figure 66. PCB Layout Example

TPS54240
10.3 Estimated Circuit Area

The estimated printed circuit board area for the components used in the design of Figure 49 is 0.55 in2. This area
does not include test points or connectors.
11 Device and Documentation Support
11.1 Device Support

11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support

11.2.1 Related Documentation
Create an Inverting Power Supply From a Step-Down Regulator, application report SLVA317
Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator, application report SLVA369
Creating GSM-GPRS Power Supply, application report SLVA412
11.3 Trademarks
Eco-Mode, PowerPAD are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPS54240DGQ ACTIVE HVSSOP DGQ 10 80 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 54240
& no Sb/Br)
TPS54240DGQR ACTIVE HVSSOP DGQ 10 2500 Green (RoHS NIPDAUAG Level-1-260C-UNLIM -40 to 125 54240
& no Sb/Br)
TPS54240DRCR ACTIVE VSON DRC 10 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 54240
& no Sb/Br)
TPS54240DRCT ACTIVE VSON DRC 10 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 54240
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54240 :
• Automotive: TPS54240-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54240DGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS54240DGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1
TPS54240DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS54240DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jul-2020
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54240DGQR HVSSOP DGQ 10 2500 364.0 364.0 27.0
TPS54240DGQR HVSSOP DGQ 10 2500 346.0 346.0 35.0
TPS54240DRCR VSON DRC 10 3000 346.0 346.0 35.0
TPS54240DRCT VSON DRC 10 250 203.0 203.0 35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10 VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204102-3/M
PACKAGE OUTLINE
DRC0010J SCALE 4.000
VSON - 1 mm max height
3.1 B
A
2.9
PIN 1 INDEX AREA

3.1
2.9
1.0 C
0.8
SEATING PLANE
0.05
0.00 0.08 C
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED 4X (0.25)
THERMAL PAD
5 6
2X 11 SYMM
2
2.4 0.1
10
1
8X 0.5 0.30
10X
0.18
PIN 1 ID SYMM
0.1 C A B
(OPTIONAL)
0.5 0.05 C
10X
0.3
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J VSON - 1 mm max height
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
SYMM (2.4)
(3.4)
(0.95)
8X (0.5)
5 6
(R0.05) TYP
( 0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL
SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J VSON - 1 mm max height
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
11 TYP
10X (0.6)
1
10
(1.53)
10X (0.24) 2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

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Product Sample & Technical Tools & Support &

Folder Buy Documents Software Community

TPS54240 3.5-V to 42-V Step-Down DC - DC Converter With Eco-Mode™

Simplified Schematic Efficiency vs Load Current

Changes from Revision A (April 2010) to Revision B Page

Changes from Original (April 2010) to Revision A Page

• Added 10-Pin 3mm x 3mm SON to Features......................................................................................................................... 1

2 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated

Product Folder Links: TPS54240

5 Pin Configuration and Functions

Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 3

6.2 Handling Ratings

6.3 Recommended Operating Conditions

4 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated

Product Folder Links: TPS54240

6.4 Thermal Information

Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 5

6.5 Electrical Characteristics

6 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated

Product Folder Links: TPS54240

Electrical Characteristics (continued)

Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 7

6.6 Typical Characteristics

375 BOOT-PH = 3 V 0.808

Voltage Reference (V)

Figure 1. On Resistance vs Junction Temperature Figure 2. Voltage Reference vs Junction Temperature

Switching Frequency (kHz)

8 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated

Product Folder Links: TPS54240

Typical Characteristics (continued)

Figure 7. EA Transconductance during Slow Start vs Figure 8. EA Transconductance vs Junction Temperature

Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 9

Typical Characteristics (continued)

10 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated

Product Folder Links: TPS54240

Typical Characteristics (continued)

PWRGD Threshold (% of Vref)

Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 11

12 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated

Product Folder Links: TPS54240

7.2 Functional Block Diagram

7.3 Feature Description

7.3.2 Slope Compensation Output Current

7.3.3 Pulse Skip Eco-Mode

Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 13

Feature Description (continued)

7.3.4 Low Dropout Operation and Bootstrap Voltage (BOOT)

14 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated

Product Folder Links: TPS54240

Feature Description (continued)

Input Voltage (V)

7.3.5 Error Amplifier

7.3.6 Voltage Reference

7.3.7 Adjusting The Output Voltage

7.3.8 Enable And Adjusting Undervoltage Lockout

Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 15

Feature Description (continued)