NI FlexRIO Spec
NI FlexRIO Spec
NI FlexRIO Spec
Specifications
This document lists the specifications of the National Instruments FlexRIO FPGA modules (NI PXI-7951R, NI PXI-7952R,
NI PXI-7953R, NI PXI-7954R, NI PXIe-7961R, NI PXIe-7962R, and NI PXIe-7965R) devices. Typical values are
representative of an average unit operating at room temperature. These specifications are typical at 25 °C unless otherwise noted.
Reconfigurable FPGA
DSP48 Slices Embedded Block
Device FPGA LUTs/Flip-Flops (25 18 Multiplier) RAM (kbits)
Timebase accuracy
NI PXI-795xR............................. ±100 ppm, 250 ps
peak-to-peak jitter
NI PXIe-796xR........................... ±50 ppm, 250 ps
peak-to-peak jitter
Protection.........................................Refer to
www.xilinx.com
Current.............................................Refer to
www.xilinx.com
Maximum I/O data rates
Single-ended ...............................400 Mb/s for LVDCI25
Differential..................................1 Gb/s for LVDS
Connection resources
NI PXI-795xR .............................PXI triggers, Clk10, and
PXI star trigger
NI PXIe-796xR ...........................PXI triggers, Clk10,
PXI star trigger, DStarA,
DStarB, DStarC, and
Sync100
1 The 132 channels span across four FPGA banks. Refer to the Device Signals section for more information.
Bank 0
+12V P2 P2 +12V GND G20 G20 GND
Bank 1
VccoB S72 S146 VccoA GPIO_30 S38 S112 GPIO_14
Veeprom S71 S145 RSVD GPIO_30_n S37 S111 GPIO_14_n
GND G37 G37 GND GND G19 G19 GND
RSVD_A2 S70 S144 IoModSyncClk_n1 GPIO_31 S36 S110 GPIO_15
RSVD_A1 S69 S143 IoModSyncClk2 GPIO_31_n S35 S109 GPIO_15_n
GND G36 G36 GND GND G18 G18 GND
GPIO_16 S68 S142 GPIO_0 GPIO_32 S34 S108 GPIO_49
GPIO_16_n S67 S141 GPIO_0_n GPIO_32_n S33 S107 GPIO_49_n
GND G35 G35 GND GND G17 G17 GND
GPIO_17 S66 S140 GPIO_1 GPIO_33 S32 S106 GPIO_50
GPIO_17_n S65 S139 GPIO_1_n GPIO_33_n S31 S105 GPIO_50_n
GND G34 G34 GND NI PXI-795x R GND G16 G16 GND
GPIO_18 S64 S138 GPIO_2 FlexRIO GPIO_34 S30 S104 GPIO_51
GPIO_18_n S63 S137 GPIO_2_n GPIO_34_n S29 S103 GPIO_51_n
GND G33 G33 GND GND G15 G15 GND
GPIO_19 S62 S136 GPIO_3 GPIO_35 S28 S102 GPIO_52
GPIO_19_n S61 S135 GPIO_3_n GPIO_35_n S27 S101 GPIO_52_n
GND G32 G32 GND GND G14 G14 GND
GPIO_20 S60 S134 GPIO_4_CC GPIO_36 S26 S100 GPIO_53
GPIO_20_n S59 S133 GPIO_4_n_CC GPIO_36_n S25 S99 GPIO_53_n
GND G31 G31 GND GND G13 G13 GND
GPIO_21 S58 S132 GPIO_5_CC GPIO_37_CC S24 S98 GPIO_54
GPIO_21_n S57 S131 GPIO_5_n_CC GPIO_37_n_CC S23 S97 GPIO_54_n
GND G30 G30 GND GND G12 G12 GND
GPIO_22 S56 S130 GPIO_6_CC GPIO_38_CC S22 S96 GPIO_55
GPIO_22_n S55 S129 GPIO_6_n_CC GPIO_38_n_CC S21 S95 GPIO_55_n
Bank 0
Bank 1
Bank 3
Bank 2
Figure 1. NI FlexRIO FPGA Module Front Connector Pin Assignments and Locations