614 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO.

2, FEBRUARY 2005

A 24-GHz SiGe Phased-Array

Receiver—LO Phase-Shifting Approach
Hossein Hashemi, Member, IEEE, Xiang Guan, Student Member, IEEE, Abbas Komijani, Student Member, IEEE,
and Ali Hajimiri, Member, IEEE

Abstract—A local-oscillator phase-shifting approach is intro- associated wavelength that reduces the required size of the
duced to implement a fully integrated 24-GHz phased-array common resonant-based antennas and their spacing in a mul-
receiver using an SiGe technology. Sixteen phases of the local
tiple antenna scheme. The smaller antenna size will, however,
oscillator are generated in one oscillator core, resulting in a raw
beam-forming accuracy of 4 bits. These phases are distributed to result in a reduced collected power at these higher frequen-
all eight receiving paths of the array by a symmetric network. The cies. A recent study of an indoor wireless channel in an office
appropriate phase for each path is selected using high-frequency environment at a variety of carrier frequencies [8] reveals that,
analog multiplexers. The raw beam-steering resolution of the
at 24 GHz, the large absorbance of walls and ceilings results
array is better than 10 for a forward-looking angle, while the
array spatial selectivity, without any amplitude correction, is in more isolation between multiple floors and allows for in-
better than 20 dB. The overall gain of the array is 61 dB, while the creasing the frequency reuse and overall system capacity. It
array improves the input signal-to-noise ratio by 9 dB. also shows that the 24-GHz carrier frequency can support a
Index Terms—BiCMOS integrated circuits, phase-locked loops, higher data rate due to lower delay spreads. The excess path
phased arrays, radio receivers, silicon, voltage-controlled oscilla- loss at 24 GHz is more or less comparable to the 2.4- and
tors (VCOs). 5.2-GHz bands due to the waveguide effect inside the building
at higher frequencies.
I. INTRODUCTION To demonstrate the feasibility of a phased-array system on
silicon and explore its advantages, we have implemented the

P HASED ARRAYS are capable of beam forming and elec-

tronic steering by adjusting the relative phases of the signal
received or transmitted by each antenna. In the past, the high
first fully integrated 24-GHz phased-array receiver in silicon
[3]. After a brief description of narrow-band phased arrays
in Section II, we will focus on various architectural choices
price of discrete microwave modules limited the achievable
for a fully integrated phased-array receiver in Section III. The
complexity level of such systems for consumer applications.
receiver architecture of an eight-path phased-array receiver
A low-cost fully integrated silicon-based phased-array trans-
based on a local-oscillator (LO) phase-shifting scheme will
ceiver facilitates widespread commercial applications such as
be presented in Section IV. Multiple LO phase generation and
ultrahigh-speed wireless communications and vehicular radar.
distribution are covered in Section V, followed by receiver
The Federal Communications Commission (FCC), has allo-
array measured results in Section VI.
cated 250 MHz of bandwidth around the 24-GHz frequency
for unlicensed industrial, scientific, and medical (ISM) applica- II. NARROW-BAND PHASED ARRAYS
tions, in addition to field-disturbance sensors, as well as fixed
and point-to-point wireless operation [1]. The FCC has also When a plane electromagnetic (EM) wave arrives at an
opened up a 7-GHz window between 22-29 GHz for ultrawide- antenna array at an angle with respect to the normal to
band vehicular radar systems [2]. Consequently, research on array plane, the signal is received by each antenna at a different
24-GHz range wireless technologies has accelerated, demon- time due to the spatial path differences. In general, an angle-
strating various building blocks and single path receivers at this dependent time delay at the receiver can compensate the arrival
frequency [4]–[7]. delay and effectively focus the beam in a desired direction. In a
Compared to the 2.4- and 5-GHz frequencies that are com- one-dimensional array, the effective beam angle is related to
monly used for today’s short-range wireless data communi- the delay difference of two adjacent elements , the spacing
cations schemes, the 24-GHz carrier frequency has a smaller of two adjacent antennas , and the speed of light via

(1)
Manuscript received April 23, 2004; revised August 11, 2004. This work was
supported in part by the National Science Foundation and by the Lee Center for With ideal delay elements following each antenna, the beam
Advanced Networking. forming works independently of the frequency and bandwidth
H. Hashemi is with the Department of Electrical Engineering—Electro-
physics, University of Southern California, Los Angeles, CA 91030 USA
of the signal. Unfortunately, there are practical challenges to
(e-mail: hosseinh@usc.edu). implementation of such broad-band tunable delay elements in
X. Guan, A. Komijani, and A. Hajimiri are with the Department of Electrical the RF signal path, e.g., signal attenuation, noise, and linearity
Engineering, California Institute of Technology, Pasadena, CA 91125 USA
(e-mail: xiangg@caltech.edu; komijani@caltech.edu; hajimiri@caltech.edu). degradation, as well as signal dispersion. Fortunately, in many
Digital Object Identifier 10.1109/TMTT.2004.841218 practical applications, such as wireless communications, the
0018-9480/$20.00 © 2005 IEEE
HASHEMI et al.: 24-GHz SiGe PHASED-ARRAY RECEIVER 615

Fig. 1. Output signal constellation of an eight-path narrow-band phased-array

receiver.

bandwidth of interest is a small fraction of the center frequency

and, hence, a uniform delay (linear phase) is only required Fig. 2. EVM for two signal bandwidths of 750 MHz (1 Gb/s) and 7.5 GHz
(10 Gb/s) in an eight-path narrow-band phased-array receiver at 24 GHz.
over this narrow bandwidth. One way to implement the delay
is to approximate the uniform delay with a constant phase shift
inside the signal bandwidth. This makes the carrier phase at
different paths coherent, but because of the constant phase
shift and, hence, zero group delay, it does not synchronize the
baseband modulation signals. As the ratio of signal bandwidth
to carrier frequency increases, this baseband time incoherence
affects the signal integrity and results in constellation spreading.
This signal degradation is independent of the mechanism and/or
the architecture used to produce the phase shift. The effect can
be best seen through the following example.
Fig. 1 shows the simulated constellation of the received signal
(without noise) for an eight-path phased-array receiver at bit
rates of 1 and 10 Gb/s at the worst case incident angle of 90
with respect to normal, using a quadrature phase-shift keying
(QPSK) modulation scheme with a carrier frequency of 24 GHz.
A square-root raised cosine filter with a rolloff factor of 0.5 is
used at both the transmitter and receiver for pulse shaping. A Fig. 3. Simplified scheme of phase shifting at RF in a homodyne receiver.
of 0.5 corresponds to a spectrum efficiency of 1.33 bits/s/Hz.
As the direction of the beam becomes more oblique, the delay
As mentioned earlier, phase shifting can be performed at dif-
between the paths increases and so does the error introduced by
ferent stages, giving rise to different phase-array architectures.
constant phase-shift approximation. The constellation spreading
These architectural variations will be discussed below.
is a function of the signal’s angle of arrival, ratio of signal
bandwidth to the carrier frequency, and the modulation pulse
shape. The error vector magnitude (EVM) is a measure of III. PHASED-ARRAY RADIO ARCHITECTURES
constellation spreading and quantifies the difference between the A. Signal Path Phase Shifting
measured and ideal modulated signals. In a typical receiver, the
The most common method of adjusting the signal time delay
EVM is degraded due to noise, nonlinearity, and mismatches
is by approximating it with a variable phase shift at the
between in-phase (I) and quadrature-phase (Q) paths. The
bandwidth of interest in each signal path, as shown in Fig. 3.
approximation of propagation delay with a constant phase shift
The phase shifters should have a relatively low loss across the
is another factor contributing to a higher EVM in phased-array bandwidth of the received signal so that they do not attenuate the
systems. The EVM of the received signal is calculated for received signal and degrade the overall signal-to-noise ratio. A
different signal bandwidths and angles of incidence and the low-loss and broad-band variable phase shifter at high frequen-
result is plotted in Fig. 2. As can be noted, for a carrier of 24 cies is a challenging building block to implement in an inte-
GHz, even for bit rates as high as 1 Gb/s and an incidence angle grated setting and is a source of active research [10], [11]. By
of 90 (worst case), the level of EVM is lower than 2 , and the phase shifting and signal combining at RF, other radio blocks are
signal integrity is maintained without the need for any additional shared among the paths resulting in reduced area and power con-
equalization. This figure shows the narrow-band phase-shifting sumption. Additionally, since the unwanted interference signals
approach to be a viable solution for wireless communications are cancelled after signal combining, the dynamic-range (both
at 24 GHz. Of course, there is a gradual degradation of the linearity and noise figure) requirements of the following blocks
constellation integrity as the signal bandwidth continues to are more relaxed, allowing them to trade this with other system
increase. requirements such as power consumption. If amplitude control
616 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Fig. 4. Simplified scheme of digital-array implementation in a homodyne

receiver.

is needed (e.g., for null placement), it can be achieved by vari- Fig. 5. Simplified scheme of phase shifting at the LO in a homodyne receiver.
able-gain low-noise amplifiers (LNAs) before or after the phase
shifters at RF.
a comparison, the fastest rate for sending the data into a per-
Phase shifting and signal combining can also be performed
sonal computer using today’s peripheral component intercon-
after down-converting the received signals to an IF. Due to the
nect (PCI) standard is bits MHz Gb/s. This
additional signal amplification at the RF stages, phase-shifter
rate is almost halved when notebook computers are used (e.g.,
loss will have a less deteriorating effect on receiver sensitivity
the IEEE1394 Standard supports 400 Mb/s). Alternatively, a
in case it is performed at the IF stage. However, some of the
very powerful digital signal processing (DSP) core can be used
aforementioned advantages, including a lower dynamic-range
to process this large influx of data, but it is going to be bulky,
requirement for the RF mixer, become less effective. Moreover,
power-hungry, and expensive in today’s technology.
the value of passive components (e.g., inductors and capacitors)
In short, until faster and more power-efficient digital data
needed to provide a certain phase shift is inversely proportional
processing becomes available at a lower price, digital imple-
to the carrier frequency. Since the values of integrated passive
mentations still seems to be a more expensive solution for
components are directly related to their physical size (i.e., area),
multiple-antenna systems.
passive phase shifters at IF consume a larger area compared to
the ones at RF.
C. LO Path Phase Shifting
As an alternative approach, one can indirectly vary the phase
B. Digital Arrays of the received signal by adjusting the phase of the LO signal
used to down-convert the signal to a lower frequency. This is
The delay and amplitude of the received signal can be ad- due to the fact that the output phase of a multiplier (or mixer) is
justed at the baseband using a digital processor (Fig. 4). Dig- a linear combination of its input phases, i.e.,
ital-array architecture is very flexible and can be adapted for
other multiple antenna systems used for spatial diversity such as
multiple-input multiple-output (MIMO) schemes [13], [14]. De-
spite its potential versatility, baseband phased-array architecture (2)
uses a larger number of components compared to the previous
two approaches, resulting in a larger area and more power con- Fig. 5 shows a simplified phase-array receiver that uses LO
sumption. At the same time, since the interference signals are phase shifting. Phase shifting at the LO port is advantageous
not cancelled before baseband processing, all the circuit blocks, in that the phase-shifter loss does not directly deteriorate the
including the power-hungry analog-to-digital converters, need receiver sensitivity. Additionally, the nonlinearity and loss of
to have a large dynamic range to accommodate all the incoming active phase shifters such as phase-interpolating implementa-
signals without distortion. Above all, handling and processing a tions (e.g., [12]) can be more easily tolerated in the LO path
large amount of data through multiple parallel receivers can be compared to the signal path. However, since the undesired
challenging even for today’s advanced digital technology. interferences are only rejected after the combining step at the
For instance, imagine a digital array of eight receivers where IF, the RF amplifiers and mixers need to have a higher dy-
each has a 6-bit analog-to-digital converter that samples the namic range than the ones in the signal-path phase-shifting
signal with a 10-MHz channel bandwidth at twice the Nyquist scheme. The signal amplitude can be controlled using RF or
rate. These numbers are on the low end of the acceptable range IF variable-gain amplifiers (VGAs).
for a typical wireless system. Nevertheless, the baseband data This architecture is particularly attractive for silicon-based in-
rate of the whole system can be calculated to be 1.92 GB/s. As tegrated systems due to the large number of transistors available
HASHEMI et al.: 24-GHz SiGe PHASED-ARRAY RECEIVER 617

Fig. 6. Block diagram of the fully integrated 24-GHz phased-array receiver.

and the possibility of accurate multiple phase generation and The aforementioned considerations led to the design of a
distribution, which will be discussed in great details below. phased-array receiver that uses different phases at the LO path.
The block-diagram schematics of the 24-GHz phased-array
receiver consisting of eight paths is shown in Fig. 6. The
IV. 24-GHz PHASED-ARRAY RECEIVER ARCHITECTURE
receiver uses a two-step down-conversion architecture with
The implemented phased-array receiver employs an LO an IF of 4.8 GHz for two main reasons. Firstly, compared to
phase-shifting architecture for several reasons. Phase single down-conversion schemes such as homodyne, a hetero-
shifting and signal processing at baseband (i.e., digital arrays) dyne-type receiver achieves more selectivity and gain control at
was eliminated due to the larger chip area, power consumption, multiple stages. Secondly, with the mentioned frequency plan-
and the high demand on the baseband digital interface, particu- ning, both LO frequencies can be generated in one synthesizer
larly for the high data rates of interest. loop with the use of a divide-by-four block, as shown in the
Passive variable phase shifters at 24-GHz RF will have a rela- upper right part of Fig. 6.
tively higher loss due to ohmic and silicon substrate loss in inte- A single oscillator core generates 16 discrete phases (i.e.,
grated passive components (especially inductors and varactors). 4-bit resolution) that are used to control the phase of each path.
This loss in the signal path deteriorates the receiver’s overall The effect of using discrete phase compensation is discussed
sensitivity and can be minimized by providing more gain at the in Section V. A set of eight phase selectors (i.e., analog phase
LNA preceding them. More importantly, the phase-shifter’s loss multiplexer) provides the appropriate phase of the LO to the
usually changes significantly with its phase shift that necessi- corresponding RF mixer for each path independently. In other
tates the use of RF VGAs with fine resolution to compensate words, the LO phase for each path can be chosen irrespective of
these variations. Additionally, phase-shifter nonlinearity will be the phase of the other paths. The phase-selection data is serially
directly in the signal path, making the receiver more sensitive to loaded to an on-chip shift register using a computer interface.
a strong blocker. The image frequency of the first down-conversion at
In contrast, the signal loss in the LO phase-shifting networks 14.4 GHz is attenuated by the narrow-band transfer function of
can be easily compensated by high-gain amplifiers (e.g., lim- the front-end (i.e., antenna and LNA). Since communication
iters) without the need for any amplitude tuning. The reason for schemes around the image-frequency band are mainly low
this is that many RF mixer implementations (e.g., Gilbert type) power, and due to the directionality of the phased-array re-
perform better when driven to switch with a large amplitude at ceiver, no additional image-rejection provisions are introduced.
the LO port making their conversion gain less sensitive to the The final down-conversion to baseband or very low-IF is done
LO amplitude. This approach also makes it possible to generate by a pair of quadrature mixers. The divide-by-four block that
multiple phases of an LO signal by efficient methods other than is used to generate the second LO will naturally produce I and
using phase shifters. Q signals to drive these mixers.
618 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Each RF path consists of two stages of low-noise amplifica-

tion and a down-conversion mixer. The design of the 24-GHz
front-end and receiver signal path is discussed in [9]. In Sec-
tion V, multiple phase generation and distribution of the 19-GHz
LO are described in detail.

V. MULTIPLE PHASE GENERATION AND DISTRIBUTION

A. Quantized Phase Effects

An on-chip LO generates 16 discrete phases of the LO that
can either be directly applied to the RF mixers or interpolated
between to generate additional intermediate phases in order to
compensate the narrow-band phase shift of the carrier frequency Fig. 7. EVM for continuous-phase 5-bit (one-step interpolation), 4-bit (raw
at each path. This discrete method can only compensate the resolution), and 3-bit (hypothetical) phase-shifting resolutions.
carrier phase shift at a few incidence angles precisely. For all
other angles, the signal constellation at each received path is
rotated with an amount equal to the value of phase quantiza-
tion error. Clearly, the phase quantization error depends on the
desired phase shift for each path, itself a function of the angle
of incidence. Since the constellation at each received path is ro-
tated differently, the combined signals are not added coherently,
causing interference between the I and Q channels.
Fig. 7 plots the EVM as a function of the angle of incidence
when discrete phase shifts are used at the receiver for 8 (3 bit),
16 (4 bit), and 32 (5 bit) equally spaced phases. The signal has
a bandwidth of 7.5 GHz and all the other simulation parameters
are identical to the ones described in Section II. Using a 4-bit
phase-shifting scheme with phase steps of 22.5 creates a peak
EVM at an incidence angle of 70 , which is 1.5 times larger
than the peak EVM generated if an LO with a continuous phase
shift was available. For continuously adjustable phase shift, the
peak naturally happens at an incidence angle of 90 , which cor- Fig. 8. Array pattern with 4-bit phase-shifting resolution.
responds to largest time delay between antennas. As a compar-
ison, if a 3-bit phase shifting scheme with 45 phase steps was In our design, a ring connection of eight fully differential
used, this peak occurs at incidence angle of 60 with a peak CMOS amplifiers forms the 19.2-GHz voltage-controlled oscil-
EVM value, which is 1.8 times the peak EVM value for a 4-bit lator (VCO) capable of generating 16 phases (Fig. 9) [16]. By
scheme. The ratio of these peaks depends on the bandwidth of flipping one of the connections, the number of amplifying stages
signal, and tends to increase for lower signal bandwidths. is cut into half in a fully differential structure (top left connec-
In Fig. 8, we show that using discrete LO phases does not tion of Fig. 9). These phases are then applied to phase selectors
sacrifice the beam-forming accuracy significantly. In fact, in the that can also function as interpolators generating a finer phase
worst case, the signal loss is less than 1 dB in this 4-bit phase- resolution.
shifting scheme for a full spatial coverage. If no inductors at the amplifier outputs were used (e.g., differ-
ential pair with resistive load or CMOS inverters), each ampli-
B. Multiple Phase Generation fier should have operated at a speed very close to the maximum
operating frequency of transistors in the process causing chal-
At least two distinct methods to create various phases of an lenges for a reliable startup. To better observe this, imagine that
LO signal can be envisioned. In the first approach, only one each amplifier could be modeled as a single-pole system
phase is generated in the oscillator core (two phases considering
differential signals). Phase shifters, phase interpolators, or sim- (3)
ilar blocks follow the oscillator in order to generate multiple
phases of its output signal in a continuous or discrete fashion
[12], [15]. These blocks can be narrow-band around the LO fre- Each amplifier could produce a phase shift equal to
quency and their loss is usually not a major concern in the LO . In the case of a 22.5 phase shift for each
path. In the second scheme, multiple phases are generated in- amplifier at 19 GHz, the pole frequency should be at least at
side the oscillator core. Usually, this method results in discrete 46 GHz. Since the gain of each stage should be more than
phases with a minimum resolution of , where is an in- one to guarantee oscillation startup, the unity-gain frequency
teger number. of each amplifier approaches the device cutoff
HASHEMI et al.: 24-GHz SiGe PHASED-ARRAY RECEIVER 619

Fig. 9. Schematic of the 16-phase 19.2-GHz CMOS ring VCO.

Fig. 11. Schematic of the third-order PLL.

An on-chip third-order phased-locked loop (PLL) with a

loop bandwidth of 7 MHz is designed to lock the 19.2-GHz LO
signal to a 75-MHz external reference signal source (Fig. 11).
The integrated synthesizer uses a standard tri-state frequency
phase detector [22] and a multiswitch charge pump [17] to
Fig. 10. Schematic of the VCO buffer.
minimize the reference feed-through. All divide-by-two blocks
use a master–slave architecture and an emitter coupled logic
frequency. Unfortunately, this imposes unnecessary restrictions for high-speed operation (Fig. 12).
on the individual transistor’s speed and current consumption. In order not to disturb the symmetry of VCO output phases,
However, inductors can generate the necessary phase shift none of them are connected to any external pads for measure-
for each amplifier in the following fashion. At the oscillation ments. Nevertheless, we can verify the standalone VCO per-
frequency , the equivalent parallel load causes a phase formance by picking up the high-frequency signal via a loop
shift of antenna placed on top of the chip.
The frequency of the VCO can be continuously varied from
(4) 18.8 GHz to 21 GHz (Fig. 13). The slope of this transfer char-
acteristic is 2.1 GHz/V at 19.2 GHz and reaches a maximum of
In the case of a 22.5 phase shift for each stage, we should have 2.67 GHz/V close to 19.6 GHz.
The output spectrum and phase noise of the VCO at
(5) 18.70 GHz is shown in Fig. 14. The VCO achieves a phase
noise of 103 dBc/Hz at 1-MHz offset from the carrier. The
where is the load quality factor and is equal to . For measurement at higher offset frequencies is limited by the
at 19 GHz in this process, or thermal noise floor of the spectrum analyzer used to measure
. In other words, each amplifier is almost tuned at the phase noise.
the oscillation frequency. Each of the designed amplifier stages The output spectrum and phase noise of the locked VCO
draws less than 3.2 mA from a 2.5-V supply resulting in a total are shown in Fig. 15. As can be seen, the phase noise stays
power consumption of 63 mW for the oscillator. constant within the loop bandwidth as the frequency changes.
The center frequency can be tuned by changing the control Our synthesizer phase-noise measurements have been limited
voltage of differential MOS varactors. In order to make the by the phase noise of a synthesized sweeper that was used as the
high-frequency oscillator insensitive to loading, all the eight 75-MHz input reference signal. Better phase noise is expected
differential outputs are buffered prior to connection to other if a crystal type reference is used.
circuit blocks (Fig. 10). Emitter followers and differential
pairs draw approximately 1 and 1.9 mA from a 2.5-V supply, C. Systematic Phase Distribution
respectively. This results in approximately 9.8 mW of power It is essential that the 16 generated phases of the VCO are
consumption for each buffer. fed to each of the eight phase selectors in Fig. 6 with equal
620 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Fig. 12. Schematic of the high-speed divide-by-two blocks.

where is the per-unit-length coupling capacitance to the ad-

jacent line. In general, the traveling wave can be considered as
a linear combination of even- and odd-mode transmissions. Let
and denote the characteristic impedances of and ,
respectively. The magnitude and phase of and are re-
lated to phase difference by

(8)

(9)
Fig. 13. VCO frequency versus control voltage.

It can be seen that and form a complex conjugate pair,

amplitudes and delays. A symmetric binary tree structure, as
which are equal only for or 180 .
shown in Fig. 16(a), is used to distribute LO phases. Each
EM crosstalk between nonadjacent lines can also cause
path consists of 16 metal lines running in parallel, similar to
phase and amplitude errors [19]. EM simulations are performed
Fig. 16(b).
on an array of 16 on-chip transmission lines, as shown in
Due to the strong EM coupling between the closely spaced
Fig. 16(b). In our design, each line is 4- m thick, 5- m wide, and
metal lines, the symmetry not only depends on the path length,
200- m long with a 5- m edge-to-edge spacing. These lines are
but also on the phase arrangement within the bus due to EM
12 m above the silicon substrate. Fig. 17 shows the extracted
coupling between the lines. Several mechanisms, such as
mutual inductance and coupling capacitance normalized to
multimode excitation, coupling between nonadjacent lines, and
the inductance and capacitance , respectively. It illustrates
boundary discontinuity of a finite array can cause phase and
that although the capacitive coupling is negligible between
amplitude mismatches in the tree structures of Fig. 16(a) and
nonadjacent lines, the magnetic coupling is significant and the
(b). To understand the multimode excitation, consider two iden-
mutual inductance decreases very slowly with the distance.
tical lossless transmission lines and running in parallel
Fig. 16(b) shows three different phase arrangements in a
and driven by two signal sources and , respectively.
transmission-line bus carrying multiple phases. If the array has
If (even-mode excitation), the characteristic impedance
an infinite number of lines, arrangement 1 provides the best
of each line is given by
symmetry, and the characteristic impedance can be calculated
to be
(6)

where , , and are per-unit-length capacitance to ground,

inductance, and mutual inductance, respectively. On the other (10)
hand, for a (odd-mode excitation), the characteristic
impedance of each line is given by
where and are the mutual inductance and coupling
(7) capacitance between two lines with phase difference of .
HASHEMI et al.: 24-GHz SiGe PHASED-ARRAY RECEIVER 621

Fig. 14. VCO output spectrum and phase noise at 18.7 GHz.

Fig. 15. Output spectrum and phase noise of the locked VCO.

Fig. 17. Simulated coupling capacitor and inductor of the phase distribution
line array of Fig. 16.

Fig. 16. (a) LO phase distribution tree structure. (b) Phased transmission-line
array.

However, in a finite array, the discontinuity at the edge and the

inductive crosstalk between nonadjacent lines can produce sig-
nificant mismatch at the outputs of arrangement 1.
According to Ampere’s law, placing differential phase pairs Fig. 18. Output voltage of the phase distribution line versus the source
as shown in arrangements 2 and 3 can minimize magnetic cou- impedance value.
pling. If is small (in this study, ), arrangement 3 has
better phase- and amplitude-matching characteristics than the coupling between them is minimized. For a small , the char-
other two. This is because, in arrangement 3, the adjacent lines acteristic impedance of the transmission lines in arrangement 3
of two different pairs are closer in phase so that the capacitive can be approximated by the odd-mode impedance given by (7).
622 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Fig. 19. Comparison of different phase distribution configurations of Fig. 16(b). (a) Amplitude matching. (b) Phase matching.

Fig. 20. Phase-selection circuitry.

To compare these three proposed phase arrangements,

EM simulations were performed. Each of the three arrays is
driven by 16 evenly spaced phases of a 19.2-GHz sinusoid.
The transmission lines see a resistance at both input and
output ports. Fig. 18 illustrates the voltage at the output
port of the central wire as a function of . It verifies that
using resistance values estimated by (10) and (7) results
in maximum for arrangements 1 and 3, respectively.
Fig. 19(a) and (b) shows the magnitudes and phases of the
voltages at the 16 output ports for three arrangements. It
can be seen that arrangement 3 exhibits less mismatch and,
hence, is adopted in our 24-GHz phased-array receiver.
The LO phase distribution lines transform the input
impedance of the phase-selection circuitry to a new impedance
at the LO buffer output node of Fig. 9. This transformed
impedance should be made equal to the complex conjugate of
the output impedance of the LO buffer to achieve the maximum Fig. 21. Die microphotograph.
power transfer and, hence, the largest LO amplitude at the input
of phase-selection circuitry. Under a conjugate matched condi- where and are the tail current and output resistance
tion and neglecting the loss in distribution lines, the theoretical of the differential-pair buffer in Fig. 9, respectively; is the
maximum achievable differential signal swing at the input of input resistance of each phase selector and is the number
each phase-selection circuitry is of phase selectors that are connected to a single LO buffer. In
our implementation, the maximum swing based on (11) is ap-
(11)
proximately 140 mV. Due to the inaccuracies in prediction and
HASHEMI et al.: 24-GHz SiGe PHASED-ARRAY RECEIVER 623

Fig. 22. High-frequency measurement setup.

Fig. 23. Array measurement setup.

modeling of LO distribution lines in addition to their loss at pairs at the output of each stage partially cancel the loss asso-
19 GHz, we expect the amplitude to be smaller in practice. How- ciated with the inductors and transistors’ outputs and, hence,
ever, the phase-selection circuitry discussed below is designed increase the LO amplitude driving RF mixers.
to maintain the required LO amplitude across RF mixers. Phase interpolation can be achieved by turning on more than
one tail transistor at any given time, forcing the output to be the
D. Phase Selector/Interpolator vector sum of all the turned-on phases. A first-order interpola-
As previously mentioned, each receiver path has independent tion can be achieved by turning two adjacent paths on simulta-
access to all 16 phases of the LO. In order to minimize the com- neously, doubling the phase resolution.
plexity of the phase-selection circuitry, the appropriate phase of
the LO for each path is selected in two steps. Initially, an array VI. RECEIVER MEASUREMENT RESULTS
of eight differential pairs with switchable current sources and The phased-array receiver is implemented in an IBM
a shared tuned load are used to select one of the eight output 7HP SiGe BICMOS process with an HBT of 120 GHz
pairs of oscillator (Fig. 20). A dummy array with complemen- and 0.18- m CMOS transistor [20]. The die micrograph of
tary switching signals is used to maintain a constant load and the chip is shown in Fig. 21. The chip occupies an area of
prevent relative changes in phases while switching. In the basic 3.3 mm 3.5 mm.
mode of operation, at any given time, one of the LO phases is For all measurements, the silicon chip has been mounted on
fed to the output of the main analog multiplexer, while other a gold-plated brass substrate to provide a good grounding. A
phases are fed to the output of the unused multiplexer. In the next high-frequency Duroid board surrounds the chip and is used to
step, another pair of cross-coupled differential pairs selects the connect the input, bias, and control signal lines using wire bonds
sign bit, resulting in complete access to all LO 16 phases. The (Fig. 22). Special attention has been paid to minimize the length
above-mentioned cascaded configuration reduces the necessary of wire bonds at RF input and ground lines. All signal and bias
number of phase selectors (i.e., differential pairs in our case) lines are fed with standard subminiature A (SMA) connectors
from 2 to 2 2 for each path. The cross-coupled differential attached to the brass membrane.
624 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Fig. 24. Measured array patterns with two operating paths.

TABLE I
SUMMARY OF THE MEASURED PERFORMANCE

Fig. 25. Measured array pattern with four operating paths.

Ideally, all the input paths have to be connected to on-board

antennas [4] and the reception pattern of the array has to be mea-
sured. However, in order to separate the effect of the antenna
eight paths is expected to significantly improve this number, as
array from the receiver, phase shifters in the input path are used
well as make the beamwidth narrower. Theoretical receiver pat-
to emulate the phase difference of signals at each path. Array
terns and the measurements at three different angles are shown
measurements have been performed with a signal being fed to
in Fig. 25 for a four-channel setup.
only four of the receiver paths. The setup used for array mea-
Table I summarizes the measurement results.
surements is shown in Fig. 23.
Receiver pattern measurements at eight different angles with
only two operating paths are shown in Fig. 24. The difference VII. CONCLUSION
between the peak and the null is 10–20 dB in all cases. This Moore’s 1965 seminal paper [21] ends with the following
value is mostly limited by the mismatch in different paths and prediction: “It is difficult to predict at the present time just how
can be significantly improved with a gain control block in each extensive the invasion of the microwave area by integrated elec-
receiver path for future implementations. In any event, using all tronics will be . The successful realization of such items such
HASHEMI et al.: 24-GHz SiGe PHASED-ARRAY RECEIVER 625

as phased-array antennas, for example, using a multiplicity [16] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data recovery cir-
of integrated microwave power sources, could completely cuit with a half-rate binary phase-frequency detector,” IEEE J. Solid-
State Circuits, vol. 38, no. 1, pp. 13–21, Jan. 2003.
revolutionize radar.” In this paper, almost 40 years later, we [17] J. Cranincks and M. Steyaert, Wireless CMOS Frequency Synthesizer
have demonstrated the first silicon-based fully integrated Design. Norwell, MA: Kluwer, 1998.
phased-array receiver at microwave frequencies for use in ul- [18] D. Ham, “Statistical electronics—Noise processes in integrated commu-
nication systems,” Ph.D. dissertation, Dept. Elect. Eng., California Inst.
trahigh-speed wireless communication and radar applications. Technol., Pasadena, CA, 2002.
[19] C.-K. Cheng et al., Interconnect Analysis and Synthesis. New York:
Wiley, 2000.
[20] A. Joseph et al., “A 0.18 m BiCMOS technology featuring 120/100
ACKNOWLEDGMENT GHz (ft=f ) HBT and ASIC-compatible CMOS using copper inter-
connect,” in Proc. IEEE Bipolar/BiCMOS Circuits Technology Meeting,
2001, pp. 143–146.
The authors would like to thank A. Natarajan, R. Aparicio, [21] G. E. Moore, “Cramming more components onto integrated circuits,”
D. Lu, M. Morgan, and Prof. D. Rutledge, all of the California Electronics, vol. 38, no. 8, pp. 114–117, Apr. 1965.
Institute of Technology, Pasadena, for valuable technical dis- [22] B. Razavi, RF Microelectronics. Upper Saddle River, NJ: Prentice-
Hall, 1998.
cussions. The authors acknowledge N. Wadefalk, and A. Shen,
both of the California Institute of Technology, both of whom
assisted in printed circuit board and microwave package prepa-
ration. The original version of the software for programming the
phased-array receiver was provided by R. Chunara, California Hossein Hashemi (M’99) received the B.S. and
Institute of Technology. M.S. degrees in electronics engineering from the
Sharif University of Technology, Tehran, Iran, in
1997 and 1999, respectively, and the M.S. and Ph.D.
degrees in electrical engineering from the California
Institute of Technology, Pasadena, in 2001 and 2003,
REFERENCES respectively.
In 2003, he joined the Department of Elec-
trical Engineering—Electrophysics, University of
[1] “Code of federal regulations, title 47–telecommunication, chapter I,”
Southern California, as an Assistant Professor,
Federal Commun. Commission, pt. 15—Radio Frequency Devices, secs.
where the core of his research constitutes the study
15.245 and 15.249, 2004.
of integrated communication circuits and systems.
[2] “Code of federal regulations, title 47–telecommunication, chapter I,”
Dr. Hashemi is an associate editor for the IEEE TRANSACTIONS ON CIRCUITS
Federal Commun. Commission, pt. 15—Radio Frequency Devices, secs.
AND SYSTEMS—PART II: ANALOG AND DIGITAL SIGNAL PROCESSING. He was
15.515 and 15.521, 2004. the recipient of the 2000 Outstanding Accomplishment Award presented by the
[3] H. Hashemi, X. Guan, and A. Hajimiri, “A fully integrated 24 GHz von Brimer Foundation, the 2001 Outstanding Student Designer Award pre-
8-path phased-array receiver in silicon,” in IEEE Int. Solid-State Cir- sented by Analog Devices, and a 2002 Intel Fellowship.
cuits Conf. Tech. Dig., Feb. 2004, pp. 390–391.
[4] D. Lu, D. Rutledge, M. Kovacevic, and J. Hacker, “A 24 GHz patch
array with a power amplifier/low-noise amplifier MMIC,” Int. J. Infrared
Millim. Waves, vol. 23, pp. 693–704, May 2002.
[5] X. Guan and A. Hajimiri, “A 24 GHz CMOS front-end,” in Eur. Solid-
State Circuits Conf. Tech. Dig., Sept. 2002, pp. 155–158. Xiang Guan (S’98) received the B.S. degree in elec-
[6] E. Sonmez, A. Trasser, K. Schad, R. Abele, and H. Schumacher, “A trical engineering from Tsinghua University, Beijing,
single chip 24 GHz receiver front-end using a commercially available China, in 1996, the M.Eng. degree in electrical engi-
SiGe HBT foundry process,” in IEEE Radio Frequency Integrated Cir- neering from the National University of Singapore,
cuits Symp. Dig., Jun. 2002, pp. 159–162. Singapore, in 2000, and is currently working toward
[7] I. Gresham, A. Jenkins, R. Egri, C. Eswarappa, F. Kolak, R. Wohlert, the Ph.D. degree at the California Institute of Tech-
J. Bennett, and J. Lanteri, “Ultra wide band 24 GHz automotive radar nology, Pasadena.
front-end,” in IEEE MTT-S Int. Microwave Symp. Dig., Jun. 2003, pp. From 1996 to 1997, he was a Research Assistant
369–372. with the Integrated Circuits Group, Instituto Superior
[8] D. Lu and D. Rutledge, “Investigation of indoor radio channel from 2.4 Tecnico, Lisbon, Portugal, where he was involved in
GHz to 24 GHz,” in IEEE AP-S Int. Symp. Dig., Jun. 2003, pp. 134–137. the development of a data acquisition chip for elec-
[9] X. Guan, H. Hashemi, and A. Hajimiri, “A fully integrated 24-GHz trocardiogram remote monitoring devices. During the summer of 2003, he was
8-path phased-array receiver in silicon,” IEEE J. Solid-State Circuits, a Co-Op Researcher with the IBM T. J. Watson Research Center, Yorktown
vol. 39, no. 12, pp. 2311–2320, Dec. 2004. Heights, NY.
[10] D. Parker and D. Zimmermann, “Phased-arrays—Part II: Implemen- Mr. Guan was the recipient of the 2002 Analog Devices Outstanding Student
tations, applications, and future trends,” IEEE Trans. Microw. Theory Designer Award.
Tech., vol. 50, no. 3, pp. 688–698, Mar. 2002.
[11] H. Zarei and D. Allstot, “A low-loss phase shifter in 180 nm CMOS
for multiple-antenna receivers,” in IEEE Int. Solid-State Circuits Conf.
Tech. Dig., Feb. 2004, pp. 392–393.
[12] M. Chua and K. Martin, “1 GHz programmable analog phase shifter
for adaptive antennas,” in Proc. IEEE Custom Integrated Circuits Conf., Abbas Komijani (S’98) received the B.S. and M.S.
May 1998, pp. 11–14. degrees in electronics engineering from the Sharif
[13] T. Rappaport, Wireless Communications: Principles and Prac- University of Technology, Tehran, Iran, in 1995
tice. Upper Saddle River, NJ: Prentice-Hall, 1996. and 1997, respectively, and is currently working
[14] T. Alamouti, “A simple transmit diversity technique for wireless com- toward the Ph.D. degree at the California Institute of
munications,” IEEE J. Sel. Area Commun., vol. 16, no. 8, pp. 1451–1458, Technology, Pasadena.
Oct. 1998. His research interests include high-frequency
[15] T. Yamaji, D. Kurose, O. Watanabe, S. Obayashi, and T. Itakura, “A power amplifiers, wireless transceivers, and phased-
four-input beam-forming downconverter for adaptive antennas,” IEEE array architectures.
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626 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 53, NO. 2, FEBRUARY 2005

Ali Hajimiri (S’95–M’99) received the B.S. degree

in electronics engineering from the Sharif University
of Technology, Tehran, Iran, in 1994, and the M.S.
and Ph.D. degrees in electrical engineering from
Stanford University, Stanford, CA, in 1996 and
1998, respectively.
From 1993 to 1994, he was a Design Engineer
with Philips Semiconductors, where he was involved
with a BiCMOS chipset for global system for
mobile communications (GSM) and cellular units.
In 1995, he was with Sun Microsystems, where
he was involved with the UltraSPARC microprocessor’s cache RAM design
methodology. During the summer of 1997, he was with Lucent Technologies
(Bell Laboratories), Murray Hill, NJ, where he investigated low phase-noise
integrated oscillators. In 1998, he joined the Faculty of the California Institute
of Technology, Pasadena, where he is currently an Associate Professor of elec-
trical engineering and the Director of Microelectronics and Noise Laboratories.
He is a cofounder of Axiom Microdevices Inc. He coauthored The Design of
Low Noise Oscillators (Boston, MA: Kluwer, 1999). He holds several U.S.
and European patents. His research interests are high-speed and RF integrated
circuits. He was a Guest Editorial Board member of Transactions of the Institute
of Electronics, Information and Communication Engineers of Japan (IEICE).
Dr. Hajimiri is an associate editor for the IEEE JOURNAL OF SOLID-STATE
CIRCUITS. He is a member of the Technical Program Committee of the Inter-
national Solid-State Circuits Conference (ISSCC). He has also served as an
associate editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—Part II:
ANALOG AND DIGITAL SIGNAL PROCESSING. He is a member of the Technical
Program Committees of the International Conference on Computer-Aided
Design (ICCAD). He was a guest editor for the IEEE TRANSACTIONS ON
MICROWAVE THEORY AND TECHNIQUES. He is listed on the Top 100 Innovators
(TR100) List. He was the recipient of the Gold Medal of the National Physics
Competition and of the Bronze Medal of the 21st International Physics
Olympiad, Groningen, The Netherlands. He was a corecipient of the ISSCC
1998 Jack Kilby Outstanding Paper Award and a three-time recipient of the
IBM Faculty Partnership Award, as well as the National Science Foundation
(NSF) CAREER Award.