Baud Rate (Bits Per Second) Factor To Nominal (Baud Rate / 9600) Remarks

REPORT
Project specifications:
This project aims at building a simple hardware description of a sequential circuit in Verilog
HDL which goal is to produce clock signals for serial communication baud rate generators.
Asynchronous serial communication requires clocks to be generated for being able to recover
the information from the received bits. The requirements are:
 Support multiple baud rates (symbols or bits per second)
 A clock signal of frequency 16 times the baud rate frequency should be generated
for every supported baud rate value.
The supported bit rates are given in the table below. They are all based on the nominal baud
rate of 9600 bits per second
Baud Rate (bits Factor to Nominal Remarks
per second) (Baud Rate / 9600)
9600 1 Nominal
19200 2 2x times
38400 4 4x times
115200 12 12x times
The circuit will have the following interface:

 A system clock input called clk
 A synchronous reset called reset
 A set of outputs called
o clk96: is the 9600 bps clock signal
Our circuit is used to generate different clock of different clock frequencies as mentioned
above. We have chosen the system clock frequency as 125 MHz. The design style should be
based on the use of synchronous frequency division counters along with simple change
detection circuits.
We have made four blocks for the four different clock generation namely clk1152, clk384,
clk192 and clk96. These signals are used to produce clocks of different frequency according to
the specifications mentioned above. So we have used 4 different counters to produce the
respective clocks. Their division factors using system clock as 125 MHz are shown below:
Division factor for 115200 baud rate:

The following is an example of one step of the circuit that uses a system clock of 125 MHz
frequency.
The first clock output circuit will generate clk1152. Its frequency is
f 1152=115200 ×16=1,843,200=1.8432 MHz
To generate this clock signal output, a counter is used to divides the system clock by the
following factor:
f system
N= =33.9≈ 34
f 1152 × 2
The factor 2 in the denominator is used to guarantee a 50% duty cycle. Similarly,

f 384 =38400 ×16=614,400=0.6144 MHz
following factor:
f system
N= =101.7 ≈ 102
f 384 × 2

f 192=19200 ×16=307,200=0.3072 MHz
following factor:
f system
N= =203.45 ≈ 203
f 192 ×2
f 96=9600 ×16=153,600=0.1536 MHz
following factor:
f system
N= =406.9 ≈ 407
f 96 × 2
Design HDL code:
So there are different parts of the HDL code , below is the brief description of each part :
So first is the module ports declaration:

module bdgen( clk,reset,clk1152,clk384,clk192,clk96
);
input clk,reset;
output reg clk1152,clk384,clk192,clk96;
Here we have declared different input and output ports. Inputs ports are clk, reset and output
ports are clk1152,clk384,clk192 and clk96.
Then there is parameter declaration and different counter variables which is being declared as
register.
parameter DIV1=34;
reg[5:0] cnt1;
reg[1:0] cnt2;
reg[2:0] cnt3;
reg[3:0] cnt4;
Here we have decided the DIV1 parameter should be 34 according to 115200 baud rate as
calculated above.
Then there comes the main four always block which is the main building of the code. In each
blocks we have generated clock of different frequencies with the help of counter as mentioned
above. Each always block is running on positive edge of the 125 MHz Clk which is being
produced in the testbench.
Test bench and its features:
In order to simulate and test the circuit, a testbench should be developed. The testbench needs
to:
 instantiate the design and connect its inputs and outputs
 create the input clock with the appropriate frequency
Following is the test bench code:
`timescale 100ps / 100ps

module bdgentb;
// Inputs
reg clk;
reg reset;
// Outputs
wire clk1152;
wire clk384;
wire clk192;
wire clk96;
// Instantiate the Unit Under Test (UUT)

bdgen uut (
.clk(clk),
.reset(reset),
.clk1152(clk1152),
.clk384(clk384),
.clk192(clk192),
.clk96(clk96)
);
initial begin
clk=0;
reset=0;
#15 reset=1;
#80 reset = 0;
end
always
#40 clk=~clk;
initial
#200000 $finish;
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1, bdgentb);
end
endmodule
First we have declared inputs of design module as reg and outputs as wire, then we have
instantiated the design module with correct port association. Our timescale directive is
100ps/100ps which means #1 delay is equal to 100ps delay and precision is of 100ps.
So then the initial block where we initialise the system clock as 0 and made reset =0. Then we
made reset high at 1500ps and low at 8000ps. Then comes the always block which is used to
produce clock of 125 MHz frequency. After that there are two initial blocks first one is used to
finish the simulation at 20000000ps and second one is used to save all the signal transition into
wave files.
SIMULATION WAVEFORM:
So we run simulation up to 19,996,000ps which made it possible to view all the clocks of
different frequencies in one window. First row gives Clk of 125 MHz frequency.
Based on which different rows show different clocks of given frequencies. Simulation shows
the output as expected as clk1152 should be of highest frequency and subsequent clocks will be
of lower frequencies.
Discussion and issues faced:
There were many issues faced during the making of the project:
 First we have to find division factor for given clock frequency which is the little
difficult task to perform.
 Then we faced problem in deciding length of the counter variables as one time during
the simulation it was not showing the correct output because the length of the one of
counter variables was less.
 We have an issue during port association in the test bench as we have not declared the
one of the inputs.
Rest all the things went good , project is completed successfully with correct output waveform.
APPENDIX:
EDA playground link:
https://www.edaplayground.com/x/7KgU
Design HDL code listing:
// Code your design here

module bdgen( clk,reset,clk1152,clk384,clk192,clk96

);
input clk,reset;
output reg clk1152,clk384,clk192,clk96;
parameter DIV1=34;//fsystem/f1152*2,fsystem=125Mhz
reg[5:0] cnt1;
reg[1:0] cnt2;
reg[2:0] cnt3;
reg[3:0] cnt4;
//clk for 115200bps

always@(posedge clk)
begin
if(reset)
begin
cnt1<=0;
clk1152<=0;
end
else
if(cnt1==(DIV1-1))
begin
cnt1 <= 0;
clk1152<=~clk1152;
end
else
cnt1<=cnt1+1;
end
//clk for 38400bps

always @(posedge clk)
begin
if(reset)
begin
cnt2<=0;
clk384<=0;
end
else
if(cnt1==(DIV1-1))
begin
if(cnt2==2)
begin
cnt2<=0;
clk384<=~clk384;
end
else
cnt2<=cnt2+1;
end
end
//clk for 19200bps

begin
if(reset)
begin
cnt3<=0;
clk192<=0;
end
else
if(cnt1==(DIV1-1))
begin
if(cnt3==5)
begin
cnt3<=0;
clk192<=~clk192;
end
else
cnt3<=cnt3+1;
end
end
//clk for 9600bps

begin
if(reset)
begin
cnt4<=0;
clk96<=0;
end
else
if(cnt1==(DIV1-1))
begin
if(cnt4==11)
begin
cnt4<=0;
clk96<=~clk96;
end
else
cnt4<=cnt4+1;
end
end
endmodule
Testbench HDL code listing:
module bdgentb;
// Inputs
reg clk;
reg reset;
// Outputs
wire clk1152;
wire clk384;
wire clk192;
wire clk96;
// Instantiate the Unit Under Test (UUT)

bdgen uut (
.clk(clk),
.reset(reset),
.clk1152(clk1152),
.clk384(clk384),
.clk192(clk192),
.clk96(clk96)
);
initial begin
clk=0;
reset=0;
#15 reset=1;
#80 reset = 0;
end
always
#40 clk=~clk;
initial
#200000 $finish;
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1, bdgentb);
end
endmodule
Waveform screen capture:

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REPORT

The circuit will have the following interface:

Division factor for 115200 baud rate:

Division factor for 38400 baud rate:

f 384 =38400 ×16=614,400=0.6144 MHz

Division factor for 19200 baud rate:

f 192=19200 ×16=307,200=0.3072 MHz

f 96=9600 ×16=153,600=0.1536 MHz

So first is the module ports declaration:

Following is the test bench code:

`timescale 100ps / 100ps

// Instantiate the Unit Under Test (UUT)

EDA playground link:

Design HDL code listing:

// Code your design here

module bdgen( clk,reset,clk1152,clk384,clk192,clk96

//clk for 115200bps

//clk for 38400bps

//clk for 19200bps

//clk for 9600bps

Testbench HDL code listing:

`timescale 100ps / 100ps

// Instantiate the Unit Under Test (UUT)

Waveform screen capture:

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