RTL8370 (M)

RTL8370-GR
LAYER 2 MANAGED 8-PORT 10/100/1000 SWITCH CONTROLLER
RTL8370M-GR
LAYER 2 MANAGED 8+2-PORT 10/100/1000 SWITCH CONTROLLER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.1
25 March 2011
Track ID: JATR-2265-11
Realtek Semiconductor Corp.

No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8370(M)
Datasheet
COPYRIGHT
©2011 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
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means without the written permission of Realtek Semiconductor Corp.
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Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT

This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8370(M) ICs.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary
1.0 2010/08/20 First release.
1.1 2011/03/25 Added section 13.5.3 MDIO Slave Mode Timing Characteristics, page 84.
Revised section 13.6 Power and Reset Characteristics, page 90.
Revised Table 2 Pin Assignment Table (RTL8370M: TQFP-176), page 12 (Pin 107 and
Pin 108).
Revised Table 15 Extension GMAC0 MII Pins (MII MAC Mode or MII PHY Mode) of
the RTL8370M (TQFP176), page 31.
Revised Table 20 Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and
EN_FLASH) (RTL8370M), page 39.
Revised Table 27 RTL8370M General Purpose Interfaces Pin Definitions, page 63.
Revised Table 32 Extension GMAC0 MII Pins, page 67.
Revised Table 60 EEPROM SMI Host Mode Timing Characteristics, page 83.
Revised Figure 25 EEPROM SMI Slave Mode Timing Characteristics, page 83.
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RTL8370(M)
Datasheet
Table of Contents
1. GENERAL DESCRIPTION ..............................................................................................................................................1
2. FEATURES .........................................................................................................................................................................3
3. SYSTEM APPLICATIONS...............................................................................................................................................5
4. APPLICATION EXAMPLES ...........................................................................................................................................5
4.1. 8-PORT 1000BASE-T SWITCH ......................................................................................................................................5
4.2. 8-PORT 1000BASE-T ROUTER WITH DUAL MII/RGMII/GMII (RTL8370M) ..............................................................6
5. BLOCK DIAGRAM ...........................................................................................................................................................7
6. PIN ASSIGNMENTS .........................................................................................................................................................8
6.1. RTL8370 PIN ASSIGNMENTS (LQFP-128)...................................................................................................................8
6.2. PACKAGE IDENTIFICATION ...........................................................................................................................................8
6.3. RTL8370M PIN ASSIGNMENTS (TQFP-176) ...............................................................................................................9
6.4. PACKAGE IDENTIFICATION ...........................................................................................................................................9
6.5. PIN ASSIGNMENT TABLE (RTL8370: LQFP-128) ......................................................................................................10
6.6. PIN ASSIGNMENT TABLE (RTL8370M: TQFP-176) ..................................................................................................12
7. PIN DESCRIPTIONS (RTL8370)...................................................................................................................................15
7.1. MEDIA DEPENDENT INTERFACE PINS (RTL8370)......................................................................................................15
7.2. PARALLEL LED PINS (RTL8370) ..............................................................................................................................16
7.3. SCAN MODE LED PINS (RTL8370) (LQFP128) ........................................................................................................18
7.4. CONFIGURATION STRAPPING PINS (RTL8370) ..........................................................................................................19
7.5. MISCELLANEOUS PINS (RTL8370) ............................................................................................................................21
7.6. TEST PINS (RTL8370)................................................................................................................................................22
7.7. POWER AND GND PINS (RTL8370) ...........................................................................................................................22
8. PIN DESCRIPTIONS (RTL8370M) ...............................................................................................................................23
8.1. MEDIA DEPENDENT INTERFACE PINS (RTL8370M) ..................................................................................................23
8.2. GENERAL PURPOSE INTERFACES (RTL8370M) .........................................................................................................24
8.2.1. GMII Interface Pins (RTL8370M) ........................................................................................................................24
8.2.2. RGMII Pins (RTL8370M).....................................................................................................................................28
8.2.3. MII Pins (RTL8370M) ..........................................................................................................................................31
8.2.4. LED Pins (RTL8370M).........................................................................................................................................35
8.3. CONFIGURATION STRAPPING PINS (RTL8370M) .......................................................................................................38
8.4. MISCELLANEOUS PINS (RTL8370M).........................................................................................................................40
8.5. TEST PINS (RTL8370M) ............................................................................................................................................41
8.6. POWER AND GND PINS (RTL8370M) .......................................................................................................................41
9. PHYSICAL LAYER FUNCTIONAL OVERVIEW......................................................................................................42
9.1. MDI INTERFACE ........................................................................................................................................................42
9.2. 1000BASE-T TRANSMIT FUNCTION ...........................................................................................................................42
9.3. 1000BASE-T RECEIVE FUNCTION ..............................................................................................................................42
9.4. 100BASE-TX TRANSMIT FUNCTION...........................................................................................................................42
9.5. 100BASE-TX RECEIVE FUNCTION .............................................................................................................................43
9.6. 10BASE-T TRANSMIT FUNCTION ...............................................................................................................................43
9.7. 10BASE-T RECEIVE FUNCTION ..................................................................................................................................43
9.8. AUTO-NEGOTIATION FOR UTP ..................................................................................................................................43
9.9. CROSSOVER DETECTION AND AUTO CORRECTION .....................................................................................................44
9.10. POLARITY CORRECTION .............................................................................................................................................44
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10. GENERAL FUNCTION DESCRIPTION .................................................................................................................45

10.1. RESET ........................................................................................................................................................................45
10.1.1. Hardware Reset ...............................................................................................................................................45
10.1.2. Software Reset .................................................................................................................................................45
10.2. IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................45
10.3. HALF DUPLEX FLOW CONTROL .................................................................................................................................46
10.3.1. Back-Pressure Mode........................................................................................................................................46
10.4. SEARCH AND LEARNING ............................................................................................................................................47
10.5. SVL AND IVL/SVL ...................................................................................................................................................47
10.6. ILLEGAL FRAME FILTERING .......................................................................................................................................47
10.7. IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL .............................................................................48
10.8. BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL .....................................................................................48
10.9. PORT SECURITY FUNCTION ........................................................................................................................................48
10.10. MIB COUNTERS ....................................................................................................................................................49
10.11. PORT MIRRORING..................................................................................................................................................49
10.12. VLAN FUNCTION..................................................................................................................................................49
10.12.1. Port-Based VLAN ............................................................................................................................................50
10.12.2. IEEE 802.1Q Tag-Based VLAN.......................................................................................................................50
10.12.3. Protocol-Based VLAN .....................................................................................................................................51
10.12.4. Port VID ..........................................................................................................................................................51
10.13. QOS FUNCTION .....................................................................................................................................................52
10.13.1. Input Bandwidth Control .................................................................................................................................52
10.13.2. Priority Assignment .........................................................................................................................................52
10.13.3. Priority Queue Scheduling...............................................................................................................................53
10.13.4. IEEE 802.1p/Q and DSCP Remarking ............................................................................................................53
10.13.5. ACL-Based Priority .........................................................................................................................................54
10.14. IGMP & MLD SNOOPING FUNCTION ....................................................................................................................54
10.15. IEEE 802.1X FUNCTION ........................................................................................................................................54
10.15.1. Port-Based Access Control..............................................................................................................................54
10.15.2. Authorized Port-Based Access Control ...........................................................................................................54
10.15.3. Port-Based Access Control Direction..............................................................................................................55
10.15.4. MAC-Based Access Control.............................................................................................................................55
10.15.5. MAC-Based Access Control Direction ............................................................................................................55
10.15.6. Optional Unauthorized Behavior.....................................................................................................................55
10.15.7. Guest VLAN .....................................................................................................................................................55
10.16. IEEE 802.1D FUNCTION .......................................................................................................................................56
10.17. EMBEDDED 8051 ...................................................................................................................................................56
10.18. REALTEK CABLE TEST (RTCT).............................................................................................................................56
10.19. LED INDICATOR....................................................................................................................................................57
10.19.1. Parallel LED Mode..........................................................................................................................................57
10.19.2. Scan LED Mode...............................................................................................................................................58
10.20. GREEN ETHERNET .................................................................................................................................................60
10.20.1. Link-On and Cable Length Power Saving .......................................................................................................60
10.20.2. Link-Down Power Saving ................................................................................................................................60
10.21. IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ..........................................................................60
10.22. INTERRUPT PIN FOR EXTERNAL CPU ....................................................................................................................60
11. INTERFACE DESCRIPTIONS .................................................................................................................................61
11.1. EEPROM SMI HOST TO EEPROM ...........................................................................................................................61
11.2. EEPROM SMI SLAVE FOR EXTERNAL CPU..............................................................................................................62
11.3. GENERAL PURPOSE INTERFACE (RTL8370M ONLY) .................................................................................................63
11.3.1. Extension Port 0 and Port 1 GMII Mode Interface (1Gbps) ...........................................................................64
11.3.2. Extension Port 0 and Port 1 RGMII Mode (1Gbps) ........................................................................................66
11.3.3. Extension Port 0 and Port 1 MII MAC/PHY Mode Interface (10/100Mbps)...................................................67
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12. REGISTER DESCRIPTIONS ....................................................................................................................................69

12.1. PAGE 0: PCS REGISTER (PHY 0~7) ...........................................................................................................................69
12.2. REGISTER 0: CONTROL ...............................................................................................................................................70
12.3. REGISTER 1: STATUS ..................................................................................................................................................71
12.4. REGISTER 2: PHY IDENTIFIER 1 .................................................................................................................................72
12.5. REGISTER 3: PHY IDENTIFIER 2 .................................................................................................................................72
12.6. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT .................................................................................................72
12.7. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY.......................................................................................73
12.8. REGISTER 6: AUTO-NEGOTIATION EXPANSION ..........................................................................................................74
12.9. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER ..................................................................................74
12.10. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ............................................................75
12.11. REGISTER 9: 1000BASE-T CONTROL REGISTER ....................................................................................................75
12.12. REGISTER 10: 1000BASE-T STATUS REGISTER .....................................................................................................76
12.13. REGISTER 15: EXTENDED STATUS .........................................................................................................................76
13. ELECTRICAL CHARACTERISTICS......................................................................................................................77
13.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................77
13.2. RECOMMENDED OPERATING RANGE..........................................................................................................................77
13.3. THERMAL CHARACTERISTICS.....................................................................................................................................78
13.3.1. TQFP 176 ........................................................................................................................................................78
13.3.2. LQFP-128........................................................................................................................................................79
13.4. DC CHARACTERISTICS ...............................................................................................................................................81
13.5. AC CHARACTERISTICS ...............................................................................................................................................82
13.5.1. EEPROM SMI Host Mode Timing Characteristics .........................................................................................82
13.5.2. EEPROM SMI Slave Mode Timing Characteristics ........................................................................................83
13.5.3. MDIO Slave Mode Timing Characteristics .....................................................................................................84
13.5.4. GMII Timing Characteristics...........................................................................................................................85
13.5.5. MII MAC Mode Timing ...................................................................................................................................86
13.5.6. MII PHY Mode Timing ....................................................................................................................................87
13.5.7. RGMII Timing Characteristics ........................................................................................................................88
13.6. POWER AND RESET CHARACTERISTICS ......................................................................................................................90
14. MECHANICAL DIMENSIONS.................................................................................................................................91
14.1. RTL8370: LQFP 128-PIN E-PAD PACKAGE .............................................................................................................91
14.2. RTL8370M: TQFP176-PIN E-PAD PACKAGE ..........................................................................................................92
15. ORDERING INFORMATION ...................................................................................................................................93
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Datasheet
List of Tables
TABLE 1. PIN ASSIGNMENT TABLE (RTL8370: LQFP-128) ........................................................................................................10
TABLE 2. PIN ASSIGNMENT TABLE (RTL8370M: TQFP-176).....................................................................................................12
TABLE 3. MEDIA DEPENDENT INTERFACE PINS (RTL8370) (LQFP128) .....................................................................................15
TABLE 4. PARALLEL LED PINS (RTL8370) (LQFP128)..............................................................................................................16
TABLE 5. SCAN MODE LED PINS (RTL8370) (LQFP128) ..........................................................................................................18
TABLE 6. CONFIGURATION STRAPPING PINS (RTL8370) (LQFP128)..........................................................................................19
TABLE 7. MISCELLANEOUS PINS (RTL8370) (LQFP128)............................................................................................................21
TABLE 8. TEST PINS (RTL8370) (LQFP128)...............................................................................................................................22
TABLE 9. POWER AND GND PINS (RTL8370) (LQFP128) ..........................................................................................................22
TABLE 10. MEDIA DEPENDENT INTERFACE PINS (RTL8370M) (TQFP176) .................................................................................23
TABLE 11. EXTENSION GMAC0 GMII PINS (RTL8370M) (TQFP176) ........................................................................................25
TABLE 12. EXTENSION GMAC1 GMII PINS (RTL8370M) (TQFP176) ........................................................................................27
TABLE 13. EXTENSION GMAC0 RGMII PINS (RTL8370M) (TQFP176)) ....................................................................................28
TABLE 14. EXTENSION GMAC1 RGMII PINS (RTL8370M) (TQFP176) .....................................................................................30
TABLE 15. EXTENSION GMAC0 MII PINS (MII MAC MODE OR MII PHY MODE) OF THE RTL8370M (TQFP176)....................31
TABLE 16. EXTENSION GMAC1 MII PINS (MII MAC MODE OR MII PHY MODE) OF THE RTL8370M (TQFP176)....................33
TABLE 17. PARALLEL MODE LED PINS (RTL8370M) (TQFP176)...............................................................................................35
TABLE 18. SCAN MODE LED PINS (RTL8370M) (TQFP176).......................................................................................................37
TABLE 19. CONFIGURATION STRAPPING PINS (RTL8370M) (TQFP176)......................................................................................38
TABLE 20. CONFIGURATION STRAPPING PINS (DISAUTOLOAD, DIS_8051, AND EN_FLASH) (RTL8370M) .........................39
TABLE 21. MISCELLANEOUS PINS (RTL8370M) (TQFP176)........................................................................................................40
TABLE 22. TEST PINS (RTL8370M) (TQFP176)...........................................................................................................................41
TABLE 23. POWER AND GND PINS (RTL8370M) (TQFP176) ......................................................................................................41
TABLE 24. MEDIA DEPENDENT INTERFACE PIN MAPPING ............................................................................................................44
TABLE 25. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE .........................................................................................48
TABLE 26. LED DEFINITIONS........................................................................................................................................................57
TABLE 27. RTL8370M GENERAL PURPOSE INTERFACES PIN DEFINITIONS ..................................................................................63
TABLE 28. EXTENSION GMAC0 GMII MODE PINS .......................................................................................................................64
TABLE 29. EXTENSION GMAC1 GMII MODE PINS .......................................................................................................................65
TABLE 30. EXTENSION GMAC0 RGMII PINS ...............................................................................................................................66
TABLE 31. EXTENSION GMAC1 RGMII PINS ...............................................................................................................................66
TABLE 32. EXTENSION GMAC0 MII PINS ....................................................................................................................................67
TABLE 33. EXTENSION GMAC1 MII PINS ....................................................................................................................................67
TABLE 34. PAGE 0: PCS REGISTER (PHY 0~7) .............................................................................................................................69
TABLE 35. REGISTER 0: CONTROL ................................................................................................................................................70
TABLE 36. REGISTER 1: STATUS....................................................................................................................................................71
TABLE 37. REGISTER 2: PHY IDENTIFIER 1...................................................................................................................................72
TABLE 38. REGISTER 3: PHY IDENTIFIER 2...................................................................................................................................72
TABLE 39. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT ...................................................................................................72
TABLE 40. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY ........................................................................................73
TABLE 41. REGISTER 6: AUTO-NEGOTIATION EXPANSION ............................................................................................................74
TABLE 42. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER....................................................................................74
TABLE 43. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ...................................................................75
TABLE 44. REGISTER 9: 1000BASE-T CONTROL REGISTER ...........................................................................................................75
TABLE 45. REGISTER 10: 1000BASE-T STATUS REGISTER ............................................................................................................76
TABLE 46. REGISTER 15: EXTENDED STATUS ...............................................................................................................................76
TABLE 47. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................77
TABLE 48. RECOMMENDED OPERATING RANGE ...........................................................................................................................77
TABLE 49. ASSEMBLY DESCRIPTION .............................................................................................................................................78
TABLE 50. MATERIAL PROPERTIES ...............................................................................................................................................78
TABLE 51. SIMULATION CONDITIONS ...........................................................................................................................................78
TABLE 52. THERMAL PERFORMANCE OF E-PAD TQFP-176 ON PCB UNDER STILL AIR CONVECTION .........................................79
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Datasheet
TABLE 53. THERMAL PERFORMANCE OF E-PAD TQFP-176 ON PCB UNDER FORCED CONVECTION ............................................79
TABLE 54. ASSEMBLY DESCRIPTION .............................................................................................................................................79
TABLE 55. MATERIAL PROPERTIES ...............................................................................................................................................80
TABLE 56. SIMULATION CONDITIONS ...........................................................................................................................................80
TABLE 57. THERMAL PERFORMANCE OF E-PAD LQFP-128 ON PCB UNDER STILL AIR CONVECTION ..........................................80
TABLE 58. THERMAL PERFORMANCE OF E-PAD LQFP-128 ON PCB UNDER FORCED CONVECTION .............................................80
TABLE 59. DC CHARACTERISTICS .................................................................................................................................................81
TABLE 60. EEPROM SMI HOST MODE TIMING CHARACTERISTICS .............................................................................................83
TABLE 61. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ...........................................................................................83
TABLE 62. MDIO TIMING CHARACTERISTICS AND REQUIREMENTS .............................................................................................84
TABLE 63. GMII TIMING CHARACTERISTICS ................................................................................................................................85
TABLE 64. MII MAC MODE TIMING .............................................................................................................................................86
TABLE 65. MII PHY MODE TIMING CHARACTERISTICS ................................................................................................................87
TABLE 66. RGMII TIMING CHARACTERISTICS ..............................................................................................................................89
TABLE 67. POWER AND RESET CHARACTERISTICS ........................................................................................................................90
TABLE 68. ORDERING INFORMATION ............................................................................................................................................93
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List of Figures
FIGURE 1. 8-PORT 1000BASE-T SWITCH .......................................................................................................................................5
FIGURE 2. 8-PORT 1000BASE-T ROUTER WITH DUAL MII/RGMII/GMII .....................................................................................6
FIGURE 3. RTL8370(M) BLOCK DIAGRAM ...................................................................................................................................7
FIGURE 4. RTL8370 PIN ASSIGNMENTS (LQFP-128)....................................................................................................................8
FIGURE 5. RTL8370M PIN ASSIGNMENTS (TQFP-176) ................................................................................................................9
FIGURE 6. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION ..................................................................................................44
FIGURE 7. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART ..................................................................................51
FIGURE 8. RTL8370(M) MAX-MIN SCHEDULING DIAGRAM .....................................................................................................53
FIGURE 9. PULL-UP AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED...........................................................................58
FIGURE 10. PULL-UP AND PULL-DOWN OF LED PINS FOR BI-COLOR LED ..................................................................................58
FIGURE 11. SCAN MODE LED CONNECTION DIAGRAM (GROUP A: SINGLE-COLOR LED (LED0)) ..............................................59
FIGURE 12. SCAN MODE LED CONNECTION DIAGRAM (GROUP B: BI-COLOR LED (LED1 & LED2)) ........................................59
FIGURE 13. SMI START AND STOP COMMAND ..............................................................................................................................61
FIGURE 14. EEPROM SMI HOST TO EEPROM............................................................................................................................61
FIGURE 15. EEPROM SMI HOST MODE FRAME...........................................................................................................................61
FIGURE 16. EEPROM SMI WRITE COMMAND FOR SLAVE MODE ................................................................................................62
FIGURE 17. EEPROM SMI READ COMMAND FOR SLAVE MODE ..................................................................................................62
FIGURE 18. MAC GMII MODE INTERFACE (1GBPS) SIGNAL DIAGRAM........................................................................................65
FIGURE 19. RGMII MODE INTERFACE SIGNAL DIAGRAM .............................................................................................................66
FIGURE 20. SIGNAL DIAGRAM OF MII PHY MODE INTERFACE (100MBPS) ..................................................................................68
FIGURE 21. SIGNAL DIAGRAM OF MII MAC MODE INTERFACE (100MBPS) .................................................................................68
FIGURE 22. EEPROM SMI HOST MODE TIMING CHARACTERISTICS ............................................................................................82
FIGURE 23. SCK/SDA POWER ON TIMING ....................................................................................................................................82
FIGURE 24. EEPROM AUTO-LOAD TIMING..................................................................................................................................82
FIGURE 25. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ..........................................................................................83
FIGURE 26. MDIO SOURCED BY MASTER (RTL8370(M) LINK PARTNER CPU)...........................................................................84
FIGURE 27. MDIO SOURCED BY SLAVE (RTL8370(M))...............................................................................................................84
FIGURE 28. GMII TIMING CHARACTERISTICS ...............................................................................................................................85
FIGURE 29. MII MAC MODE CLOCK TO DATA OUTPUT DELAY TIMING ......................................................................................86
FIGURE 30. MII MAC MODE INPUT TIMING .................................................................................................................................86
FIGURE 31. MII PHY MODE OUTPUT TIMING ...............................................................................................................................87
FIGURE 32. MII PHY MODE CLOCK OUTPUT TO DATA INPUT DELAY TIMING .............................................................................87
FIGURE 33. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=0) ................................................................88
FIGURE 34. RGMII OUTPUT TIMING CHARACTERISTICS (RGX_TXCLK_DELAY=2NS) ............................................................88
FIGURE 35. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=0)....................................................................88
FIGURE 36. RGMII INPUT TIMING CHARACTERISTICS (RGX_RXCLK_DELAY=2NS)................................................................89
FIGURE 37. POWER AND RESET CHARACTERISTICS .......................................................................................................................90
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1. General Description
The RTL8370 is an LQFP128 E-PAD, high-performance 8-port Gigabit Ethernet switch, and the
RTL8370M is a TQFP176 E-PAD, high-performance 8+2-port Gigabit Ethernet switch.
Both the RTL8370 and RTL8370M feature low-power integrated 8-port Giga-PHYs that support
1000Base-T, 100Base-T, and 10Base-T.
The RTL8370M supports two extra GMII/RGMII/MII ports for specific applications. The RTL8370 and
RTL8370M integrate all the functions of a high-speed switch system; including SRAM for packet
buffering, non-blocking switch fabric, and internal register management into a single CMOS device. Only
a 25MHz crystal is required; an optional EEPROM is offered for internal register configuration.
The embedded packet storage SRAM in the RTL8370(M) features superior memory management
technology to efficiently utilize memory space. The RTL8370(M) integrates an 8K-entry look-up table
with a 4-way XOR Hashing algorithm for address searching and learning. The table provides read/write
access from the EEPROM Serial Management Interface (SMI), and each of the entries can be configured
as a static entry. The entry aging time is between 200 and 400 seconds. Eight Filtering Databases are used
to provide Independent VLAN Learning and Shared VLAN Learning (IVL/SVL) functions.
Unfinished file and contains much errors. Do not use for anything. The Extension GMAC0 and Extension
GMAC1 of the RTL8370M implement dual GMII/RGMII/MII interfaces for connecting with an external
PHY or MAC in specific applications. This interface could be connected to an external CPU or RISC as
8-port Gigabit Router applications. In router applications, the RTL8370(M) supports Port VID (PVID) for
each port to insert a PVID in the VLAN tag on egress. When using this function, VID information carried
in the VLAN tag will be changed to PVID.
Note: The RTL8370M (only) Extra Interface (Extension GMAC0 and Extension GMAC1) supports:
Gigabit Media Independent Interface (GMII)
Reduced Gigabit Media Independent Interface (RGMII)
Media Independent Interface (MII)
The RTL8370(M) supports standard 802.3x flow control frames for full duplex, and optional
backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the
availability of system resources, including the packet buffers and transmitting queues. The RTL8370(M)
supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-
blocked ports only. For IP multicast applications, the RTL8370(M) supports IPv4 IGMPv1/v2/v3 and
IPv6 MLDv1/v2 snooping.
In order to support flexible traffic classification, the RTL8370(M) supports 64-entry ACL rule check and
multiple actions options. Each port can optionally enable or disable the ACL rule check function. The
ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an
ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value
in 802.1q/Q tag, and rate policing. The rate policing mechanism supports from 8Kbps to 1Gbps (in 8Kbps
steps).
In Bridge operation the RTL8370(M) supports 16 sets of port configurations: disable, block, learning, and
forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and
management application requirements, the RTL8370(M) supports IEEE 802.1x Port-based/MAC-based
Access Control. For those ports that do not pass IEEE 802.1x authentication, the RTL8370(M) provides a
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Datasheet
Port-based/MAC-based Guest VLAN function for them to access limited network resources. A 1-set Port
Mirroring function is configured to mirror traffic (RX, TX, or both) appearing on one of the switch’s
ports. Support is provided on each port for multiple RFC MIB Counters, for easy debug and diagnostics.
To improve real-time or multimedia networking applications, the RTL8370(M) supports eight priority
assignments for each received packet. These are based on (1) Port-based priority; (2) 802.1p/Q VLAN tag
priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority. Each output port supports a
weighted ratio of eight priority queues to fit bandwidth requirements in different applications. The input
bandwidth control function helps limit per-port traffic utilization. There is one leaky bucket for average
packet rate control for each queue of all ports. Queue scheduling algorithm can use Strict Priority (SP) or
Weighted Fair Queue (WFQ) or mixed.
The RTL8370(M) provides a 4K-entry VLAN table for 802.1Q port-based, tag-based, and protocol-based
VLAN operation to separate logical connectivity from physical connectivity. The RTL8370(M) supports
four Protocol-based VLAN configurations that can optionally select EtherType, LLC, and RFC1042 as
the search key. Each port may be set to any topology via EEPROM upon reset, or EEPROM SMI Slave
after reset.
In router applications, the router may want to know the input port of the incoming packet. The
RTL8370(M) supports an option to insert a VLAN tag with VID=Port VID (PVID) on each egress port.
The RTL8370(M) also provides an option to admit VLAN tagged packet with a specific PVID only. If
this function is enabled, the RTL8370(M) will drop all non-tagged packets and packets with an incorrect
PVID.
RTL8370(M)
Datasheet
2. Features
Optional setting of per-port action to
RTL8370M: Single-chip 8+2-port gigabit
take when ACL mismatch
non-blocking switch architecture;
RTL8370: Single-chip 8-port gigabit non- Supports IEEE 802.1Q VLAN
blocking switch architecture
Supports 4K VLANs and 32 Extra
Embedded 8-port 10/100/1000Base-T PHY Enhanced VLANs
Supports Un-tag definition in each
Each port supports full duplex
VLAN
10/100/1000M connectivity (half duplex
only supported in 10/100M mode) Supports VLAN policing and VLAN
forwarding decision
Full-duplex and half-duplex operation with
Supports Port-based, Tag-based, and
IEEE 802.3x flow control and backpressure
Protocol-based VLAN
Supports 9216-byte jumbo packet length Up to 4 Protocol-based VLAN entries
forwarding at wire speed
Supports per-port and per-VLAN egress
Supports Realtek Cable Test (RTCT) VLAN tagging and un-tagging
function
Supports IVL, SVL, and IVL/SVL
RTL8370M Extra Interface (Extension Supports 8K-entry MAC address table
GMAC0 and Extension GMAC1) supports with 4-way hash algorithm
Dual-port Media Independent Interface Up to 8K L2/L3 Filtering Database
(MII)
Supports Spanning Tree port behavior
Dual-port Reduced Gigabit Media
configuration
Independent Interface (RGMII)
IEEE 802.1w Rapid Spanning Tree
Dual-port Gigabit Media Independent
Interface (GMII) IEEE 802.1s Multiple Spanning Tree
with up to 16 Spanning Tree instances
Supports 64-entry ACL Rules
Supports IEEE 802.1x Access Control
Search keys support physical port,
Protocol
Layer2, Layer3, and Layer4 information
Port-Based Access Control
Actions support mirror, redirect,
dropping, priority adjustment, traffic MAC-Based Access Control
policing, CVLAN decision, and SVLAN
Guest VLAN
assignment
Supports 5 types of user defined ACL
rule format for 64 ACL rules
Optional per-port enable/disable of ACL
function
RTL8370(M)
Datasheet
Supports Quality of Service (QoS) Supports OAM and EEE LLDP (Energy
Efficient Ethernet Link Layer Discovery
Supports per port Input Bandwidth
Protocol
Control
Traffic classification based on IEEE Supports Loop Detection
802.1p/Q priority definition, physical
Port, IP DSCP field, ACL definition, Security Filtering
VLAN based priority, MAC based Disable learning for each port
priority, and SVLAN based priority
Disable learning-table aging for each
Eight Priority Queues per port port
Per queue flow control Drop unknown DA for each port
Min-Max Scheduling
Broadcast/Multicast/Unknown DA storm
Strict Priority and Weighted Fair Queue control protects system from attack by
(WFQ) to provide minimum bandwidth hackers
One leaky bucket to constrain the
average packet rate of each queue Supports Realtek Green Ethernet features
Link-On Cable Length Power Saving
Supports rate limiting (64 shared meters,
with 8kpbs granulation) Link-Down Power Saving
Supports RFC MIB Counter Supports 1 interrupt output to external CPU

for notification (RTL8370M only)
MIB-II (RFC 1213)
Ethernet-Like MIB (RFC 3635) Each port supports 3 parallel LED or scan
LED outputs
Interface Group MIB (RFC 2863)
RMON (RFC 2819) Supports EEPROM SMI Slave interface to
access configuration register
Bridge MIB (RFC 1493)
Bridge MIB Extension (RFC 2674) Supports 16K-byte EEPROM space for
configuration
Supports Stacking VLAN and Port Isolation
with 8 Enhanced Filtering Databases Integrated 8051 microprocessor
Supports IEEE 802.1ad Stacking VLAN Supports Flash Interface

Supports 64 SVLANs 25MHz crystal or 3.3V OSC input
Supports 32 L2/IPv4 Multicast mappings
to SVLAN RTL8370M: TQFP 176-pin E-PAD package
RTL8370: LQFP 128-pin E-PAD package
Supports 4 IEEE 802.3ad Link aggregation
port groups
RTL8370(M)
Datasheet
3. System Applications
8-Port 1000Base-T Switch
8-Port 1000Base-T Router with Dual MII/RGMII/GMII
4. Application Examples
4.1. 8-Port 1000Base-T Switch
Figure 1. 8-Port 1000Base-T Switch
RTL8370(M)
Datasheet
4.2. 8-Port 1000Base-T Router with Dual MII/RGMII/GMII

(RTL8370M)
MII/RGMII/GMII
MII/RGMII/GMII
EEPROM
Address Table MIB Counter SMI
Extension Extension
Giga Giga
Packet Buffer MAC 1 MAC 0
Queue Manager ALE EEPROM

SMI Host
/Slave Slave Mode
ACL
Giga Giga Giga Giga Giga Giga Giga Giga

MAC 0 MAC 1 MAC 2 MAC 3 MAC 4 MAC 5 MAC 6 MAC 7
Giga Giga Giga Giga Giga Giga Giga Giga

PHY 0 PHY 1 PHY 2 PHY 3 PHY 4 PHY 5 PHY 6 PHY 7
RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45

Jack Jack Jack Jack Jack Jack Jack Jack
Figure 2. 8-Port 1000Base-T Router with Dual MII/RGMII/GMII
Note: Extra Interface (Extension GMAC0 and Extension GMAC1) in MII/RGMII/GMII Mode.
RTL8370(M)
Datasheet
5. Block Diagram
RTL8370/RTL8370M Block Diagram

UTP P0
Giga-PHY PCS GMAC
UTP
Giga-PHY PCS
P1 SRAM
GMAC
Controller Packet Buffer
UTP SRAM
P2
Giga-PHY PCS GMAC
UTP P3
Giga-PHY PCS GMAC
UTP P4
Queue
Giga-PHY PCS Managment
GMAC Linking Lists
UTP P5
Giga-PHY PCS GMAC
UTP P6
Giga-PHY PCS GMAC 8K MAC
Address Table
UTP P7
Lookup
Giga-PHY PCS GMAC Engine
MII/GMII/
RGMII MII
Extension
GMAC
/RGMII 0 4096 VLAN
MII/GMII/ Table
Extension
RGMII MII GMAC
/RGMII 1
GNIC
MAC
Control
GNIC 8051
Registers
PLL I2C
+
I2C Host MIB Counter
Flash Interface Slave
25MHz FLASH SCK/SDA

Crystal
Figure 3. RTL8370(M) Block Diagram
RTL8370(M)
Datasheet
6. Pin Assignments
6.1. RTL8370 Pin Assignments (LQFP-128)
Figure 4. RTL8370 Pin Assignments (LQFP-128)
6.2. Package Identification

Green package is indicated by the ‘G’ in GXXXX (Figure 4).
RTL8370(M)
Datasheet
6.3. RTL8370M Pin Assignments (TQFP-176)
Figure 5. RTL8370M Pin Assignments (TQFP-176)
6.4. Package Identification

Green package is indicated by the ‘G’ in GXXXX (Figure 5).
RTL8370(M)
Datasheet
6.5. Pin Assignment Table (RTL8370: LQFP-128)

Upon Reset: Defined as a short time after the end of a hardware reset.
After Reset: Defined as the time after the specified ‘Upon Reset’ time.
I: Input Pin AI: Analog Input Pin
O: Output Pin AO: Analog Output Pin
I/O: Bi-Direction Input/Output Pin AI/O: Analog Bi-Direction Input/Output Pin
P: Digital Power Pin AP: Analog Power Pin
G: Digital Ground Pin AG: Analog Ground Pin
IPU: Input Pin With Pull-Up Resistor; OPU: Output Pin With Pull-Up Resistor;
(Typical Value = 75K Ohm) (Typical Value = 75K Ohm)
IS: Input Pin With Schmitt Trigger
Table 1. Pin Assignment Table (RTL8370: LQFP-128)

Name Pin No. Type Name Pin No. Type
P2MDICP 1 AI/O P4MDIAP 25 AI/O
P2MDICN 2 AI/O P4MDIAN 26 AI/O
P2MDIDP 3 AI/O P4MDIBP 27 AI/O
P2MDIDN 4 AI/O P4MDIBN 28 AI/O
AVDDH 5 AP AVDDL 29 AP
P3MDIAP 6 AI/O P4MDICP 30 AI/O
P3MDIAN 7 AI/O P4MDICN 31 AI/O
P3MDIBP 8 AI/O P4MDIDP 32 AI/O
P3MDIBN 9 AI/O P4MDIDN 33 AI/O
AVDDL 10 AP AVDDH 34 AP
P3MDICP 11 AI/O P5MDIAP 35 AI/O
P3MDICN 12 AI/O P5MDIAN 36 AI/O
P3MDIDP 13 AI/O P5MDIBP 37 AI/O
P3MDIDN 14 AI/O P5MDIBN 38 AI/O
AVDDH 15 AP AVDDL 39 AP
AGND 16 AG P5MDICP 40 AI/O
MDIREF 17 AO P5MDICN 41 AI/O
AVDDL 18 AP P5MDIDP 42 AI/O
AVDDH 19 AP P5MDIDN 43 AI/O
DVDDL 20 P PLLVDDL1 44 AP
DVDDL 21 P P6MDIAP 45 AI/O
DVDDL 22 P P6MDIAN 46 AI/O
DVDDL 23 P P6MDIBP 47 AI/O
AVDDH 24 AP P6MDIBN 48 AI/O
RTL8370(M)
Datasheet

AVDDL 49 AP P1LED0/SLED_P2_6A/ 89 I/OPU
P6MDICP 50 AI/O RESERVED
P6MDICN 51 AI/O P1LED1/SLED_P1_5A 90 I/OPU
P6MDIDP 52 AI/O P0LED2/SLED_P0_4A/GPIO2/ 91 I/OPU
P6MDIDN 53 AI/O EN_PHY
DVDDL 92 P
AVDDH 54 AP
LED_DA/P0LED1/SLED_G2A 93 I/OPU
P7MDIAP 55 AI/O
P7MDIAN 56 AI/O LED_CK/P0LED0/SLED_P4B/ 94 I/OPU
SMI_SEL
P7MDIBP 57 AI/O
DVDDL 95 P
P7MDIBN 58 AI/O
AVDDH 96 AP
AVDDL 59 AP
XTALO 97 AO
P7MDICP 60 AI/O
XTALI 98 AI
P7MDICN 61 AI/O
nRESET 99 IS
P7MDIDP 62 AI/O
SCK/MMD_MDC 100 I/O
P7MDIDN 63 AI/O
SDA/MMD_MDIO 101 I/O
AVDDH 64 AP
AVDDH 102 AP
RESERVED 65 AO
P0MDIAP 103 AI/O
RESERVED 66 AO
P0MDIAN 104 AI/O
P7LED2/RESERVED 67 I/OPU
P0MDIBP 105 AI/O
P0MDIBN 106 AI/O
AVDDL 107 AP
P0MDICP 108 AI/O
P6LED0/GPIO1 71 I/OPU
P0MDICN 109 AI/O
P0MDIDP 110 AI/O
P0MDIDN 111 AI/O
AVDDH 112 AP
P5LED1 75 I/OPU
P1MDIAP 113 AI/O
DVDDL 76 P
P1MDIAN 114 AI/O
DVDDIO 77 P
P1MDIBP 115 AI/O
DVDDL 78 P
P1MDIBN 116 AI/O
P4LED2/SLED_P7B/GPIO3 79 I/OPU
AVDDL 117 AP
P4LED0/SLED_P6B/ 80 I/OPU
P1MDICP 118 AI/O
EEPROM_MOD
P1MDICN 119 AI/O
P4LED1/SLED_P5B/GPIO6 81 I/OPU
P3LED1/SLED_G1A/GPIO5 82 I/OPU P1MDIDP 120 AI/O
83 I/OPU P1MDIDN 121 AI/O
P3LED2/SLED_P3B/
RESERVED PLLVDDL0 122 AP
P3LED0/SLED_P2B/RESERVED 84 I/OPU ATESTCK0 123 AO
P2LED2/SLED_P1B/DIS_8051 85 I/OPU P2MDIAP 124 AI/O
P2LED0/SLED_P0B/ 86 I/OPU P2MDIAN 125 AI/O
DISAUTOLOAD P2MDIBP 126 AI/O
P2LED1/SLED_G1B/GPIO4 87 I/OPU P2MDIBN 127 AI/O
P1LED2/SLED_P3_7A/ 88 I/OPU AVDDL 128 AP
RESERVED GND EPAD G
RTL8370(M)
Datasheet
6.6. Pin Assignment Table (RTL8370M: TQFP-176)

Table 2. Pin Assignment Table (RTL8370M: TQFP-176)
AVDDH 1 AP AVDDH 42 AP
P3MDIAP 2 AI/O P5MDIAP 43 AI/O
P3MDIAN 3 AI/O P5MDIAN 44 AI/O
P3MDIBP 4 AI/O P5MDIBP 45 AI/O
P3MDIBN 5 AI/O P5MDIBN 46 AI/O
AVDDL 6 AP AVDDL 47 AP
P3MDICP 7 AI/O P5MDICP 48 AI/O
P3MDICN 8 AI/O P5MDICN 49 AI/O
P3MDIDP 9 AI/O P5MDIDP 50 AI/O
P3MDIDN 10 AI/O P5MDIDN 51 AI/O
AVDDH 11 AP PLLVDDL1 52 AP
GND 12 G PLLGND1 53 AG
RESERVED 13 AI AVDDH 54 AP
RESERVED 14 AO P6MDIAP 55 AI/O
AGND 15 AG P6MDIAN 56 AI/O
MDIREF 16 AO P6MDIBP 57 AI/O
AVDDL 17 AP P6MDIBN 58 AI/O
RTT1 18 AO AVDDL 59 AP
RTT2 19 AO P6MDICP 60 AI/O
AVDDH 20 AP P6MDICN 61 AI/O
DVDDIO 21 P P6MDIDP 62 AI/O
DVDDL 22 P P6MDIDN 63 AI/O
GND 23 G AVDDH 64 AP
INTERRUPT 24 OPU P7MDIAP 65 AI/O
BUZZER/DIS_LPD 25 I/OPU P7MDIAN 66 AI/O
DVDDL 26 P P7MDIBP 67 AI/O
RESERVED 27 IPU P7MDIBN 68 AI/O
GND 28 G AVDDL 69 AP
DVDDL 29 P P7MDICP 70 AI/O
DVDDL 30 P P7MDICN 71 AI/O
GND 31 G P7MDIDP 72 AI/O
AVDDH 32 AP P7MDIDN 73 AI/O
P4MDIAP 33 AI/O AVDDH 74 AP
P4MDIAN 34 AI/O RESERVED 75 AO
P4MDIBP 35 AI/O RESERVED 76 AO
P4MDIBN 36 AI/O G1_CRS/M1M_CRS/M1P_CRS 77 I/O
AVDDL 37 AP G1_COL/M1M_COL/M1P_COL 78 I/O
P4MDICP 38 AI/O G1_TXD7/P7LED2/SPI_CLK 79 I/OPU
P4MDICN 39 AI/O G1_TXD6/P7LED0/SPI_D0 80 I/OPU
P4MDIDP 40 AI/O G1_TXD5/P7LED1/SPI_D1 81 I/OPU
P4MDIDN 41 AI/O G1_TXD4/P6LED2/SPI_CS 82 I/OPU
RTL8370(M)
Datasheet

G1_TXD3/RG1_TXD3/ 83 O G0_RXD3/RG0_RXD3/ 113 I
M1M_TXD3/M1P_RXD3 M0M_RXD3/M0P_TXD3
G1_TXEN/RG1_TXCTL/ 87 O G0_RXDV/RG0_RXCTL/ 117 I/O
M1M_TXEN/M1P_RXDV M0M_RXDV/M0P_TXEN/GPIO6
DVDDIO_1 88 P G0_RXC/RG0_RXCLK/ 118 I/O
G1_GTXC/RG1_TXCLK/ 89 I/O M0M_RXCLK/M0P_TXCLK
M1M_TXCLK/M1P_RXCLK G0_RXER/P2LED2/GPIO7/ 119 I/OPU
G1_TXCLK/P6LED0/GPIO1 90 I/OPU SLED_P1B
G1_TXER/M1M_TXER/ 91 I/OPU G0_TXER/P2LED0/EEPROM_MOD 120 I/OPU
M1P_RXER/RESERVED /SLED_P0B
G1_RXER/M1M_RXER/ 92 I G0_TXCLK/P2LED1/SLED_G1B 121 I/OPU
M1P_TXER G0_GTXC/RG0_TXCLK/ 122 I/O
G1_RXC/RG1_RXCLK/ 93 I/O M0M_TXCLK/M0P_RXCLK/GPIO5
M1M_RXCLK/M1P_TXCLK G0_TXEN/RG0_TXCTL/ 123 I/O
G1_RXDV/RG1_RXCTL/ 94 I M0M_TXEN/M0P_RXDV/
M1M_RXDV/M1P_TXEN RESERVED
G1_RXD0/RG1_RXD0/ 95 I G0_TXD0/RG0_TXD0/M0M_TXD0 124 I/OPU
M1M_RXD0/M1P_TXD0 /M0P_RXD0/EN_FLASH
G1_RXD1/RG1_RXD1/ 96 I G0_TXD1/RG0_TXD1/ 125 I/OPU
M1M_RXD1/M1P_TXD1 M0M_TXD1/M0P_RXD1/DIS_8051
G1_RXD2/RG1_RXD2/ 97 I G0_TXD2/RG0_TXD2/M0M_TXD2 126 I/OPU
M1M_RXD2/M1P_TXD2 /M0P_RXD2/DISAUTOLOAD
G1_RXD3/RG1_RXD3/ 98 I G0_TXD3/RG0_TXD3/ 127 I/OPU
M1M_RXD3/M1P_TXD3 M0M_TXD3/M0P_RXD3/
G1_RXD4/P6LED1 99 I/OPU RESERVED/GPIO4
G1_RXD5/P5LED2/GPIO0 100 I/OPU G0_TXD4/P1LED2/SLED_P3_7A/ 128 I/OPU
RESERVED
G1_RXD6/P5LED0 101 I/OPU
G0_TXD5/P1LED0/SLED_P2_6A/ 129 I/OPU
G1_RXD7/P5LED1 102 I/OPU RESERVED
DVDDL 103 P G0_TXD6/P1LED1/SLED_P1_5A 130 I/OPU
DVDDIO_1 104 P G0_TXD7/P0LED2/EN_PHY/GPIO2 131 I/OPU
DVDDIO_0 105 P /SLED_P0_4A
DVDDL 106 P DVDDIO_0 132 P
G0_CRS/M0M_CRS/M0P_CRS/ 107 I/OPU DVDDL 133 P
P4LED2/SLED_P7B/GPIO3 LED_DA/P0LED1/SLED_G2A 134 I/OPU
G0_COL/M0M_COL/M0P_COL/ 108 I/OPU LED_CK/P0LED0/SLED_P4B/ 135 I/OPU
P4LED0/SLED_P6B SMI_SEL
G0_RXD7/P4LED1/SLED_P5B 109 I/OPU DVDDL 136 P
G0_RXD6/P3LED1/SLED_G1A 110 I/OPU AVDDH 137 AP
G0_RXD5/P3LED2/SLED_P3B 111 I/OPU XTALO 138 AO
G0_RXD4/P3LED0/SLED_P2B 112 I/OPU
RTL8370(M)
Datasheet

XTALI 139 AI AVDDL 159 AP
DVDDIO 140 P P1MDICP 160 AI/O
nRESET 141 IS P1MDICN 161 AI/O
SCK/MMD_MDC 142 I/O P1MDIDP 162 AI/O
SDA/MMD_MDIO 143 I/O P1MDIDN 163 AI/O
AVDDH 144 AP PLLVDDL0 164 AP
P0MDIAP 145 AI/O ATESTCK0 165 AO
P0MDIAN 146 AI/O PLLGND0 166 AG
P0MDIBP 147 AI/O AVDDH 167 AP
P0MDIBN 148 AI/O P2MDIAP 168 AI/O
AVDDL 149 AP P2MDIAN 169 AI/O
P0MDICP 150 AI/O P2MDIBP 170 AI/O
P0MDICN 151 AI/O P2MDIBN 171 AI/O
P0MDIDP 152 AI/O AVDDL 172 AP
P0MDIDN 153 AI/O P2MDICP 173 AI/O
AVDDH 154 AP P2MDICN 174 AI/O
P1MDIAP 155 AI/O P2MDIDP 175 AI/O
P1MDIAN 156 AI/O P2MDIDN 176 AI/O
P1MDIBP 157 AI/O GND EPAD G
P1MDIBN 158 AI/O
RTL8370(M)
Datasheet
7. Pin Descriptions (RTL8370)

7.1. Media Dependent Interface Pins (RTL8370)
Table 3. Media Dependent Interface Pins (RTL8370) (LQFP128)
Pin Name Pin No. Type Drive Description
RTL8370 (mA)
P0MDIAP/N 103 AI/O 10 Port 0 Media Dependent Interface A~D.
104 For 1000Base-T operation, differential data from the media is
P0MDIBP/N 105 transmitted and received on all four pairs. For 100Base-Tx and
106 10Base-T operation, only MDIAP/N and MDIBP/N are used. Auto
P0MDICP/N 108 MDIX can reverse the pairs MDIAP/N and MDIBP/N.
109
P0MDIDP/N 110 Each of the differential pairs has an internal 100-ohm termination
111 resistor.
119
121 resistor.
2
4 resistor.
12
14 resistor.
31
33 resistor.
RTL8370(M)
Datasheet

RTL8370 (mA)
41
43 resistor.
51
53 resistor.
61
63 resistor.
7.2. Parallel LED Pins (RTL8370)

Table 4. Parallel LED Pins (RTL8370) (LQFP128)
RTL8370 (mA)
P7LED2/ 67 I/OPU - Port 7 LED2 Output Signal.
RESERVED P7LED2 indicates information is defined by register or EEPROM.
P6LED1/GPIO7 72 I/OPU - Port 6 LED1 Output Signal.
P6LED1 indicates information is defined by register or EEPROM.
RTL8370(M)
Datasheet

RTL8370 (mA)
P5LED1 75 I/OPU - Port 5 LED1 Output Signal.
EEPROM_MOD P4LED0 indicates information is defined by register or EEPROM.
DIS_8051 P2LED2 indicates information is defined by register or EEPROM.
DISAUTOLOAD P2LED0 indicates information is defined by register or EEPROM.
EN_PHY P0LED2 indicates information is defined by register or EEPROM.
LED_DA P0LED1 indicates information is defined by register or EEPROM.
LED_CK/ P0LED0 indicates information is the same as P7LED0 and is defined
SMI_SEL by register or EEPROM.
Note: See section 10.19 LED Indicator, page 57 for details.
RTL8370(M)
Datasheet
7.3. Scan Mode LED Pins (RTL8370) (LQFP128)

Table 5. Scan Mode LED Pins (RTL8370) (LQFP128)
RTL8370 (mA)
SLED_G1A/P3LED1 82 I/OPU - Scan Mode LED Group A G1A Output Signal.
/GPIO5
SLED_G2A/LED_DA 93 I/OPU - Scan Mode LED Group A G2A Output Signal.
/P0LED1
SLED_P0_4A/GPIO2 91 I/OPU - Scan Mode LED Group A P0_4A Output Signal.
/EN_PHY/P0LED2
SLED_P1_5A 90 I/OPU - Scan Mode Group A LED P1_5A Output Signal.
/P1LED1
SLED_P2_6A/ 89 I/OPU - Scan Mode LED Group A P2_6A Output Signal.
P1LED0/RESERVED
SLED_P3_7A 88 I/OPU - Scan Mode LED Group A P3_7A Output Signal.
/P1LED2/RESERVED
SLED_G1B/P2LED1 87 I/OPU - Scan Mode LED Group B G1B Output Signal.
/GPIO4
SLED_P0B/P2LED0 86 I/OPU - Scan Mode LED Group B P0B Output Signal.
/DISAUTOLOAD
/DIS_8051
/RESERVED
/RESERVED
SLED_P4B/LED_CK 94 I/OPU - Scan Mode LED Group B P4B Output Signal.
/P0LED0/SMI_SEL
/GPIO6
/EEPROM_MOD
/GPIO3
Note: See section 10.19.2 Scan LED Mode, page 58 for details.
RTL8370(M)
Datasheet
7.4. Configuration Strapping Pins (RTL8370)

Table 6. Configuration Strapping Pins (RTL8370) (LQFP128)
Pin Name Pin No. Type Description
RTL8370
RESERVED/P5LED0 74 I/OPU Internal Use/Reserved.
Note: This pin must be kept floating, or pulled high via an external
4.7k ohm resistor upon power on or reset.
When pulled high, the LED output polarity will be low active. See
section 10.19 LED Indicator, page 57 for more details.
EEPROM_MOD/P4LED0 80 I/OPU EEPROM Mode Selection.
Pull Up: EEPROM 24Cxx Size greater than 16Kbits (24C32~)
Pull Down: EEPROM 24Cxx Size less than or equal to 16Kbit
(24C02~24C16).
Note: This pin must be kept floating, or pulled high or low via an
external 4.7k ohm resistor upon power on or reset.
When this pin is pulled low, the LED output polarity will be high
active. When this pin is pulled high, the LED output polarity will
change from high active to low active. See section 10.19 LED
Indicator, page 57 for more details.
Note: This pin must be pulled low via an external 4.7k ohm resistor
upon power on or reset.
When pulled low, the LED output polarity will be high active. See
DIS_8051/P2LED2 85 I/OPU Disable Embedded 8051.
Pull Up: Disable embedded 8051 upon power on or reset
Pull Down: Enable embedded 8051 upon power on or reset
RTL8370(M)
Datasheet

RTL8370
DISAUTOLOAD/P2LED0 86 I/OPU Disable EEPROM Autoload.
Pull Up: Disable EEPROM autoload upon power on or reset
Pull Down: Enable EEPROM autoload upon power on or reset
Note1: When DIS_8051=1 and DISAUTOLOAD=0, the EEPROM
data will be treat as register configuration data upon power on or
reset initial stage. When DIS_8051 = 0 and DISAUTOLOAD =0, the
EEPROM data will be loaded to embedded 8051 instruction memory
upon power on or reset.
Note2: This pin must be kept floating, or pulled high or low via an
EN_PHY/P0LED2 91 I/OPU Enable Embedded PHY.
Pull Up: Enable embedded PHY
Pull Down: Disable embedded PHY
SMI_SEL/P0LED0/ 94 I/OPU EEPROM SMI/MII Management Interface Selection.
LED_CK Pull Up: EEPROM SMI interface
Pull Down: MII Management Interface
RTL8370(M)
Datasheet
7.5. Miscellaneous Pins (RTL8370)

Table 7. Miscellaneous Pins (RTL8370) (LQFP128)
RTL8370
XTALI 98 AI 25MHz Crystal Clock Input and Feedback Pin.
25MHz +/-50ppm tolerance crystal reference or oscillator input.
XTALO 97 AO 25MHz Crystal Clock Output Pin.
25MHz +/-50ppm tolerance crystal output.
MDIREF 17 AO Reference Resistor.
A 2.49K ohm (1%) resistor must be connected between MDIREF and
GND.
RESERVED 65 AO Reserved. Must be left floating in normal operation.
SCK/MMD_MDC 100 I/O EEPROM SMI Interface Clock/MII Management Interface Clock
(selected via the hardware strapping pin 94, SMI_SEL).
SDA/MMD_MDIO 101 I/O EEPROM SMI Interface Data/MII Management Interface Data
nRESET 99 IS System Reset Input Pin.
When low active will reset the RTL8370.
P5LED2/GPIO0 73 I/OPU General Purpose Input/Output Interfaces IO0.
P0LED2/SLED_P0_4A/ 91 I/OPU General Purpose Input/Output Interfaces IO2.
GPIO2/EN_PHY
P4LED2/SLED_P7B/ 79 I/OPU General Purpose Input/Output Interfaces IO3.
GPIO3
P2LED1/SLED_G1B/ 87 I/OPU General Purpose Input/Output Interfaces IO4.
GPIO4
P3LED1/SLED_G1A/ 82 I/OPU General Purpose Input/Output Interfaces IO5.
GPIO5
P4LED1/SLED_P5B/ 81 I/OPU General Purpose Input/Output Interfaces IO6.
GPIO6
RTL8370(M)
Datasheet
7.6. Test Pins (RTL8370)

Table 8. Test Pins (RTL8370) (LQFP128)
RTL8370
ATESTCK0 123 AO Reserved for Internal Use. Must be left floating.
7.7. Power and GND Pins (RTL8370)

Table 9. Power and GND Pins (RTL8370) (LQFP128)
RTL8370
DVDDIO 77 P Digital I/O High Voltage Power for INTERRUPT, SMI, nRESET
DVDDL 20, 21, 22, 23, 76, P Digital Low Voltage Power.
78, 92, 95
AVDDH 5, 15, 19, 24, 34, 54, AP Analog High Voltage Power.
64, 96, 102, 112
AVDDL 10, 18, 29, 39, 49, AP Analog Low Voltage Power.
59, 107, 117, 128
PLLVDDL0 122 AP PLL0 Low Voltage Power.
GND EPAD G GND.
AGND 15 AG Analog GND.
RTL8370(M)
Datasheet
8. Pin Descriptions (RTL8370M)

8.1. Media Dependent Interface Pins (RTL8370M)
Table 10. Media Dependent Interface Pins (RTL8370M) (TQFP176)
RTL8370M (mA)
151
153 resistor.
161
163 resistor.
174
176 resistor.
8
10 resistor.
39
41 resistor.
RTL8370(M)
Datasheet

RTL8370M (mA)
49
51 resistor.
61
63 resistor.
71
73 resistor.
8.2. General Purpose Interfaces (RTL8370M)

The RTL8370M supports multi-function General Purpose Interfaces that can be configured as extra
interfaces of Extension GMAC0 and Extension GMAC1, LED interfaces, or other Digital I/O interfaces.
The RTL8370M supports two extension interfaces (Extension GMAC0 and Extension GMAC1) for
connecting with an external PHY, MAC, or CPU in specific applications. These two extension interfaces
support GMII, RGMII, MII MAC mode, or MII PHY mode via register configuration. The extension
interface 0 data path connects to extension GMAC0, and the extension interface 1 data path connects to
extension GMAC1. The General Purpose Interface also could be configured to parallel mode LED or scan
mode LED interface when the GMII interface is disabled.
8.2.1. GMII Interface Pins (RTL8370M)

The Extension GMAC0 and Extension GMAC1 of the RTL8370M support two GMII interfaces when
register configuration is set to GMII mode interface. When the extension interface operates at 1Gbps, the
interface will be GMII. When the extension interfaces operate at 100Mbps/10Mbps, the interface will be
MII. Note that 1Gbps Half Duplex is not supported in this configuration.
RTL8370(M)
Datasheet
Table 11. Extension GMAC0 GMII Pins (RTL8370M) (TQFP176)

RTL8370M (mA)
G0_CRS 107 IPU - G0_CRS Carrier Sense Input when the Extension GMAC0 GMII
interface operates in 10/100 MII half duplex mode.
G0_CRS is only valid in 10/100Mbps MII half duplex mode. It is
asserted high when a valid carrier is detected on the media.
This pin must be pulled low with a 1K ohm resistor when not used.
G0_COL 108 IPU - G0_COL Collision Detect Input when the Extension GMAC0 GMII
G0_COL is only valid in 10/100Mbps MII half duplex mode. It is
asserted high when a collision is detected on the media.
G0_RXD7 109 IPU - G0_RXD[7:0] Extension GMAC0 GMII Receive Data Input.
G0_RXD6 110 IPU Received data is received synchronously at the rising edge of
G0_RXD5 111 IPU G0_RXC.
G0_RXD4 112 IPU In 10/100Mbps MII mode, only G0_RXD[3:0] are available.
G0_RXD3 113 I These pins must be pulled low with a 1K ohm resistor when not
G0_RXD2 114 I used.
G0_RXD1 115 I
G0_RXD0 116 I
G0_RXDV 117 I - G0_RXDV Extension GMAC0 GMII Receive Data Valid Input.
Receive Data Valid is received synchronously at the rising edge of
G0_RXC in both 1Gbps GMII and 10/100Mbps MII MAC mode.
G0_RXC 118 I - G0_RXC Extension GMAC0 GMII Receive Clock Input.
In GMII mode: 125MHz receive clock. Used to synchronize
G0_RXD[7:0], G0_RXER , and G0_RXDV.
In MII 10/100Mbps mode: G0_RXC is 2.5/25MHz. Used to
synchronize G0_RXD[3:0], G0_RXER, G0_RXDV, G0_CRS, and
G0_COL.
G0_RXER 119 IPU - G0_RXER Extension GMAC0 GMII Receive Data Error.
Indicates that the received data contains errors. The switch filters
the received packets once G0_RXER is asserted at the rising edge
of G0_RXC. Valid both in 1000Mbps GMII mode and 10/100Mbps
MII MAC mode.
G0_TXER 120 I/OPU - G0_TXER Extension GMAC0 GMII Transmit Data Error Output.
Indicates that the transmitted data contains errors.
G0_TXCLK 121 I/OPU - G0_TXCLK 2.5/25MHz Transmit Clock Input when the Extension
GMAC0 GMII interface operates in 10/100 MII mode.
2.5/25MHz clock driven by PHY when operating in 10/100Mbps
MII mode. Used to synchronize G0_TX[3:0], G0_TXEN, and
G0_TXER.
G0_GTXC 122 O - G0_GTXC Extension GMAC0 GMII Transmit Clock Output.
125MHz transmit clock output when GMII is operating at 1Gbps.
Used to synchronize G0_TXD[7:0], G0_TXEN, and G0_TXER.
RTL8370(M)
Datasheet

RTL8370M (mA)
G0_TXEN/ 123 O - G0_TXEN Extension GMAC0 GMII Transmit Data Enable Output.
RESERVED Transmit enable that is sent synchronously at the rising edge of
G0_GTXC in GMII mode.
Transmit enable that is sent synchronously at the rising edge of
G0_TXCLK in 10/100Mbps MII mode.
This pin must be pulled high with a 4.7K ohm resistor when in
normal operation.
G0_TXD [7:0] Extension GMAC0 GMII Transmit Data Output.
In 1000Mbps GMII mode, G0_TXD [7:0] transmitted data is sent
synchronously at the rising edge of G0_GTXC.
In 10/100Mbps MII mode, only G0_TXCLK [3:0] are available for
transmitting and receiving data at the rising edge of G0_TXCLK.
G0_TXD0/ 124 I/OPU - G0_TXD0/EN_FLASH:
EN_FLASH Pull Up: Enable FLASH interface
Pull Down: Disable FLASH interface
G0_TXD1/ 125 I/OPU G0_TXD1/DIS_8051:
DIS_8051 Pulled High: Disable embedded 8051 upon power on or reset.
Pulled Low: Enable embedded 8051 upon power on or reset.
G0_TXD2/ 126 I/OPU G0_TXD2/DISAUTOLOAD:
DISAUTOLOAD Pulled High: Disable auto load EEPROM upon power on or reset.
Pulled Low: Enable auto load EEPROM when power on/reset.
G0_TXD3/ 127 I/OPU G0_TXD3/RESERVED:
RESERVED This pin must be pulled high with a 4.7K ohm resistor when in
normal operation.
RESERVED These pins must be pulled high with a 4.7K ohm resistor when in
normal operation.
RESERVED These pins must be pulled high with a 4.7K ohm resistor when in
normal operation.
G0_TXD6 130 I/OPU G0_TXD6/RESERVED:
RESERVED Reserved.
G0_TXD7/EN_PHY:
G0_TXD7/ 131 I/OPU Pulled High: Enables embedded PHY upon power on or reset.
EN_PHY Pulled Low: Disables embedded PHY upon power on or reset.
RTL8370(M)
Datasheet
Table 12. Extension GMAC1 GMII Pins (RTL8370M) (TQFP176)

RTL8370M (mA)
G1_CRS 77 I - G1_CRS Carrier Sense Input when the Extension GMAC1 GMII
G1_CRS is only valid in 10/100Mbps MII half duplex mode. It is
asserted high when a valid carrier is detected on the media.
G1_COL 78 I - G1_COL Collision Detect Input when the Extension GMAC1 GMII
G1_COL is only valid in 10/100Mbps MII half duplex mode. It is
asserted high when a collision is detected on the media.
G1_TXD7 79 I/OPU - G1_TXD [7:0] Extension GMAC1 GMII Transmit Data Output.
G1_TXD6 80 I/OPU In 1000Mbps GMII mode, G1_TXD [7:0] transmitted data is sent
G1_TXD5 81 I/OPU synchronously at the rising edge of G1_GTXC.
G1_TXD4 82 I/OPU In 10/100Mbps MII mode, only G1_TXCLK [3:0] are available for
G1_TXD3 83 O transmitting and receiving data at the rising edge of G1_TXCLK.
G1_TXD2 84 O
G1_TXD1 85 O
G1_TXD0 86 O
G1_TXEN 87 O - G1_TXEN Extension GMAC1 GMII Transmit Data Enable Output.
G1_GTXC in GMII mode.
G1_TXCLK in 10/100Mbps MII mode.
G1_GTXC 89 O - G1_GTXC Extension GMAC1 GMII Transmit Clock Output.
125MHz transmit clock output when GMII is operating at 1Gbps.
Used to synchronize G1_TXD[7:0], G1_TXEN, and G1_TXER.
G1_TXCLK 90 IPU - G1_TXCLK 2.5/25MHz Transmit Clock Input when the Extension
GMAC1 GMII interface operates in 10/100 MII mode.
2.5/25MHz clock driven by PHY when operating in 10/100Mbps
MII mode. Used to synchronize G1_TX[3:0], G1_TXEN, and
G1_TXER.
G1_TXER/ 91 I/OPU - G1_TXER Extension GMAC1 GMII Transmit Data Error Output.
RESERVED Indicates that the transmitted data contains errors.
G1_RXER 92 I - G1_RXER Extension GMAC1 GMII Receive Data Error.
Indicates that the received data contains errors. The switch filters
the received packets once G1_RXER is asserted at the rising edge
of G1_RXC. Valid both in 1000Mbps GMII mode and 10/100Mbps
MII MAC mode.
G1_RXC 93 I - G1_RXC Extension GMAC1 GMII Receive Clock Input.
In GMII mode: 125MHz receive clock. Used to synchronize
G1_RXD[7:0], G1_RXER, and G1_RXDV.
In MII 10/100Mbps mode: G1_RXC is 2.5/25MHz. Used to
synchronize G1_RXD[3:0], G1_RXER, G1_RXDV, G1_CRS, and
G1_COL.
RTL8370(M)
Datasheet

RTL8370M (mA)
G1_RXDV 94 I - G1_RXDV Extension GMAC1 GMII Receive Data Valid Input.
Receive Data Valid is received synchronously at the rising edge of
G1_RXC in both 1Gbps GMII and 10/100Mbps MII MAC mode.
G1_RXD0 95 I - G1_RXD[7:0] Extension GMAC1 GMII Receive Data Input.
G1_RXD1 96 I Received data is received synchronously at the rising edge of
G1_RXD2 97 I G1_RXC.
G1_RXD3 98 I In 10/100Mbps MII mode, only G1_RXD[3:0] are available.
G1_RXD4 99 IPU These pins must be pulled low with a 1K ohm resistor when not
G1_RXD5 100 IPU used.
G1_RXD6 101 IPU
G1_RXD7 102 IPU
8.2.2. RGMII Pins (RTL8370M)

The Extension GMAC0 and Extension GMAC1 of the RTL8370M support two RGMII interfaces to
connect with an external MAC or PHY device when register configuration is set to RGMII mode
interface.
Table 13. Extension GMAC0 RGMII Pins (RTL8370M) (TQFP176))
RTL8370M (mA)
RG0_RXD3 113 I - RG0_RXD[3:0] Extension GMAC0 RGMII Receive Data Input.
RG0_RXD2 114 Received data is received synchronously by RG0_RXCLK.
RG0_RXD1 115 These pins must be pulled low with a 1K ohm resistor when not
RG0_RXD0 116 used.
RG0_RXCTL 117 I - RG0_RXCTL Extension GMAC0 RGMII Receive Control signal
input.
The RG0_RXCTL indicates RX_DV at the rising of RG0_RXCLK
and RX_ER at the falling edge of RG0_RXCLK.
At RG0_RXCLK falling edge, RG0_RXCTL= RX_DV (XOR)
RX_ER.
RG0_RXCLK 118 I - RG0_RXCLK Extension GMAC0 RGMII Receive Clock Input.
RG0_RXCLK is 125MHz @ 1Gbps, 25MHz @ 100Mbps, and
2.5MHz @ 10Mbps.
Used for RG0_RXD[3:0] and RG0_RXCTL synchronization at both
RG0_RXCLK rising and falling edges.
RG0_TXCLK 122 O - RG0_TXCLK Extension GMAC0 RGMII Transmit Clock Output.
RG0_TXCLK is 125MHz @ 1Gbps, 25MHz @ 100Mbps, and
2.5MHz @ 10Mbps.
Used for RG0_TXD[3:0] and RG0_TXCTL synchronization at
RG0_TXCLK on both rising and falling edges.
RTL8370(M)
Datasheet

RTL8370M (mA)
RG0_TXCTL/ 123 O - RG0_TXCTL Extension GMAC0 RGMII Transmit Control signal
RESERVED Output.
The RG0_TXCTL indicates TX_EN at the rising edge of
RG0_TXCLK, and TX_ER at the falling edge of RG0_TXCLK.
At the RG0_TXCLK falling edge, RG0_TXCTL= TX_EN (XOR)
TX_ER.
normal operation.
RG0_TXD[3:0] Extension GMAC0 RGMII Transmit Data Output.
Transmitted data is sent synchronously to RG0_TXCLK.
RG0_TXD0/ 124 I/OPU - RG0_TXD0/EN_FLASH:
EN_FLASH Pull Up: Enable FLASH interface
Pull Down: Disable FLASH interface
RG0_TXD1/ 125 I/OPU RG0_TXD1/DIS_8051:
DIS_8051 Pulled High: Disable embedded 8051 upon power on or reset.
Pulled Low: Enable embedded 8051 upon power on or reset.
RG0_TXD2/ 126 I/OPU RG0_TXD2/DISAUTOLOAD:
DISAUTOLOAD Pulled High: Disable auto load EEPROM upon power on or reset.
Pulled Low: Enable auto load EEPROM upon power on or reset.
RG0_TXD3/ 127 I/OPU RG0_TXD3/RESERVED:
RESERVED This pin must be pulled high with a 4.7K ohm resistor when in
normal operation.
RTL8370(M)
Datasheet
Table 14. Extension GMAC1 RGMII Pins (RTL8370M) (TQFP176)

RTL8370M (mA)
RG1_TXD3 83 O - RG1_TXD[3:0] Extension GMAC1 RGMII Transmit Data Output.
RG1_TXD2 84 Transmitted data is sent synchronously to RG1_TXCLK.
RG1_TXD1 85
RG1_TXD0 86
RG1_TXCTL 87 O - RG1_TXCTL Extension GMAC1 RGMII Transmit Control signal
Output.
The RG1_TXCTL indicates TX_EN at the rising edge of
RG1_TXCLK, and TX_ER at the falling edge of RG1_TXCLK.
At the RG1_TXCLK falling edge, RG1_TXCTL= TX_EN (XOR)
TX_ER.
RG1_TXCLK 89 O - RG1_TXCLK Extension GMAC1 RGMII Transmit Clock Output.
RG1_TXCLK is 125MHz @ 1Gbps, 25MHz @ 100Mbps, and
2.5MHz @ 10Mbps.
Used for RG1_TXD[3:0] and RG1_TXCTL synchronization at
RG1_TXCLK on both rising and falling edges.
RG1_RXCLK 93 I - RG1_RXCLK Extension GMAC1 RGMII Receive Clock Input.
RG1_RXCLK is 125MHz @ 1Gbps, 25MHz @ 100Mbps, and
2.5MHz @ 10Mbps.
Used for RG1_RXD[3:0] and RG1_RXCTL synchronization at both
RG1_RXCLK rising and falling edges.
RG1_RXCTL 94 I - RG1_RXCTL Extension GMAC1 RGMII Receive Control signal
input.
The RG1_RXCTL indicates RX_DV at the rising of RG1_RXCLK
and RX_ER at the falling edge of RG1_RXCLK.
At RG1_RXCLK falling edge, RG1_RXCTL= RX_DV (XOR)
RX_ER.
RG1_RXD0 95 I - RG1_RXD[3:0] Extension GMAC1 RGMII Receive Data Input.
RG1_RXD1 96 Received data is received synchronously by RG1_RXCLK.
RG1_RXD2 97 These pins must be pulled low with a 1K ohm resistor when not
RG1_RXD3 98 used.
RTL8370(M)
Datasheet
8.2.3. MII Pins (RTL8370M)

The Extension GMAC0 and Extension GMAC1 of the RTL8370M also support two MII interfaces to
connect with an external MAC or PHY device when register configuration is set to MII mode interface.
These two MII interfaces also can be configured as MII MAC mode or MII PHY mode by register.
Table 15. Extension GMAC0 MII Pins (MII MAC Mode or MII PHY Mode) of the RTL8370M (TQFP176)
RTL8370M (mA)
M0M_CRS/ 107 I/OPU - M0M_CRS Extension GMAC0 MII MAC Mode Carrier Sense
M0P_CRS Input when operating in 10/100 MII half duplex mode.
M0P_CRS Extension GMAC0 MII MAC Mode Carrier Sense
Output when operating in 10/100 MII half duplex mode.
M0M_COL/ 108 I/OPU - M0M_COL Extension GMAC0 MII MAC Mode Collision Detect
M0P_COL Input when operating in 10/100 MII half duplex mode.
M0P_COL Extension GMAC0 MII MAC Mode Collision Detect
M0M_RXD3/ 113 I - M0M_RXD[3:0] Extension GMAC0 MII MAC Mode Receive Data
M0P_TXD3 Input.
M0M_RXD2/ 114 Received data that is received synchronously at the rising edge of
M0P_TXD2 M0M_RXCLK.
M0M_RXD1/ 115 M0P_TXD[3:0] Extension GMAC0 MII PHY Mode Transmit Data
M0P_TXD1 Input.
M0M_RXD0/ 116 Transmitted data is received synchronously at the rising edge of
M0P_TXD0 M0P_TXCLK.
These pins must be pulled low with a 1K ohm resistor when not
used.
M0M_RXDV/ 117 I - M0M_RXDV Extension GMAC0 MII MAC Mode Receive Data
M0P_TXEN Valid Input.
Receive Data Valid sent synchronously at the rising edge of
M0M_RXCLK.
M0P_TXEN Extension GMAC0 MII PHY Mode Transmit Data
Enable Input.
Transmit Data Enable is received synchronously at the rising edge
of M0P_TXCLK.
M0M_RXCLK/ 118 I/O - M0M_RXCLK Extension GMAC0 MII MAC Mode Receive Clock
M0P_TXCLK Input.
In MII 100Mbps, M0M_RXCLK is 25MHz Clock Input.
In MII 10Mbps, M0M_RXCLK is 2.5MHz Clock Input.
Used to synchronize M0M_RXD[3:0], and M0M_RXDV.
M0P_TXCLK GMAC0 MII PHY Mode Transmit Clock Output.
In MII 100Mbps, M0P_TXCLK is 25MHz Clock Output.
In MII 10Mbps, M0P_TXCLK is 2.5MHz Clock Output.
Used to synchronize M0P_TXD[3:0], and M0P_TXEN.
RTL8370(M)
Datasheet

RTL8370M (mA)
M0M_TXCLK/ 122 I/O - M0M_TXCLK Extension GMAC0 MII MAC Mode Transmit
M0P_RXCLK Clock Input.
In MII 100Mbps, M0M_TXCLK is 25MHz Clock Input.
In MII 10Mbps, M0M_TXCLK is 2.5MHz Clock Input.
Used to synchronize M0M_TXD[3:0], and M0M_TXEN.
M0P_RXCLK Extension GMAC0 MII PHY Mode Receive Clock
Output.
In MII 100Mbps, M0P_RXCLK is 25MHz Clock Output.
In MII 10Mbps, M0P_RXCLK is 2.5MHz Clock Output.
Used to synchronize M0P_RXD[3:0], and M0P_RXDV.
M0M_TXEN/ 123 O - M0M_TXEN Extension GMAC0 MII MAC Mode Transmit Data
M0P_RXDV/ Enable Output.
RESERVED Transmit enable that is sent synchronously at the rising edge of
M0M_TXCLK.
M0P_RXDV Extension GMAC0 MII PHY Mode Receive Data
Valid Output.
Receive Data Valid signal that is sent synchronously at the rising
edge of M0P_RXCLK.
normal operation.
M0M_TXD[3:0] Extension GMAC0 MII MAC Mode Transmit
Data Output.
Transmitted data is sent synchronously at the rising edge of
M0M_TXCLK.
M0P_RXD[3:0] Extension GMAC0 MII PHY Mode Receive Data
Output.
Received data is received synchronously at the rising edge of
M0P_RXCLK.
M0M_TXD0/ 124 I/OPU - M0M_TXD0/M0P_RXD0/EN_FLASH:
M0P_RXD0/ Pull Up: Enable FLASH interface
EN_FLASH Pull Down: Disable FLASH interface
M0M_TXD1/ 125 I/OPU M0M_TXD1/M0P_RXD1/DIS_8051:

M0P_RXD1/ Pulled High: Disable embedded 8051 upon power on or reset.
DIS_8051 Pulled Low: Enable embedded 8051 upon power on or reset.
M0M_TXD2/ 126 I/OPU M0M_TXD2/M0P_RXD2/DISAUTOLOAD:

M0P_RXD2/ Pulled High: Disable auto load EEPROM upon power on or reset.
DISAUTOLOAD Pulled Low: Enable auto load EEPROM upon power on or reset.
M0M_TXD3/ 127 I/OPU M0M_TXD3/M0P_RXD3/RESERVED:

M0P_RXD3/ This pin must be pulled high with a 4.7K ohm resistor when in
RESERVED normal operation.
RTL8370(M)
Datasheet
Table 16. Extension GMAC1 MII Pins (MII MAC Mode or MII PHY Mode) of the RTL8370M (TQFP176)
RTL8370M (mA)
M1M_CRS/ 77 I/O - M1M_CRS Extension GMAC1 MII MAC Mode Carrier Sense
M1P_CRS Input when operating in 10/100 MII half duplex mode.
M1P_CRS Extension GMAC1 MII MAC Mode Carrier Sense
M1M_COL/ 78 I/O - M1M_COL Extension GMAC1 MII MAC Mode Collision Detect
M1P_COL Input when operating in 10/100 MII half duplex mode.
M1P_COL Extension GMAC1 MII MAC Mode Collision Detect
M1M_TXD3/ 83 O - M1M_TXD[3:0] Extension GMAC1 MII MAC Mode Transmit
M1P_RXD3 Data Output.
M1M_TXD2/ 84 Transmitted data is sent synchronously at the rising edge of
M1P_RXD2 M1M_TXCLK.
M1M_TXD1/ 85 M1P_RXD[3:0] Extension GMAC1 MII PHY Mode Receive Data
M1P_RXD1 Output.
M1M_TXD0/ 86 Received data is received synchronously at the rising edge of
M1P_RXD0 M1P_RXCLK.
M1M_TXEN/ 87 O - M1M_TXEN Extension GMAC1 MII MAC Mode Transmit Data
M1P_RXDV Enable Output.
M1M_TXCLK.
M1P_RXDV Extension GMAC1 MII PHY Mode Receive Data
Valid Output.
Receive Data Valid signal that is sent synchronously at the rising
edge of M1P_RXCLK.
M1M_TXCLK/ 89 I/O - M1M_TXCLK Extension GMAC1 MII MAC Mode Transmit
M1P_RXCLK Clock Input.
In MII 100Mbps, M1M_TXCLK is 25MHz Clock Input.
In MII 10Mbps, M1M_TXCLK is 2.5MHz Clock Input.
Used to synchronize M1M_TXD[3:0], M1M_TXEN, and
M1M_TXER.
M1P_RXCLK Extension GMAC1 MII PHY Mode Receive Clock
Output.
In MII 100Mbps, M1P_RXCLK is 25MHz Clock Output.
In MII 10Mbps, M1P_RXCLK is 2.5MHz Clock Output.
Used to synchronize M1P_RXD[3:0], M1P_RXDV, M1P_RXER,
M1P_CRS, and M1P_COL.
M1M_TXER/ 91 I/OPU - M1M_TXER Extension GMAC1 MII MAC Mode Transmit Data
M1P_RXER/ Error Output.
RESERVED Transmit Error that is sent synchronously at the rising edge of
M1M_TXCLK.
M1P_RXER Extension GMAC1 MII PHY Mode Receive Error
Output.
Receive Error signal that is sent synchronously at the rising edge of
M1P_RXCLK.
RTL8370(M)
Datasheet

RTL8370M (mA)
M1M_RXER/ 92 I - M1M_RXER Extension GMAC1 MII MAC Mode Transmit Data
M1P_TXER Error Input.
Receive Error that is received synchronously at the rising edge of
M1M_TXCLK.
M1P_TXER Extension GMAC1 MII PHY Mode Receive Error
Input.
Transmit Error signal that is received synchronously at the rising
edge of M1P_RXCLK.
M1M_RXCLK/ 93 I/O - M1M_RXCLK Extension GMAC1 MII MAC Mode Receive Clock
M1P_TXCLK Input.
In MII 100Mbps, M1M_RXCLK is 25MHz Clock Input.
In MII 10Mbps, M1M_RXCLK is 2.5MHz Clock Input.
Used to synchronize M1M_RXD[3:0], M1M_RXDV, M1M_TXER,
M1P_CRS, and M1P_COL.
M1P_TXCLK GMAC1 MII PHY Mode Transmit Clock Output.
In MII 100Mbps, M1P_TXCLK is 25MHz Clock Output.
In MII 10Mbps, M1P_TXCLK is 2.5MHz Clock Output.
Used to synchronize M1P_TXD[3:0], M1P_TXEN, and
M1P_TXER.
M1M_RXDV/ 94 I - M1M_RXDV Extension GMAC1 MII MAC Mode Receive Data
M1P_TXEN Valid Input.
Receive Data Valid sent synchronously at the rising edge of
M1M_RXCLK.
M1P_TXEN Extension GMAC1 MII PHY Mode Transmit Data
Enable Input.
Transmit Data Enable is received synchronously at the rising edge
of M1P_TXCLK.
M1M_RXD0/ 95 I - M1M_RXD[3:0] Extension GMAC1 MII MAC Mode Receive Data
M1P_TXD0 Input.
M1M_RXD1/ 96 Received data that is received synchronously at the rising edge of
M1P_TXD1 M1M_RXCLK.
M1M_RXD2/ 97 M1P_TXD[3:0] Extension GMAC1 MII PHY Mode Transmit Data
M1P_TXD2 Input.
M1M_RXD3/ 98 Transmitted data is received synchronously at the rising edge of
M1P_TXD3 M1P_TXCLK.
These pins must be pulled low with a 1K ohm resistor when not
used.
RTL8370(M)
Datasheet
8.2.4. LED Pins (RTL8370M)

The General Purpose Interface can be configured to parallel mode LED, scan mode LED, or serial mode
LED interface via Register configuration. When the LED is configured as parallel mode LED, dual
RGMII or dual MII interfaces are also supported, however the GMII interface is not supported. When the
LED is configured to scan mode LED, dual RGMII, dual MII, or extension port 1 GMII interface are also
supported, however extension port 0 GMII interface is not supported. When the LED is configured to
serial mode LED, all extension port interfaces are supported. LED0, LED1, and LED2 of Port n indicate
information that can be defined via register or EEPROM.
In parallel mode LED interface, when the LED pin is pulled low, the LED output polarity will be high
active. When the LED pin is pulled high, the LED output polarity will change from high active to low
active. See section 10.19 LED Indicator, page 57 for more details.
Table 17. Parallel Mode LED Pins (RTL8370M) (TQFP176)
RTL8370M (mA)
P7LED2/G1_TXD7 79 I/OPU - Port 7 LED2 Output Signal.
/SPI_CLK P7LED2 indicates information is defined by register or EEPROM.
/SPI_D1 P7LED1 indicates information is defined by register or EEPROM.
/SPI_D0 P7LED0 indicates information is defined by register or EEPROM.
/SPI_CS P6LED2 indicates information is defined by register or EEPROM.
P6LED1/G1_RXD4 99 I/OPU - Port 6 LED1 Output Signal.
G1_TXCLK/GPIO1 P6LED0 indicates information is defined by register or EEPROM.
/GPIO0 P5LED2 indicates information is defined by register or EEPROM.
P4LED2/G0_CRS/ 107 I/OPU - Port 4 LED2 Output Signal.
M0M_CRS/ P4LED2 indicates information is defined by register or EEPROM.
M0P_CRS/
SLED_P7B/GPIO3
/SLED_P5B P4LED1 indicates information is defined by register or EEPROM.
P4LED0/G0_COL/ 108 I/OPU - Port 4 LED0 Output Signal.
M0M_COL/ P4LED0 indicates information is defined by register or EEPROM.
M0P_COL/
SLED_P6B
/SLED_G1A P3LED1 indicates information is defined by register or EEPROM.
RTL8370(M)
Datasheet

RTL8370M (mA)
P2LED2/G0_RXER 119 I/OPU - Port 2 LED2 Output Signal.
/SLED_P1B/GPIO7 P2LED2 indicates information is defined by register or EEPROM.
/G0_TXCLK P2LED1 indicates information is defined by register or EEPROM.
/SLED_G1B
P2LED0/G0_TXER 120 I/OPU - Port 2 LED0 Output Signal.
/EEPROM_MOD
/SLED_P3_7A P1LED2 indicates information is defined by register or EEPROM.
/RESERVED
/SLED_P1_5A P1LED1 indicates information is defined by register or EEPROM.
/SLED_P2_6A/ P1LED0 indicates information is defined by register or EEPROM.
/RESERVED
/EN_PHY P0LED2 indicates information is defined by register or EEPROM.
/SLED_P0_4A
/GPIO2
P0LED1/LED_DA/ 134 I/OPU - Port 0 LED1 Output Signal.
SLED_G2A P0LED1 indicates information is defined by register or EEPROM.
P0LED0/LED_CK 135 I/OPU - Port 0 LED0 Output Signal.
/SMI_SEL
Note: See section 10.19 LED Indicator, page 57 for more details.
RTL8370(M)
Datasheet
Table 18. Scan Mode LED Pins (RTL8370M) (TQFP176)

RTL8370M (mA)
SLED_G1A/ 110 I/OPU - Scan Mode LED Group A G1A Output Signal.
G0_RXD6/P3LED1
SLED_G2A/LED_DA 134 I/OPU - Scan Mode LED Group A G2A Output Signal.
/P0LED1
G0_TXD7/P0LED2/
EN_PHY/GPIO2
SLED_P1_5A/ 130 I/OPU - Scan Mode Group A LED P1_5A Output Signal.
G0_TXD6/P1LED1
G0_TXD5/P1LED0/
RESERVED
G0_TXD4/P1LED/
RESERVED
SLED_G1B/ 121 I/OPU - Scan Mode LED Group B G1B Output Signal.
G0_TXCLK/P2LED1
SLED_P0B/ 120 I/OPU - Scan Mode LED Group B P0B Output Signal.
G0_TXER/P2LED0/
EEPROM_MOD
G0_RXER/P2LED2/
GPIO7
G0_RXD4/P3LED0
G0_RXD5/P3LED2
SLED_P4B/LED_CK/ 135 I/OPU - Scan Mode LED Group B P4B Output Signal.
P0LED0/SMI_SEL
G0_RXD7/P4LED1
SLED_P6B/G0_COL/ 108 I/OPU - Scan Mode LED Group B P6B Output Signal.
M0M_COL/
M0P_COL/P4LED0
SLED_P7B/G0_CRS/ 107 I/OPU - Scan Mode LED Group B P7B Output Signal.
M0M_CRS/M0P_CRS
/P4LED2/GPIO3
Note: See section 10.19.2 Scan LED Mode, page 58 for details.
RTL8370(M)
Datasheet
8.3. Configuration Strapping Pins (RTL8370M)

Table 19. Configuration Strapping Pins (RTL8370M) (TQFP176)
RTL8370M
RESERVED/G1_TXER/ 91 I/OPU Internal Use/Reserved.
M1M_TXER/M1P_RXER Note: This pin must be pulled low via an external 4.7k ohm resistor
upon power on or reset for normal operation.
EEPROM_MOD/ 120 I/OPU EEPROM mode selection.
G0_TXER/P2LED0/ Pull Up: EEPROM 24Cxx Size great than 16Kbits (24C32~)
SLED_P0B Pull Down: EEPROM 24Cxx Size less or equal than 16Kbit
(24C02~24C16).
RESERVED/G0_TXEN/ 123 I/O Internal Use/Reserved.
RG0_TXCTL/ Note: This pin must be kept floating, or pulled high via an external
M0M_TXEN/M0P_RXDV 4.7k ohm resistor upon power on or reset.
EN_FLASH/G0_TXD0/ 124 I/OPU Enable FLASH Interface.
RG0_TXD0/M0M_TXD0/ Pull Up: Enable FLASH interface
M0P_RXD0 Pull Down: Disable FLASH interface
Note1: The strapping pin DISAUTOLOAD, DIS_8051, and
EN_FLASH are for power on or reset initial stage configuration.
Refer to Table 20 Configuration Strapping Pins (DISAUTOLOAD,
DIS_8051, and EN_FLASH) (RTL8370M), page 39 for details.
DIS_8051/G0_TXD1/ 125 I/OPU Disable Embedded 8051.
RG0_TXD1/M0M_TXD1/ Pull Up: Disable embedded 8051
M0P_RXD1 Pull Down: Enable embedded 8051
DISAUTOLOAD/ 126 I/OPU Disable EEPROM Autoload.
G0_TXD2/RG0_TXD2/ Pull Up: Disable EEPROM autoload
M0M_TXD2/M0P_RXD2 Pull Down: Enable EEPROM autoload
RTL8370(M)
Datasheet

RTL8370M
RESERVED/G0_TXD3/ 127 I/OPU Internal Use/Reserved.
RG0_TXD3/M0M_TXD3/ Note: This pin must be kept floating, or pulled high via an external
M0P_RXD3 4.7k ohm resistor upon power on or reset.
RESERVED 27 IPU Internal Use/Reserved.
P1LED2/SLED_P3_7A Note: This pin must be kept floating, or pulled high via an external
P1LED0/SLED_P2_6A Note: This pin must be kept floating, or pulled high via an external
EN_PHY/G0_TXD7/ 131 I/OPU Enable Embedded PHY.
P0LED2/SLED_P0_4A/ Pull Up: Enable embedded PHY
GPIO2 Pull Down: Disable embedded PHY
SMI_SEL/LED_CK/ 135 I/OPU EEPROM SMI/MII Management Interface Selection.
P0LED0/SLED_P4B Pull Up: EEPROM SMI interface
Pull Down: MII Management Interface
BUZZER/DIS_LPD 25 I/OPU Realtek Loop Detection Configuration.
Pull Up: Disable Loop detection function
Pull Down: Enable Loop detection function
external 4.7k ohm resistor upon power on or reset. 2KHz signal out
when looping is detected.
Table 20. Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_FLASH) (RTL8370M)
DISAUTOLOAD DIS_8051 EN_FLASH Initial Stage (Power On or Reset) Loading Data
From To
0 EEPROM Embedded 8051 Instruction Memory
0
0 1 FLASH Embedded 8051 Instruction Memory
1 0 EEPROM Register
1 Irrelevant Irrelevant Do Nothing Do Nothing
RTL8370(M)
Datasheet
8.4. Miscellaneous Pins (RTL8370M)

Table 21. Miscellaneous Pins (RTL8370M) (TQFP176)
RTL8370M
XTALI 139 AI 25MHz Crystal Clock Input and Feedback Pin.
25MHz +/-50ppm tolerance crystal reference or oscillator input.
XTALO 138 AO 25MHz Crystal Clock Output Pin.
25MHz +/-50ppm tolerance crystal output.
MDIREF 16 AO Reference Resistor.
A 2.49K ohm (1%) resistor must be connected between MDIREF and
GND.
RESERVED 13 AI This pin must be pulled low via a 1k ohm resister when in normal
operation.
SCK/MMD_MDC 142 I/O EEPROM SMI Interface Clock/MII Management Interface Clock
SDA/MMD_MDIO 143 I/O EEPROM SMI Interface Data/MII Management Interface Data
INTERRUPT 24 O Interrupt Output for External CPU.
nRESET 141 IS System Reset Input Pin.
When low active will reset the RTL8370M.
G1_TXD7/SPI_CLK/ 79 I/OPU Serial Clock (FLASH Interface).
P7LED2
G1_TXD6/SPI_D0/ 80 I/OPU Serial Data 0 (FLASH Interface).
P7LED0
G1_TXD5/SPI_D1/ 81 I/OPU Serial Data 1 (FLASH Interface).
P7LED1
G1_TXD4/SPI_CS/ 82 I/OPU Chip Selection (FLASH Interface).
P6LED2
G1_RXD5/P5LED2/ 100 I/OPU General Purpose Input/Output Interfaces IO0.
GPIO0
G1_TXCLK/P6LED0/ 90 I/OPU General Purpose Input/Output Interfaces IO1.
GPIO1
G0_TXD7/P0LED2/ 131 I/OPU General Purpose Input/Output Interfaces IO2.
SLED_P0_4A/EN_PHY/
GPIO2
G0_CRS/M0M_CRS/ 107 I/OPU General Purpose Input/Output Interfaces IO3.
M0P_CRS/P4LED2/
GPIO3
G0_TXD3/RG0_TXD3/ 127 I/OPU General Purpose Input/Output Interfaces IO4.
M0M_TXD3/
M0P_RXD3/RESERVED
/GPIO4
G0_GTXC/RG0_TXCLK 122 I/O General Purpose Input/Output Interfaces IO5.
/M0M_TXCLK/
M0P_RXCLK/GPIO5
RTL8370(M)
Datasheet

RTL8370M
G0_RXDV/RG0_RXCTL 117 I/O General Purpose Input/Output Interfaces IO6.
/M0M_RXDV/
M0P_TXEN/GPIO6
G0_RXER/P2LED2/ 119 I/OPU General Purpose Input/Output Interfaces IO7.
GPIO7
8.5. Test Pins (RTL8370M)

Table 22. Test Pins (RTL8370M) (TQFP176)
RTL8370M
RTT1 18 AO Reserved for Internal Use. Must be left floating.
RTT2 19 AO Reserved for Internal Use. Must be left floating.
ATESTCK0 165 AO Reserved for Internal Use. Must be left floating.
8.6. Power and GND Pins (RTL8370M)

Table 23. Power and GND Pins (RTL8370M) (TQFP176)
RTL8370M
DVDDIO_0 105, 132 P Digital I/O High Voltage Power for Extension Port 0 General Purpose
Interfaces.
DVDDIO_1 88, 104 P Digital I/O High Voltage Power for Extension Port 1 General Purpose
Interfaces.
DVDDIO 21, 140 P Digital I/O High Voltage Power for INTERRUPT, SMI, nRESET
DVDDL 22, 26, 29, 30, P Digital Low Voltage Power.
103, 106, 133, 136
AVDDH 1, 11, 20, 32, 42, AP Analog High Voltage Power.
54, 64, 74, 137,
144, 154, 167
AVDDL 6, 17, 37, 47, 59, AP Analog Low Voltage Power.
69, 149, 159, 172
GND 12, 23, 28, 31, G GND.
EPAD
AGND 15 AG Analog GND.
PLLGND0 166 AG PLL0 GND.
PLLGND1 53 AG PLL1 GND.
RTL8370(M)
Datasheet
9. Physical Layer Functional Overview

9.1. MDI Interface
The RTL8370(M) embeds eight Gigabit Ethernet PHYs in one chip. Each port uses a single common
MDI interface to support 1000Base-T, 100Base-Tx, and 10Base-T. This interface consists of four signal
pairs-A, B, C, and D. Each signal pair consists of two bi-directional pins that can transmit and receive at
the same time. The MDI interface has internal termination resistors, and therefore reduces BOM cost and
PCB complexity. For 1000Base-T, all four pairs are used in both directions at the same time. For 10/100
links and during auto-negotiation, only pairs A and B are used.
9.2. 1000Base-T Transmit Function

The 1000Base-TX transmit function performs 8B/10B coding, scrambling, and 4D-PAM5 encoding.
These code groups are passed through a waveform-shaping filter to minimize EMI effects, and are
transmitted onto 4-pair CAT5 cable at 125MBaud/s through a D/A converter.
9.3. 1000Base-T Receive Function

Input signals from the media pass through the sophisticated on-chip hybrid circuit to subtract the
transmitted signal from the input signal for effective reduction of near-end echo. The received signal is
then processed with state-of-the-art technology, e.g., adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. The 8-bit-wide data is recovered and is sent to the GMII interface at a clock speed of 125MHz.
The RX MAC retrieves the packet data from the internal receive MII/GMII interface and sends it to the
packet buffer manager.
9.4. 100Base-TX Transmit Function

The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling,
NRZ/NRZI conversion, and MLT-3 encoding. The 5-bit serial data stream after 4B/5B coding is then
scrambled as defined by the TP-PMD Stream Cipher function to flatten the power spectrum energy such
that EMI effects can be reduced significantly.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit
stream is driven onto the network media in the form of MLT-3 signaling. The MLT-3 multi-level
signaling technology moves the power spectrum energy from high frequency to low frequency, which
also reduces EMI emissions.
RTL8370(M)
Datasheet
9.5. 100Base-TX Receive Function

The receive path includes a receiver composed of an adaptive equalizer and DC restoration circuits (to
compensate for an incoming distorted MLT-3 signal), an MLT-3 to NRZI and NRZI to NRZ converter to
convert analog signals to digital bit-stream, and a PLL circuit to clock data bits with minimum bit error
rate. A de-scrambler, 5B/4B decoder, and serial-to-parallel conversion circuits are followed by the PLL
circuit. Finally, the converted parallel data is fed into the MAC.
9.6. 10Base-T Transmit Function

The output 10Base-T waveform is Manchester-encoded before it is driven onto the network media. The
internal filter shapes the driven signals to reduce EMI emissions, eliminating the need for an external
filter.
9.7. 10Base-T Receive Function

The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit
detects the signal level is above squelch level.
9.8. Auto-Negotiation for UTP

The RTL8370(M) obtains the states of duplex, speed, and flow control ability for each port in UTP mode
through the auto-negotiation mechanism defined in the IEEE 802.3 specifications. During auto-
negotiation, each port advertises its ability to its link partner and compares its ability with advertisements
received from its link partner. By default, the RTL8370(M) advertises full capabilities (1000Full,
100Full, 100Half, 10Full, 10Half) together with flow control ability.
RTL8370(M)
Datasheet
9.9. Crossover Detection and Auto Correction

The RTL8370(M) automatically determines whether or not it needs to crossover between pairs (see
Table 24) so that an external crossover cable is not required. When connecting to another device that does
not perform MDI crossover, when necessary, the RTL8370(M) automatically switches its pin pairs to
communicate with the remote device. When connecting to another device that does have MDI crossover
capability, an algorithm determines which end performs the crossover function.
The crossover detection and auto correction function can be disabled via register configuration. The pin
mapping in MDI and MDI Crossover mode is given below.
Table 24. Media Dependent Interface Pin Mapping
Pairs MDI MDI Crossover
1000Base-T 100Base-TX 10Base-T 1000Base-T 100Base-TX 10Base-T
A A TX TX B RX RX
B B RX RX A TX TX
C C Unused Unused D Unused Unused
D D Unused Unused C Unused Unused
9.10. Polarity Correction

The RTL8370(M) automatically corrects polarity errors on the receiver pairs in 1000Base-T and 10Base-
T modes. In 100Base-TX mode, the polarity is irrelevant.
In 1000Base-T mode, receive polarity errors are automatically corrected based on the sequence of idle
symbols. Once the de-scrambler is locked, the polarity is also locked on all pairs. The polarity becomes
unlocked only when the receiver loses lock.
In 10Base-T mode, polarity errors are corrected based on the detection of valid spaced link pulses. The
detection begins during the MDI crossover detection phase and locks when the 10Base-T link is up. The
polarity becomes unlocked when the link is down.
Link Partner RTL8370(M)
+ +
RX _ _ TX
+ _ +
TX _ + _ RX
Figure 6. Conceptual Example of Polarity Correction
RTL8370(M)
Datasheet
10. General Function Description

10.1. Reset
10.1.1. Hardware Reset
In a power-on reset, an internal power-on reset pulse is generated and the RTL8370(M) will start the reset
initialization procedures. These are:
• Determine various default settings via the hardware strap pins at the end of the nRESET signal
• Autoload the configuration from EEPROM if EEPROM is detected
• Complete the embedded SRAM BIST process
• Initialize the packet buffer descriptor allocation
• Initialize the internal registers and prepare them to be accessed by the external CPU
10.1.2. Software Reset

The RTL8370(M) supports two software resets; a chip reset and a soft reset.
10.1.2.1 CHIP_RESET
When CHIP_RESET is set to 0b1 (write and self-clear), the chip will take the following steps:
1. Download configuration from strap pin and EEPROM
2. Start embedded SRAM BIST (Built-In Self Test)
3. Clear all the Lookup and VLAN tables
4. Reset all registers to default values
5. Restart the auto-negotiation process
10.1.2.2 SOFT_RESET
When SOFT_RESET is set to 0b1 (write and self-clear), the chip will take the following steps:
1. Clear the FIFO and re-start the packet buffer link list
2. Restart the auto-negotiation process
10.2. IEEE 802.3x Full Duplex Flow Control

The RTL8370(M) supports IEEE 802.3x flow control in 10/100/1000M modes. Flow control can be
decided in two ways:
• When Auto-Negotiation is enabled, flow control depends on the result of NWay
• When Auto-Negotiation is disabled, flow control depends on register definition
RTL8370(M)
Datasheet
10.3. Half Duplex Flow Control

In half duplex mode, the CSMA/CD media access method is the means by which two or more stations
share a common transmission medium. To transmit, a station waits (defers) for a quiet period on the
medium (that is, no other station is transmitting) and then sends the intended message in bit-serial form. If
the message collides with that of another station, then each transmitting station intentionally transmits for
an additional predefined period to ensure propagation of the collision throughout the system. The station
remains silent for a random amount of time (backoff) before attempting to transmit again.
When a transmission attempt has terminated due to a collision, it is retried until it is successful. The
scheduling of the retransmissions is determined by a controlled randomization process called “truncated
binary exponential backoff”. At the end of enforcing a collision (jamming), the switch delays before
attempting to retransmit the frame. The delay is an integer multiple of slot time (512 bit times). The
number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed
random integer ‘r’ in the range:
0 ≤ r < 2k
where:
k = min (n, backoffLimit). The backoffLimit for the RTL8370(M) is 9.
The half duplex back-off algorithm in the RTL8370(M) does not have the maximum retry count
limitation of 16 (as defined in IEEE 802.3). This means packets in the switch will not be dropped if the
back-off retry count is over 16.
10.3.1. Back-Pressure Mode

In Back-Pressure mode, the RTL8370(M) sends a 4-byte jam pattern (data=0xAA) to collide with
incoming packets when congestion control is activated. The Jam pattern collides at the fourth byte
counted from the preamble. RTL8370(M) supports 48PASS1, which receives one packet after 48
consecutive jam collisions (data collisions are not included in the 48). Enable this function to prevent port
partition after 63 consecutive collisions (data collisions + consecutive jam collisions).
RTL8370(M)
Datasheet
10.4. Search and Learning

Search
When a packet is received, the RTL8370(M) uses the destination MAC address, Filtering Identifier (FID)
and enhanced Filtering Identifier (FID) to search the 8K-entry look-up table. The 48-bit MAC address,
12-bit FID and 3-bit EFID use a hash algorithm to calculate an 11-bit index value. The RTL8370(M) uses
the index to compare the packet MAC address with the entries (MAC addresses) in the look-up table.
This is the ‘Address Search’. If the destination MAC address is not found, the switch will broadcast the
packet according to VLAN configuration.
Learning
The RTL8370(M) uses the source MAC address, FID, and EFID of the incoming packet to hash into a 11-
bit index. It then compares the source MAC address with the data (MAC addresses) in this index. If there
is a match with one of the entries, the RTL8370(M) will update the entry with new information. If there is
no match and the 8K entries are not all occupied by other MAC addresses, the RTL8370(M) will record
the source MAC address and ingress port number into an empty entry. This process is called ‘Learning’.
The RTL8370(M) supports a 64-entry Content Addressable Memory (CAM) to avoid look-up table hash
collisions. When all 8K entries in the look-up table index are occupied, the source MAC address can be
learned into the 64-entry CAM. If both the look-up table and the CAM are full, the source MAC address
will not be learned in the RTL8370(M).
Address aging is used to keep the contents of the address table correct in a dynamic network topology.
The look-up engine will update the time stamp information of an entry whenever the corresponding
source MAC address appears. An entry will be invalid (aged out) if its time stamp information is not
refreshed by the address learning process during the aging time period. The aging time of the
RTL8370(M) is between 200 and 400 seconds (typical is 300 seconds).
10.5. SVL and IVL/SVL

The RTL8370(M) supports a 4K-group Filtering Identifier (FID) for L2 search and learning. In default
operation, all VLAN entries belong to the same FID. This is called Shared VLAN Learning (SVL). If
VLAN entries are configured to different FIDs, then the same source MAC address with multiple FIDs
can be learned into different look-up table entries. This is called Independent VLAN Learning and Shared
VLAN Learning (IVL/SVL).
10.6. Illegal Frame Filtering

Illegal frames such as CRC error packets, runt packets (length <64 bytes), and oversize packets
(length >maximum length) will be discarded by the RTL8370(M). The maximum packet length may be
set to 1522, 1536, 1552, or 16K bytes.
RTL8370(M)
Datasheet
10.7. IEEE 802.3 Reserved Group Addresses Filtering Control

The RTL8370(M) supports the ability to drop/forward IEEE 802.3 specified reserved group MAC
addresses: 01-80-C2-00-00-00 to 01-80-C2-00-00-2F. The default setting enables forwarding of these
reserved group MAC address control frames. Frames with group MAC address 01-80-C2-00-00-01
(802.3x Pause) and 01-80-C2-00-00-02 (802.3ad LACP) will always be filtered. Table 25 shows the
Reserved Multicast Address (RMA) configuration mode from 01-80-C2-00-00-00 to 01-80-C2-00-00-2F.
Table 25. Reserved Multicast Address Configuration Table
Assignment Value
Bridge Group Address 01-80-C2-00-00-00
IEEE Std 802.3, 1988 Edition, Full Duplex PAUSE Operation 01-80-C2-00-00-01
IEEE Std 802.3ad Slow Protocols-Multicast Address 01-80-C2-00-00-02
IEEE Std 802.1X PAE Address 01-80-C2-00-00-03
All LANs Bridge Management Group Address 01-80-C2-00-00-10
GMRP Address 01-80-C2-00-00-20
GVRP Address 01-80-C2-00-00-21
Undefined 802.1 Bridge Address 01-80-C2-00-00-04
|
01-80-C2-00-00-0F
Undefined GARP Address 01-80-C2-00-00-22
|
01-80-C2-00-00-2F
10.8. Broadcast/Multicast/Unknown DA Storm Control

The RTL8370(M) enables or disables per-port broadcast/multicast/unknown DA storm control by setting
registers (default is disabled). After the receiving rate of broadcast/multicast/unknown DA packets
exceeds a reference rate, all other broadcast/multicast/unknown DA packets will be dropped. The
reference rate is set via register configuration.
10.9. Port Security Function

The RTL8370(M) supports three types of security function to prevent malicious attacks:
• Per-port enable/disable SA auto-learning for an ingress packet
• Per-port enable/disable look-up table aging update function for an ingress packet
• Per-port enable/disable drop all unknown DA packets
RTL8370(M)
Datasheet
10.10. MIB Counters

The RTL8370(M) supports a set of counters to support management functions.
• MIB-II (RFC 1213)
• Ethernet-Like MIB (RFC 3635)
• Interface Group MIB (RFC 2863)
• RMON (RFC 2819)
• Bridge MIB (RFC 1493)
• Bridge MIB Extension (RFC 2674)
10.11. Port Mirroring

The RTL8370(M) supports one set of port mirroring functions for all ports. The TX, or RX, or both
TX/RX packets of the source port can be monitored from a mirror port.
10.12. VLAN Function

The RTL8370(M) supports 4K VLAN groups. These can be configured as port-based VLANs,
IEEE 802.1Q tag-based VLANs, and Protocol-based VLANs. Two ingress-filtering and egress-filtering
options provide flexible VLAN configuration:
Ingress Filtering
• The acceptable frame type of the ingress process can be set to ‘Admit All’ or ‘Admit All Tagged’
• ‘Admit’ or ‘Discard’ frames associated with a VLAN for which that port is not in the member set
Egress Filtering
• ‘Forward’ or ‘Discard’ Leaky VLAN frames between different VLAN domains
• ‘Forward’ or ‘Discard’ Multicast VLAN frames between different VLAN domains
The VLAN tag can be inserted or removed at the output port. The RTL8370(M) will insert a Port VID
(PVID) for untagged frames, or remove the tag from tagged frames. The RTL8370(M) also supports a
special insert VLAN tag function to separate traffic from the WAN and LAN sides in Router and
Gateway applications.
In router applications, the router may want to know which input port this packet came from. The
RTL8370(M) supports Port VID (PVID) for each port and can insert a PVID in the VLAN tag on egress.
Using this function, VID information carried in the VLAN tag will be changed to PVID. The
RTL8370(M) also provides an option to admit VLAN tagged packets with a specific PVID only. If this
function is enabled, it will drop non-tagged packets and packets with an incorrect PVID.
RTL8370(M)
Datasheet
10.12.1. Port-Based VLAN

This default configuration of the VLAN function can be modified via an attached serial EEPROM or
EEPROM SMI Slave interface. The 4K-entry VLAN Table designed into the RTL8370(M) provides full
flexibility for users to configure the input ports to associate with different VLAN groups. Each input port
can join with more than one VLAN group.
Port-based VLAN mapping is the simplest implicit mapping rule. Each ingress packet is assigned to a
VLAN group based on the input port. It is not necessary to parse and inspect frames in real-time to
determine their VLAN association. All the packets received on a given input port will be forwarded to
this port’s VLAN members.
10.12.2. IEEE 802.1Q Tag-Based VLAN

The RTL8370(M) supports 4K VLAN entries to perform 802.1Q tag-based VLAN mapping. In 802.1Q
VLAN mapping, the RTL8370(M) uses a 12-bit explicit identifier in the VLAN tag to associate received
packets with a VLAN. The RTL8370(M) compares the explicit identifier in the VLAN tag with the 4K
VLAN Table to determine the VLAN association of this packet, and then forwards this packet to the
member set of that VLAN. Two VIDs are reserved for special purposes. One of them is all 1’s, which is
reserved and currently unused. The other is all 0’s, which indicates a priority tag. A priority-tagged frame
should be treated as an untagged frame.
When ‘802.1Q tag aware VLAN’ is enabled, the RTL8370(M) performs 802.1Q tag-based VLAN
mapping for tagged frames, but still performs port-based VLAN mapping for untagged frames. If ‘802.1Q
tag aware VLAN’ is disabled, the RTL8370(M) performs only port-based VLAN mapping both on non-
tagged and tagged frames. The processing flow when ‘802.1Q tag aware VLAN’ is enabled is illustrated
below.
Two VLAN ingress filtering functions are supported in registers by the RTL8370(M). One is the ‘VLAN
tag admit control, which provides the ability to receive VLAN-tagged frames only. Untagged or priority
tagged (VID=0) frames will be dropped. The other is ‘VLAN member set ingress filtering’, which will
drop frames if the ingress port is not in the member set.
RTL8370(M)
Datasheet
10.12.3. Protocol-Based VLAN

The RTL8370(M) supports a 4-group Protocol-based VLAN configuration. The packet format can be
RFC 1042, LLC, or Ethernet, as shown in Figure 7. There are 4 configuration tables to assign the frame
type and corresponding field value. Taking IP packet configuration as an example, the user can configure
the frame type to be ‘Ethernet’ and value to be ‘0x0800’. Each table will index to one of the entries in the
4K-entry VLAN table. The packet stream will match the protocol type and the value will follow the
VLAN member configuration of the indexed entry to forward the packets.
Figure 7. Protocol-Based VLAN Frame Format and Flow Chart
10.12.4. Port VID

In a router application, the router may want to know which input port this packet came from. The
RTL8370(M) supports Port VID (PVID) for each port to insert a PVID in the VLAN tag for untagged or
priority tagged packets on egress. When 802.1Q tag-aware VLAN is enabled, VLAN tag admit control is
enabled, and non-PVID Discard is enabled at the same time. When these functions are enabled, the
RTL8370(M) will drop non-tagged packets and packets with an incorrect PVID.
RTL8370(M)
Datasheet
10.13. QoS Function

The RTL8370(M) supports 8 priority queues and input bandwidth control. Packet priority selection can
depend on Port-based priority, 802.1p/Q Tag-based priority, IPv4/IPv6 DSCP-based priority, and ACL-
based priority. When multiple priorities are enabled in the RTL8370(M), the packet’s priority will be
assigned based on the priority selection table.
Each queue has one leaky bucket for Average Packet Rate. Per-queue in each output port can be set as
Strict Priority (SP) or Weighted Fair Queue (WFQ) for packet scheduling algorithm.
10.13.1. Input Bandwidth Control

Input bandwidth control limits the input bandwidth. When input traffic is more than the RX Bandwidth
parameter, this port will either send out a ‘pause ON’ frame, or drop the input packet depending on
register setup. Per-port input bandwidth control rates can be set from 8Kbps to 1Gbps (in 8Kbps steps).
10.13.2. Priority Assignment

Priority assignment specifies the priority of a received packet according to various rules. The
RTL8370(M) can recognize the QoS priority information of incoming packets to give a different egress
service priority.
The RTL8370(M) identifies the priority of packets based on several types of QoS priority information:
• Port-based priority
• 802.1p/Q-based priority
• IPv4/IPv6 DSCP-based priority
• ACL-based priority
RTL8370(M)
Datasheet
10.13.3. Priority Queue Scheduling

The RTL8370(M) supports MAX-MIN packet scheduling.
Packet scheduling offers two modes:
• APR leaky bucket, which specifies the average rate of one queue
• Weighted Fair Queue (WFQ), which decides which queue is selected in one slot time to guarantee the
minimal packet rate of one queue
In addition, each queue of each port can select Strict Priority or WFQ packet scheduling according to
packet scheduling mode. Figure 8 shows the RTL8370(M) packet-scheduling diagram.
Guaranteed Max. Guaranteed Min.
APR Leaky WFQ Leaky Bucket
Bucket
Queue 0
Queue 1 Scheduler
Queue 7
Figure 8. RTL8370(M) MAX-MIN Scheduling Diagram
10.13.4. IEEE 802.1p/Q and DSCP Remarking

The RTL8370(M) supports the IEEE 802.1p/Q and IP DSCP (Differentiated Services Code Point)
remarking function. When packets egress from one of the 4 queues, the packet’s 802.1p/Q priority and IP
DSCP can optionally be remarked to a configured value. Each output queue has a 3-bit 802.1p/Q, and a
6-bit IP DSCP value configuration register.
RTL8370(M)
Datasheet
10.13.5. ACL-Based Priority

The RTL8370(M) supports 64-entry ACL (Access Control List) rules. When a packet is received, its
physical port, Layer2, Layer3, and Layer4 information are recorded and compared to ACL entries.
If a received packet matches multiple entries, the entry with the lowest address is valid. If the entry is
valid, the action bit and priority bit will be applied.
• If the action bit is ‘Drop’, the packet will be dropped. If the action bit is ‘CPU’, the packet will be
trapped to the CPU instead of forwarded to non-CPU ports (except where it will be dropped by rules
other than the ACL rule)
• If the action bit is ‘Permit’, ACL rules will override other rules
• If the action bit is ‘Mirror’, the packet will be forwarded to the mirror port and the L2 lookup result
destination port. The mirror port indicates the port configured in the port mirror mechanism
• The priority bit will take effect only if the action bit is ‘CPU’, ‘Permit’, and ‘Mirror’. The Priority bit
is used to determine the packet queue ID according to the priority assignment mechanism
10.14. IGMP & MLD Snooping Function

The RTL8370(M) supports IGMP v1/v2/v3 and MLD v1/v2 snooping. The RTL8370(M) can trap all
IGMP and MLD packets to the CPU port. The CPU processes these packets, gets the IP multicast group
information of all ports, and writes the correct multicast entry to the lookup table via EEPROM SMI.
10.15. IEEE 802.1x Function

The RTL8370(M) supports IEEE 802.1x Port-based/MAC-based Access Control.
• Port-Based Access Control for each port
• Authorized Port-Based Access Control for each port
• Port-Based Access Control Direction for each port
• MAC-Based Access Control for each port
• MAC-Based Access Control Direction
• Optional Unauthorized Behavior
• Guest VLAN
10.15.1. Port-Based Access Control

Each port of the RTL8370(M) can be set to 802.1x port-based authenticated checking function usage and
authorized status. Ports with 802.1X unauthorized status will drop received/transmitted frames.
10.15.2. Authorized Port-Based Access Control

If a dedicated port is set to 802.1x port-based access control, and passes the 802.1x authorization, then its
port authorization status can be set to authorized.
RTL8370(M)
Datasheet
10.15.3. Port-Based Access Control Direction

Ports with 802.1X unauthorized status will drop received/transmitted frames only when port authorization
direction is ‘BOTH’. If the authorization direction of an 802.1X unauthorized port is IN, incoming frames
to that port will be dropped, but outgoing frames will be transmitted.
10.15.4. MAC-Based Access Control

MAC-Based Access Control provides authentication for multiple logical ports. Each logical port
represents a source MAC address. There are multiple logical ports for a physical port. When a logical port
or a MAC address is authenticated, the relevant source MAC address has the authorization to access the
network. A frame with a source MAC address that is not authenticated by the 802.1x function will be
dropped or trapped to the CPU.
10.15.5. MAC-Based Access Control Direction

Unidirectional and Bi-directional control are two methods used to process frames in 802.1x. As the
system cannot predict which port the DA is on, a system-wide MAC-based access control direction setup
is provided for determining whether receiving or bi-direction must be authorized.
If MAC-based access control direction is BOTH, then received frames with unauthenticated SA or
unauthenticated DA will be dropped. When MAC-based access control direction is IN, only received
frames with unauthenticated SA will be dropped.
10.15.6. Optional Unauthorized Behavior

Both in Port-Based Network Access Control and MAC-Based Access Control, a whole system control
setup is provided to determine unauthorized frame dropping, trapping to CPU, or tagging as belonging to
a Guest VLAN (see the following ‘Guest VLAN’ section).
10.15.7. Guest VLAN

When the RTL8370(M) enables the Port-based or MAC-based 802.1x function, and the connected PC
does not support the 802.1x function or does not pass the authentication procedure, the RTL8370(M) will
drop all packets from this port.
The RTL8370(M) also supports one Guest VLAN to allow unauthorized ports or packets to be forwarded
to a limited VLAN domain. The user can configure one VLAN ID and member set for these unauthorized
packets.
RTL8370(M)
Datasheet
10.16. IEEE 802.1D Function

When using IEEE 802.1D, the RTL8370(M) supports 16 sets and four status’ for each port for CPU
implementation 802.1D (STP) and 802.1s (MSTP) function:
• Disabled: The port will not transmit/receive packets, and will not perform learning
• Blocking: The port will only receive BPDU spanning tree protocol packets, but will not transmit any
packets, and will not perform learning
• Learning: The port will receive any packet, including BPDU spanning tree protocol packets, and will
perform learning, but will only transmit BPDU spanning tree protocol packets
• Forwarding: The port will transmit/receive all packets, and will perform learning
The RTL8370(M) also supports a per-port transmission/reception enable/disable function. Users can
control the port state via register.
10.17. Embedded 8051

An 8051 MCU is embedded in the RTL8370(M) to support management functions. The 8051 MCU can
access all of the registers in the RTL8370(M) through the internal bus. With the Network Interface Circuit
(NIC) acting as the data path, the 8051 MCU connects to the switch core and can transmit frames to or
receive frames from the Ether network. The features of the 8051 MCU are listed below:
• 256 Bytes fast internal RAM
• On-chip 32K data memory
• On-chip 16K code memory
• Supports code-banking
• 12KBytes NIC buffer
• EEPROM read/write ability
10.18. Realtek Cable Test (RTCT)

The RTL8370(M) physical layer transceivers use DSP technology to implement the Realtek Cable Test
(RTCT) feature. The RTCT function can be used to detect short, open, or impedance mismatch in each
differential pair. The RTL8370(M) also provides LED support to indicate test status and results.
RTL8370(M)
Datasheet
10.19. LED Indicator

The RTL8370(M) supports parallel LEDs and scan mode LEDs for each port. Each port has three LED
indicator pins, LED0, LED1, and LED2. Each pin may have different indicator information (defined in
Table 26). Refer to section 7.2 Parallel LED Pins (RTL8370), page 16 and section 8.2.4 LED Pins
(RTL8370M), page 35 for details. Upon reset, the RTL8370(M) supports chip diagnostics and LED
operation test by blinking all LEDs once.
Table 26. LED Definitions
LED Statuses Description
LED_Off LED pin Output disable.
Dup/Col Duplex/Collision, Indicator. Blinking when collision occurs. Low for full duplex, and high for
half duplex mode.
Link/Act Link, Activity Indicator. Low for link established. Link/Act Blinking when the corresponding
port is transmitting or receiving.
Spd1000 1000Mbps Speed Indicator. Low for 1000Mbps.
Spd1000/Act 1000Mbps Speed/Activity Indicator. Low for 1000Mbps. Blinking when the corresponding
Spd100/Act 100Mbps Speed/Activity Indicator. Low for 100Mbps. Blinking when the corresponding port
is transmitting or receiving.
Spd10/Act 10Mbps Speed/Activity Indicator. Low for 10Mbps. Blinking when the corresponding port is
transmitting or receiving.
Spd100 (10)/Act 10/100Mbps Speed/Activity Indicator. Low for 10/100Mbps. Blinking when the corresponding
Act Activity Indicator. Act blinking when the corresponding port is transmitting or receiving.
10.19.1. Parallel LED Mode

The RTL8370(M) supports parallel LED mode. The parallel LED pin also supports pin strapping
configuration functions. The PnLED0, PnLED1, and PnLED2 pins are dual-function pins: input operation
for configuration upon reset, and output operation for LED after reset. If the pin input is pulled high upon
reset, the pin output is active low after reset. If the pin input is pulled down upon reset, the pin output is
active high after reset. For details refer to Figure 9, page 58, and Figure 10, page 58. Typical values for
pull-up/pull-down resistors are 4.7KΩ.
The PnLED1 can be combined with PnLED1 or PnLED2 as a Bi-color LED.
LED_PnLED1 should operate with the same polarity as other Bi-color LED pins. For example:
• P0LED1 should pull up upon reset if P0LED1 is combined with P0LED2 as a Bi-color LED, and
P0LED2 input is pulled high upon reset. In this configuration, the output of these pins is active low
after reset
• P0LED1 should be pulled down upon reset if P0LED1 is combined with P0LED2 as a Bi-color LED,
and P0LED2 input is pulled down upon reset. In this configuration, the output of these pins is active
high after reset
RTL8370(M)
Datasheet
Pull-Up Pull-Down
DVDDIO
4.7K LED Pin

ohm 470 ohm
4.7K 470 ohm

ohm
LED Pin
LED Pins Output Active Low LED Pins Output Active High
Figure 9. Pull-Up and Pull-Down of LED Pins for Single-Color LED
Pull-Up Pull-Down
4.7K
SPD 1000 ohm DVDDIO SPD 100 4.7K ohm
470ohm 470ohm
Yellow Green Yellow Green
SPD100 4.7K SPD1000 4.7K ohm

ohm
LED Pins Output Active Low LED Pins Output Active High
Figure 10. Pull-Up and Pull-Down of LED Pins for Bi-Color LED
10.19.2. Scan LED Mode

The RTL8370(M) provides scan LED mode to reduce LED pins but keep the same number of LED
indicators as parallel LED mode. Each port includes one bi-color and one single-color LED. The bi-color
LED consists of LED1 & LED 2 (Figure 12) and the single-color LED is driven by LED0 (Figure 11).
In the bi-color LED circuit, the 30K ohm parallel connected resistor must be used if the strapping pin on
either side of the bi-color LED is pulled low. Otherwise it is not required. Some Scan mode LED pins also
support strapping pins and will not affect the LED polarity.
RTL8370(M)
Datasheet
Figure 11. Scan Mode LED Connection Diagram (Group A: Single-Color LED (LED0))
30K ohm
Green P 7 LED 1
SLED _ P 7 B
P 7 LED 2 Yellow
30K ohm
Green P 6 LED 1
SLED _ P 6 B
P 6 LED 2 Yellow
30K ohm
Green P5 LED 1
SLED _ P 5 B
P 5 LED 2 Yellow
30K ohm
Green P4 LED 1
SLED _ P 4 B Yellow
P 4 LED 2
RTL8370(M) 30K ohm
Green P3 LED 1
SLED _ P 3 B
P 3 LED 2 Yellow
30K ohm
Green P2 LED 1
SLED _ P 2 B
P 2 LED 2 Yellow
30K ohm
Green P1 LED 1
SLED _ P 1 B
P 1 LED 2 Yellow
30K ohm
Green P0 LED 1
SLED _ P 0 B
P 0 LED 2 Yellow
SLED _ G 1B
Figure 12. Scan Mode LED Connection Diagram (Group B: Bi-Color LED (LED1 & LED2))
RTL8370(M)
Datasheet
10.20. Green Ethernet

10.20.1. Link-On and Cable Length Power Saving
The RTL8370(M) provides link-on and dynamic detection of cable length and dynamic adjustment of
power required for the detected cable length. This feature provides high performance with minimum
power consumption.
10.20.2. Link-Down Power Saving

The RTL8370(M) implements link-down power saving on a per-port basis, greatly cutting power
consumption when the network cable is disconnected. After it detects an incoming signal, it wakes up
from link-down power saving and operates in normal mode.
10.21. IEEE 802.3az Energy Efficient Ethernet (EEE) Function

The RTL8370(M) support IEEE 802.3az Energy Efficient Ethernet ability for 1000Base-T, 100Base-TX
in full duplex operation, and 10Base-T in full/half duplex mode.
The Energy Efficient Ethernet (EEE) optional operational mode combines the IEEE 802.3 Media Access
Control (MAC) sub-layer with 100Base-T and 1000Base-T Physical Layers defined to support operation
in Low Power Idle mode. When Low Power Idle mode is enabled, systems on both sides of the link can
disable portions of the functionality and save power during periods of low link utilization.
• For 1000Base-T PHY: Supports Energy Efficient Ethernet with the optional function of Low Power
Idle
• For 100Base-TX PHY: Supports Energy Efficient Ethernet with the optional function of Low Power
Idle
• For 10Base-T, EEE defines a 10Mbps PHY (10Base-Te) with reduced transmit amplitude
requirements. 10Base-Te is fully interoperable with 10Base-T PHYs over 100m of class-D (Cat-5)
cable
The RTL8370(M) MAC uses Low Power Idle signaling to indicate to the PHY, and to the link partner,
that a break in the data stream is expected, and components may use this information to enter power
saving modes that require additional time to resume normal operation. Similarly, it informs the LPI Client
that the link partner has sent such an indication.
10.22. Interrupt Pin for External CPU

The RTL8370(M) provides one Interrupt output pin to interrupt an external CPU. The polarity of the
Interrupt output pin can be configured via register access. In configuration registers, each port has link-up
and link-down interrupt flags with mask.
When port link-up or link-down interrupt mask is enabled, the RTL8370(M) will raise the interrupt signal
to alarm the external CPU. The CPU can read the interrupt flag to determine which port has changed to
which status.
RTL8370(M)
Datasheet
11. Interface Descriptions

11.1. EEPROM SMI Host to EEPROM
The EEPROM interface of the RTL8370(M) uses the serial bus EEPROM Serial Management Interface
(SMI) to read the 8K-bit 24C08 EEPROM. When the RTL8370(M) is powered up, it drives SCK and
SDA to read the registers from the EEPROM.
SCK
SDA
START STOP
Figure 13. SMI Start and Stop Command
SCK
1 8 9
DATA IN
DATA OUT
START ACKNOWLEDGE
Figure 14. EEPROM SMI Host to EEPROM
Figure 15. EEPROM SMI Host Mode Frame
RTL8370(M)
Datasheet
11.2. EEPROM SMI Slave for External CPU

When EEPROM auto-load is complete, the RTL8370(M) registers can be accessed via SCK and SDA via
an external CPU. The device address of the RTL8370(M) is 0x4. For the start and end of a write/read
command, SCK needs one extra clock before/after the start/stop signals.
Figure 16. EEPROM SMI Write Command for Slave Mode
Figure 17. EEPROM SMI Read Command for Slave Mode
RTL8370(M)
Datasheet
11.3. General Purpose Interface (RTL8370M Only)

The RTL8370M shares two extension interfaces and an LED interface with the General Purpose
Interface. The interface function mux is summarized in Table 27. When the extension interfaces are
configured as dual RGMII or MII mode, the LED interface can support per-port 3 LED pins for 8 UTP
ports. When the extension interfaces are configured as dual GMII mode, the LED interface only supports
LED_DA and LED_CK pins in serial LED mode.
Table 27. RTL8370M General Purpose Interfaces Pin Definitions
Pin No. GMII RGMII MII MAC Mode MII PHY Mode Parallel LED Serial LED
77 G1_CRS - M1M_CRS M1P_CRS - -
78 G1_COL - M1M_COL M1P_COL - -
79 G1_TXD7 - - - P7LED2 -
80 G1_TXD6 - - - P7LED0 -
81 G1_TXD5 - - - P7LED1 -
82 G1_TXD4 - - - P6LED2 -
83 G1_TXD3 RG1_TXD3 M1M_TXD3 M1P_RXD3 - -
87 G1_TXEN RG1_TXCTL M1M_TXEN M1P_RXDV - -
89 G1_GTXC RG1_TXCLK M1M_TXCLK M1P_RXCLK - -
90 G1_TXCLK - - - P6LED0 -
91 G1_TXER - M1M_TXER M1P_RXER - -
92 G1_RXER - M1M_RXER M1P_TXER - -
93 G1_RXC RG1_RXCLK M1M_RXCLK M1P_TXCLK - -
94 G1_RXDV RG1_RXCTL M1M_RXDV M1P_TXEN - -
95 G1_RXD0 RG1_RXD0 M1M_RXD0 M1P_TXD0 - -
99 G1_RXD4 - - - P6LED1 -
100 G1_RXD5 - - - P5LED2 -
101 G1_RXD6 - - - P5LED0 -
102 G1_RXD7 - - - P5LED1 -
107 G0_CRS - M0M_CRS M0P_CRS P4LED2 -
108 G0_COL - M0M_COL M0P_COL P4LED0 -
109 G0_RXD7 - - - P4LED1 -
110 G0_RXD6 - - - P3LED1 -
111 G0_RXD5 - - - P3LED2 -
112 G0_RXD4 - - - P3LED0 -
117 G0_RXDV RG0_RXCTL M0M_RXDV M0P_TXEN - -
RTL8370(M)
Datasheet
Pin No. GMII RGMII MII MAC Mode MII PHY Mode Parallel LED Serial LED
118 G0_RXC RG0_RXCLK M0M_RXCLK M0P_TXCLK - -
119 G0_RXER - - - P2LED2 -
120 G0_TXER - - - P2LED0 -
121 G0_TXCLK - - - P2LED1 -
122 G0_GTXC RG0_TXCLK M0M_TXCLK M0P_RXCLK - -
123 G0_TXEN RG0_TXCTL M0M_TXEN M0P_RXDV - -
128 G0_TXD4 - - - P1LED2 -
129 G0_TXD5 - - - P1LED0 -
130 G0_TXD6 - - - P1LED1 -
131 G0_TXD7 - - - P0LED2 -
134 - - - - P0LED1 LED_DA
135 - - - - P0LED0 LED_CK
11.3.1. Extension Port 0 and Port 1 GMII Mode Interface (1Gbps)

The Extension GMAC0 and Extension GMAC1 of the RTL8370M support GMII interfaces to an external
CPU.
Table 28 and Table 29 show the pin numbers and names in the RTL8370M. Figure 18 shows the signal
diagram for the MAC in GMII interface.
Table 28. Extension GMAC0 GMII Mode Pins
Pin No. Type Extension Port 0 GMII
107 I G0_CRS
108 I G0_COL
131, 130, 129, 128 O G0_TXD[7:4]
127, 126, 125, 124 O G0_TXD[3:0]
123 O G0_TXEN
122 O G0_GTXC (125MHz)
121 I G0_TXCLK (25/2.5MHz)
120 O G0_TXER
119 I G0_RXER
118 I G0_RXC (125/25/2.5MHz)
117 I G0_RXDV
116, 115, 114, 113 I G0_RXD[0:3]
112, 111, 110, 109 I G0_RXD[4:7]
RTL8370(M)
Datasheet
Table 29. Extension GMAC1 GMII Mode Pins

Pin No. Type Extension Port 1 GMII
77 I G1_CRS
78 I G1_COL
79, 80, 81, 82 O G1_TXD[7:4]
83, 84, 85, 86 O G1_TXD[3:0]
87 O G1_TXEN
89 O G1_GTXC (125MHz)
90 I G1_TXCLK (25/2.5MHz)
91 O G1_TXER
92 I G1_RXER
93 I G1_RXC (125/25/2.5MHz)
94 I G1_RXDV
95, 96, 97, 98 I G1_RXD[0:3]
99, 100, 101, 102 I G1_RXD[4:7]
Figure 18. MAC GMII Mode Interface (1Gbps) Signal Diagram
RTL8370(M)
Datasheet
11.3.2. Extension Port 0 and Port 1 RGMII Mode (1Gbps)

The Extension GMAC0 and Extension GMAC1 of the RTL8370M support RGMII interfaces to an
external CPU. The pin numbers and names are shown in Table 30 and Table 31. Figure 19 shows the
signal diagram for Extension Port 0 and Extension Port 1 in RGMII interfaces.
Table 30. Extension GMAC0 RGMII Pins
Pin No. Type Extension Port 0 RGMII
127, 126, 125, 124 O RG0_TXD[3:0]
123 O RG0_TXCTL
122 O RG0_TXCLK
118 I RG0_RXCLK
117 I RG0_RXCTL
116, 115, 114, 113 I RG0_RXD[0:3]
Table 31. Extension GMAC1 RGMII Pins

Pin No. Type Extension Port 1 RGMII
83, 84, 85, 86 O RG1_TXD[3:0]
87 O RG1_TXCTL
89 O RG1_TXCLK
93 I RG1_RXCLK
94 I RG1_RXCTL
95, 96, 97, 98 I RG1_RXD[0:3]
Figure 19. RGMII Mode Interface Signal Diagram
RTL8370(M)
Datasheet
11.3.3. Extension Port 0 and Port 1 MII MAC/PHY Mode Interface

(10/100Mbps)
Both the Extension GMAC0 and Extension GMAC1 of the RTL8370M support MII MAC/PHY mode
interfaces to an external CPU. The pin numbers and names are shown in Table 32 and Table 33. Figure 20,
page 68 shows the signal diagram for the MII PHY mode interface, and Figure 21, page 68 for the MII
MAC mode interface.
Table 32. Extension GMAC0 MII Pins
Extension Port 0 Extension Port 0
Pin No. Type Type
MII MAC Mode MII PHY Mode
107 I M0M_CRS O M0P_CRS
108 I M0M_COL O M0P_COL
113, 114, 115, 116 I M0M_RXD[3:0] I M0P_TXD[3:0]
117 I M0M_RXDV I M0P_TXEN
118 I M0M_RXCLK O M0P_TXCLK
122 I M0M_TXCLK O M0P_RXCLK
123 O M0M_TXEN O M0P_RXDV
127, 126, 125, 124 O M0M_TXD[3:0] O M0P_RXD[3:0]
Table 33. Extension GMAC1 MII Pins

Extension Port 1 Extension Port 1
Pin No. Type Type
MII MAC Mode MII PHY Mode
77 I M1M_CRS O M1P_CRS
78 I M1M_COL O M1P_COL
91 O M1M_TXER O M1P_RXER
92 I M1M_RXER I M1P_TXER
98, 97, 96, 95 I M1M_RXD[3:0] I M1P_TXD[3:0]
94 I M1M_RXDV I M1P_TXEN
93 I M1M_RXCLK O M1P_TXCLK
89 I M1M_TXCLK O M1P_RXCLK
87 O M1M_TXEN O M1P_RXDV
83, 84, 85, 86 O M1M_TXD[3:0] O M1P_RXD[3:0]
RTL8370(M)
Datasheet
Figure 20. Signal Diagram of MII PHY Mode Interface (100Mbps)
Figure 21. Signal Diagram of MII MAC Mode Interface (100Mbps)
RTL8370(M)
Datasheet
12. Register Descriptions

In this section the following abbreviations are used:
RO: Read Only LH: Latch High until clear

RW: Read/Write SC: Self Clearing
LL: Latch Low until clear
12.1. Page 0: PCS Register (PHY 0~7)

Table 34. Page 0: PCS Register (PHY 0~7)
Register Register Description Default
0 Control Register 0x1140
1 Status Register 0x7949
2 PHY Identifier 1 0x001C
3 PHY Identifier 2 0xC980
4 Auto-Negotiation Advertisement Register 0x0DE1
5 Auto-Negotiation Link Partner Ability Register 0x0000
6 Auto-Negotiation Expansion Register 0x0004
7 Auto-Negotiation Page Transmit Register 0x2001
8 Auto-Negotiation Link Partner Next Page Register 0x0000
9 1000Base-T Control Register 0x0E00
10 1000Base-T Status Register 0x0000
11~14 Reserved 0x0000
15 Extended Status 0x2000
16~31 ASIC Control Register -
RTL8370(M)
Datasheet
12.2. Register 0: Control

Table 35. Register 0: Control
Reg.bit Name Mode Description Default
0.15 Reset RW/SC 1: PHY reset 0
0: Normal operation
This bit is self-clearing.
0.14 Loopback RW 1: Enable loopback. This will loopback TXD to RXD and ignore 0
(Digital loopback) all activity on the cable media
0: Normal operation
This function is usable only when this PHY is operated in
10Base-T full duplex, 100Base-TX full duplex, or 1000Base-T full
duplex.
0.13 Speed Selection[0] RW [0.6,0.13] Speed Selection[1:0] 0
11: Reserved
10: 1000Mbps
01: 100Mbps
00: 10Mbps
This bit can be set through SMI (Read/Write).
0.12 Auto Negotiation RW 1: Enable auto-negotiation process 1
Enable 0: Disable auto-negotiation process
0.11 Power Down RW 1: Power down. All functions will be disabled except SMI function 0
0: Normal operation
0.10 Isolate RW 1: Electrically isolates the PHY from GMII. The PHY is still able 0
to respond to MDC/MDIO
0: Normal operation
0.9 Restart Auto RW/SC 1: Restart Auto-Negotiation process 0
Negotiation 0: Normal operation
0.8 Duplex Mode RW 1: Full duplex operation 1
0: Half duplex operation
0.7 Collision Test RO 1: Collision test enabled 0
0: Normal operation
When set, this bit will cause the COL signal to be asserted in
response to the assertion of TXEN within 512-bit times. The COL
signal will be de-asserted within 4-bit times in response to the de-
assertion of TXEN.
0.6 Speed Selection[1] RW See Bit 13 1
0.[5:0] Reserved RO Reserved 000000
RTL8370(M)
Datasheet
12.3. Register 1: Status

Table 36. Register 1: Status
1.15 100Base-T4 RO 0: No 100Base-T4 capability 0
The RTL8370(M) does not support 100Base-T4 mode and this bit
should always be 0.
1.14 100Base-TX-FD RO 1: 100Base-TX full duplex capable 1
0: Not 100Base-TX full duplex capable
1.13 100Base-TX-HD RO 1: 100Base-TX half duplex capable 1
0: Not 100Base-TX half duplex capable
1.12 10Base-T-FD RO 1: 10Base-T full duplex capable 1
1.11 10Base-T-HD RO 1: 10Base-T half duplex capable 1
1.10 100Base-T2-FD RO 0: Not 100Base-T2 full duplex capable 0
should always be 0.
1.9 100Base-T2-HD RO 0: Not 100Base-T2 half duplex capable 0
should always be 0.
1.8 Extended Status RO 1: Extended status information in Register 15 1
The RTL8370(M) always supports Extended Status Register.
1.7 Reserved RO Reserved 0
1.6 MF Preamble RO The RTL8370(M) will accept management frames with preamble 1
Suppression suppressed.
1.5 Auto-negotiate RO 1: Auto-negotiation process completed 0
Complete 0: Auto-negotiation process not completed
1.4 Remote Fault RO/LH 1: Remote fault condition detected 0
0: No remote fault detected
This bit will remain set until it is cleared by reading register 1 via
the management interface.
1.3 Auto-Negotiation RO 1: Auto-negotiation capable (permanently =1) 1
Ability
1.2 Link Status RO/LL 1: Link is established. If the link fails, this bit will be 0 until after 0
reading this bit again
0: Link has failed since previous read
If the link fails, this bit will be set to 0 until bit is read.
1.1 Jabber Detect RO/LH 1: Jabber detected 0
0: No Jabber detected
Jabber is supported only in 10Base-T mode.
1.0 Extended RO 1: Extended register capable (permanently =1) 1
Capability
RTL8370(M)
Datasheet
12.4. Register 2: PHY Identifier 1

The PHY Identifier Registers #1 and #2 together form a unique identifier for the PHY section of this
device. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the
vendor’s model number, and the model revision number. A PHY may return a value of zero in each of the
32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management.
Table 37. Register 2: PHY Identifier 1
2.[15:0] OUI RO Composed of the 3rd to 18th bits of the Organizationally Unique 0x001C
Identifier (OUI), respectively.
12.5. Register 3: PHY Identifier 2

Table 38. Register 3: PHY Identifier 2
3.[15:10] OUI RO Assigned to the 19th through 24th bits of the OUI 110010
3.[9:4] Model Number RO Manufacturer’s model number 011000
3.[3:0] Revision Number RO Manufacturer’s revision number 0000
12.6. Register 4: Auto-Negotiation Advertisement

This register contains the advertisement abilities of this device as they will be transmitted to its Link
Partner during Auto-negotiation.
Note: Each time the link ability of the RTL8370(M) is reconfigured, the auto-negotiation process should
be executed to allow the configuration to take effect.
Table 39. Register 4: Auto-Negotiation Advertisement
4.15 Next Page RO 1: Additional next pages exchange desired 0
0: No additional next pages exchange desired
4.14 Acknowledge RO Permanently=0 0
4.13 Remote Fault RW 1: Advertises that the RTL8370(M) has detected a remote fault 0
0: No remote fault detected
4.11 Reserved RW Reserved 0
4.10 Pause RW 1: Advertises that the RTL8370(M) has flow control capability 1
0: No flow control capability
4.9 100Base-T4 RO 1: 100Base-T4 capable 0
0: Not 100Base-T4 capable (Permanently =0)
4.8 100Base-TX-FD RW 1: 100Base-TX full duplex capable 1
4.7 100Base-TX RW 1: 100Base-TX half duplex capable 1
RTL8370(M)
Datasheet

4.6 10Base-T-FD RW 1: 10Base-TX full duplex capable 1
4.5 10Base-T RW 1: 10Base-TX half duplex capable 1
4.[4:0] Selector Field RO [00001]=IEEE 802.3 00001
Note 1: The setting of Register 4 has no effect unless auto-negotiation is restarted or the link goes down.
Note 2: If 1000Base-T is advertised, then the required next pages are automatically transmitted.
12.7. Register 5: Auto-Negotiation Link Partner Ability

This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The
content changes after a successful Auto-negotiation.
Table 40. Register 5: Auto-Negotiation Link Partner Ability
5.15 Next Page RO 1: Link partner desires Next Page transfer 0
0: Link partner does not desire Next Page transfer
5.14 Acknowledge RO 1: Link Partner acknowledges reception of Fast Link Pulse (FLP) 0
words
0: Not acknowledged by Link Partner
5.13 Remote Fault RO 1: Remote Fault indicated by Link Partner 0
0: No remote fault indicated by Link Partner
5.11 Asymmetric Pause RO 1: Asymmetric Flow control supported by Link Partner 0
0: No Asymmetric flow control supported by Link Partner. When
auto-negotiation is enabled, this bit reflects Link Partner ability
5.10 Pause RO 1: Flow control supported by Link Partner. 0
0: No flow control supported by Link Partner.
When auto-negotiation is enabled, this bit reflects Link Partner
ability
5.9 100Base-T4 RO 1: 100Base-T4 supported by Link Partner 0
0: 100Base-T4 not supported by Link Partner
5.8 100Base-TX-FD RO 1: 100Base-TX full duplex supported by Link Partner 0
0: 100Base-TX full duplex not supported by Link Partner
5.7 100Base-TX RO 1: 100Base-TX half duplex supported by Link Partner 0
0: 100Base-TX half duplex not supported by Link Partner
5.6 10Base-T-FD RO 1: 10Base-TX full duplex supported by Link Partner 0
0: 10Base-TX full duplex not supported by Link Partner
5.5 10Base-T RO 1: 10Base-TX half duplex supported by Link Partner 0
0: 10Base-TX half duplex not supported by Link Partner
5.[4:0] Selector Field RO [00001]=IEEE 802.3 00000
RTL8370(M)
Datasheet
12.8. Register 6: Auto-Negotiation Expansion

Table 41. Register 6: Auto-Negotiation Expansion
6.[15:5] Reserved RO Ignore on read 0
6.4 Parallel Detection RO/LH 1: A fault has been detected via the Parallel Detection function 0
Fault 0: No fault has been detected via the Parallel Detection function
6.3 Link Partner Next RO 1: Link Partner is Next Page able 0
Page Ability 0: Link Partner is not Next Page able
6.2 Local Next Page RO Not supported. Permanently =0 1
Ability
6.1 Page Received RO/LH 1: A New Page has been received 0
0: A New Page has not been received
6.0 Link Partner Auto- RO If Auto-Negotiation is enabled, this bit means: 0
Negotiation 1: Link Partner is Auto-Negotiation able
Ability 0: Link Partner is not Auto-Negotiation able
12.9. Register 7: Auto-Negotiation Page Transmit Register

Table 42. Register 7: Auto-Negotiation Page Transmit Register
7.15 Next Page RW 1: Link partner desires Next Page transfer 0
0: Link partner does not desire Next Page transfer
7.14 Reserved RO 1: A fault has been detected via the Parallel Detection function 0
0: No fault has been detected via the Parallel Detection function
7.13 Message Page RW 1: Message page 1
0: No Message page ability
7.12 Acknowledge 2 RW 1: Local device has the ability to comply with the message 0
received
0: Local device has no ability to comply with the message received
7.11 Toggle RO Toggle bit 0
7.[10:0] Message/ RW Content of message/unformatted page 1
Unformatted Field
RTL8370(M)
Datasheet
12.10. Register 8: Auto-Negotiation Link Partner Next Page

Register
Table 43. Register 8: Auto-Negotiation Link Partner Next Page Register
8.15 Next Page RO Received Link Code Word Bit 15 0
8.14 Acknowledge RO Received Link Code Word Bit 14 0
8.13 Message Page RO Received Link Code Word Bit 13 0
8.12 Acknowledge 2 RO Received Link Code Word Bit 12 0
8.11 Toggle RO Received Link Code Word Bit 11 0
8.[10:0] Message/ RO Received Link Code Word Bit 10:0 0
Unformatted Field
12.11. Register 9: 1000Base-T Control Register

Table 44. Register 9: 1000Base-T Control Register
9.[15:13] Test Mode RW Test Mode Select. 000
000: Normal mode
001: Test mode 1 – Transmit waveform test
010: Test mode 2 – Transmit jitter test in MASTER mode
011: Test mode 3 – Transmit jitter test in SLAVE mode
100: Test mode 4 – Transmitter distortion test
101, 110, 111: Reserved
9.12 MASTER/SLAVE RW 1: Enable MASTER/SLAVE manual configuration 0
Manual Configuration 0: Disable MASTER/SLAVE manual configuration
Enable
9.11 MASTER/SLAVE RW 1: Configure PHY as MASTER during MASTER/SLAVE 1
Configuration Value negotiation, only when bit 9.12 is set to logical one
0: Configure PHY as SLAVE during MASTER/SLAVE
negotiation, only when bit 9.12 is set to logical one
9.10 Port Type RW 1: Multi-port device 1
0: Single-port device
9.9 1000Base-T Full Duplex RW 1: Advertise PHY is 1000Base-T full duplex capable 1
0: Advertise PHY is not 1000Base-T full duplex capable
9.8 1000Base-T Half Duplex RW 1: Advertise PHY is 1000Base-T half duplex capable 0
0: Advertise PHY is not 1000Base-T half duplex capable
9.[7:0] Reserved RW Reserved 0
RTL8370(M)
Datasheet
12.12. Register 10: 1000Base-T Status Register

Table 45. Register 10: 1000Base-T Status Register
10.15 MASTER/SLAVE RO/LH/ 1: MASTER/SLAVE configuration fault detected 0
Configuration Fault SC 0: No MASTER/SLAVE configuration fault detected
10.14 MASTER/SLAVE RO 1: Local PHY configuration resolved to MASTER 0
Configuration Resolution 0: Local PHY configuration resolved to SLAVE
10.13 Local Receiver Status RO 1: Local receiver OK 0
0: Local receiver not OK
10.12 Remote Receiver Status RO 1: Remote receiver OK 0
0: Remote receiver not OK
10.11 Link Partner 1000Base-T RO 1: Link partner is capable of 1000Base-T full duplex 0
Full Duplex 0: Link partner is not capable of 1000Base-T full duplex
10.10 1000Base-T Half Duplex RO 1: Link partner is capable of 1000Base-T half duplex 0
0: Link partner is not capable of 1000Base-T half duplex
10.[7:0] Idle Error Count RO/SC Idle Error Counter. 0
The counter stops automatically when it reaches 0xFF
12.13. Register 15: Extended Status

Table 46. Register 15: Extended Status
15.15 1000Base-X Full Duplex RO 1: 1000Base-X full duplex capable 0
0: Not 1000Base-X full duplex capable
15.14 1000Base-X Half Duplex RO 1: 1000Base-X half duplex capable 0
0: Not 1000Base-X half duplex capable
15.13 1000Base-T Full Duplex RO 1: 1000Base-T full duplex capable 1
0: Not 1000Base-T full duplex capable
15.12 1000Base-T Half Duplex RO 1: 1000Base-T half duplex capable 0
0: Not 1000Base-T half duplex capable
RTL8370(M)
Datasheet
13. Electrical Characteristics

13.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device, or device reliability will be affected. All voltages are specified reference to GND unless
otherwise specified.
Table 47. Absolute Maximum Ratings
Parameter Min Max Units
Junction Temperature (Tj) - +125 °C
Storage Temperature -45 +125 °C
DVDDIO, DVDDIO_0, DVDDIO_1, AVDDH, Supply
GND-0.3 +3.63 V
Referenced to GND and AGND
DVDDL, AVDDL, PLLVDDL0, PLLVDDL1 Supply Referenced
GND-0.3 +1.1 V
to GND, AGND, PLLGND0, and PLLGND1
Digital Input Voltage GND-0.3 VDDIO+0.3 V
13.2. Recommended Operating Range

Table 48. Recommended Operating Range
Parameter Min Typical Max Units
Ambient Operating Temperature (Ta) 0 - 70 °C
DVDDIO, AVDDH Supply Voltage Range 3.135 3.3 3.465 V
DVDDIO_0, DVDDIO_1 Supply 3.3V 3.135 3.3 3.465 V
Voltage Range 2.5V 2.375 2.5 2.626 V
DVDDL, AVDDL, PLLVDDL0, PLLVDDL1 Supply Voltage
0.95 1.0 1.05 V
Range
RTL8370(M)
Datasheet
13.3. Thermal Characteristics

13.3.1. TQFP 176
13.3.1.1 Assembly Description
Table 49. Assembly Description
Package Type E-Pad TQFP-176
Dimension (L x W) 20 x 20mm
Thickness 1.0mm
PCB PCB Dimension (L x W) 130 x 75mm
PCB Thickness 1.6mm
2-Layer:
- Top layer (1oz): 20% coverage of Cu
- Bottom layer (1oz): 75% coverage of Cu
4-Layer:
Number of Cu Layer-PCB
- 1st layer (1oz): 20% coverage of Cu
- 2nd layer (1oz): 80% coverage of Cu
- 3rd layer (1oz): 80% coverage of Cu
- 4th layer (1oz): 75% coverage of Cu
13.3.1.2 Material Properties

Table 50. Material Properties
Item Material Thermal Conductivity K (W/m-k)
Die Si 147
Silver Paste 1033BF 2.5
Package
Lead Frame CDA7025 168
Mold Compound 7372 0.9
Cu 400
PCB
FR4 0.2
13.3.1.3 Simulation Conditions

Table 51. Simulation Conditions
Input Power 2.8W
Test Board (PCB) 2L (2S)/4L (2S2P)
Control Condition Air Flow = 0, 1, 2 m/s
RTL8370(M)
Datasheet
13.3.1.4 Thermal Performance of E-Pad TQFP-176 on PCB Under Still Air

Convection
Table 52. Thermal Performance of E-Pad TQFP-176 on PCB Under Still Air Convection
θJA θJB θJC ΨJB
4L PCB 25.3 18.2 6.2 15.7
2L PCB 38.2 24.5 6.9 18.8
Note:
θJA: Junction to ambient thermal resistance
θJB: Junction to board thermal resistance
θJC: Junction to case thermal resistance
ΨJB: Junction to bottom surface center of PCB thermal characterization
13.3.1.5 Thermal Performance of E-Pad TQFP-176 on PCB under Forced

Convection
Table 53. Thermal Performance of E-Pad TQFP-176 on PCB Under Forced Convection
Air Flow (m/s) 0 1 2
θJA 25.3 22.8 21.8
4L PCB
ΨJB 15.7 15.6 15.4
θJA 38.2 34.9 33
2L PCB
ΨJB 18.8 18.7 18.4
13.3.2. LQFP-128
13.3.2.1 Assembly Description
Table 54. Assembly Description
Package Type E-Pad LQFP128
Dimension (L x W) 14 x 20 mm
Thickness 1.4 mm
PCB PCB Dimension (L x W) 130 x 75mm
PCB Thickness 1.6 mm
2-Layer:
- Top layer (1oz): 20% coverage of Cu
- Bottom layer (1oz): 75% coverage of Cu
4-Layer:
Number of Cu Layer-PCB
- 1st layer (1oz): 20% coverage of Cu
- 2nd layer (1oz): 80% coverage of Cu
- 3rd layer (1oz): 80% coverage of Cu
- 4th layer (1oz): 75% coverage of Cu
RTL8370(M)
Datasheet
13.3.2.2 Material Properties

Table 55. Material Properties
Item Material Thermal Conductivity K (W/m-k)
Die Si 147
Silver Paste 1033BF 2.5
Package
Lead Frame CDA7025 168
Mold Compound 7372 0.88
Cu 400
PCB
FR4 0.2
13.3.2.3 Simulation Conditions

Table 56. Simulation Conditions
Input Power 2.6W
Test Board (PCB) 2L (2S)/4L (2S2P)
Control Condition Air Flow = 0, 1, 2 m/s
13.3.2.4 Thermal Performance of E-Pad LQFP-128 on PCB under Still Air

Convection
Table 57. Thermal Performance of E-Pad LQFP-128 on PCB under Still Air Convection
θJA θJB θJC ΨJT ΨJB
4L PCB 18.2 8.2 7.5 2.5 8.8
2L PCB 30.1 10.0 8.9 3.4 11
Note:
θJA: Junction to ambient thermal resistance
θJB: Junction to board thermal resistance
θJC: Junction to case thermal resistance
ΨJT: Junction to top center of package thermal characterization
ΨJB: Junction to bottom surface center of PCB thermal characterization
13.3.2.5 Thermal Performance of E-Pad LQFP-128 on PCB under Forced

Convection
Table 58. Thermal Performance of E-Pad LQFP-128 on PCB under Forced Convection
Air Flow (m/s) 0 1 2
θJA 18.2 15.2 14.2
4L PCB ΨJT 2.5 2.8 3.5
ΨJB 8.8 8.6 8.3
θJA 30.1 25.9 24.2
2L PCB ΨJT 3.4 4.5 5.6
ΨJB 11 10.7 10.5
RTL8370(M)
Datasheet
13.4. DC Characteristics
Table 59. DC Characteristics
Parameter SYM Min Typical Max Units
Power Supply Current for GMII0 DVDDIO_0 (3.3V) IDVDDIO_0 - 56 - mA
(For General Purpose Interface)
Power Supply Current for GMII1 DVDDIO_1 (3.3V) IDVDDIO_1 - 56 - mA
Power Supply Current for RGMII0 DVDDIO_0 (2.5V) IDVDDIO_0 - 32 - mA
Power Supply Current for RGMII1 DVDDIO_1 (2.5V) IDVDDIO_1 - 32 - mA
System Idle (No UTP Port Link Up, 1 System Power LED)
Power Supply Current for VDDH IDVDDIO, IAVDDH - 55 - mA
Power Supply Current for VDDL IDVDDL, IAVDDL, - 282 - mA
IPLLVDDL
Total Power Consumption for All Ports PS - 464 - mW
1000M Active (8 UTP Ports Link Up, 1 System Power LED, 8 Activity LEDs, 8 Speed LEDs)
IPLLVDDL
100M Active (8 UTP Ports Link Up, 1 System Power LED, 8 Activity LEDs, 8 Speed LEDs)
IPLLVDDL
10M Active (8 UTP Ports Link Up, 1 System Power LED, 8 Activity LEDs)
IPLLVDDL
VDDIO=3.3V
TTL Input High Voltage Vih 1.9 - - V
TTL Input Low Voltage Vil - - 0.7 V
Output High Voltage Voh 2.7 - - V
Output Low Voltage Vol - - 0.6 V
VDDIO=2.5V
TTL Input High Voltage Vih 1.7 - - V
TTL Input Low Voltage Vil - - 0.7 V
Output High Voltage Voh 2.25 - - V
Output Low Voltage Vol - - 0.4 V
Note1: DVDDIO=3.3V, AVDDH=3.3V, DVDDIO_0=3.3V, DVDDIO_1=3.3V, DVDDL=1.0V, AVDDL=1.0V
PLLVDDL=1.0V.
Note2: Both IDVDDIO_0 & IDVDDIO_1 should be added to the total current consumption when the dual extension ports of the
RTL8370M are enabled.
RTL8370(M)
Datasheet
13.5. AC Characteristics
13.5.1. EEPROM SMI Host Mode Timing Characteristics
t1
t2 t3
SCK
t4 t5 t6 t7 t8
SDA Data Valid Data Valid
Figure 22. EEPROM SMI Host Mode Timing Characteristics
t9
nRESET
SCK
SDA
Figure 23. SCK/SDA Power on Timing
Figure 24. EEPROM Auto-Load Timing
RTL8370(M)
Datasheet
Table 60. EEPROM SMI Host Mode Timing Characteristics

Symbol Description Type Min Typical Max Units
t1 SCK Clock Period O 4.7 5.04 - µs
t2 SCK High Time O 1.7 2.52 - µs
t3 SCK Low Time O 1.7 2.52 - µs
t4 START Condition Setup Time O 2.2 2.54 - µs
t5 START Condition Hold Time O 2.2 2.5 - µs
t6 Data Hold Time O 1 1.24 - µs
t7 Data Setup Time O 1 1.28 - µs
t8 STOP Condition Setup Time O 2.2 2.6 - µs
t9 SCK/SDA Active from Reset Ready O 100 105.6 - ms
t10 8K-bits EEPROM Auto-Load Time O 120 124.8 - ms
- SCK Rise Time (10% to 90%) O - 0.7 1.0 ns
- SCK Fall Time (10% to 90%) O - 0.7 1.0 ns
- Duty Cycle O 40 50 60 %
Note: t6, t7, and t10 are measured with the ATMEL AT24C08 EEPROM.
13.5.2. EEPROM SMI Slave Mode Timing Characteristics
Figure 25. EEPROM SMI Slave Mode Timing Characteristics
Table 61. EEPROM SMI Slave Mode Timing Characteristics

Symbol Description Type Min Typical Max Units
t1 SCK High Time I 4.0 - - µs
t2 SCK Low Time I 4.0 - - µs
t3 START Condition Setup Time I 4.0 - - µs
t4 START Condition Hold Time I 4.0 - - µs
t5 Data Hold Time I 5.0 - - µs
t6 Data Setup Time I 250 - - ns
t7 Clock to Data Output Delay O - 100 - ns
t8 STOP Condition Setup Time I 4.0 - - µs
RTL8370(M)
Datasheet
13.5.3. MDIO Slave Mode Timing Characteristics

The RTL8370(M) supports MDIO slave mode. The Master (the RTL8370(M) link partner CPU) can
access the Slave (RTL8370(M)) registers via the MDIO interface. The MDIO is a bi-directional signal
that can be sourced by the Master or the Slave. In a write command, the Master sources the MDIO signal.
In a read command, the Slave sources the MDIO signal.
• The timing characteristics (t1, t2, and t3 in Table 62) of the Master (the RTL8370(M) link partner
CPU) are provided by the Master when the Master sources the MDIO signal (Write command)
• The timing characteristics (t4 in Table 62)of the Slave (RTL8370(M)) are provided by the
RTL8370(M) when the RTL8370(M) sources the MDIO signal (Read command)
Figure 26. MDIO Sourced by Master (RTL8370(M) Link Partner CPU)
Figure 27. MDIO Sourced by Slave (RTL8370(M))
Table 62. MDIO Timing Characteristics and Requirements

Parameter SYM Description/Condition Type Min Typical Max Units
MDC Clock Period t1 Clock Period I 125 - - ns
MDIO to MDC Rising Setup t2 Input Setup Time
I 26 - - ns
Time (Write Data)
MDIO to MDC Rising Hold t3 Input Hold Time
I 26 - - ns
Time (Write Data)
MDC to MDIO Delay Time t4 Clock (Falling Edge) to Data Delay
O 0 - 40 ns
(Read Data) Time
RTL8370(M)
Datasheet
13.5.4. GMII Timing Characteristics
TG_RX_CYC
VIH
Gx_RXC
VIL
TG_RX_SU TG_RX_HO
Gx_RXD[7:0]
Gx_RXDV VIH
Gx_RXER
Gx_COL VIL
Gx_CRS
Figure 28. GMII Timing Characteristics
Table 63. GMII Timing Characteristics

1000Base-T Gx_GTXC Output Cycle TG_TX_CYC 125MHz Clock Output O 7.5 8.0 8.4 ns
Time
1000Base-T Gx_RXC Input Cycle TG_RX_CYC 125MHz Clock Input I 7.5 - - ns
Time
1000Base-T Gx_TXD[7:0], Gx_TXER, TG_TX_SU - O 1 - - ns
Gx_TXEN to Gx_GTXC Output Setup
Time
1000Base-T Gx_TXD[7:0], Gx_TXER, TG_TX_HO - O 0.5 - - ns
Gx_TXEN to Gx_GTXC Output Hold
Time
1000Base-T Gx_RXD[7:0], TG_RX_SU - I 0.9 - - ns
Gx_RXDV, Gx_RXER, Gx_CRS,
Gx_COL to Gx_RXC Input Setup Time
1000Base-T Gx_RXD[7:0], TG_RX_HO - I 0 - - ns
Gx_RXDV, Gx_RXER, G0_CRS,
Gx_COL to Gx_RXC Input Hold Time
RTL8370(M)
Datasheet
13.5.5. MII MAC Mode Timing
Figure 29. MII MAC Mode Clock to Data Output Delay Timing
Figure 30. MII MAC Mode Input Timing
Table 64. MII MAC Mode Timing

100Base-T MxM_TXCLK and TMM_TX_CYC 25MHz Clock Input. I - 40 - ns
MxM_RXCLK Input Cycle Time TMM_RX_CYC
10Base-T MxM_TXCLK and TMM_TX_CYC 2.5MHz Clock Input. I - 400 - ns
MxM_RXCLK Input Cycle Time TMM_RX_CYC
MxM_TXCLK to MxM_TXD[3:0], TMM_COD - O - 4.6 - ns
MxM_TXEN, and MxM_TXER
Output Delay Time
MxM_RXD[3:0], MxM_RXDV, TMM_RX_SU - I 10 - - ns
MxM_RXER, MxM_COL, and
MxM_CRS Input Setup Time
MxM_RXD[3:0], MxM_RXDV, TMM_RX_HO - I 10 - - ns
MxM_RXER, MxM_COL, and
MxM_CRS Input Hold Time
RTL8370(M)
Datasheet
13.5.6. MII PHY Mode Timing
Figure 31. MII PHY Mode Output Timing
Figure 32. MII PHY Mode Clock Output to Data Input Delay Timing
Table 65. MII PHY Mode Timing Characteristics

100M MxP_RXCLK and TMP_RX_CYC 25MHz Clock Output. O - 40 - ns
MxP_TXCLK Output Cycle Time TMP_TX_CYC
10M MxP_RXCLK and TMP_RX_CYC 2.5MHz Clock Output. O - 400 - ns
MxP_TXCLK Output Cycle Time TMP_TX_CYC
100M MxP_RXD[3:0], MxP_RXDV, TMP_RX_SU - O - 19.2 - ns
MxP_RXER, MxP_COL, and
MxP_CRS to MxP_RXCLK Output
Setup Time
100M MxP_RXD[3:0], MxP_RXDV, TMP_RX_HO - O - 20.4 - ns
MxP_RXER, MxP_COL, and
MxP_CRS to MxP_RXCLK Output
Hold Time
100M MxP_TXCLK Clock Output to TMP_COD - I 0 - 25 ns
MxP_TXD[3:0], MxP_TXEN and
MxP_TXER Input Delay Time
RTL8370(M)
Datasheet
13.5.7. RGMII Timing Characteristics
Figure 33. RGMII Output Timing Characteristics (RGx_TXCLK_DELAY=0)
Figure 34. RGMII Output Timing Characteristics (RGx_TXCLK_DELAY=2ns)
Figure 35. RGMII Input Timing Characteristics (RGx_RXCLK_DELAY=0)
RTL8370(M)
Datasheet
Figure 36. RGMII Input Timing Characteristics (RGx_RXCLK_DELAY=2ns)
Table 66. RGMII Timing Characteristics

1000M RGx_TXCLKc Output Cycle TTX_CYC 125MHz Clock Output. O 7.7 8 8.3 ns
Time Refer to Figure 33, page 88.
100M RGx_TXCLK Output Cycle TTX_CYC 25MHz Clock Output. O 38 40 42 ns
10M RGx_TXCLK Output Cycle TTX_CYC 2.5MHz Clock Output. O 380 400 420 ns
RGx_TXD[3:0] and RGx_TXCTL to TskewT Disable Output Clock Delay. O -500 -140 500 ps
RGx_TXCLK Output Skew (RGx_TXCLK_DELAY=0).
Refer to Figure 33, page 88.
RGx_TXD[3:0] and RGx_TXCTL to TTX_SU Enable Output Clock Delay. O 1.2 2.0 - ns
RGx_TXCLK Output Setup Time (RGx_TXCLK_DELAY=1).
RGx_TXD[3:0] and RGx_TXCTL to TTX_HO Enable Output Clock Delay. O 1.2 1.8 - ns
RGx_TXCLK Output Hold Time (RGx_TXCLK_DELAY=1).
RGx_RXD[3:0] and RGx_RXCTL TRX_SU Disable Input Clock Delay. I 1.0 - - ns
to RGx_RXCLK Input Setup Time (RGx_RXCLK_DELAY=0).
RGx_RXD[3:0] and RGx_RXCTL TRX_HO Disable Input Clock Delay. I 1.0 - - ns
to RGx_RXCLK Input Hold Time (RGx_RXCLK_DELAY=0).
RGx_RXD[3:0] and RGx_RXCTL TskewR Enable Input Clock Delay. I -600 - 600 ps
to RGx_RXCLK Input Skew (RGx_RXCLK_DELAY=1).
RTL8370(M)
Datasheet
13.6. Power and Reset Characteristics
Figure 37. Power and Reset Characteristics
Table 67. Power and Reset Characteristics

Reset Delay Time t1 The duration from all powers steady to
I 10 - - ms
the reset signal released to high.
Reset Low Time t2 The duration of reset signal remain low
I 10 - - ms
time for issuing a reset to RTL8370(M).
VDDL Power Rising Settling t3 DVDDL and AVDDL power rising
I 1 - - ms
Time settling time.
VDDH Power Rising t4 DVDDIO, DVDDIO_0, DVDDIO_1,
I 1 - - ms
Settling Time and AVDDH power rising settling time.
RTL8370(M)
Datasheet
14. Mechanical Dimensions

14.1. RTL8370: LQFP 128-Pin E-PAD Package
Thermally Enhanced Low-profile Quad Flat Package (LQFP) 128 Leads 14x20mm Outline.
Symbol Dimension in mm Dimension in inch

Min Nom Max Min Nom Max
A - - 1.60 - - 0.063
A1 0.05 - 0.15 0.002 - 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
b 0.17 0.2 0.27 0.007 0.009 0.011
D 22.00BSC 0.866BSC
D1 20.00BSC 0.787BSC
D2 - 6.60 - - 0.260 -
E 16.00BSC 0.630BSC
E1 14.00BSC 0.551BSC
E2 - 6.10 - - 0.240 -
e 0.50BSC 0.020BSC
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00REF 0.039REF
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MS-26.
RTL8370(M)
Datasheet
14.2. RTL8370M: TQFP176-Pin E-PAD Package

Thermally Enhanced Thin Quad Flat Pack (TQFP) 176 Leads 20x20mm Outline.
Symbol Dimension in mm Dimension in inch

Min Nom Max Min Nom Max
A - - 1.20 - - 0.047
A1 0.05 - 0.15 0.002 - 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.13 0.18 0.23 0.005 0.007 0.009
D 22.00BSC 0.866BSC
D1 20.00BSC 0.787BSC
D2 17.20BSC 0.677BSC
D3 - 6.20 - - 0.244 -
E 22.00BSC 0.866BSC
E1 20.00BSC 0.787BSC
E2 17.20BSC 0.677BSC
E3 - 6.00 - - 0.236 -
e 0.40BSC 0.016BSC
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00REF 0.039REF
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MS-26.
RTL8370(M)
Datasheet
15. Ordering Information

Table 68. Ordering Information
Part Number Package Status
RTL8370-GR LQFP 128-Pin E-PAD ‘Green’ Package -
RTL8370M-GR TQFP 176-Pin E-PAD ‘Green’ Package -
Note 1: RTL8370-GR is for 8-Port Gigabit Switch applications.
Note 2: RTL8370M-GR is for 8-Port Gigabit Router applications.
Note 3: See page 8 (RTL8370-GR) and page 9 (RTL8370M-GR) for package identification.
Realtek Semiconductor Corp.

Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com

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RTL8370-GR

LAYER 2 MANAGED 8-PORT 10/100/1000 SWITCH CONTROLLER

Realtek Semiconductor Corp.

USING THIS DOCUMENT

10. GENERAL FUNCTION DESCRIPTION .................................................................................................................45

12. REGISTER DESCRIPTIONS ....................................................................................................................................69

 Supports RFC MIB Counter  Supports 1 interrupt output to external CPU

 Supports IEEE 802.1ad Stacking VLAN  Supports Flash Interface

 8-Port 1000Base-T Router with Dual MII/RGMII/GMII

Figure 1. 8-Port 1000Base-T Switch

4.2. 8-Port 1000Base-T Router with Dual MII/RGMII/GMII

Queue Manager ALE EEPROM

Giga Giga Giga Giga Giga Giga Giga Giga

Giga Giga Giga Giga Giga Giga Giga Giga

RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45 RJ-45

Figure 2. 8-Port 1000Base-T Router with Dual MII/RGMII/GMII

RTL8370/RTL8370M Block Diagram

25MHz FLASH SCK/SDA

Figure 3. RTL8370(M) Block Diagram

Figure 4. RTL8370 Pin Assignments (LQFP-128)

6.2. Package Identification

6.3. RTL8370M Pin Assignments (TQFP-176)

Figure 5. RTL8370M Pin Assignments (TQFP-176)

6.4. Package Identification

6.5. Pin Assignment Table (RTL8370: LQFP-128)

I: Input Pin AI: Analog Input Pin

O: Output Pin AO: Analog Output Pin

I/O: Bi-Direction Input/Output Pin AI/O: Analog Bi-Direction Input/Output Pin

P: Digital Power Pin AP: Analog Power Pin

G: Digital Ground Pin AG: Analog Ground Pin

IS: Input Pin With Schmitt Trigger

Table 1. Pin Assignment Table (RTL8370: LQFP-128)

Name Pin No. Type Name Pin No. Type

6.6. Pin Assignment Table (RTL8370M: TQFP-176)

Name Pin No. Type Name Pin No. Type

Name Pin No. Type Name Pin No. Type

7. Pin Descriptions (RTL8370)

Pin Name Pin No. Type Drive Description

7.2. Parallel LED Pins (RTL8370)

Pin Name Pin No. Type Drive Description

7.3. Scan Mode LED Pins (RTL8370) (LQFP128)

7.4. Configuration Strapping Pins (RTL8370)

Pin Name Pin No. Type Description

7.5. Miscellaneous Pins (RTL8370)

7.6. Test Pins (RTL8370)

7.7. Power and GND Pins (RTL8370)

8. Pin Descriptions (RTL8370M)

Pin Name Pin No. Type Drive Description

8.2. General Purpose Interfaces (RTL8370M)

8.2.1. GMII Interface Pins (RTL8370M)

Table 11. Extension GMAC0 GMII Pins (RTL8370M) (TQFP176)

Pin Name Pin No. Type Drive Description

Table 12. Extension GMAC1 GMII Pins (RTL8370M) (TQFP176)

Pin Name Pin No. Type Drive Description

8.2.2. RGMII Pins (RTL8370M)

Pin Name Pin No. Type Drive Description

Table 14. Extension GMAC1 RGMII Pins (RTL8370M) (TQFP176)

8.2.3. MII Pins (RTL8370M)

Pin Name Pin No. Type Drive Description

Supports RFC MIB Counter Supports 1 interrupt output to external CPU

Supports IEEE 802.1ad Stacking VLAN Supports Flash Interface

8-Port 1000Base-T Router with Dual MII/RGMII/GMII