SystemVerilog Procedural Statements

• New Operators

Increment and decrement operator (Similar to C)

Post-increment/decrement and pre-increment/decrement
j=i++ j is assigned value of i and then i is incremented by 1
j=++i i is incremented by 1 and thenj is assigned value of i
j=i--; j is assigned value of i and then i is decremented by 1
j=--i; i is decremented by 1 and then j is assigned value of i

May cause a race condition since ++ and -- operators behave as
blocking assignments
Example while (i++ < MAX) begin
. . .
end
Last value of i inside the loop will be MAX

while (++j < MAX) begin

. . .
end
Last value of j inside the loop will be MAX-1

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SystemVerilog Procedural Statements

• Assignment Operators
 Equality operators

Case equality operator === , !== (looks for an exact match of x
or z values)

Logical equality operator ==, != (returns 1’bx if x or z in either
operand)

SystemVerilog introduces two new operators known as
wildcard equality operators ( ==? and !=? )

Performs a bitwise operation and treat X and Z values in a
given bit position of their right operand as a wildcard.

X and Z values in the left operand are not treated as wildcards.

a=4’b11x0; a=4’b1001;
b=4’b1100; b=4’b1x01;
a==?b a==?b

unknown Result ?

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SystemVerilog Procedural Statements

• Set Membership Operator - inside

 inside operator is a comma-separated list of expressions or ranges
 inside is used to check if a given value lies within a range
specified
logic [3:0] a;
if ((a==4’b0001)||(a==4’b0010)||(a==4’b0100 || (a==4’b1000)))

Equivalent to
logic [3:0] a;
if (a inside {4’b0001, 4’b0010, 4’b0100, 4’b1000})

integer a;
a inside { [16:23], [32:47] };

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SystemVerilog Procedural Statements

• Type Casting casting_type’(expression)


Verilog automatically converts values of one type to another type
using assignment statement

SystemVerilog adds a typecast operator

Type casting is used to specify that a conversion should occur at
any point during the evaluation of an expression,rather than just
part of an assignment
example

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SystemVerilog Procedural Statements

• Size Casting casting_size’(expression)


SystemVerilog allows widths of the vector to be cast to a different
size

If an expression is cast to a smaller vector size then the left-most
bits of the expression are truncated

If an expression is cast to a larger vector size, then the expression
is left extended
parameter P = 16;
integer x;
logic [15:0]y;
y=(P+1)'(x – 2)

Sign Casting sign’(expression) unsign’(expression)

 SystemVerilog allows casting the signedness of a
value
 Signedness of an operand can be cast
 Signedness of an operation result can be cast
product= signed’(x) * signed’(y); if(unsigned’(a-b)<=8)
Cast operand Cast intermediate result

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SystemVerilog Procedural Statements

• Enhanced for loops


In verilog, variable used to control a for loop must be declared
prior to the loop ( Concurrent loops may interfere with each other )

SystemVerilog allows the variables of for loop to be declared
inside the loop

A variable declared as part of a for loop is local to the loop and do
not exist outside the loops

Each variable is unique to the loop, so it prevents interference

Local loop variables are automatic variables.
always @(negedge clk) begin
for (int j=0; j<= 255; j++)
…
end
endmodule

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SystemVerilog Procedural Statements

• do…while loop

A while loop in Verilog might not execute at all
If the expression is not true at the beginning of the execution of
the while-loop, the statement shall not be executed at all.

do..while loop in System Verilog is similar to C

A do while loop executes atleast once

tests its control expression at the end of the loop

All logic for setting the outputs of the loop can be placed inside
the loop

Makes code more compact and intuitive

do <statement or statement block>

while (<condition>);

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 Verilog Tasks and Functions Overview
• Functions

A function shall not contain any time-controlled statements such
as #100, @(posedge clock) or wait(ready)
function [range]

A function cannot call a task function_name;

The purpose of function is to return a value parameters

Functions evaluate and execute in “0” time input declarations

A function shall contain at least one input reg declarations
… text body …
argument and no output or inout argument. endfunction
Tasks

Tasks shall contain input, multiple outputs or inout arguments

Tasks consume time so it can contain Delay, Timing and
Events
task task_name;
parameters
input declarations
output declarations
inout declarations
reg declarations
… text body …
endtask

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 SystemVerilog Tasks and Functions
• Tasks and Functions
 Begin and end statements are optional in systemverilog functions
and tasks.
 Functions can have output and inout as formal arguments
 Void functions do not return a value
• Return Statement

SystemVerilog adds a return statement

If a return statement is executed that value is returned else the last
value assigned to the function name is the return value

A return statement can be used to exit a task or a function before
reaching its end

The return statement shall override any value assigned to the function
name.
function [15:0] myfunc1 (input [7:0] x,y);
myfunc1 = x * y – 1;
endfunction

function [15:0] myfunc2 (input [7:0] x,y); Return has priority

myfunc2 = x * y – 1;
over returning on
return 45;
endfunction name of function

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SystemVerilog Tasks and Functions

• Void functions
 Void functions do not have a return value
 Output and inout formal arguments allow a void function to
propagate changes to the scope
 Void functions can be called as statements like tasks, but have

the syntax and semantic restrictions of functions.

function void print_sum (int a[]);

int sum = 0;
for (int i=0; i<a.size; i++) begin
sum += a[i]; end
$display("The sum of the arrays is ", sum);
endfunction

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SystemVerilog Tasks and Functions
• Passing task/function arguments by name

SystemVerilog allows arguments to tasks and functions to be
bound by name of formal arguments

It reduces error

Named argument values can be passed in any order

Syntax for named argument passing is same as Verilog’s syntax
for named port connections

function int multiply (input int

multiplicand, multiplier);
return multiplicand*multiplier;
endfunction

always @(posedge clock)

result<=multiply(b,a);

always @(posedge clock)

result<=multiply(.multiplicand(b),.multiplier(a));

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SystemVerilog Tasks and Functions
• Default formal argument direction and type

Systemverilog allows to specify a default type & value for each
formal argument

When a task or function is called, arguments with defaults can be
omitted from the call

If a value is not passed the default values are used

task read(int j = 0, int k, int data = 1 );

...
endtask

read ( ,5); //is equivalent to read(0,5,1)

read (2,5); //is equivalent to read(2,5,1)
read (1,5,2); //is equivalent to read(1,5,2)
read ( ,5, ); //is equivalent to read(0,5,1)
read ( ); // error: k has no default value
read (1, ,7); // error: k has no default value

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SystemVerilog Tasks and Functions

• Passing argument values by reference instead of copy


Values are passed by copy to tasks and functions (pass by value)

SystemVerilog has explicit pass by reference task/function
arguments

ref keyword is used (instead of input, output or inout)

tasks and functions should be automatic to have ref arguments

function automatic int crc( ref byte packet [1000:1] );

for( int j= 1; j <= 1000; j++ ) begin
crc ^= packet[j];
end
endfunction

// function call
byte packet1[1000:1];
int k = crc( packet1 ); // pass by value or by reference: call is the same

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SystemVerilog Tasks and Functions
• Passing argument values by reference instead of copy

Pass by reference can be read-only by the use of const keyword

Const qualifier can be used together with ref to indicate that the
argument is a read-only variable.

Protect arguments from being modified by task/function

Task ref arguments are sensitive to change

Ref arguments can read current values

Ref arguments can propagate changes immediately
Read only

task automatic show ( const ref byte data [] );

for ( int j = 0; j < data.size ; j++ )
$display( data[j] ); // data can be read but not written
endtask

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SystemVerilog Tasks and Functions
• Argument Passing
 Type is sticky, following arguments default to that type
 input - copy value in at beginning - default
 output - copy value out at end
 inout - copy in at beginning and out at end
 ref - pass by reference (effects seen right away)
► Saves time and memory for passing arrays to tasks & functions
 Modifier: const - argument cannot be modified

Default dir is input, x, y: input logic

default type is logic q, q: output bit [7:0]

task
task final(x,
final(x, y,
y, output
output bit
bit [7:0]
[7:0] p,
p, q);
q);

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