MVSILICON AU6850 USB HOST MP3 DECODER SOC

AU6850 Datasheet
USB Host MP3 Decoder SOC

Rev 1.0

Nov 24 , 2007

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

DISCLAIMER

All information and data contained in this document are without any commitment, are not
to be considered as an offer for conclusion of a contract, nor shall they be construed as to
create any liability. Any new issue of this document invalidates previous issues. Product
availability and delivery are exclusively subject to our respective order confirmation form;
the same applies to orders based on development samples delivered. By this publication,
Shanghai Mountain View Silicon Technology Co. Ltd.(“MVSILICON”) does not assume
responsibility for patent infringements or other rights of third parties that may result from
its use.

No part of this publication may be reproduced, photocopied, stored in a retrieval system, or

translated in any form or by any means, electronic, mechanical, manual, optical, or
otherwise, without the prior written permission of Shanghai Mountain View Silicon
Technology Co. Ltd.

Shanghai Mountain View Silicon Technology Co. Ltd. assumes no responsibility for any
errors contained herein.

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

Revision History

Data Revision Description

2007-11-24 1.0 Initial release

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

Contents

Revision History ........................................................................................................................iii

Contents...................................................................................................................................... iv
Figures ......................................................................................................................................... v
Tables.......................................................................................................................................... vi
1. Overview................................................................................................................................. 1
1.1 Features ......................................................................................................................... 1
1.2 Chip Architecture ......................................................................................................... 2
2. System Application ................................................................................................................ 4
3. Pin Description ....................................................................................................................... 5
3.1 AU6850A Pin Description........................................................................................... 5
3.2 AU6850 Pin Description.............................................................................................. 7
4. Package.................................................................................................................................... 9
4.1 Package Diagram.......................................................................................................... 9
4.2 Package Dimension Parameter.................................................................................. 11
5. Electrical Specification ........................................................................................................ 13
5.1 Absolute Maximum Ratings (Note 1)....................................................................... 13
5.2 Recommended Operating Conditions ....................................................................... 13
5.3 Electrical Characteristics ........................................................................................... 13
Contact Information.................................................................................................................. 14

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

Figures

Figure 1 AU6850A Functional Block Diagram ............................................................... 2

Figure 2 AU6850 Functional Block Diagram .................................................................. 3
Figure 3 MP3 Mini Audio System .................................................................................... 4
Figure 4 AU6850A Package Diagram (LQFP100-14x14mm / TOP View)................... 9
Figure 5 AU6850 Package Diagram (LQFP64-10x10mm / TOP View)...................... 10
Figure 6 LQFP100-14x14mm Package Dimension Parameter ..................................... 11
Figure 7 LQFP64-10x10mm Package Dimension Parameter ....................................... 12

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

Tables

Table 1 AU6850A Pin Description ................................................................................... 5

Table 2 AU6850 Pin Description ...................................................................................... 7
Table 3 Absolute Maximum Ratings .............................................................................. 13
Table 4 Recommended Operating Conditions................................................................ 13
Table 5 Electrical Characteristics.................................................................................... 13

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

1. Overview

A highly integrated SOC for MP3 player, AU6850 integrates MCU, MP3
decoder, USB Host controller, SD/MMC card controller, a 16-bit audio decoder and an
IR decoder in a single chip. Besides AU6850 embedded a 32KB OTP memory, which
provide an ultra low cost, low power consumption, flexible and more powerful Host
MP3 player solution compared with other traditional flash-MP3 player.

1.1 Features

l Low power 0.18um CMOS technology

l Power supply 1.8V/3.3V, power consumption 80mW
l Enhanced 8051, up to 10 times faster than standard 8051
l Dynamic MCU running clock frequency adjustment to reduce power
consumption and EMI
l USB2.0 full-speed host controller
l SD/MMC card controller
l Support MPEG 1/2/2.5 layer3 decoding, data rate 32kbps ~ 320kbps, including
VBR
l Support 9 sampling frequency:
8kHz/11.025kHz/12kHz/16kHz/22.05kHz/24kHz/32kHz/44.1kHz/48kHz
l Embedded sound equalizer
l Support tag format ID3v1 and ID3v2.4
l Support FAT16/FAT32 file system
l Embedded 16-bit sigma-delta audio DAC
l Embedded headphone amplifier
l Support IR Remote control
l GPIO for various purposes
l Embedded 32KB OTP memory for program code storage
l Support external NOR flash for program code storage (AU6850A only)
l Support in-system debug through external emulator (AU6850A only)

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

1.2 Chip Architecture

NOR Flash

GPIO PLL
MCU 32KB
& & Clock
8bit OTP
IR Decoder Genenator

SD/MMC MP3
DMA
Controller Decoder

USB Host DAC

Figure 1 AU6850A Functional Block Diagram

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

Figure 2 AU6850 Functional Block Diagram

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

2. System Application

● MP3 mini audio system

Figure 3 MP3 Mini Audio System

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

3. Pin Description

AU6850A/AU6850 is a CMOS device. Floating level on input signals causes

unstable device operation and abnormal current consumption. Pull-up or Pull-down
resistors should be used appropriately for input or bidirectional pins.

Notation Description
I Input
O Output
I/O Bidirectional
I/OD Bidirectional, Open drain output
AI Analog Input
AO Analog Output
PWR Power
GND Ground

3.1 AU6850A Pin Description

Table 1 AU6850A Pin Description

Pin name Pin # Type Description
NOR flash memory interface pins
FSH_DB [7:6] 17:18 I/O Flash memory data bus
FSH_DB [5:2] 22:25 I/O Flash memory data bus
FSH_DB [1:0] 32:33 I/O Flash memory data bus
FSH_AB[15:14] 61:62 I/O Flash memory address bus
FSH_AB[13] 64 I/O Flash memory address bus
FSH_AB[12] 60 I/O Flash memory address bus
FSH_AB[11] 68 I/O Flash memory address bus
FSH_AB[10] 43 I/O Flash memory address bus
FSH_AB[9] 67 I/O Flash memory address bus
FSH_AB[8] 65 I/O Flash memory address bus
FSH_AB[7:6] 54:53 I/O Flash memory address bus
FSH_AB[5:4] 44:45 I/O Flash memory address bus
FSH_AB[3:1] 35:37 I/O Flash memory address bus
FSH_AB[0] 42 I/O Flash memory address bus
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USB interface pins
DP 49 I/O USB Function D+ bus
DM 48 I/O USB Function D- bus

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

CARD interface pins

SD_CLK 56 O SD Card clock
SD_CMD 58 I/O SD Card command line
SD_DAT 59 I/O SD Card data line
Remote control pin
IR 21 I Inferred remote controller signal
DAC AUDIO interface pins
HPOUTL 4 AO Head phone left channel output
HPOUTR 1 AO Head phone right channel output
VREF 7 AO Internal voltage reference
GPIO/MCU IO pins
P1[7:3] 88:84 I/OD MCU P1 PORT
P1[2:0] 71:69 I/OD MCU P1 PORT
P0[1] 16 I/OD MCU P0 PORT, can used as RXD
P0[0] 15 I/OD MCU P0 PORT, can used as TXD
GP_A[7:4] 79:76 I/O GPIO Bank A PORT
GP_A[3:2] 73:72 I/O GPIO Bank A PORT
GP_A[1:0] 52:51 I/O GPIO Bank A PORT
GP_B[7:4] 41:38 I/O GPIO Bank B PORT
GP_B[3:0] 29:26 I/O GPIO Bank B PORT
CLK & Reset pins
XIN 11 I Crystal oscillator input for PLL
XOUT 12 O Crystal oscillator output for PLL
RESETn 20 I System reset, active low
Debug pin
DEBUG 93 I When tied high, chip enter into debug mode and use
external emulator. When tie low, chip works in normal
mode
EXROM 94 I When tied high, chip use external flash as MCU program
code rom. When tie low, chip use internal OTP as MCU
program code rom.
Power/Ground pins
AVDD33 5 PWR Analog power for DAC(3.3V)
6
AVSS 3 GND Analog ground for DAC
2
PLL_AVSS 8 GND Analog ground for PLL
PLL_AVDD18 9 PWR Analog power for PLL(1.8V)
VDD33 13 PWR Digital power for I/O(3.3V)
34
50
55
74
92
VSS 19 GND Digital IO/core ground
30
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57
66
81
VDD18 10 PWR Digital power for core (1.8V)

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

31
46
63
80
Reserved 100:95 NC Don’t used, leave them floating
91:89
83:82
75
14

3.2 AU6850 Pin Description

Table 2 AU6850 Pin Description

Pin name Pin # Type Description
USB interface pins
DP 31 I/O USB Function D+ bus
DM 30 I/O USB Function D- bus
CARD interface pins
SD_CLK 36 O SD Card clock
SD_CMD 38 I/O SD Card command line
SD_DAT 39 I/O SD Card data line
Remote control pin
IR 16 I Inferred remote controller signal
DAC AUDIO interface pins
HPOUTL 3 AO Headphone left channel output
HPOUTR 1 AO Headphone right channel output
VREF 5 AO Internal voltage reference
GPIO/MCU IO pins
P1[7:3] 59:55 I/OD MCU P1 PORT
P1[2:0] 44:42 I/OD MCU P1 PORT
P0[1] 13 I/OD MCU P0 PORT, can used as RXD
P0[0] 12 I/OD MCU P0 PORT, can used as TXD
GP_A[7:4] 52:49 I/O GPIO Bank A PORT
GP_A[3:2] 46:45 I/O GPIO Bank A PORT
GP_A[1:0] 34:33 I/O GPIO Bank A PORT
GP_B[7:4] 27:24 I/O GPIO Bank B PORT
GP_B[3:0] 20:17 I/O GPIO Bank B PORT
CLK & Reset pins
XIN 9 I Crystal oscillator input for PLL
XOUT 10 O Crystal oscillator output for PLL
RESETn
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Power/Ground pins
AVDD33 4 PWR Analog power for DAC(3.3V)
AVSS 2 GND Analog ground for DAC

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PLL_AVSS 6 GND Analog ground for PLL

PLL_AVDD18 7 PWR Analog power for PLL(1.8V)
VDD33 11 PWR Digital power for I/O(3.3V)
23
32
35
47
60
VSS 14 GND Digital IO/core ground
21
29
37
41
54
VDD18 8 PWR Digital power for core (1.8V)
22
28
40
53
Reserved 64:61 NC Don’t used, leave them floating
48

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

4. Package

4.1 Package Diagram

EXROM
DEBUG
VDD33

VDD18
GP_A7
GP_A6
GP_A5
GP_A4
P1_7
P1_6
P1_5
P1_4
P1_3

VSS
NC
NC
NC
NC
NC
NC

NC
NC
NC

NC
NC
100
99
98
97

89

87
86
85
84
83
82
81
80
79
78
77
76
95
94
93
92
91
90

88
96

HPOUTR 1 75 NC
AVSS 2 74 VDD33
AVSS 3 73 GP_A3
HPOUTL 4 72 GP_A2
AVDD33 5 71 P1_2
AVDD33 6 70 P1_1
VREF 7 69 P1_0
PLL_AVSS 8 68 FSH_AB11
PLL_AVDD18 9 67 FSH_AB9
VDD18 10 66 VSS
XIN
XOUT
VDD33
11
12
13
MVSILICON 65
64
63
FSH_AB8
FSH_AB13
VDD18
NC
P0_0
14
15 AU6850A 62
61
FSH_AB14
FSH_AB15
P0_1 16 60 FSH_AB12
FSH_DB7 17 59 SD_DAT
FSH_DB6 18 58 SD_CMD
VSS 19 57 VSS
ResetN 20 56 SD_CLK
IR 21 55 VDD33
FSH_DB5 22 54 FSH_AB7
FSH_DB4 23 53 FSH_AB6
FSH_DB3 24 52 GP_A1
FSH_DB2 25 51 GP_A0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GP_B0
GP_B1
GP_B2
GP_B3

VDD18
FSH_DB1
FSH_DB0
VDD33
FSH_AB3
FSH_AB2
FSH_AB1
GP_B4
GP_B5
GP_B6
GP_B7
FSH_AB0
FSH_AB10
FSH_AB5
FSH_AB4
VDD18

VDD33
VSS

VSS

DP
DM

Figure 4 AU6850A Package Diagram (LQFP100-14x14mm / TOP View)

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VDD33

VDD18
GP_A7
GP_A6
GP_A5
GP_A4
P1_7
P1_6
P1_5
P1_4
P1_3
VSS
NC
NC
NC
NC
62

60
59
58
57
56
55
54
53
52
51
50
49
64
63

61
HPOUTR 1 48 NC
AVSS 2 47 VDD33
HPOUTL 3 46 GP_A3
AVDD33 4 45 GP_A2
VREF 5 44 P1_2
PLL_AVSS 6 43 P1_1
PLL_AVDD18
VDD18
7
8 MVSILICON 42
41
P1_0
VSS
XIN
XOUT
9
10 AU6850 40
39
VDD18
SD_DAT
VDD33 11 38 SD_CMD
P0_0 12 37 VSS
P0_1 13 36 SD_CLK
VSS 14 35 VDD33
ResetN 15 34 GP_A1
IR 16 33 GP_A0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GP_B0
GP_B1
GP_B2
GP_B3

VDD18
VDD33
GP_B4
GP_B5
GP_B6
GP_B7
VDD18

VDD33
VSS

VSS

DP
DM

Figure 5 AU6850 Package Diagram (LQFP64-10x10mm / TOP View)

Notes: The “NC” IO in these diagrams means “not connected”, please leave them floating.

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4.2 Package Dimension Parameter

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Figure 6 LQFP100-14x14mm Package Dimension Parameter

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Figure 7 LQFP64-10x10mm Package Dimension Parameter

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 MVSILICON AU6850 USB HOST MP3 DECODER SOC

5. Electrical Specification

5.1 Absolute Maximum Ratings (Note 1)

Table 3 Absolute Maximum Ratings

Parameter Symbol Rating Unit
Power Supply Voltage (IO) VCC_IO_AB -0.5 to 4.6 V
Power Supply Voltage (Core) VCC_CORE_AB 0 to 2 V
Power Supply Voltage (PLL) VCC_PLL_AB -0.2 to 2.2 V
Power Supply Voltage (DAC) VCC_DAC_AB -0.3 to 3.6 V
Storage Temperature TEMP_STG -65 to 150 C

5.2 Recommended Operating Conditions

Table 4 Recommended Operating Conditions

Parameter Symbol Min Typ Max Unit
Power Supply Voltage (IO) VCC_IO_OP 3.0 3.3 3.6 V
Power Supply Voltage (Core) VCC_CORE_OP 1.62 1.8 1.98 V
Power Supply Voltage (PLL) VCC_PLL_OP 1.62 1.8 1.98 V
Power Supply Voltage (DAC) VCC_DAC_OP 3.0 3.3 3.6 V
Input Voltage (digital) VIN 0 3.6 V
Operating Temperature TEMP_OPR 0 70 C

5.3 Electrical Characteristics

Table 5 Electrical Characteristics

Symbol Parameter Condition Min Typ Max Unit
VIH Input High Voltage 2.0 3.6 V
VIL Input Low Voltage 0 0.8 V
VOH Output high voltage @IOH=2mA 2.4 V
VOL Output low voltage @IOL=2mA 0.4 V
IOL Low level output current for @VOL = 0.4V 9.4 15.9 19.8 mA
8mA pins
IOH Low level output current for @VOH = 2.4V 11.2 23.8 38.3 mA
8mA pins
IL Input leakage current -10 10 uA
IOZ Tri-state output leakage -10 10 uA
current
P_PLAY Power consumption when Playing mode 80 mW
playing

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1. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They
are not meant to imply that the device should be operated at these limits.

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Contact Information

Shanghai Mountain View Silicon Technology Co Ltd

Shanghai Headquarter:
Suite 403, Jinying Tower A, 1518 Minsheng Road, Pudong New Area,
Shanghai, P.R. China
Zip code: 200135
Tel: 86-21-68549851
Fax: 86-21-68549859

Shenzhen Sales & Technical Support Office:

Suite 8C Olympic Plaza, Shangbao Road, Futian District,
Shenzhen, Guangdong, P.R. China
Zip code: 518034
Tel: 86-755-83522955
Fax: 86-755-83522957

Email: support@mvsilicon.com
Website: http://www.mvsilicon.com

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