ELECTRONICS

Oscillator Jitter FAQ

Jitter, in the sense of timing error, was a life- Fortunately, jitter in electronics circuits is usu-
or-death matter for WW1 aircraft armed ally less dire. In an emergency, of course,
with synchronized machine guns. The loss of communications can nonetheless
machine gun’s firing mechanisms was become a very serious matter. This JITTER
timed to fire rounds through the whirling pro- FAQ discusses some of the obvious aspects
peller blades. Too often, timing errors of communiations circuit jitter, and draws
caused the gun to ‘remodel’ the propeller, the reader’s attention to some of jitter’s less
with untoward results. than obvious consequences.
 Page: 2

By:
Dan Nehring, V-P Engineering Tel: 800 331 1236
MF Electronics Corp Fax: 914-712-2290
10 Commerce Drive Internet: http//www.mfelectronics.com
New Rochelle, NY 10801 email:dan@mfelectronics.com

Oscillator Jitter FAQ

Jitter is a heightened concern for wireless systems, especially as frequency and
data rate push ineluctably upwards. From the standpoint of a oscillator manu-
facturer, there are aspects of clock and data signal waveform jitter that merit
particular attention. The following Jitter FAQ discussion highlights some of them.
Hopefully, the answers to the jitter questions will provide guideposts for mini-
mizing jitter-induced data error.

SUMMARY
Q1 What is jitter?
Q2 What causes jitter?
Q3 How are ONE and ZERO values read?
Q4 How does data jitter compromise readability?
Q5 How do data & clock jitter together cause unreadability?
Q6 Why is jitter an increasing concern at higher frequencies?
Q7 Why is data signal rise rate important?
Q8 Why should clock signals have fast rise time?
Q9 Why is clock waveform symmetry important?
Q10 What’s the benefit of dual complementary logic?
Q11 What clock oscillator parameters besides jitter are important?
Q12 How do you measure jitter?

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Introduction which subsequent circuits will decode.
Rapid growth of the wireless infrastructure has
elevated jitter from an obscure circuit characteris- A clock oscillator’s signal is used to initiate the
tic to a priority specification. This is especially data interrogation process. That is, it times the
true for clock oscillators and VCXOs, which reading of ONE or ZERO values. The clock’s
provide time and frequency references for today’s rising edge “views” the center of the data wave-
wireless systems. form. (Ringing and rise time transients have
subsided by this time). Illustration Q1A shows
Range of waveform timing variations (jitter) how the clock waveform’s leading edge is aligned
with the center of a data signal. Jitter that causes
Waveform transition is too early
the waveform to be late or early (relative to the
Ideal waveform Waveform transition is too late
clock’s center-waveform timing), can displace the
interrogation “window” beyond the point of data
readability.

Q2— What Causes Jitter? The ubiquitous noise

associated with all semiconductor circuits is one
source of waveform triggering uncertainty (jitter).
Worst-case jitter Wireless applications expose communications
Q1—What Is Jitter? Jitter refers to a waveform’s timing uncertainty. Suc-
circuits to a wider range of interference. Radio
cessive waveforms—although at fixed frequency—don’t arrive at the expected signals are susceptible to atmospheric effects,
intervals. Historically, when digital systems operated in the kilohertz frequency
range, jitter was largely inconsequential. At today’s frequencies, a few nano-
lightning, RFI, and reflections from nearby struc-
seconds timing uncertainty can amount to a substantial fraction of the cycle’s tures. Cell phones and mobile wireless systems are
total duration.
vulnerable to signal multipaths, making the system
Q1—What is Jitter? In simplest terms, jitter especially vulnerable to jitter’s information cor-
refers to the uncertainty, or variability, of wave- rupting effects. Power supply transients and faulty
form timing. connections also take their toll.

Q1 illustration presents the general idea of a Illustration Q2 shows how a logic gate’s noise
“jittery” waveform. Successive cycles of the creates variable triggering. In this example, the
waveform (shown as perfect squarewaves) arrive at circuit’s vulnerability to thermal and other noise is
their destination slightly late, or slightly early. In exaggerated for simplicity of explanation.
wireless communications, such waveforms will
The logic gate is designed to make a transition
typically convey logic ONE or ZERO values,
whenever the rising edge of the triggering wave-
form reaches approximately 2.5V. That is Vdd/2
Data Signal for 5V systems. Circuit designers are actually less
concerned with absolute triggering voltage than
consistency of triggering at some voltage near this
Logic 2.5V value.
Device Output
The gate of Q2 will rarely respond to the trigger-
ing waveform at exactly 2.5V. In normal circum-
Clock Signal stances, there will be a Gaussian distribution of
Q1A—The clock signal’s rising edge is synchronized with the center of the triggering thresholds around the 2.5V level.
data waveform to initiate the reading of ONE or ZERO data values. Excessive
jitter alters timing of the clock or data signal (or both), increasing the likeli-
hood of a reading error. (See Figures Q3 thru Q5 for discussion). To highlight the jitter creating mechanisms, con-

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sider how Q2 logic gate responds to three succes- Jitter between successive signal cycles is referred
sive input waveforms at 2.4V, 2.5V and 2.6V. to as cycle-to-cycle jitter. This is typically not the
Actual trigger voltage span is then -0.1V to +0.1V. critical measure of jitter. In most instances, many
random waveforms are sampled for period dura-
tion. Jitter is then analyzed over the entire popula-
Logic tion of waveform duration measurement. The
Triggering Signal Device result is known as period jitter measurements.
Output
2.5V Q3—How are ONE and ZERO values read?
Successive triggering waveforms produce logic device Communications and digital processing depend on
transitions at 2.4V, 2.5V and 2.6V, respectively the ability to decode and “read” the ONE and
Rise rate: 1 Volt/µsec ZERO values of logic waveforms. In illustration

2.6V
2.5V Clock signal’s positive-going edges
2.4V “inspect” data signal for ONE or ZERO value

Logic device triggers at 2.4V

(Early by 0.1µsecond)
Succesive output transitions

Clock Signal Reads Data

Device triggers at 2.5V

(Center of timing variation)

Device triggers at 2.6V

(Late by 0.1 µsecond)

Transitions at voltages between 2.4V and

2.6V produce ±0.1 µs timing variation
} Center of each data cycle is
“sampled” for ONE or ZERO value
Q3—Reading One And Zero Values. This simple configuration presents a
jitter-free data signal, plus a clock signal to initiate the data reading process.
The clock signal’s leading edge monitors the center of the data waveform,
Input Data Signal
where there’s least ambiguity reading in the ONE or ZERO state. Output
circuits reproduce the ONE or ZERO value that the clock signal “sees.”

ONE ONE ZERO ONE ONE ONE ZERO ONE

One Decoded Word Of Data

Q2—What causes jitter? (One cause of jitter is a logic device’s variable trig-
gering threshold. Instead of switching between ONE and ZERO values when
the triggering voltage rises to 2.5V (for instance), the logic circuit responds to
various triggering voltages around this 2.5V threshold. In this example, the Q3—How are ONE and ZERO values read? This simplified diagram pre-
logic circuit responds when successive triggering waveforms reach 2.4V, 2.5V sents a jitter-free data signal, plus a clock signal that initiates the data reading
and 2.6V. A triggering voltage rise rate of 1 volt per microsecond produces process. Full scale signal voltage occurs at the center of the data waveform, so
logic device transitions with ±0.1V variability around the 2.5 nominal trigger- that’s where the clock signal’s leading edge “looks” at the data. (The waveform’s
ing level. Waveform timing uncertainty (jitter) is then ±0.1 µs. ONE or ZERO state is expressed least ambiguously at this full scale signal
voltage). Output circuits reproduce the ONE or ZERO data values that the
(Typically, the range of triggering voltages would clock signal “sees.”
be much smaller).
Q3, the leading edge of the clock waveform
Suppose the input waveform rises at the rate of 1 initiates the data signal inspection process. It
volt per microsecond. The ±0.1V triggering vari- “looks at” the data signal to determine whether
ability leads in turn to a ±0.1V ÷ 1V/µs = ±0.1µs there are ONE or ZERO logic values.
range of triggering uncertainty. In other words,
jitter extends from -0.1µs to +0.1µs. Inspection, in this example, is undertaken at the
center of the data signal. This region of the data

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waveform is least ambiguously a ONE or a ZERO. panel shows jitter on both data and clock signals.
(Ringing or other distortions will have settled The bottom panel is an expanded view of the
down by the center of that region). resulting data reading process. Jitter imposes a
twofold penalty. First, data signal jitter narrows the
Input data signal with jitter viewing window for determining ONE or ZERO
values. Second, jitter on the clock signal displaces
ONE ONE ZERO ONE ONE ONE ZERO ONE the rising edge from the center of the data “win-
dow.” In this bottom Q5 view, excessive data and
Input Data Signal clock signal jitter cause the clock’s leading edge to

sampling window ONE ONE ZERO ONE ONE ONE ZERO ONE

Clock Signal Reads Data

“Ideal” jitter free data and clock signals

Clock Data
Signal

Jitter
on Clock
incoming
data signal
narrows
data Jitter prone data and clock signals
sampling
window, Data
degrades data
integrity
Clock

Q4—How does data signal jitter compromise readability? Jitter on the data
signal reduces the width of the effective “window” available for determining
ONE or ZERO values. See the expanded region for clarity.
Data
Q4—How Does Data Signal Jitter Compromise
Window
Readability? Jitter on the data signal reduces the
usable width of the center-waveform “window”
available for monitoring logic values. The result
Leading
can be an indecipherable message. Edge
Jitter causes clock to
Designers of today’s wireless systems demand the “see” ZERO, not ONE Clock
use of low jitter circuit components and topology.
Critical timing components, such as clock oscilla-
tors and VCXOs, are required to have rigorous
control over jitter performance.
Q5—How do simultaneous data and clock jitter prevent readability? In
Q5—How do simultaneous data and clock this illustration—disastrously! The “early” clock signals coincide with “late”
data signals to read ZERO when actual value is ONE. Conversely, the late
signal jitter prevent readability? Illustrations Q5 clock signals look at early data signals, again “seeing” ZERO when the true
(top) shows data and clock free of jitter. The center value is ONE. The net result is unequivocally a reading error.

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“see” a ZERO value when ONE is the true infor- differently, jitter becomes a progressively larger
mation content. proportion of the data monitoring window.

Q6—Why is Q8—Why
jitter an increas- 50 MHz Data Signal should clock Slow Rise Clock
ing concern at signals have
10 ns Sampling Window 2.6V
higher frequen- fast rise rates. 2.5V
2.4V
cies? For each 200 MHz Data Signal Slow clock Small variations in logic circuit
switching voltage....
doubling of oscillator rise
2.5 ns Sampling Window Logic Transitions
frequency, the rate paves the
Q 6—Why is jitter an increasing concern as
maximum “win- frequency rises? For every doubling of fre-
way for ..... produce exaggerated variations
in logic circuit transition timing (jitter)
dow” available for quency, the window for determining a signal’s variability in
ONE or ZERO value is halved. At 50 MHz the
reading ONE or window duration is 10 nanoseconds. At 200
data signal
Q8—Why Should Clock Signals Have Fast Rise
ZERO data values MHz, it shrinks to 2.5 ns. Jitter of ±100 pico- sampling. (The Rate? The clock signal initiates a logic transition
seconds peak-peak amounts to 1% of of the win-
is halved. (Dia- dow duration at 50 MHz. At 200, jitter is 4% of
clock signal’s when its voltage rises to a critical threshold. (To nomi-
nal 2.5V in this example). Variations in this transi-
gram Q6). Jitter the maximum sampling window. At gigahertz rising edge tion voltage will advance or delay the logic circuit’s
±100 ps jitter becomes completely
then amounts to a frequencies,
unacceptable!
initiates the transition. Slow-rise clock waveforms exaggerate the
effect of triggering voltage variations. At 1 volt per
proportionately reading of data microsecond clock rise rate, a +0.1V deviation from
larger fraction of the ONE or ZERO waveform values). But nominal 2.5V triggering voltage delays the logic tran-
sition by 0.1 microsecond. At 0.5V/µs rise rate, the
duration. The effective window for data reading with a slow- same +0.1V triggering voltage variation doubles the
therefore shrinks significantly with increasing rise clock, transition delay.
frequency. where exactly is the waveform’s leading edge? In
Window reduced by wave- fact, the functional leading edge is the actual
form’s finite rise rate Q7—Why is voltage threshold that initiates data determination.
data signal Illustration Q8 shows how logic circuit triggering
Slow

rise rate thresholds vary from one data cycle to the next.
important? Variable timing leads to advancing or retarding the
Slow-rise data logic transitions. That is, slow clock rise rates
Slower rise rate further signals shrink increase the potential for clock jitter. The slower
shrinks sampling window
the duration of the rise rate, the more exaggerated the timing
the waveform’s
er

variation (jitter) becomes.

Slow

full scale
signal voltage. Q9—Why is waveform symmetry important?
The time spent Communications circuits use leading and trailing
Q7—Why is data signal rise rate important?
Slow-rise waveforms reduce the period of full scale
in rising to full edges of their waveforms to trigger subsequent
signal voltage. (The most unambiguous window for scale, then logic events. Such triggering processes require
reading ONE or ZERO data values). Reduction of
the usable sampling window makes the signal in-
returning system-wide synchronism between all the trigger-
creasingly susceptible to reading error caused by towards zero ing functions. Otherwise, the triggering edge of
jitter and other distortions
subtracts from one waveform will not coincide with the window
the maximum period of full scale voltage. (In other awaiting its triggering stimulus. Ideal logic wave-
words, the “window” for determining ONE and forms have 50%/50% symmetry. That is, both
ZERO values is reduced). waveform half cycles have the same duration.
Actual waveforms, of course, depart from this
The upper and lower waveforms of illustration Q7 ideal.
demonstrate how progressively slower signal rise
rate cuts into the data sampling window. Put Illustration Q9 demonstrates the need for wave-

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form symmetry. As discussed earlier, the midpoint
Differential
of each data waveform provides an interrogating Hz Logic
50 M p s
window. Clock signals (top panel), aligned with C • 2e r • R1O0NIC S425 P!
V D
3 . 3 J i t t ELECoTdel A8
Low M
ZA
window centers, initiate the ONE or ZERO data •
reading process.
Oscillator’s dual
complementary
Data Waveform outputs permit
differential
Disparate transmission
50% 50% 50% ZA Ground
P! Potentials
Clock’s Leading edge aligned
with center of data waveform
Q10—What’s The Benefit Of Differential Transmission? Differential logic
circuits respond to signals between the input connections, not between a single
50% 50% 50% input and ground. Accordingly, differential transmission through parallel PCB
traces provides immunity to transients capacitively or inductively coupled from
nearby circuits. Transients injected into the ground plane are likewise ignored.

Clock’s 60/40 Assymmetry The analog signal world has long exploited differ-
Data Waveform ential transmission to minimize interference. With
rising frequency, and RFI everywhere, so too are
50% 50% 50% wireless technologies.

Clock assymmetry offsets leading Differential clock

edge from center of data waveform and signal Clock Oscillator Specs
transmission
60% 40% 60% across circuit (Jitter related specs)
board traces Jitter
Output rise/fall times
provides signifi- Output symmetry
cant protection Dual complementary output
Q9—Why is clock waveform symmetry important? Rising and trailing
edges of 50%/50% symmetry clock waveforms are easily synchronized with against pickup (General specs)
data reading “windows” (top). Asymmetrical clock waveforms (bottom), dis- from neighboring Frequency
place either the leading or trailing edges away from the center of the data
windows circuits. This is Logic type
because interfer- Thermal
Aging
stability
The bottom panel of Q9 illustrates the effect of
ence tends to be Operating voltage
clock waveform asymmetry. The mark-space ratio
coupled into both Maximum load current
is no longer 50%/50%. Lack of waveform symme- Package type, size
conductors
try offsets the clock’s rising edge from the center
simultaneously. Q11—What clock oscillator parameters besides
of the data window. Data reading then becomes
Differential logic jitter are important? Output rise/fall rate and
susceptible to jitter and other distortions. waveform symmetry have a direct role in mini-
devices respond mizing the effect of jitter. So can dual complemen-
tary outputs. Good engineering practice matches
Q10—What’s the jitter resisting benefit of dual to the signal the remaining specifications to the job.
complementary logic? Signal traffic traveling in difference be-
all directions on a printed circuit board brings to tween inputs, not to signals between input and
mind a busy railroad switching yard. Some of the ground. Put more technically, crosstalk and noise
PCB traces carry data signals, others haul DC become common-mode and are ignored in propor-
supplies, and most traces are potential receivers or tion to the device’s common mode rejection ratio
transmitters of transients and noise. (CMRR).

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Q11—What clock oscillator parameters besides instrument manufacturers offer communications
jitter are important. This FAQ article has already signal analyzers or oscilloscope-based systems for
highlighted several important oscillator param- jitter measurement and analysis. Among them:
eters. They include low jitter (typically below 10 Agilent, Tektronix, LeCroy and Wavecrest. Typi-
picoseconds RMS) Q1, fast rise rate Q8, and cal jitter measuring instruments present a compos-
waveform symmetry Q9. Dual complementary ite picture of waveform and jitter characteristics
outputs Q10 may be a luxury or a necessity, and statistics.
depending on the need for noise immunity.
The instrument analyzes the user-selected portion
Additional oscillator specifications of importance of a waveform, or measures the periods ofa signal.
include frequency, thermal stability, and long-term Illustration Q12 shows the rising edge of a high
stability. The operating voltage needs to be speci- speed, low jitter clock oscillator output. Clock
fied, as well as maximum load current. Oscillators waveform jitter is measured as each rising cycle
come in a variety of through hole and surface crosses a fixed voltage threshold. Many successive
mount packages—a further variable that needs to clock waveforms are superimposed on one another
be pinned-down. to “spread” the plot. The broader the jitter span,
the thicker the plot. The instrument then plots a
Q12—How do you measure jitter? Several
histogram of jitter characteristics in red (center,
bottom).

The jitter histogram affords insight into the

waveform’s behavior. Does it exhibit multiple
peaks? If so, it is likely that a dominant factor,
such as power supply ripple, is modulating the
clock. Alternatively, you may be measuring a clock
with significant amounts of sub-harmonic energy.
Is the histogram tall and narrow or short and fat?
Tall and narrow is usually the desired result,
implying a tight control over jitter.

A short and fat jitter distribution pattern, but

symmetrical about its peak, indicates a clock
oscillator that is inherently noisy. Or maybe the
clock’s spectrum has been purposely “spread” to
enhance EMI compliance.

Is the jitter distribution notably asymmetrical? Of

particular concern would be a hystogra where there
are unexplained outliers from a normal distribu-
tion. The outliers would cause “large displace-
ment” timing failures, and wreak havoc on bit
error rates in wireless systems.
Q12—How do you measure jitter? Typical jitter instrumentation permits a
section of the waveform to be selected and viewed in detail. In this display, the
jitter characteristics of a clock oscillator’s rising edge are analyzed. The in-
strument presents a section of the waveform (diagonal line) as it crosses a
fixed threshold voltage. The display includes a histogram of jitter behavior
(red) for the selected waveform section. In addition, the instrument determines
END
signal rise rate, peak-to-peak and RMS jitter values, plus additional analytical
information

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