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Lab 6

The document describes two digital circuit design tasks using dataflow modeling in Verilog. Task 1 designs a circuit to perform bitwise AND, OR, XOR, and XNOR operations on a 4-bit input and 4'b1001. Task 2 designs a circuit that performs an XNOR operation on two 5-bit inputs and conditionally shifts the result right by 3 bits depending on the value of a control bit input. Both circuits are tested using stimulus test benches and display output on LEDs.

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SHAHZAIB AHMAD QURESHI
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© © All Rights Reserved
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45 views

Lab 6

The document describes two digital circuit design tasks using dataflow modeling in Verilog. Task 1 designs a circuit to perform bitwise AND, OR, XOR, and XNOR operations on a 4-bit input and 4'b1001. Task 2 designs a circuit that performs an XNOR operation on two 5-bit inputs and conditionally shifts the result right by 3 bits depending on the value of a control bit input. Both circuits are tested using stimulus test benches and display output on LEDs.

Uploaded by

SHAHZAIB AHMAD QURESHI
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital System Design LAB 6

Spring 2021
Lab Report 6
DESIGN AND IMPLEMENTATION USING DATAFLOW
MODELING

Course: Digital System Design (EE 320L)

Resource Persons: Sir Awais Saeed

Prepared By:
Shahzaib Ahmad Qureshi: F2016019065
Digital System Design LAB 6

Objectives:
On successful completion of this lab, students will be able to:
a. Design and Implement the digital circuits using Dataflow level modeling.
b. Describe the continuous assignment (assign) statement, restrictions on the assign
statement, and the implicit continuous assignment statement.
c. Define expressions, operators, and operands.
d. Use operator types for all possible operations-arithmetic, logical, relational,
equality, bitwise, reduction, shift, concatenation, and conditional.
e. Use Dataflow level modeling constructs to model practical digital circuits in Verilog

Task1:
Take a 4 bit input from user and perform bit wise AND, OR, XOR, XNOR with 4’b1001 and display each
output on LEDs on nexus board.

Verilog Code:
module All_Gates(A,O,XO,XN,X);

output [3:0] A,O,XO,XN;

input [3:0] X;

assign A = (X & 4'b0101);

assign O = (X | 4'b0101);

assign XO = (X ^ 4'b0101);

assign XN = (X ~^ 4'b0101);

endmodule

Test-bench File:
module All_Gates_tb;

// Inputs

reg [3:0] X;

// Outputs

wire [3:0] A;

wire [3:0] O;

wire [3:0] XO;


Digital System Design LAB 6

wire [3:0] XN;

// Instantiate the Unit Under Test (UUT)

All_Gates uut (.A(A), .O(O), .XO(XO), .XN(XN), .X(X));

initial begin

// Initialize Inputs

X = 0000; #100;

X = 0001; #100;

X = 0010; #100;

X = 0011; #100;

X = 0100; #100;

X = 0101; #100;

X = 0110; #100;

X = 0111; #100;

X = 1000; #100;

X = 1001; #100;

X = 1010; #100;

X = 1011; #100;

X = 1100; #100;

X = 1101; #100;

X = 1110; #100;

X = 1111; #100;

// Add stimulus here

end

endmodule
Digital System Design LAB 6

OUTPUT:

Design Problem 1:
Design a digital circuit which takes one 1 bit input and two 5 bits inputs from the user and perform
XNOR operation. If one bit input is equal to 1 output the data and shift the data by 3 bits right if one bit
value is 0. Display the output on LEDs on nexus board

Verilog Code:
module Shift_Data(F,A,B,Control);

output [4:0] F;

input [4:0] A,B;

input Control;

assign F = (Control == 1'b1) ? ((A^~B) >> 3) : (A^~B);

endmodule

Test-bench File:
module Shift_Data_tb;

// Inputs

reg [4:0] A;

reg [4:0] B;

reg Control;

// Outputs
Digital System Design LAB 6

wire [4:0] F;

// Instantiate the Unit Under Test (UUT)

Shift_Data uut (.F(F), .A(A), .B(B), .Control(Control));

initial begin

// Initialize Inputs

A = 00000; B = 01010; Control = 0; #100;

A = 00000; B = 01010; Control = 1; #100;

A = 11110; B = 01011; Control = 0; #100;

A = 11110; B = 01011; Control = 1; #100;

A = 11110; B = 01000; Control = 0; #100;

A = 11110; B = 01000; Control = 1; #100; // Add stimulus here

end

endmodule

OUTPUT:

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