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CMOS Transceiver For Bluetooth

The document describes a fully integrated CMOS transceiver for Bluetooth. It includes all receiver and transmitter components on a single chip and operates at 2.4 GHz. It achieves low power consumption of 46-47 mA while maintaining good receiver sensitivity and transmitter output power.

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SRL MECH
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14 views

CMOS Transceiver For Bluetooth

The document describes a fully integrated CMOS transceiver for Bluetooth. It includes all receiver and transmitter components on a single chip and operates at 2.4 GHz. It achieves low power consumption of 46-47 mA while maintaining good receiver sensitivity and transmitter output power.

Uploaded by

SRL MECH
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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CMOS Transceiver for Bluetooth

A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in


receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive
and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator
(VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for
higher level of integration and lower power consumption. It achieves a sensitivity of 82
dBm at 0.1% BER, and a third-order input intercept point (IIP3) of 7 dBm. The direct-
conversion transmitter delivers a GFSK modulated spectrum at a nominal output power
of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of 120
dBc/Hz at 3-MHz offset.
The BLUETOOTH standard defines short-range wireless connection between
mobile phones, mobile PCs and other portable devices. It specifies a 2.4-GHz frequency-
hopped spread-spectrum system that enables the users to easily connect to a wide range
of computing and telecommunication devices without the need for wires or cabling of
any kind. Space and cost considerations are among the primary motivators for the drive
toward a single-chip radio solution. Bluetooth uses the unlicensed 2.4-GHz ISM band,
and supports a moderate data rate of 1 Mb/s. The modulation scheme is Gaussian binary
FSK (GFSK), with frequency deviations of +/-160 kHz around the carrier.
The transceiver uses a time division duplexing system. A Bluetooth device must
satisfy some certain requirements. It should be low cost and low power to integrate with
other portable devices efficiently, and yet it must have a robust performance to function
properly along with interferers. Such interferers exist in a noisy RF environment in which
several powerful radio signals are present in the proximity of the Bluetooth radio, such as
GSM or CDMA signals. This clearly spells great design challenges to realize such a high-
performance radio. It presents a low-power and highly integrated transceiver
implemented in a digital 0.35- m CMOS process. The all CMOS design allows the single-
chip integration of the radio and base band chips.
Fig. 1. Bluetooth transceiver architecture.

TRANSCEIVER ARCHITECTURE:
The radio transceiver is fully integrated, including RF and analog sections. The
size of the radio transceiver is minimized as a result of full integration of the system. The
transceiver architecture is based on a time-division duplexing (TDD) scheme, isolating
cross coupling between transmitter and receiver. Since the system is TDD, the
synthesizer can provide different RF local oscillators for the transmitter and receiver.
Specifically, the radio transceiver consists of the receiver, the transmitter, and clock
generator blocks, as shown in Fig. 1.
Receiver Architecture:
While direct-conversion architecture is best suitable for FSK receivers, it is not
used in this design based on the following reasons.
1) Unlike wide-band FSK modulation, GFSK spectrum has considerable energy at zero-
IF. Therefore, dc offset and flicker noise may significantly degrade the receiver
performance. Particularly, the flicker noise caused by the switches in a current-
commutating mixer may be of a magnitude that limits the overall noise figure of the
receiver.
2) A limiter at base band cannot be used, since the low-frequency components of the
GFSK spectrum produce harmonics which lie inside the desired signal down converted to
a zero IF. This degrades the signal-to-noise ratio (SNR) significantly. This problem may
be evaded if an automatic gain control (AGC) is used. However, AGC’s are complex and
dissipate more power.
On the other hand, a super heterodyne receiver maintains the signal at a higher IF,
typically 50 to 200 MHz, and therefore, it does not compete with flicker noise or dc
offset. However, super heterodyne receivers require off-chip filters for channel selection
and image rejection. This opposes the goal of single-chip integration, and disqualifies this
architecture. In addition to that, driving off-chip low-impedance filters increases the
overall receiver current consumption.
The proposed Bluetooth receiver uses a low-IF architecture with 2-MHz
intermediate frequency (Fig. 1). The 2-MHz IF positions the desired signal well beyond
the flicker noise corner. Moreover, the harmonics of the limited signal located at 6 MHz
and above, are easily removed by a post-limiter band pass filter (BPF). A higher IF (3
MHz or above) raises the power dissipation of the IF blocks. While an IF of 1 MHz is
also a possible choice, removing the dc offset and image signal is more difficult, since
they are closer to the desired channel. This disqualifies the choice of 1-MHz IF. Clearly,
the IF must be a multiple of 1 MHz to allow the selection of the desired Bluetooth
channel.
A low-noise amplifier (LNA) tuned to 2.4 GHz boosts the incoming signal, and
mixers driven by quadrature clock signals down convert it to a 2-MHz IF. A complex-
domain band pass filter centered at 2 MHz selects the desired channel, and rejects the
image signal which falls inside the ISM band, that is, four channels away from the
desired signal. Therefore, the image-reject requirement is relaxed and achieved by on-
chip complex BPF. Appropriate amount of gain is dispersed between the front-end blocks
to keep the noise and linearity as required the digital bits at the receiver output. Since the
frequency characteristics of the entire IF stages are determined by the RC time constant,
an RC calibration circuit is employed to tune RC to the reference crystal frequency (Fig.
1). All capacitors are implemented as digitally controlled switch able array of
capacitances. The RC calibration block produces the proper control word by measuring
the unit RC time constant.
Transmitter Architecture:
The transmitter uses direct-conversion architecture (Fig. 1) to achieve low power
consumption, and high level of integration. An on-chip modulator produces FSK signal
with 160-kHz frequency deviation at base band, Gaussian low-pass filters to shape the
spectrum. Single side-band mixers up convert the GFSK spectrum at base band to 2.4
GHz. A class-AB power amplifier (PA) delivers a typical output power of 4 dBm to 50 .
The PA linearity is not an issue, since the up converted spectrum carries the input signal
information in its phase, not amplitude. The RC calibration circuit tunes the frequency
response of the transmitter filters as well. Since the transmitter directly up converts the
base band spectrum to the ISM band, image rejection and LO suppression requirements
are relaxed, and achieved on chip. Other in-band Spurs are mainly produced due to the up
conversion mixer nonlinearity. Thus, the mixers must be designed to meet certain IP3

Fig. 2. Clock generator architecture

Set by the standard. The third-order input intercept point (IIP3) of the transmitter mixers
is about 15 dBm in this design. For a clean LO signal driving the transmitter mixers, out-
band spurs are mainly limited to the harmonics of the up converted signal. These spurs
are quite far from the carrier, and removed by on-chip tuned circuits at the transmitter
output. In a more practical scenario, the unwanted signals present at the mixer LO port
also lead to out-of-band spurs at the transmitter output. This issue is discussed in Section
the sole LO in a direct-conversion transmitter coincides in frequency with the large
modulated signal at the PA output (on the order of 500 mV in Bluetooth). Therefore, in
general, this architecture suffers from a major drawback, the disturbance of the local
oscillator by the PA, namely, LO pulling by the PA. This problem is more severe in a
system which integrates the voltage-controlled oscillator (VCO) and the PA on the same
chip. As discussed in the next section, a careful frequency plan avoids the pulling
problem in the direct-conversion transmitter.

Clock Generator Architecture:


As shown in Fig. 2, the clock generator consists of a divide- by-two which
produces 800-MHz and signals from the 1.6-GHz VCO, followed by two mixers which
generate quadrature clock signals at 2.4 GHz. Buffers between the stages provide
isolation, signal amplification, and filtering. The VCO frequency is 800 MHz away from
the PA output frequency, and thus, the transceiver is insensitive to direct or harmonic
pulling issues. Measurements show that the VCO frequency remains undisturbed at an
output power of up to +20 dBm, using an external power amplifier. Because of the hard-
switching action in a Gilbert-type mixer, such as the one used in the clock generator,
spurious signals accompany the desired 2.4-GHz clock. For a VCO frequency of, the
clock generator output can be expressed as

Equation (1) indicates that the m’th harmonic of the VCO output mixes with the
n’th harmonic of the divider output. The closest spurs are the lower sideband at 800
MHz, and the VCO third harmonic mixed with the divider output, producing a spur at 4
GHz. However, these spurs are attenuated by the on-chip LC filters at the
Fig. 3. Circuit of the low-noise amplifier.

Output of the clock generator mixer and its buffer. The on-chip inductors have a quality
factor of 5.5 at 2.4 GHz. Therefore each LC circuit attenuates the spur at 1.6 GHz away
by about 20 dB. These spurs will be rejected furthermore by the on-chip LC filters in the
receive and transmit paths. Measurements indicate that all the out-of-band spurs are
within the requirements set by the Bluetooth standard, without needing an off-chip
preselect filter. Compared to a conventional dual-conversion transceiver, the advantage of
the proposed architecture is that one step of frequency translation is performed inside the
clock generator, where noise or linearity are not an issue. Since mixers are inherently
noisy and nonlinear, this leads to a better performance at low power consumption.

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