176 IEEE TRANSACTIONS ON CIRCUITS AND ,SY,STEM,S—II: EXPRE,S,S BRIEFS, VOL. 64, NO.

2, FEBRUARY
2017

Design of Low-Power High-Performance 2—4 and

4-16 Mixed-Logic Line Decoders
Dimitrios Balobas and Nikos Konofaos

Afisfraci—This brief introduces a mixed-logic design method online at http://ieeexplore.ieee.org.

for line decoders, combining transmission gate logic, pass transis- Digital Object Identifier 10.1109/TCSII.2016.2555020
tor dual-value logic, and static complementary metal-oxide semi-
conductor (CMOS). Two novel topologies are presented for
the 2-4 decoder: a 14-transistor topology aiming on minimizing
tran- sistor count and power dissipation and a 15-transistor
topology aiming on high power-delay performance. Both normal
and invert- ing decoders are implemented in each case,
yielding a total of four new designs. Furthermore, four new 4—
16 decoders are designed by using mixed-logic 2—4 predecoders
combined with standard CMOS postdecoder. All proposed
decoders have full-swinging capability and reduced transistor
count compared to their con- ventional CMOS counterparts.
Finally, a variety of comparative spice simulations at 32 rim
shows that the proposed circuits present a significant
improvement in power and delay, outperforming CMOS in
almost all cases.
Index Z’erzn,s—Line decoder, mixed-logic, power-delay
optimization.

I. INTRODUCTION

S TATIC cmos circuits are used for the vast majority of

logic
gates in integrated circuits [1]. They consist of
complemen- tary N-type metal-oxide-semiconductor(nMOS)
pulldown and P-type metal-oxide semiconductor (pMOS)
pullup networks and present good performance as well as
resistance to noise and device variation. Therefore,
complementary metal-oxide semiconductor (CMOS) logic is
characterized by robustness against voltage scaling and
transistor sizing and thus reliable operation at low voltages
and small transistor sizes [2]. Input signals are connected to
transistor gates only, offering reduced design complexity and
facilitation of cell-based logic synthesis and design.
Pass transistor logic (PTL) was mainly developed in the
1990s, when various design styles were introduced [3]—[6],
aiming to provide a viable alternative to CMOS logic and im-
prove speed, power, and area. Its main design difference is
that inputs are applied to both the gates and the source/drain
diffu- sion terminals of transistors. Pass transistor circuits are
imple- mented with either individual nMOS/pMOS pass
transistors or parallel pairs of nMOS and pMOS called
transmission gates.
Line decoders are fundamental circuits, widely used in the
peripheral circuitry of memory arrays (e.g., SRAM) [7]—[9].
This brief develops a mixed-logic methodology for their im-

Manuscript received November 2, 2015; accepted April 5, 2016. Date

of
publication April 15, 2016; date or current ver,sion January 27, 2017.
This brief was recommended by Associate Editor C. K. Tse.
The authors are with the Department of Informatics, Aristotle
University of The,s,saloniki, 54124 Thessaloniki, Greece (e-mail:
dmpaloinpHcsd.auth.gr; nkonofaoHcsd.auth.gr).
Color ver,sion,s of one or more of the figures in thi,s brief are available
 TABLE I II. OVERVIEW OF LINE DECODER CIRCUITS
TRUTH TABLE OF THE 2—4 DECODER
In digital systems, discrete quantities of information are
repre- sented by binary codes. An n-bit binary code can
represent up to 2‘ distinct elements of coded data. A decoder
is a combina- tional circuit that converts binary information
from n input lines to a maximum of 2“ unique output lines or
fewer if the n-bit coded information has unused combinations.
TAB LE II The circuits ex- amined here are n-to-tn line decoders,
TRUTH TAB LE OF THE INVERTING 2—4
DECODER which generate the rn = 2‘ minterms of n input variables.

A. 2—4 Line Decoder

A 2—4 line decoder generates the 4 minterms D9 —3 of
2 input variables A and &. Its logic operation is
summarized in Table I. Depending on the input
plementation, opting for improved performance compared combination, one of the 4 outputs is selected and set to 1,
to single-style design. while the others are set to 0. An inverting 2—4 decoder
The rest of this brief is organized as follows: Section II generates the complementary minterms Jo-3. thus the
provides a brief overview of the examined decoder selected output is set to 0 and the rest are set to 1, as shown
circuits, implemented with conventional CMOS logic. in Table II. In conventional CMOS design, NAND and
Section III in- troduces the new mixed-logic designs. NoR gates are preferred to AND and OR, since they can be
Section IV conducts a comparative simulation study implemented with 4 transistors, as opposed to 6, therefore
among the proposed and con- ventional decoders, with a implementing logic functions with higher efficiency. A 2—
detailed discussion on the derived results. Section V 4 decoder can be implemented with 2 inverters and 4 NOR
provides the summary and final conclusions of the work gates Fig. 1(a), whereas an inverting decoder requires 2
presented. inverters and 4 NAND gates Fig. 1(b), both yielding 20
transistors.

1549-7747 O 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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BALOBAS AND KONOFAO,S: LOW-POWER HIGH-PERFORMANCE 2—4 AND 4—16 MIXED-LOGIC LINE DECODER,S 177
and

(a) (b)

Fig. 1. 20-transistor 2—4 line decoders implemented with CMOS logic.

(a) Noninverting NOR-based decoder. (b) liiverting NAND-based decoder.

Fig. 2. 104-transistor 4—16 line decoders implemented with CMOS logic

and predecoding. (a) Noninverting decoder implemented with two 2—4
inverting predecoders and a NOE-based po,stdecoder. (b) Inverting decoder
implemented with two 2—4 noninverting predecoders and a NAND-
based postdecoder.

B. 4—16 Line Decoder With 2—4 Predecoder,s

A 4-16 line decoder generates the 16 minterms Dg - z of
4 input variables A, B, C, and D, and an inverting 4—16
line decoder generates the complementary minterm o—i
Such circuits can be implemented using a predecoding
technique, according to which blocks of n address bits can
be predecoded into 1-of-2 predecoded lines that serve as
inputs to the final stage decoder [1]. Therefore, a 4—16
decoder can be imple- mented with 2 2—4 inverting decoders
and 16 2-input NOR gates [Fig. 2(a)], and an inverting one
can be implemented with 2 2—4 decoders and 16 2-input
NAND gates [Fig. 2(b)]. In CMOS logic, these designs
require 8 inverters and 24 2-input gates, yielding a total of
104 transistors each.

III. NEW MIXED-LOGIC DESIGNS

Transmission gate logic (TGL) can efficiently implement

AND/OR gates [5], thus it can be applied in line decoders.
The 2-input TGL AND/OR gates are shown in Fig. 3(a)
and (b), respectively. They are full-swinging, but not
restoring for all input combinations.
Regarding PTL, there are two main circuit styles: those
that use nMOS-only pass transistor circuits, like CPL [3],
Fig. 3. Three-tran,si,stor AND/oR gates con,sidered in thi,s work. (a) TGL
AND gate. (b) TGL ox gate. (c) DVL AND gate. (d) DvL oR gate.

those that use both nMOS and pMOS pass transistors,

like DPL [4] and DVL [6]. The style we consider in this
work is DVL, which preserves the full swing operation
of DPL with reduced transistor count [10]. The 2-input
DVL AND/oR gates are shown in Fig. 3(c) and (d),
respectively. They are full- swinging but non-restoring,
as well.
Assuming that complementary inputs are available, the
TGL/DVL gates require only 3 transistors. Decoders are
high fan-out circuits, where few inverters can be used by
multiple gates, thus using TGL and DVL can result to
reduced transistor count. An important common
characteristic of these gates is their asymmetric nature, ie
the fact that they do not have balanced input loads. As
shown in Fig. 3, we labeled the 2 gate inputs A and V. In
TGL gates, input A controls the gate terminals of all 3
transistors, while input V propagates to the output node
through the transmission gate. In DVL gates, input A
controls 2 transistor gate terminals, while input V
controls 1 gate terminal and propagates through a pass
transistor to the output. We will refer to A and V as the
control signal and propagate signal of the gate,
respectively.
Using a complementary input as the propagate signal
is not a good practice, since the inverter added to the
propagation path increases delay significantly. Therefore,
when implementing the inhibition (A'B) or implication
(A' + B) function, it is more efficient to choose the
inverted variable as control signal. When implementing
the AND (AB) Or OR (A + B) function, either choice is
equally efficient. Finally, when implementing the NAND
(A’ -}- &') or NOR (A'B') function, either choice results
to a complementary propagate signal, perforce.

A. 14-Transi,stor 2—4 Low-Power Topolog y

Designing a 2—4 line decoder with either TGL or DVL
gates would require a total of 16 transistors (12 for
AND/oR gates and 4 for inverters). However, by mixing
both AND gate types into the same topology and using
proper signal arrangement, it is possible to eliminate one
of the two inverters, therefore reducing the total
transistor count to 14.
Let us assume that, out of the two inputs, namely, A
and B, we aim to eliminate the B inverter from the circuit.
The D minterm (A’B') is implemented with a DVL gate,
where A is used as the propagate signal. The D 1 minterm
(AB') is implemented with a TGL gate, where B is used
as the propagate signal. The D2 minterm (A'B) is
implemented with a DVL gate, where A is used as the
propagate signal. Finally, The Dz minterm (AB) is
implemented with a TGL gate, where B is used as the
propagate signal. These particular choices completely
avert the use of the complementary B signal;
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