Kogge Stone Adder with GDI Technique in 130nm

Technology for High performance DSP Applications

Bujjibabu Penumutchi,IEEE Member Satyanarayana Vella,AMIETE Harichandraprasad Satti
Associate Professor Associate Professor Assistant Professor
Dept.of ECE,AEC-533437 Dept.of ECE,AEC-533437 Dept.of ECE,AEC-533437
Email:bujjibabu82foru@gmail.com Email: vasece453@gmail.com Email: hariprasad.aec@gmail.com

Abstract—In VLSI system, the integrated circuit design has is due to the propagation of carry from initial stage to final
modest importance. The important parameters considered for stage.
the design of the circuit are power, delay, area and complexity
of the circuit. Binary adder is the fundamental element in
the digital circuit design viz., multipliers and digital signal
processors. Nowadays, extensive research is focused on reducing
the power consumption, and delay in the computation. There are
different types of adders, but these are not dominant in terms
of propagation delay. The adder with less time for computation
is preferred in such a high speed applications. So, in order to
optimize the delay, parallel prefix adders like Kogge Stone Adder
is preferred. It is the fastest adder which focuses on design
time and is said to be a good alternative for high performance
applications. The speedy nature of Kogge Stone Adder (KSA) Fig. 1. Ripple Carry Adder
is because of minimum logic depth and restricted fan-out. In
KSA, parallel advance will give scope to generate fast carry for
intermediate stages. Each level generates Propagation Generation B. Carry Look Ahead Adder (CLA):
(PG) blocks simultaneously. Among all types of 64 bit adders, a
KSA has less delay (11.37ns). In this work, a 64 bit GDI logic CLA enhances the speed by lowering the amount of time
based KSA schematic is designed by using Mentor Graphics required to resolve carry bits. CLA works by creating two
EDA Tool in 130nm Technology. Performance parameters like signals, viz., carry propagator and carry generator. The carry
delay, average power consumption (at various dimensions of MOS propagator is propagated to the next levels where as carry
transistors and over a range of supply voltages) are measured
and the best adder in terms of performance is observed as the generator is used to generate output carry in spite of of input
one with a delay of 407.07ps designed in GDI Technique. carry. Kogge-Stone Adder (KSA) is an example of CLA.
Keywords—Propagation delay, parallel prefix adders, GDI
logic, Kogge Stone Adder (KSA), Propagation Generation (PG).

I. I NTRODUCTION
An adder is a digital circuit used to get summation as
output from the given inputs. In computers and other kinds of
processors these summing networks are used in the arithmetic
logic units. Besides, they are also used to calculate addresses,
table indice, increment, and decrements operations. The adders
can be constructed for different number representations, such
as binary-coded decimal or excess-3.The most common adders
operate on binary numbers. Though many adders are available, Fig. 2. Carry Look Ahead Adder
the selection of adder will be based on parameters, viz. area,
power consumption and time of computation
C. Carry-Select Adder (CSA):
A. Ripple Carry Adder)(RCA): The CSA usually consists of two ripple carry adders and
It is a logical circuit to add an N-bit numbers. For an N-bit a multiplexer. Adding two n-bit numbers with a carry-select
parallel adder it is required use N number of Full Adder (FA). adder is done with two adders (therefore two ripple carry
Here, the carry out of each FA is the carry in of the next most adders) to carry out the computation twice, one time with the
significant FA. The delay of the ripple carry adder will change assumption of the carry-in is being a logic zero and the other
w.r.t length of the carry propagator path. The worst case delay assuming as logic one. After the two results are calculated, the

978-1-5386-0569-1$31.00 2017
c IEEE 5
correct sum, and the correct carry-out, is then selected with TABLE I
the multiplexer.. [?] once the correct carry-in is also finalized. D ELAY COMPARISON BETWEEN ADDERS

S.No Name of the Adder Delay[nS] Pt[mW]

1 Ripple Carry Adder 14.946 44.35
2 Carry Look Ahead Adder 14.806 48.88
3 Carry Select Adder 15.262 49.60
4 Carry Skip Adder FBS 15.042 44.79
5 Carry Skip Adder VBS 15.042 44.81
6 Kogge Stone Adder 12.477 48.97

and adds up the multiplexers too and is not a good choice in

terms of hardware. The most competent way to add numbers
is by the use of Kogge Stone Adder in which the number
is added bit by bit with high computational speed [15]. In
the above architecture, there are three propagator generator
Fig. 3. Ripple Carry Adder blocks represented with three different colors. The continuous
dimension drop driven by Moores law and the corresponding
decrease of the supply voltage (needed to maintain the electric
D. Kogge - Stone Adder (KSA): field on the transistor gates constant) causes a huge raise in the
The KSA was developed by PETER M KOGGE and static power consumption, taking it reverse to a non negligible
HEROLD S STONE. The adder uses the concept of gener- basis of consumption. There are two primary reasons and the
ating and propagating carriers [1]–[3]. It is the fastest adder former is the reduction of the threshold voltage imposed by
which focuses on design time and is common choice for the Vdd reduction in order to preserve the speed to a tolerable
high performance adder [13], [15].The better throughput of level, and the later is the new electrical effects originated by
KSA is because of minimum logic depth and confined fan the decrease in the transistors geometries, like Drain Induced
out. Delay comparison results of different two operand 64 Barrier Lowering (DIBL) and Punch through effect, and Hot
Electrons effect.

II. KOGGE STONE ADDER (KSA) DESIGN

The performance of any complex system is interdependent
of respective sub system performance. Particularly, in data
processing systems like DSPs, the speed of computation is
dominated by the individual performance of adders/multiplier
modules. KSA is one among them which is used for high
speed addition even for large numbers. In 1973, Kogge and
Stone came up with the idea of parallel-prefix [18]computation
[1], [7].The Kogge Stone adder [2] comprises of three stages
like Pre- processing Stage, Carry generation Stage and Post-
Processing Stage. In the pre-processing stage propagation and
generation signals are generated. Carry Generation used to
generate carry for the next stages and finally Post-processing
Stage is used to generate Sum and carry out bit. From the
pre-processing stage P(a,b) and G(a,b) Signals are available
such viz.

P (a, b) = A + B, G(a, b) = A.B (1)

Fig. 4. Kogge Stone Adder general architecture
From the Carry Generation Stage we get the Black
bit adders [4], [5]in Xilinx are obtained as given in Table cell and Grey Cells.The equations for those are
I. From the above table, it is concluded that Kogge Stone
Adder has less delay. Ripple Carry Adder [1], [8], [13], [14] Gblack = (Gprev.P ) + G (2)
is the most key adder made just by joining adders with P black = (P.P prev)AN DGgrey = (Gprev.P ) + G (3)
no exercise on speed. As the speed increases in carry look
ahead adder, its hardware becomes complex [6] which would Sum and Carry out bit is generated in the Post-Processing
play a adverse role in addition of numbers with large word Stage.
lengths. Carry Select Adder almost doubles its components Sn = (P nORCn − 1) (4)

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The carry generate, (G) and the carry Propagate (P) values can
be combined before being used. The three fundamental gates
that are required to design the KSA are, CMOS AND, OR,
and EXOR gates. In the first block, Propagator is obtained
by EX-OR of two input bits and Generator is obtained by
AND of two input bits. In the second block, the propagator

Fig. 7. Second block RTL diagram

Fig. 5. Pre-Processing stage RTL diagram

bit is obtained by AND of present state propagator bit and

previous state propagator bit. Generator is obtained by AND
of present state propagator input with previous state generator
input which is then OR with present state generator input.The
generator bit is obtained by AND of previous state propagator
Fig. 8. Kogge Stone Adder for two 16 bit Addition
and previous state generator bits which is then OR with present
state generator bit. These three blocks will be used to design
a 16 bit Kogge Stone Adder which is given in the following
figure.Using the 16 bit KSA as sub module, the 64 bit KSA of transistors results in low power [16] dissipation besides
is designed and simulated using mentor graphics with 130nm the optimization in the speed of computation. Fewer number
technology in CMOS configuration. The delay of basic 64 bit of transistors will results in producing the IC with small
KSA is 49.894ns and the power is 18.313 watts. The delay area along with effectiveness in resultant interconnections,
and power can be further reduced by using GDI technique. reduced number of DRCs so that much reduced maintenance
and production cost. So GDI technique [11], [12] is used
to reduce the parameters like delay, power and area with
controllable figures of RE and NRE costs. By comparing
two schematics (one is in conventional CMOS and the other
is using GDI technique) it is observed that the number of
transistors required to design a CMOS OR gate is 6, where as

Fig. 6. Carry Propagator and Carry Generator RTL diagram

III. GDI TECHNIC

However, using a lower VDD increases the delay. The alter-
nate way of decreasing the power dissipation is by reducing the
number of switching transistors. Circuit with reduced number Fig. 9. Simulation results from 16 bit KSA

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the number of transistor are reduced to 2 by using this GDI
technique. As described earlier, the advantages come with the
number of transistors reduction by using this technique. The

Fig. 10. OR gate in CMOS and GDI logic

GDI cell is similar to a CMOS inverter structure. In a CMOS

inverter the source of the PMOS is connected to VDD and the Fig. 11. GDI based AND21 gate schematic diagram
source of NMOS is grounded. But in a GDI cell this might
not necessarily occur. There are some important differences
between the two. The three inputs in GDI are namely-
G- common inputs to the gate of NMOS and PMOS
N- input to the source/drain of NMOS
P- input to the source/drain of PMOS
Bulks of both NMOS and PMOS are connected to N or
P (respectively),that is it can be arbitrarily biased unlike
in CMOS inverter. Moreover, the most important difference
between CMOS and GDI is that in GDI N, P and G terminals
could be given a supply VDD or can be grounded or can
be supplied with input signal depending upon the circuit to
be designed and hence effectively minimizing the number of
transistors used in case of most logic circuits (eg. AND, OR, Fig. 12. GDI based AND21 gate test bench
XOR, MUX, etc). As the allotment of supply and ground to
PMOS and NMOS is not fixed in case of GDI, therefore,
problem of low voltage swing arises which is a disadvantage
and hence finds difficulty in case of development of analog
circuits. As major part of the switching power dissipation is
contributed by the capacitance of MOSFET, it is observed
that the reduction in number of transistors also reduces the
depletion capacitance part in the total load capacitance CL.
By using GDI technique one can design fast low power
circuits through less number of transistors.In GDI technique,
the ports are connected in such a way that the CMOS inverter
could be reconfigured to work as two input AND gate. Input
a is supplied to gate terminals of both PMOS and NMOS
transistors. Drain of NMOS is connected with input b, where Fig. 13. GDI based AND21 gate simulation results
as drain of PMOS is connected to ground as shown in Fig 14.
It is observed that the ports at the Inverter are connected in
such a way that the CMOS Inverter could be reconfigured to
work as two input AND gate.

TABLE II
P OWER DISSIPATION IN GDI TWO INPUT OR GATE @ DIFFERENT VDD

Vdd Vgs1[V] Vgs2[V] Wp[U] Wn[U] Delay[pS] Power[nW]

2.5 2.0 2.0 0.15 0.15 244.45 21.693
2.5 2.0 2.0 0.45 0.15 256.53 24.276
2.5 2.0 2.0 0.30 0.15 204.13 29.485
2.5 3.3 2.0 0.15 0.15 69.073 28.685
2.0 2.0 2.0 0.15 0.15 212.93 16.080
2.0 2.0 2.0 0.45 0.15 242.69 20.058
2.0 3.3 3.3 0.45 0.15 117.70 24.04m
Fig. 14. GDI based OR21 gate Schematic diagram
2.0 3.3 3.3 0.30 0.15 049.92 254.5u

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 Fig. 15. GDI based OR21 gate test bench

Fig. 19. GDI based ExOR21 gate Simulation results

We are considering the delay and power by varying different

parameters and a better case with best delay and power is taken
and it is used for designing of Kogge Stone Adder to get high
performance. The same procedure is followed for GDI AND,
OR AND EX-OR gates. With the reference of 16 bit KSA, 64
bit KSA is designed and is given in figure below:

Fig. 16. GDI based OR21 gate simulation results

Fig. 20. 64 bit KSA Schematic in GDI Technique

Fig. 17. GDI based ExOR21 gate Schematic diagram

Fig. 21. GDI based 64 bit KSA Simulation results

In current scenario, the KSA is run with different supply

voltages at gate and even the probability is verified wrt variable
Fig. 18. GDI based ExOR21 gate test bench
voltages at different gate terminals of the transistors with
which internal sub modules (basic gates) are designed. Thus,
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Much more advanced tool support is required to design KSA
with the exact expected performance.
ACKNOWLEDGMENT
We would like to thank the people from AOKI Laboratory
for their support towards the analysis, and also the manage-
ment,Aditya Engineering College,Surampalem who allowed us
to work on MentorGraphics EDA Tools.We also thankful to
PG and UG students for their continues work in getting the
required data.
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