PD- 95146

IRFB4710PbF
IRFS4710PbF
IRFSL4710PbF
HEXFET® Power MOSFET
Applications VDSS RDS(on) max ID
l High frequency DC-DC converters
l Motor Control
100V 0.014Ω 75A
l Uninterrutible Power Supplies
l Lead-Free
Benefits
l Low Gate-to-Drain Charge to Reduce
Switching Losses
l Fully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
l Fully Characterized Avalanche Voltage TO-220AB D2Pak TO-262
IRFB4710 IRFS4710 IRFSL4710
and Current

Absolute Maximum Ratings

Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 75
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 53 A
IDM Pulsed Drain Current  300
PD @TA = 25°C Power Dissipation ‡ 3.8 W
PD @TC = 25°C Power Dissipation 200
Linear Derating Factor 1.4 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery dv/dt ƒ 8.2 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting torqe, 6-32 or M3 screw† 10 lbf•in (1.1N•m)

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.74
RθCS Case-to-Sink, Flat, Greased Surface † 0.50 ––– °C/W
RθJA Junction-to-Ambient† ––– 62
RθJA Junction-to-Ambient‡ ––– 40

Notes  through ‡ are on page 11

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IRFB/IRFS/IRFL4710PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.11 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 0.011 0.014 Ω VGS = 10V, ID = 45A „
VGS(th) Gate Threshold Voltage 3.5 ––– 5.5 V VDS = VGS, ID = 250µA
––– ––– 1.0 VDS = 95V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 80V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V

Dynamic @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 35 ––– ––– S VDS = 50V, ID = 45A
Qg Total Gate Charge ––– 110 170 ID = 45A
Qgs Gate-to-Source Charge ––– 43 ––– nC VDS = 50V
Qgd Gate-to-Drain ("Miller") Charge ––– 40 ––– VGS = 10V,
td(on) Turn-On Delay Time ––– 35 ––– VDD = 50V
tr Rise Time ––– 130 ––– ns ID = 45A
td(off) Turn-Off Delay Time ––– 41 ––– R G = 4.5Ω
tf Fall Time ––– 38 ––– VGS = 10V „
Ciss Input Capacitance ––– 6160 ––– VGS = 0V
Coss Output Capacitance ––– 440 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 250 ––– pF ƒ = 1.0MHz
Coss Output Capacitance ––– 1580 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 280 ––– VGS = 0V, VDS = 80V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance ––– 430 ––– VGS = 0V, VDS = 0V to 80V …

Avalanche Characteristics
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy‚ ––– 190 mJ
IAR Avalanche Current ––– 45 A
EAR Repetitive Avalanche Energy ––– 20 mJ

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D

––– ––– 75
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 300

(Body Diode) † p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 45A, VGS = 0V „
trr Reverse Recovery Time ––– 74 110 ns TJ = 25°C, IF = 45A
Qrr Reverse RecoveryCharge ––– 180 260 nC di/dt = 100A/µs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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1000 VGS 1000 VGS
TOP 15V TOP 15V
12V 12V
10V 10V
I D , Drain-to-Source Current (A)

8.0V

I D , Drain-to-Source Current (A)

8.0V
100 7.5V 7.5V
7.0V 7.0V
6.5V 6.5V
BOTTOM 6.0V BOTTOM 6.0V
100
10

1
6.0V
10

6.0V
0.1

0.01

20µs PULSE WIDTH
T = 25 C
J °
1

20µs PULSE WIDTH
T = 175 C
J °

0.1 1 10 100 0.1 1 10 100

VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 3.0

ID = 75A
R DS(on) , Drain-to-Source On Resistance

2.5
I D , Drain-to-Source Current (A)


TJ = 175 ° C
100
2.0
(Normalized)

10 1.5


TJ = 25 ° C 1.0
1

0.5

0.1
 V DS = 50V
20µs PULSE WIDTH 
VGS = 10V
0.0
6.0 7.0 8.0 9.0 10.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( °C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature
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 IRFB/IRFS/IRFL4710PbF

20
10000
VGS = 0V, f = 1 MHZ 
ID = 45A


Ciss = Cgs + Cgd, Cds SHORTED VDS = 80V
VDS = 50V

VGS , Gate-to-Source Voltage (V)

Crss = Cgd
8000 16 VDS = 20V
Coss = Cds + Cgd
C, Capacitance(pF)

Ciss
6000 12

4000 8

2000 4
Coss

0
Crss
0
 FOR TEST CIRCUIT
SEE FIGURE 13
1 10 100 0 40 80 120 160 200
VDS, Drain-to-Source Voltage (V) QG , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 1000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ISD , Reverse Drain Current (A)

ID , Drain-to-Source Current (A)

100 100


TJ = 175 ° C 100µsec
10 10

1msec

TJ = 25 ° C
1
1
Tc = 25°C 10msec
Tj = 175°C
Single Pulse

V GS = 0 V 0.1
0.1
0.0 0.4 0.8 1.2 1.6 1 10 100 1000
VSD ,Source-to-Drain Voltage (V) VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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 IRFB/IRFS/IRFL4710PbF

80 RD
VDS

VGS
D.U.T.
60 RG
+
-VDD
I D , Drain Current (A)

10V
Pulse Width ≤ 1 µs
40
Duty Factor ≤ 0.1 %

Fig 10a. Switching Time Test Circuit

20
VDS
90%

0
25 50 75 100 125 150 175
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs. td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

1
Thermal Response (Z thJC )

D = 0.50

0.20


0.1 0.10

0.05 P DM

0.02  SINGLE PULSE

(THERMAL RESPONSE)
t1

0.01 t2

0.01
 Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC

0.00001 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRFB/IRFS/IRFL4710PbF


350
1 5V
ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP 18A
300 32A
BOTTOM 45A
L D R IV E R
VD S
250

RG D .U .T + 200
- VD D
IA S A
2V0GS
V
tp 0 .0 1 Ω 150

Fig 12a. Unclamped Inductive Test Circuit 100

50
V (B R )D SS
tp
0
25 50 75 100 125 150 175
Starting TJ , Junction Temperature ( °C)

Fig 12c. Maximum Avalanche Energy

IAS Vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Current Regulator
Same Type as D.U.T.

QG
50KΩ

10 V 12V .2µF
.3µF
QGS QGD +
V
D.U.T. - DS

VG VGS

3mA

IG ID
Charge Current Sampling Resistors

Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

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 IRFB/IRFS/IRFL4710PbF

Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T
• Low Stray Inductance
• Ground Plane
ƒ
• Low Leakage Inductance
Current Transformer
-

+
‚
„
- +
-


RG • dv/dt controlled by RG +
• Driver same type as D.U.T. VDD
-
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test

Driver Gate Drive

P.W.
Period D=
P.W. Period

VGS=10V *

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 14. For N-Channel HEXFET® Power MOSFETs

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IRFB/IRFS/IRFL4710PbF

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

1 0 .5 4 (.4 1 5 ) 3 .7 8 (.1 4 9 ) -B -
2 .8 7 (.1 1 3 ) 1 0 .2 9 (.4 0 5 ) 3 .5 4 (.1 3 9 ) 4 .6 9 (.1 8 5 )
2 .6 2 (.1 0 3 ) 4 .2 0 (.1 6 5 )
-A - 1 .3 2 (.0 5 2 )
1 .2 2 (.0 4 8 )
6 .4 7 (.2 5 5 )
6 .1 0 (.2 4 0 )
4
1 5 .24 ( .6 0 0 )
1 4 .84 ( .5 8 4 )
LEAD ASSIGNMENTS
1 .1 5 (.0 4 5 ) L E A D A S S IG N M E N T S
M IN HEXFET IGBTs, CoPACK
1 - GATE
1 2 3 1- GATE 2 - D R A IN 1- GATE
2- DRAIN 3 - S O U R C E 2- COLLECTOR
3- SOURCE4 - D R A IN 3- EMITTER
4- DRAIN 4- COLLECTOR
1 4 .0 9 (.5 5 5 )
1 3 .4 7 (.5 3 0 ) 4 .0 6 ( .1 6 0 )
3 .5 5 ( .1 4 0 )

0 .9 3 (.0 3 7 ) 0 .5 5 (.0 2 2 )
3X 3X
0 .6 9 (.0 2 7 ) 0 .4 6 (.0 1 8 )
1 .4 0 (.0 5 5 )
3X
1 .1 5 (.0 4 5 ) 0 .3 6 (.0 1 4 ) M B A M
2 .9 2 (.1 1 5 )
2 .6 4 (.1 0 4 )
2 .5 4 (.1 0 0 )
2X
N O TE S :
1 D IM E N S IO N IN G & T O L E R A N C IN G P E R A N S I Y 1 4 .5 M , 1 9 8 2 . 3 O U TL IN E C O N F O R M S TO J E D E C O U T L IN E TO -2 2 0 A B .
2 C O N T R O L L IN G D IM E N S IO N : IN C H 4 H E A T S IN K & L E A D M E A S U R E M E N TS D O NO T IN C L U D E B U R R S .

TO-220AB Part Marking Information

E XAMPL E : T HIS IS AN IR F1010

LOT CODE 1789
AS S E MB LE D ON WW 19, 1997 INT E RNAT IONAL PAR T NU MB E R
IN T HE AS S E MBL Y L INE "C" RE CT IF IE R
L OGO
Note: "P" in assembly line
position indicates "Lead-Free" DAT E CODE
YE AR 7 = 1997
AS S E MB LY
LOT CODE WE E K 19
L INE C

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 IRFB/IRFS/IRFL4710PbF

D2Pak Package Outline

Dimensions are shown in millimeters (inches)

D2Pak Part Marking Information (Lead-Free)

T H I S IS AN IR F 53 0S WIT H P AR T N U MB E R
L OT COD E 80 24 IN T E R N AT ION AL
AS S E MB L E D ON WW 0 2, 20 00 R E CT IF IE R F 53 0S
IN T H E AS S E MB L Y L INE "L " L OGO
D AT E COD E
N ote: "P " in as s embly line YE AR 0 = 2 00 0
pos ition indicates "L ead-F ree" AS S E MB L Y
L OT COD E WE E K 02
L IN E L

OR
P AR T N U MB E R
IN T E R N AT ION AL
R E CT IF IE R F 530 S
L OGO
D AT E COD E
P = D E S IGN AT E S L E AD -F R E E
AS S E MB L Y P R OD U CT (OP T ION AL )
L OT COD E Y E AR 0 = 2000
WE E K 02
A = AS S E MB L Y S IT E COD E

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IRFB/IRFS/IRFL4710PbF
TO-262 Package Outline

TO-262 Part Marking Information

E XAMPL E : T H IS IS AN IR L 3103L
L OT CODE 1789 PAR T NU MB E R
INT E R NAT IONAL
AS S E MB L E D ON WW 19, 1997
R E CT IF IE R
IN T H E AS S E MB L Y L INE "C" L OGO
Note: "P " in as s embly line DAT E CODE
pos ition indicates "L ead-F ree" YE AR 7 = 1997
AS S E MB L Y
L OT CODE WE E K 19
L INE C

OR
PAR T NU MB E R
INT E R NAT IONAL
R E CT IF IE R
L OGO
DAT E CODE
P = DE S IGNAT E S L E AD-F R E E
AS S E MB L Y PR ODU CT (OPT IONAL )
L OT CODE YE AR 7 = 1997
WE E K 19
A = AS S E MB L Y S IT E CODE

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D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)

TR R

1 .60 (.0 6 3 )
1 .50 (.0 5 9 )
1 .6 0 (.0 6 3 )
4 .10 (.16 1 ) 1 .5 0 (.0 5 9 )
3 .90 (.15 3 ) 0 .3 6 8 (.0 1 4 5 )
0 .3 4 2 (.0 1 3 5 )

F E E D D I R E C T IO N 1 .8 5 (.07 3 ) 1 1 .6 0 (.4 5 7 )
1 .6 5 (.06 5 ) 1 1 .4 0 (.4 4 9 ) 2 4 .3 0 (.9 5 7 )
1 5 .4 2 (.6 0 9 )
2 3 .9 0 (.9 4 1 )
1 5 .2 2 (.6 0 1 )
TR L
1 .7 5 (. 0 6 9 )
1 0 .9 0 (.4 2 9 ) 1 .2 5 (. 0 4 9 )
1 0 .7 0 (.4 2 1 ) 4 .7 2 (.1 3 6 )
1 6 .1 0 ( .6 3 4 ) 4 .5 2 (.1 7 8 )
1 5 .9 0 ( .6 2 6 )

F E E D D IR E C T I O N

1 3 .5 0 (.5 3 2 ) 2 7 .40 (1 .0 7 9)
1 2 .8 0 (.5 0 4 ) 2 3 .90 (.9 4 1 )

330.00 6 0 .0 0 (2 .3 6 2)
(14.173) M IN .
M AX .

3 0 .4 0 (1 .19 7 )
N O TES : M AX.
1 . C O M F O R M S T O E IA- 4 1 8. 26.40 (1.039) 4
2 . C O N T R O L L IN G D IM E N S IO N : M ILL IM E T E R . 24.40 (.961)
3 . D IM E N S IO N M E A S U R E D @ H U B .
3
4 . IN C L U D E S F L A N G E D IS T O R T IO N @ O U T E R E D G E .

Notes:
 Repetitive rating; pulse width limited by „ Pulse width ≤ 400µs; duty cycle ≤ 2%.
max. junction temperature.
‚ Starting TJ = 25°C, L = 190µH … Coss eff. is a fixed capacitance that gives the same charging time
RG = 25Ω, IAS = 45A, VGS = 10V as Coss while VDS is rising from 0 to 80% VDSS
ƒ ISD ≤ 45A, di/dt ≤ 420A/µs, VDD ≤ V(BR)DSS, † This is only applied to TO-220AB package
TJ ≤ 175°C
‡ This is applied to D2Pak, when mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.04/04
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/