MAX9273 22-Bit GMSL Serializer With Coax or STP Cable Drive: General Description Benefits and Features

EVALUATION KIT AVAILABLE
MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
General Description Benefits and Features
The MAX9273 compact serializer is designed to drive S Ideal for Camera Applications
50I coax or 100I shielded twisted-pair (STP) cable.  Drives Low-Cost 50I Coax Cable and FAKRA
The device pairs with the MAX9272 deserializer. The Connectors or 100I STP
parallel input is programmable for single or double input.  Error Detection/Correction
Double input allows higher pixel clock input frequency by  9.6kbps to 1Mbps Control Channel in I2C-to-I2C
registering two pixels of typical image-sensor video data Mode with Clock Stretch Capability
before serializing. This doubles the maximum pixel clock  Best-in-Class Supply Current: 75mA (max)
frequency compared to single input.  Double-Rate Clock for Megapixel Cameras
The device features an embedded control channel that  Serializer Pre/Deemphasis Allows 15m Cable at
Full Speed
operates at 9.6kbps to 1Mbps in UART and mixed UART/
 40-Pin (6mm x 6mm) TQFN Package with 0.5mm
I2C modes, and up to 400kbps in I2C mode. Using the
Lead Pitch
control channel, a microcontroller (FC) is capable of
programming serializer, deserializer, and camera (or any S High-Speed Data Serialization for Megapixel
peripheral) registers at any time, independent of video Cameras
timing. There is one dedicated GPIO, four optional GPIOs,  Up to 1.5Gbps Serial-Bit Rate with Single or
and a GPO output, allowing remote power-up of a camera Double Input: 6.25MHz to 100MHz Clock
module, camera frame synchronization, and other uses. S Multiple Control-Channel Modes for System
Error-detection and correction coding are programmable. Flexibility
For driving longer cables, the serializer has program-  9.6kbps to 1Mbps Control Channel in UART-to-
mable pre/deemphasis. Programmable spread spectrum UART or UART-to-I2C Modes
is available on the serial output. The serial output meets S Reduces EMI and Shielding Requirements
ISO 10605 and IEC 61000-4-2 ESD standards. The core
supply range is 1.7V to 1.9V and the I/O supply range is  Output Programmable for 100mV to 500mV
Single-Ended or 100mV to 400mV Differential
1.7V to 3.6V. The device is available in a 40-pin (6mm x
 Programmable Spread Spectrum on the Serial
6mm) TQFN-EP package with 0.5mm lead pitch and oper-
Output Reduces EMI
ates over the -40NC to +105NC temperature range.
 Bypassable Input PLL for Parallel Clock Jitter
Attenuation
Applications  Tracks Spread Spectrum on Parallel Input
Automotive Camera Systems S Peripheral Features for Camera Power-Up and
Verification
Navigation Displays
 Built-In PRBS Generator for BER Testing of the
Serial Link
 Up to Five GPIO Ports
 Dedicated “Up/Down” GPO for Camera Frame
Sync Trigger and Other Uses
S Reduces Power Requirements
 Remote/Local Wake-Up from Sleep Mode
Ordering Information appears at end of data sheet.
S Meets Rigorous Automotive and Industrial
Typical Application Circuit appears at end of data sheet. Requirements
 -40NC to +105NC Operating Temperature
For related parts and recommended products to use with this part,  ±8kV Contact and ±15kV Air ISO 10605 and
refer to www.maximintegrated.com/MAX9273.related. IEC 61000-4-2 ESD Protection
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-6384; Rev 1; 11/12
MAX9273
STP Cable Drive
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Link Signaling and Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reverse Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data-Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interfacing Command-Byte-Only I2C Devices with UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Format for Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C Communication with Remote-Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Control-Channel Broadcast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pre/Deemphasis Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Manual Programming of the Spread-Spectrum Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Additional Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Maxim Integrated 2
MAX9273
STP Cable Drive
TABLE OF CONTENTS (continued)
Hamming Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
HS/VS Encoding and/or Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Coax-Mode Splitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Configuration Inputs (CONF1, CONF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Link Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PRBS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Error Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Dual µC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Jitter-Filtering PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PCLKIN Spread Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Changing the Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Fast Detection of Loss-of-Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Providing a Frame Sync (Camera Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Software Programming of the Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Three-Level Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Compatibility with Other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Choosing I2C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Selection of AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power-Supply Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Maxim Integrated 3
MAX9273
STP Cable Drive
LIST OF FIGURES
Figure 1. Serial-Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. Output Waveforms at OUT+, OUT- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. Single-Ended Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Worst-Case Pattern Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Parallel Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. I2C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Differential Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Input Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Serializer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Link Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Single-Input Waveform (Latch on Rising Edge of PCLKIN Selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Single-Input Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Double-Input Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Double-Input Waveform (Latch on Rising Edge of PCLKIN Selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Serial-Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18. GMSL UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. GMSL UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. SYNC Byte (0x79) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. ACK Byte (0xC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 22. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0) . . . . . . . . . 26
Figure 23. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1) . . . . . . . . . 27
Figure 24. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 25. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 26. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 27. Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 28. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 29. Format for Write to Multiple Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 30. Format for I2C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 31. 2:1 Coax-Mode Splitter Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 32. Coax-Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 33. State Diagram, All Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 34. Human Body Model ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 36. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Maxim Integrated 4

MAX9273
STP Cable Drive
LIST OF TABLES
Table 1. Power-Up Default Register Map (see Table 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2. Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3. Data-Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. I2C Bit-Rate Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. TP/Coax Drive Current (CMLLVL = 1000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Serial Output Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Spread Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. Modulation Coefficients and Maximum SDIV Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. Configuration Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. Startup Procedure for Video-Display Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. Startup Procedure for Image-Sensing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. MAX9273 Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. Typical Power-Supply Currents (Using Worst-Case Input Pattern) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. Suggested Connectors and Cables for GMSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Register Table (see Table 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Maxim Integrated 5

MAX9273
STP Cable Drive
Absolute Maximum Ratings*
AVDD to EP...........................................................-0.5V to +1.9V Continuous Power Dissipation (TA = +70NC)
DVDD to EP...........................................................-0.5V to +1.9V TQFN (derate 37mW/NC above +70NC).....................2963mW
IOVDD to EP..........................................................-0.5V to +3.9V Junction Temperature......................................................+150NC
OUT+, OUT- to EP................................................-0.5V to +1.9V Operating Temperature Range.........................-40oC to +105NC
All other pins to EP............................... -0.5V to (VIOVDD + 0.5V) Storage Temperature Range.............................-65oC to +150NC
OUT+, OUT- short circuit to ground or supply .........Continuous Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
*EP connected to PCB ground.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics (Note 1)

TQFN
Junction-to-Ambient Thermal Resistance (qJA)...........27°C/W Junction-to-Case Thermal Resistance (qJC)......................1°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL= 100I ±1% (differential), EP connected to PCB ground (GND),
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

SINGLE-ENDED INPUTS (DIN_, HS, VS, MS, PWDN, DRS, AUTOS, PCLKIN)
0.65 x
High-Level Input Voltage VIH1 V
VIOVDD
0.35 x
Low-Level Input Voltage VIL1 V
VIOVDD
Input Current IIN1 VIN = 0V to VIOVDD -10 +20 FA
three-level logic inputs (CONF0, CONF1)
0.7 x
High-Level Input Voltage VIH V
VIOVDD
0.3 x
Low-Level Input Voltage VIL V
VIOVDD
Midlevel Input Current IINM (Note 2) -10 +10 FA
Input Current IIN -150 +150 FA
SINGLE-ENDED OUTPUT (GPO)
VIOVDD
High-Level Output Voltage VOH1 IOUT = -2mA V
- 0.2
Low-Level Output Voltage VOL1 IOUT = 2mA 0.2 V
VIOVDD = 3.0V to 3.6V 16 35 64
Output Short-Circuit Current IOS VO = 0V mA
VIOVDD = 1.7V to 1.9V 3 12 21
Maxim Integrated 6

MAX9273
STP Cable Drive
DC ELECTRICAL CHARACTERISTICS (continued)
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.)

OPEN-DRAIN INPUTS/OUTPUTS (RX/SDA, TX/SCL, GPIO_)
0.7 x
High-Level Input Voltage VIH2 V
VIOVDD
0.3 x
Low- Level Input Voltage VIL2 V
VIOVDD
RX/SDA, TX/SCL -110 +1
Input Current IIN2 (Note 3) FA
GPIO_ -80 +1
VIOVDD = 1.7V to 1.9V 0.4
Low-Level Output Voltage VOL2 IOUT = 3mA V
VIOVDD = 3.0V to 3.6V 0.3
Differential serial OutputS (OUT+, OUT-)
Preemphasis off (Figure 1) 300 400 500
Differential Output Voltage VOD 3.3dB preemphasis setting (Figure 2) 350 610 mV
3.3dB deemphasis setting (Figure 2) 240 425
Change in VOD Between
DVOD 25 mV
Complementary Output States
Output Offset Voltage
VOS Preemphasis off 1.1 1.4 1.56 V
(VOUT+ + VOUT-)/2 = VOS
Change in VOS Between
DVOS 25 mV
Complementary Output States
VOUT+ or VOUT- = 0V -62
Output Short-Circuit Current IOS mA
VOUT+ or VOUT- = 1.9V 25
Magnitude of Differential Output
IOSD VOD = 0V 25 mA
Short-Circuit Current
Output Termination Resistance
RO From VOUT+, VOUT- to VAVDD 45 54 63 I
(Internal)
SINGLE-ENDED SERIAL OUTPUTS (OUT+, OUT-)
Preemphasis off, high drive (Figure 3) 375 500 625
3.3dB preemphasis setting, high drive
435 765
Single-Ended Output Voltage VOD (Figure 2) mV
3.3dB deemphasis setting, high drive
300 535
(Figure 2)
VOUT+ or VOUT- = 0V -69
Output Short-Circuit Current IOS mA
VOUT+ or VOUT- = 1.9V 32
Output Termination Resistance
RO From VOUT+ or VOUT- to VAVDD 45 54 63 I
(Internal)
Maxim Integrated 7

MAX9273
STP Cable Drive
DC ELECTRICAL CHARACTERISTICS (continued)
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAV DD = VDVDD = VIOVDD = 1.8V, TA = +25NC.)

Reverse control-channel Receiver OUTPUTS (OUT+, OUT-)
High Switching Threshold VCHR 27 mV
Low Switching Threshold VCLR -27 mV
Power Supply
Single input, fPCLKIN = 25MHz 40 65
Worst-Case Supply Current BWS = 0 fPCLKIN = 50MHz 50 75
IWCS mA
(Figure 4) Double input, fPCLKIN = 50MHz 40 65
BWS = 0 fPCLKIN = 100MHz 51 75
Sleep Mode Supply Current ICCS Single wake-up receiver enabled 40 100 FA
Power-Down Supply Current ICCZ PWDN = EP 5 70 FA
ESD Protection
Human Body Model, RD = 1.5kI,
±8
CS = 100pF
IEC 61000-4-2, Contact discharge ±10
RD = 330I,
OUT+, OUT- (Note 4) VESD Air discharge ±15 kV
CS = 150pF
ISO 10605, Contact discharge ±10
RD = 2kI,
CS = 330pF Air discharge ±30
Human Body Model, RD = 1.5kI,
All Other Pins (Note 5) VESD ±4 kV
CS = 100pF
AC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground (GND),
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC)

Clock input (PCLKIN)
BWS = 1, DRS = 1 6.25 12.5
BWS = 0, DRS = 1 8.33 16.66
BWS = 1, DRS = 0 12.5 37.5
Clock Frequency fPCLKIN MHz
BWS = 0, DRS = 0 16.66 50
BWS = 1, DRS = 0, 15-bit double input 25 75
BWS = 0, DRS = 0, 11-bit double input 33.33 100
Clock Duty Cycle DC_ tHIGH/tT or tLOW/tT (Figure 5, Note 6) 35 50 65 %
Clock Transition Time tR, tF_ (Figure 5, Note 6) 4 ns
ps
Clock Jitter tJ 1.5Gbps bit rate, 300kHz sinusoidal jitter 800
(pk-pk)
Maxim Integrated 8

MAX9273
STP Cable Drive
AC ELECTRICAL CHARACTERISTICS (continued)
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground (GND),
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC)

I2C/UART and GPIO Port Timing
I2C/UART Bit Rate 9.6 1000 kbps
30% to 70%, CL = 10pF to 100pF,
Output Rise Time tR 20 120 ns
1kI pullup to IOVDD
70% to 30%, CL = 10pF to 100pF,
Output Fall Time tF 20 120 ns
1kI pullup to IOVDD
Input Setup Time tSET I2C only (Figure 6, Note 6) 100 ns
Input Hold Time tHOLD I2C only (Figure 6, Note 6) 0 ns
Switching Characteristics (Note 6)
Differential Output Rise/Fall 20% to 80%, VOD R 400mV RL = 100I,
tR, tF 250 ps
Time serial-bit rate = 1.5Gbps
1.5Gbps PRBS signal, measured at
Total Serial Output Jitter
tTSOJ1 VOD = 0V differential, preemphasis 0.25 UI
(Differential Output)
disabled (Figure 7)
1.5Gbps PRBS signal, measured at
Deterministic Serial Output
tDSOJ2 VOD = 0V differential, preemphasis 0.15 UI
Jitter (Differential Output)
disabled (Figure 7)
Total Serial Output Jitter 1.5Gbps PRBS signal, measured at VO/2,
tTSOJ1 0.25 UI
(Single-Ended Output) preemphasis disabled (Figure 3)
1.5Gbps PRBS signal, measured at VO/2,
Deterministic Serial Output
tDSOJ2 preemphasis disabled (Figure 3)1.5Gbps 0.15 UI
Jitter (Single-Ended Output)
PRBS signal
Parallel Data Input Setup Time tSET (Figure 8) 2 ns
Parallel Data Input Hold Time tHOLD (Figure 8) 1 ns
Deserializer GPI to serializer GPO
GPI-to-GPO Delay tGPIO_ 350 Fs
(Figure 9)
Spread spectrum enabled 6880
Serializer Delay (Note 7) tSD (Figure 10) Bits
Spread spectrum disabled 3040
Link Start Time tLOCK (Figure 11) 2 ms
Power-Up Time tPU (Figure 12) 7 ms
Note 2: To provide a midlevel, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than Q10µA.
Note 3: IIN min due to voltage drop across the internal pullup resistor.
Note 4: Specified pin to ground.
Note 5: Specified pin to all supply/ground.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured in serial link bit times. Bit time = 1/(30 x fPCLKIN) for BWS = 0. Bit time = 1/(40 x fPCLKIN) for BWS = 1.
Maxim Integrated 9

MAX9273
STP Cable Drive
Typical Operating Characteristics
(VAVDD = VDVDD = VIOVDD = 1.8V, DBL = low, TA = +25NC, unless otherwise noted.)
SUPPLY CURRENT vs.PCLKIN SUPPLY CURRENT vs. PCLKIN OUTPUT POWER SPECTRUM vs. PCLKIN
FREQUENCY (BWS = 0) FREQUENCY (BWS = 1) FREQUENCY (VARIOUS SPREAD)
70 70 0
MAX9273 toc03
MAX9273 toc01
MAX9273 toc02
PRBS ON, PRBS ON, fPCLKIN = 20MHz
COAX MODE PREEMPHASIS = COAX MODE -10
65 65
OUTPUT POWER SPECTRUM (dBm)

PREEMPHASIS =
0x0B TO 0x0F -20
0x0B TO 0x0F
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
60 60 0% 0.5%
-30 SPREAD SPREAD
55 55 -40
50 50 -50
-60
45 45
PREEMPHASIS = 1%
PREEMPHASIS = -70
0x01 TO 0x04 SPREAD
40 0x01 TO 0x04 40
-80 4% SPREAD
PREEMPHASIS = 0x00 PREEMPHASIS = 0x00 2% SPREAD
35 35 -90
5 10 15 20 25 30 35 40 45 50 5 10 15 20 25 30 35 40 18.5 19.0 19.5 20.0 20.5 21.0 21.5
PCLKIN FREQUENCY (MHz) PCLKIN FREQUENCY (MHz) PCLKIN FREQUENCY (MHz)
SERIAL LINK SWITCHING PATTERN SERIAL LINK SWITCHING PATTERN
OUTPUT POWER SPECTRUM vs. PCLKIN WITH 6dB PREEMPHASIS (PARALLEL BIT WITH 6dB PREEMPHASIS (PARALLEL BIT
FREQUENCY (VARIOUS SPREAD) RATE = 50MHz, 10m STP CABLE) RATE = 50MHz, 20m COAX CABLE)
MAX9273 toc05 MAX9273 toc06
0
MAX9273 toc04
fPCLKIN = 50MHz
-10
0% SPREAD
OUTPUT POWER SPECTRUM (dBm)
-20 0.5% SPREAD
-30
-40
-50
-60
-70 1%
-80 SPREAD
4% SPREAD
-90 2% SPREAD
-100
47 48 49 50 51 52 53 50mV/div 200ps/div 1.5Gbps 50mV/div 200ps/div 1.5Gbps
PCLKIN FREQUENCY (MHz)
MAXIMUM PCLKIN FREQUENCY MAXIMUM PCLKIN FREQUENCY MAXIMUM PCLKIN FREQUENCY

vs. STP CABLE LENGTH (BER ≤ 10-10) vs. COAX CABLE LENGTH (BER ≤ 10-10) vs. ADDITIONAL DIFFERENTIAL CL (BER < 10-10)
60 60 60
MAX9273 toc07
MAX9273 toc08
MAX9273 toc09
OPTIMUM PE/EQ 10m STP CABLE OPTIMUM PE/EQ

SETTINGS SETTINGS
50
6dB PE, EQ OFF 6dB PE, EQ OFF

40 40 40 6dB PE, EQ OFF
NO PE, 10.7dB EQ
NO PE, 10.7dB EQ
30
NO PE, EQ OFF NO PE, 10.7dB EQ
NO PE, EQ OFF
20 20 20
NO PE, EQ OFF
10
BER CAN BE AS LOW AS 10-12 BER CAN BE AS LOW AS 10-12 BER CAN BE AS LOW AS 10-12 FOR CL < 4pF
FOR CABLE LENGTHS LESS THAN 10m FOR CABLE LENGTHS LESS THAN 10m FOR OPTIMUM PE/EQ SETTINGS
0 0 0
0 5 10 15 20 0 5 10 15 20 25 0 2 4 6 8 10
STP CABLE LENGTH (m) COAX CABLE LENGTH (m) ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF)
Maxim Integrated 10

MAX9273
STP Cable Drive
Pin Configuration
TOP VIEW
RX/SDA
TX/SCL
AUTOS
CONF1
CONF0
PWDN
AVDD
OUT+
OUT-
DRS
30 29 28 27 26 25 24 23 22 21
PCLKIN 31 20 MS
DIN0 32 19 GPIO1
DIN1 33 18 GPO
DIN2 34 17 DIN21
DVDD 35 16 DIN20
MAX9273
DIN3 36 15 IOVDD
DIN4 37 14 DIN19/VS
DIN5 38 13 DIN18/VS
IOVDD 39 EP* 12 DIN17/GPIO5
+
DIN6 40 11 DIN16/GPIO4
1 2 3 4 5 6 7 8 9 10
DIN7
DIN8
DIN9
AVDD
DIN10
DIN11
DIN12
DIN13
DIN14/GPIO2
DIN15/GPIO3
TQFN
(6mm x 6mm x 0.75mm)
CONNECT EP TO GROUND PLANE
Pin Description
PIN NAME FUNCTION
1, 2, 3, 5–8,
16, 17, 32, DIN0–DIN13,
Parallel Data Inputs with Internal Pulldown to EP
33, 34, 36, DIN20, DIN21
37, 38
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1FF and 0.001FF capacitors as close
4, 27 AVDD
as possible to the device with the smaller capacitor closest to AVDD.
Parallel Data Inputs/GPIO. Defaults to parallel data input on power-up.
DIN14/
Parallel data input has internal pulldown to EP.
9–12 GPIO2–DIN17/
GPIO_ has an open-drain output with internal 60kI pullup to IOVDD. See register table
GPIO5
for programming details.
Parallel Data Input/Horizontal Sync with Internal Pulldown to EP. Defaults to parallel data input
13 DIN18/HS on power-up.
Horizontal sync input when VS/HS encoding is enabled (Table 2).
Parallel Data Input/Vertical Sync with Internal Pulldown to EP. Defaults to parallel data input on
14 DIN19/VS power-up.
Vertical sync input when VS/HS encoding is enabled (Table 2).
Maxim Integrated 11

MAX9273
STP Cable Drive
Pin Description (continued)
PIN NAME FUNCTION
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1FF
15, 39 IOVDD and 0.001FF capacitors as close as possible to the device with the smallest value capacitor
closest to IOVDD.
General-Purpose Output. GPO follows the GMSL deserializer GPI (or INT) input. GPO = low
18 GPO
upon power-up and when PWDN = low.
19 GPIO1 Open-Drain, General-Purpose Input/Output with Internal 60kI Pullup to IOVDD
Mode-Select Input with Internal Pulldown to EP. Set MS = low to select base mode.
20 MS
Set MS = high to select bypass mode.
Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter
21 PWDN
power-down mode to reduce power consumption.
22 DRS Data-Rate Select Input with Internal Pulldown to EP (Table 15).
23 CONF0 Configuration 0. Three-level configuration input (Table 9).
24 CONF1 Configuration 1. Three-level configuration input (Table 9).
25 OUT- Inverting Coax/Twisted-Pair Serial Output
26 OUT+ Noninverting Coax/Twisted-Pair Serial Output
UART Receive or I2C Serial-Data Input/Output with Internal 30kI Pullup to IOVDD. In UART
mode, RX/SDA is the Rx input of the serializer’s UART. In the I2C mode, RX/SDA is the
28 RX/SDA
SDA input/output of the serializer’s I2C master/slave. RX/SDA has an open-drain driver and
requires a pullup resistor.
UART Transmit or I2C Serial-Clock Input/Output with Internal 30kI Pullup to IOVDD. In UART
mode, TX/SCL is the Tx output of the serializer’s UART. In the I2C mode, TX/SCL is the SCL
29 TX/SCL
input/output of the serializer’s I2C master/slave. TX/SCL has an open-drain driver and requires
a pullup resistor.
Autostart Input with Internal Pulldown to EP. AUTOS = low enables serialization upon power-
30 AUTOS up and automatic frequency range selection of PCLKIN. AUTOS = high puts the part in sleep
mode upon power-up.
Parallel Clock Input with Internal Pulldown to EP. Latches parallel data inputs and provides
31 PCLKIN
the PLL reference clock.
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1FF and 0.001FF capacitors as close
35 DVDD
as possible to the device with the smaller value capacitor closest to DVDD.
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB
— EP
ground plane through an array of vias for proper thermal and electrical performance.
Maxim Integrated 12

MAX9273
STP Cable Drive
Functional Diagram
SSPLL
PCLKIN FILTER
PLL MAX9273
CLKDIV
DIN0–DIN13
DIN14/GPIO2 OUT+
PARALLEL
DIN15/GPIO3 TO SERIAL OUT-
DIN16/GPIO4 CML TX
DIN17/GPIO5 SCRAMBLE/
SINGLE-/
CRC/
DOUBLE-
FIFO HAMMING/ RX
INPUT
8b/10b
GPO LATCH
ENCODE
REVERSE
GPIO1
CONTROL
CHANNEL
FCC
GPIO
DIN18/HS
DIN19/VS
UART/I2C
DIN20, DIN21
TX/SCL RX/SDA
Maxim Integrated 13

MAX9273
STP Cable Drive
RL/2
OUT+
VOD
VOS
OUT-
RL/2
GND
((OUT+) + (OUT-))/2
OUT-
VOS(-) VOS(+) VOS(-)
OUT+
DVOS = |VOS(+) - VOS(-)|
VOD(+)
VOD = 0V
VOD(-) DVOD = |VOD(+) - VOD(-)| VOD(-)
(OUT+) - (OUT-)
Figure 1. Serial-Output Parameters
OUT+
OUT+ VO/2 VO VO/2 VO
VOD(P) VOD(D) OR
VOS
OUT-
OUT-
Figure 3. Single-Ended Output Template
SERIAL-BIT
TIME
PCLKIN
Figure 2. Output Waveforms at OUT+, OUT-
DIN_
NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.
Figure 4. Worst-Case Pattern Input
Maxim Integrated 14

MAX9273
STP Cable Drive
tT
VIH MIN
PCLKIN tHIGH
VIL MAX
tF tR tLOW
Figure 5. Parallel Clock Input Requirements
START BIT 7 STOP

CONDITION MSB BIT 6 BIT 0 ACKNOWLEDGE CONDITION
PROTOCOL
(S) (A7) (A6) (R/W) (A) (P)
tSU;STA tLOW tHIGH

1/fSCL
SCL
tBUF tSP
tr tf
SDA
tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO
Figure 6. I2C Timing Parameters
800mVP-P
t TSOJ1 t TSOJ1
2 2
Figure 7. Differential Output Template
Maxim Integrated 15

MAX9273
STP Cable Drive
VIH MIN
PCLKIN
VIL MAX
tSET tHOLD
VIH MIN VIH MIN

DIN_
VIL MAX VIL MAX
NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.
Figure 8. Input Setup and Hold Times
VIH_MIN
DESERIALIZER
GPI
VIL_MAX
tGPIO tGPIO
VOH_MIN
SERIALIZER
GPO
VOL_MAX
Figure 9. GPI-to-GPO Delay
Maxim Integrated 16

MAX9273
STP Cable Drive
EXPANDED TIME SCALE
DIN_
N N+1 N+2 N+3 N+4
PCLKIN
N-1 N
OUT+/-
tSD
FIRST BIT LAST BIT
Figure 10. Serializer Delay
PCLKIN
tLOCK
350Fs
SERIAL LINK INACTIVE SERIAL LINK ACTIVE
REVERSE CONTROL CHANNEL CHANNEL REVERSE CONTROL CHANNEL

DISABLED DISABLED AVAILABLE
PWDN MUST BE HIGH
Figure 11. Link Startup Time
Maxim Integrated 17

MAX9273
STP Cable Drive
PCLKIN
VIH1
PWDN
tPU
POWERED UP,
POWERED DOWN SERIAL LINK INACTIVE POWERED UP, SERIAL LINK ACTIVE
350µs
REVERSE CONTROL REVERSE CONTROL REVERSE CONTROL REVERSE CONTROL

CHANNEL DISABLED CHANNEL ENABLED CHANNEL DISABLED CHANNEL ENABLED
Figure 12. Power-Up Delay
Detailed Description Register Mapping

Registers set the operating conditions of the serializer
The MAX9273 serializer, when paired with the MAX9272 and are programmed using the control channel in base
deserializer, provides the full set of operating features, mode. The serializer holds its device address and the
but offers basic functionality when paired with any GMSL device address of the deserializer it is driving. Similarly,
deserializer. the driven deserializer holds its device address and the
The serializer has a maximum serial-bit rate of 1.5Gbps address of the serializer by which it is driven. Whenever
for 15m or more of cable and operates up to a maximum a device address is changed, be sure to write the new
input clock of 50MHz in 22-bit, single-input mode, or address to both devices. The default device address of
75MHz/100MHz in 15-bit/11-bit, double-input mode, the MAX9273 serializer (or any GMSL serializer) is 0x80
respectively. Pre/deemphasis, along with the GMSL and the default device address of any GMSL deserial-
deserializer channel equalizer, extends the link length izer is 0x90 (Table 1). Registers 0x00 and 0x01 in both
and enhances link reliability. devices hold the device addresses.
The control channel enables a FC to program serial- Input Bit Map
izer and deserializer registers and program registers The parallel input functioning and width depends on
on peripherals. The FC can be located at either end of settings of the double-/single-input mode (DBL), HS/VS
the link, or at both ends. Two modes of control-channel encoding (HVEN), error correction (EDC), and bus width
operation are available with associated protocols and (BWS). DINA are the inputs latched by the pixel clock in
data formats. Base mode uses either I2C or GMSL UART, single-input mode, or the inputs latched on the first pixel
while bypass mode uses a user-defined UART. clock in double-input mode. DINB are the inputs latched
Spread spectrum is available to reduce EMI on the serial on the second pixel clock in double-input mode. Table 2
output. The serial output complies with ISO 10605 and lists the bit map for the control pin settings.
IEC 61000-4-2 ESD protection standards.
Maxim Integrated 18

MAX9273
STP Cable Drive
Table 1. Power-Up Default Register Map (see Table 15)
REGISTER POWER-UP POWER-UP DEFAULT SETTINGS
ADDRESS (hex) DEFAULT (hex) (MSB FIRST)
SERID = 1000000, serializer device address
0x00 0x80
CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
DESID = 1001000, deserializer device address
0x01 0x90
RESERVED = 0
SS = 000, no spread spectrum
RESERVED = 1
0x02 0x1F
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
AUTOFM = 00, calibrate spread-modulation rate only once after locking
0x03 0x00
SDIV = 000000, auto calibrate sawtooth divider
SEREN = 0 (AUTOS = high), SEREN = 1(AUTOS = low), serial link enable default
depends on AUTOS pin state at power-up
CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
0x04 0x07, 0x87
SLEEP = 0, sleep mode disabled (see the Link Startup Procedure section)
INTTYPE = 01, local control channel uses UART
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)
I2CMETHOD = 0, I2C packets include register address
ENJITFILT = 0, jitter filter disabled
PRBSLEN = 00, continuous PRBS length
0x05 0x01
RESERVED = 00
ENWAKEN = 0, OUT- wake-up receiver disabled
ENWAKEP = 1, OUT+ wake-up receiver enabled
CMLLVL = 1000 or 1010, output level determined by the state of CONF1, CONF0 at
0x06 0x80, 0xA0 power-up
PREEMP = 0000, preemphasis disabled
DBL = 0, double-input mode
DRS = 0, high data-rate mode
BWS = 0, 24-bit mode
ES = 0 or 1, edge-select input setting determined by the state of CONF1,
0x07 0x00, 0x10
CONF0 at startup
RESERVED = 0
HVEN = 0, HS/VS encoding disabled
EDC = 00, 1-bit parity error detection
INVVS = 0, serializer does not invert VSYNC
0x08 0x00 INVHS = 0, serializer does not invert HSYNC
RESERVED = 000000
I2CSRCA = 0000000, I2C address translator source A is 0x00
0x09 0x00
RESERVED = 0
Maxim Integrated 19

MAX9273
STP Cable Drive
Table 1. Power-Up Default Register Map (see Table 15) (continued)
I2CDSTA = 0000000, I2C address translator destination A is 0x00
0x0A 0x00
RESERVED = 0
I2CSRCB = 0000000, I2C address translator source B is 0x00
0x0B 0x00
RESERVED = 0
I2CDSTB = 0000000, I2C address translator destination B is 0x00
0x0C 0x00
RESERVED = 0
I2CLOCACK = 1, acknowledge generated when forward channel is not available
I2CSLVSH = 01, 469ns/234ns I2C setup/hold time
0x0D 0xB6
I2CMSTBT = 101, 339kbps (typ) I2C-to-I2C master bit-rate setting
I2CSLVTO = 10, 1024Fs (typ) I2C-to-I2C slave remote timeout
DIS_REV_P = 0, OUT+ reverse channel receiver enabled
DIS_REV_N = 1, OUT- reverse channel receiver disabled
GPIO5EN = 0, GPIO5 disabled
0x0E 0x42
GPIO1EN = 1, GPIO1 enabled
RESERVED = 0
RESERVED = 11
GPIO5OUT = 1, GPIO5 set high
0x0F 0xFE GPIO3OUT = 1, GPIO3 set high
SETGPO = 0, GPO set low
RESERVED = 00
GPIO5IN = 1, GPIO5 is input high
0x10 0x3E GPIO3IN = 1, GPIO3 is input high
GPO_L = 0, GPO set low
ERRGRATE = 00, generate an error every 2560 bits

ERRGTYPE = 0, generate single-bit errors
0x11 0x00 ERRGCNT = 00, continuously generate errors
ERRGPER = 0, disable periodic error generation
ERRGEN = 0, disable error generation
0x12 0x40 RESERVED = 01000000
0x13 0x22 RESERVED = 00100010
0x14 0xXX RESERVED = XXXXXXXX
Maxim Integrated 20

MAX9273
STP Cable Drive
Table 1. Power-Up Default Register Map (see Table 15) (continued)
CXTP = 0, CXTP is low
I2CSEL = 0, input is low
LCCEN = 0, local control channel disabled
0x15 0x00
RESERVED = 000
OUTPUTEN = 0, output disabled
PCLKDET = 0, no valid PCLKIN detected
0x16 0xXX (read only) RESERVED = XXXXXXXX
0x17 0xXX (read only) RESERVED = XXXXXXXX
0x0B
0x1E ID = 00001011, device ID is 0x0B
(read only)
RESERVED = 000
0x0X
0x1F CAPS = 0, serializer is not HDCP capable
(read only)
REVISION = XXXX, revision number
X = Don’t care.
Table 2. Input Map

EDC BWS DBL HVEN DINA DINB* SERIAL LINK WORD BITS
0 0 0 0 0:21 — 0:21
0 0 0 1 0:17, 20:21, HS, VS — 0:17, 20:21
0 0 1 0 0:10 0:10 0:21
0 0 1 1 0:10, HS, VS 0:10, HS, VS 0:21
0 1 0 0 0:21 — 0:21
0 1 0 1 0:17, 20:21, HS, VS — 0:17, 20:21
0 1 1 0 0:14 0:14 0:29
0 1 1 1 0:14, HS, VS 0:14, HS, VS 0:29
1 0 0 0 0:15 — 0:15
1 0 0 1 0:15, HS, VS — 0:15
1 0 1 0 0:7 0:7 0:15
1 0 1 1 0:7, HS, VS 0:7, HS, VS 0:15
1 1 0 0 0:21 — 0:21
1 1 0 1 0:17, 20:21, HS, VS — 0:17, 20:21
1 1 1 0 0:11 0:11, HS, VS 0:23
1 1 1 1 0:11, HS, VS 0:11, HS, VS 0:23
*In double-input mode (DBL = 1), DINA are latched on the first cycle of PCLKIN and DINB are latched on the second cycle of
PCLKIN.
Maxim Integrated 21

MAX9273
STP Cable Drive
The parallel input has two input modes: single- and In double-input mode, LATCH B stores two input words
double-rate input. In single-input mode, LATCH A stores (Figure 15). Data from LATCH B is sent to the scrambler
data from DIN_ every PCLKIN cycle (Figure 13). Parallel as a combined word. The MAX9272 deserializer outputs
data from LATCH A is then sent to the scrambler for the combined word (single-output mode) or two half-sized
serialization (Figure 14). The device accepts pixel clocks words (double-output mode). The serializer/deserializer
from 6.25MHz to 50MHz. use pixel clock rates from 33.3MHz to 100MHz for 11-bit,
double-input mode and 25MHz to 75MHz for 15-bit,
double-input mode. See Figure 16 for timing details.
PCLKIN
DIN0–DIN21 FIRST WORD SECOND WORD THIRD WORD FOURTH WORD
LATCH A FIRST WORD SECOND WORD THIRD WORD FOURTH WORD
Figure 13. Single-Input Waveform (Latch on Rising Edge of PCLKIN Selected)
MAX9273
DIN0–DIN14
INPUT
DIN0–DIN21 OR
LATCH B
DIN0–DIN10 INPUT
LATCH B
INPUT
LATCH A
MAX9273
÷2
PCLKIN
PCLKIN
Figure 14. Single-Input Function Block Figure 15. Double-Input Function Block
Maxim Integrated 22

MAX9273
STP Cable Drive
PCLKIN
÷2
DIN0–DIN14
OR FIRST WORD SECOND WORD THIRD WORD FOURTH WORD
DIN0–DIN10
LATCH A FIRST WORD THIRD WORD
LATCH B FIRST AND SECOND WORD THIRD AND FOURTH WORD
Figure 16. Double-Input Waveform (Latch on Rising Edge of PCLKIN Selected)
Serial Link Signaling and Data Format Control Channel and Register Programming
The serializer uses differential CML signaling to drive The control channel is available for the FC to send and
twisted-pair cable and single-ended CML to drive coaxial receive control data over the serial link simultaneously
cable. The output amplitude is programmable. with the high-speed data. The FC controls the link from
Input data is scrambled and then 8b/10b coded. The either the serializer or deserializer side. The control chan-
deserializer recovers the embedded serial clock, then nel between the FC and serializer or deserializer runs in
samples, decodes, and descrambles the data. In 24-bit base mode or bypass mode, according to the mode-
or 32-bit mode, 22 or 30 bits contain the video data selection (MS) input of the device connected to the FC.
and/or error correction bits, if used. The 23rd or 31st bit Base mode is a half-duplex control channel and bypass
carries the forward control-channel data. The last bit is mode is a full-duplex control channel.
the parity bit of the previous 23 or 31 bits (Figure 17).
UART Interface
Reverse Control Channel In base mode, the FC is the host and can access the
The serializer uses the reverse control channel to receive registers of both the serializer and deserializer from
I2C/UART and GPO signals from the deserializer in the either side of the link using the GMSL UART protocol.
opposite direction of the video stream. The reverse The FC can also program the peripherals on the remote
control channel and forward video data coexist on side by sending the UART packets to the serializer or
the same serial cable forming a bidirectional link. The deserializer, with the UART packets converted to I2C
reverse control channel operates independently from the by the device on the remote side of the link. The FC
forward control channel. The reverse control channel is communicates with a UART peripheral in base mode
available 2ms after power-up. The serializer temporarily (through INTTYPE register settings), using the half-duplex
disables the reverse control channel for 350Fs after start- default GMSL UART protocol of the serializer/deserial-
ing/stopping the forward serial link. izer. The device addresses of the serializer/deserializer in
base mode are programmable. The default value is 0x80
Data-Rate Selection
for the serializer and 0x90 for the deserializer.
The serializer/deserializer use DRS, DBL, and BWS to set
the PCLKIN frequency range (Table 3). Set DRS = 1 for When the peripheral interface is I2C, the serializer/
a PCLKIN frequency range of 6.25MHz to 12.5MHz (32- deserializer convert UART packets to I2C that have
bit, single-input mode) or 8.33MHz to 16.66MHz (24-bit, device addresses different from those of the serializer or
single-input mode). Set DRS = 0 for normal operation. deserializer. The converted I2C bit rate is the same as the
It is not recommended to use double-input mode when original UART bit rate.
DRS = 1.
Maxim Integrated 23
MAX9273
STP Cable Drive
24 BITS 32 BITS
D0 D1 D21 FCC PCB D0 D1 D29 FCC PCB
FORWARD FORWARD
VIDEO AND ERROR- VIDEO AND ERROR-
CONTROL- CONTROL-
CORRECTION DATA CORRECTION DATA
CHANNEL BIT CHANNEL BIT
PACKET PACKET
PARITY PARITY
CHECK BIT CHECK BIT
NOTE: SERIAL DATA SHOWN BEFORE SCRAMBLING AND 8b/10b ENCODING
Figure 17. Serial-Data Format
Table 3. Data-Rate Selection Table

DRS SETTING DBL SETTING BWS SETTING PCLKIN RANGE (MHz)
0 0 (single input) 0 (24-bit mode) 16.66 to 50
0 0 1 (32-bit mode) 12.5 to 35
0 1 (double input) 0 33.3 to 100
0 1 1 25 to 75
1 0 0 8.33 to 16.66
1 0 1 6.25 to 12.5
1 1 0 Do not use
1 1 1 Do not use
The deserializer uses differential line coding to send izer registers do not take effect until after the acknowl-
signals over the reverse channel to the serializer. The edge byte is sent. This allows the FC to verify that write
bit rate of the control channel is 9.6kbps to 1Mbps in commands are received without error, even if the result
both directions. The serializer/deserializer automatically of the write command directly affects the serial link. The
detect the control-channel bit rate in base mode. Packet slave uses the SYNC byte to synchronize with the host
bit-rate changes can be made in steps of up to 3.5 UART’s data rate. If the GPI or MS/HVEN inputs of the
times higher or lower than the previous bit rate. See the deserializer toggle while there is control-channel com-
Changing the Clock Frequency section for more informa- munication, or if a line fault occurs, the control-channel
tion on changing the control-channel bit rate. communication is corrupted. In the event of a missed
Figure 19 shows the UART data format. Figure 20 and or delayed acknowledge (~1ms due to control-channel
Figure 21 detail the formats of the SYNC byte (0x79) timeout), the FC should assume there was an error in the
and the ACK byte (0xC3). The FC and the connected packet when the slave device received it, or that an error
slave chip generate the SYNC byte and ACK byte, occurred during the response from the slave device. In
respectively. Events such as device wake-up and GPI base mode, the FC must keep the UART Tx/Rx lines high
generate transitions on the control channel that can be for 16 bit times before starting to send a new packet.
ignored by the FC. Data written to the serializer/deserial-
Maxim Integrated 24

MAX9273
STP Cable Drive
WRITE DATA FORMAT
SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N
MASTER WRITES TO SLAVE ACK
MASTER READS FROM SLAVE
READ DATA FORMAT
SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES
MASTER WRITES TO SLAVE ACK BYTE 1 BYTE N
MASTER READS FROM SLAVE
Figure 18. GMSL UART Protocol for Base Mode
1 UART FRAME
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP
FRAME 1 FRAME 2 FRAME 3
STOP START STOP START
Figure 19. GMSL UART Data Format for Base Mode
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
START 1 0 0 1 1 1 1 0 PARITY STOP START 1 1 0 0 0 0 1 1 PARITY STOP
Figure 20. SYNC Byte (0x79) Figure 21. ACK Byte (0xC3)
Maxim Integrated 25

MAX9273
STP Cable Drive
As shown in Figure 22, the remote-side device converts UART Bypass Mode
packets going to or coming from the peripherals from In bypass mode, the serializer/deserializer ignore UART
UART format to I2C format and vice versa. The remote commands from the FC and the FC communicates with
device removes the byte number count and adds or the peripherals directly using its own defined UART pro-
receives the ACK between the data bytes of I2C. The I2C tocol. The FC cannot access the serializer/deserializer
bit rate is the same as the UART bit rate. registers in this mode. Peripherals accessed through the
forward control channel using the UART interface need
Interfacing Command-Byte-Only I2C
Devices with UART to handle at least one PCLKIN period Q 10ns of jitter due
The serializer/deserializer UART-to-I2C conversion can to the asynchronous sampling of the UART signal by
interface with devices that do not require register address- PCLKIN. Set MS = high to put the control channel into
es, such as the MAX7324 GPIO expander. In this mode, bypass mode. For applications with the FC connected to
the I2C master ignores the register address byte and the deserializer, there is a 1ms wait time between setting
directly reads/writes the subsequent data bytes (Figure 23). MS high and the bypass control channel being active.
Change the communication method of the I2C master using There is no delay time when switching to bypass mode
the I2CMETHOD bit. I2CMETHOD = 1 sets command-byte- when the FC is connected to the serializer. Do not send
only mode, while I2CMETHOD = 0 sets normal mode where a logic-low value longer than 100Fs to ensure proper
the first byte in the data stream is the register address. GPO functionality. Bypass mode accepts bit rates down
to 10kbps in either direction. See the GPO/GPI Control
section for GPO functionality limitations. The control-
channel data pattern should not be held low longer than
100Fs if GPO control is used.
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)

FC SERIALIZER/DESERIALIZER
11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + WR REGISTER ADDRESS NUMBER OF BYTES DATA 0 DATA N ACK FRAME
SERIALIZER/DESERIALIZER PERIPHERAL
1 7 1 1 8 1 8 1 8 1 1
S DEV ID W A REG ADDR A DATA 0 A DATA N A P
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0)

11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + RD REGISTER ADDRESS NUMBER OF BYTES ACK FRAME DATA 0 DATA N
1 7 1 1 8 1 1 7 1 1 8 1 8 1 1
S DEV ID W A REG ADDR A S DEV ID R A DATA 0 A DATA N A P
: MASTER TO SLAVE : SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE
Figure 22. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
Maxim Integrated 26

MAX9273
STP Cable Drive
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + WR REGISTER ADDRESS NUMBER OF BYTES DATA 0 DATA N ACK FRAME
1 7 1 1 8 1 8 1 1
S DEV ID W A DATA 0 A DATA N A P
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1)

11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + RD REGISTER ADDRESS NUMBER OF BYTES ACK FRAME DATA 0 DATA N
1 7 1 1 8 1 8 1 1
S DEV ID R A DATA 0 A DATA N A P
: MASTER TO SLAVE : SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE
Figure 23. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1)
I2C Interface START and STOP Conditions

In I2C-to-I2C mode, the serializer control-channel inter- Both SCL and SDA remain high when the interface is not
face sends and receives data through an I2C-compatible busy. A master signals the beginning of a transmission
2-wire interface. The interface uses a serial-data line with a START (S) condition by transitioning SDA from high
(SDA) and a serial-clock line (SCL) to achieve bidirec- to low while SCL is high (Figure 24). When the master has
tional communication between master and slave(s). A FC finished communicating with the slave, it issues a STOP
master initiates all data transfers to and from the device (P) condition by transitioning SDA from low to high while
and generates the SCL clock that synchronizes the data SCL is high. The bus is then free for another transmission.
transfer. When an I2C transaction starts on the local-side Bit Transfer
device’s control-channel port, the remote-side device’s One data bit is transferred during each clock pulse
control-channel port becomes an I2C master that inter- (Figure 25). The data on SDA must remain stable while
faces with remote-side I2C peripherals. The I2C master SCL is high.
must accept clock stretching that is imposed by the seri-
alizer (holding SCL low). The SDA and SCL lines operate Acknowledge
as both an input and an open-drain output. Pullup resis- The acknowledge bit is a clocked 9th bit that the recipient
tors are required on SDA and SCL. Each transmission uses to handshake receipt of each byte of data (Figure 26).
consists of a START condition (Figure 6) sent by a mas- Thus, each byte transferred effectively requires nine bits.
ter, followed by the device’s 7-bit slave address plus a The master generates the 9th clock pulse, and the recipi-
R/W bit, a register address byte, one or more data bytes, ent pulls down SDA during the acknowledge clock pulse.
and finally a STOP condition. The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
Maxim Integrated 27

MAX9273
STP Cable Drive
SDA
SCL
S P
START STOP
CONDITION CONDITION
Figure 24. START and STOP Conditions
SDA
SCL
DATA LINE STABLE; CHANGE OF DATA

DATA VALID ALLOWED
Figure 25. Bit Transfer
START CLOCK PULSE FOR

CONDITION ACKNOWLEDGE
1 2 8 9
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 26. Acknowledge
Maxim Integrated 28

MAX9273
STP Cable Drive
because the slave device is the recipient. When the slave Bus Reset
device is transmitting to the master, the master generates The device resets the bus with the I2C START condition
the acknowledge bit because the master is the recipient. for reads. When the R/W bit is set to 1, the serializer/
The device generates an acknowledge even when the deserializer transmit data to the master, thus the master
forward control channel is not active (not locked). To pre- is reading from the device.
vent acknowledge generation when the forward control
Format for Writing
channel is not active, set the I2CLOCACK bit low.
A write to the serializer/deserializer comprises the trans-
Slave Address mission of the slave address with the R/W bit set to zero,
The serializer/deserializer have a 7-bit-long slave address. followed by at least one byte of information. The first
The bit following a 7-bit slave address is the R/W bit, byte of information is the register address or command
which is low for a write command and high for a read byte. The register address determines which register of
command. The slave address is 10000001 for read com- the device is to be written by the next byte, if received.
mands and 10000000 for write commands. See Figure 27. If a STOP (P) condition is detected after the register
address is received, the device takes no further action
SDA 1 0 0 0 0 0 0 R/W ACK

MSB LSB
SCL
Figure 27. Slave Address
0 = WRITE
ADDRESS = 0x80 REGISTER ADDRESS = 0x00 REGISTER 0x00 WRITE DATA
S 1 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 A D7 D6 D5 D4 D3 D2 D1 D0 A P
S = START BIT
P = STOP BIT
A = ACK
D_ = DATA BIT
Figure 28. Format for I2C Write
0 = WRITE
ADDRESS = 0x80 REGISTER ADDRESS = 0x00
S 1 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 A
S = START BIT
P = STOP BIT
REGISTER 0x00 WRITE DATA REGISTER 0x01 WRITE DATA A = ACK
N = NACK
D_ = DATA BIT
D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 N P
Figure 29. Format for Write to Multiple Registers
Maxim Integrated 29

MAX9273
STP Cable Drive
beyond storing the register address (Figure 28). Any I2C Communication with Remote-Side Devices
bytes received after the register address are data bytes. The serializer supports I2C communication with a periph-
The first data byte goes into the register selected by the eral on the remote side of the communication link using
register address, and subsequent data bytes go into SCL clock stretching. While multiple masters can reside
subsequent registers (Figure 29). If multiple data bytes on either side of the communication link, arbitration is not
are transmitted before a STOP condition, these bytes provided. The connected masters need to support SCL
are stored in subsequent registers because the register clock stretching. The remote-side I2C bit-rate range must
addresses autoincrement. be set according to the local-side I2C bit rate. Supported
remote-side bit rates can be found in Table 4. Set the
Format for Reading
I2CMSTBT (register 0x0D) to set the remote I2C bit-rate. If
The serializer/deserializer are read using the internally
using a bit rate different than 400kbps, local- and remote-
stored register address as an address pointer, the same
side I2C setup and hold times should be adjusted by set-
way the stored register address is used as an address
ting the SLV_SH register settings on both sides.
pointer for a write. The pointer autoincrements after each
data byte is read using the same rules as for a write. Thus, I2C Address Translation
a read is initiated by first configuring the register address The serializer supports I2C address translation for up to
by performing a write (Figure 30). The master can now two device addresses. Use address translation to assign
read consecutive bytes from the device, with the first data unique device addresses to peripherals with limited
byte being read from the register address pointed by I2C addresses. Source addresses (address to translate
the previously written register address. Once the master from) are stored in registers 0x09 and 0x0B. Destination
sends a NACK, the device stops sending valid data. addresses (address to translate to) are stored in
registers 0x0A and 0x0C.
0 = WRITE
ADDRESS = 0x80 REGISTER ADDRESS = 0x00
S 1 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 A
S = START BIT
1 = READ P = STOP BIT
ADDRESS = 0x81 REGISTER 0x00 READ DATA A = ACK
REPEATED START N = NACK
D_ = DATA BIT
S 1 0 0 0 0 0 0 1 A D7 D6 D5 D4 D3 D2 D1 D0 N P
Figure 30. Format for I2C Read
Table 4. I2C Bit-Rate Ranges

LOCAL BIT RATE REMOTE BIT-RATE RANGE I2CMSTBT SETTING
f > 50kbps Up to 1Mbps Any
20kbps > f > 50kbps Up to 400kbps Up to 110
f < 20kbps Up to 10kbps 000
Maxim Integrated 30

MAX9273
STP Cable Drive
Control-Channel Broadcast Mode Pre/Deemphasis Driver
The serializer supports broadcast commands to control The serial line driver employs current-mode logic (CML)
multiple peripheral devices. Select an unused device signaling. The driver is differential when programmed
address to use as a broadcast device address. Program for twisted-pair cable. When programmed for coax, one
the remote-side GMSL device to translate the broadcast side of the CML driver is used. The line driver has pro-
device address (source address stored in registers 0x09, grammable pre/deemphasis that modifies the output to
0x0B) to the peripheral device address (destination compensate for cable length. There are 13 preemphasis
address stored in register 0x0A, 0x0C). Any commands settings, as shown in Table 5. Negative preemphasis
sent to the broadcast address are sent to all designated levels are deemphasis levels where the preemphasized
peripherals, while commands sent to a peripheral’s unique swing level is the same as normal swing, but the no-
device address are sent to that particular device only. transition data (e.g., a 1 followed by a 1) is deempha-
sized. Program the preemphasis levels through register
GPO/GPI Control
0x06 D[3:0] of the serializer. This preemphasis function
GPO on the serializer follows GPI transitions on the dese-
compensates the high-frequency loss of the cable and
rializer. This GPO/GPI function can be used to transmit
enables reliable transmission over longer link distances.
signals such as frame sync in a surround-view camera
Current drive for both TP and coax modes is program-
system. The GPI-to-GPO delay is 0.35ms (max). Keep
mable. CMLLVL bits (0x06, D[7:4]) program drive current
time between GPI transitions to a minimum 0.35ms. This
in TP and coax modes for single-ended voltage swings
includes transitions from the other deserializer in the
from 100mV to 500mV.
coax-mode splitter. Bit D4 of register 0x0E in the deserial-
izer stores the GPI input state. GPO is low after power-up. Spread Spectrum
The FC can set GPO by writing to the SET_GPO register To reduce the EMI generated by the transitions on the
bit. Do not send a logic-low value on the serializer RX/ serial link, the serializer output is programmable for
SDA input (UART mode) longer than 100Fs in either base spread spectrum. If the deserializer driven by the serial-
or bypass mode to ensure proper GPO/GPI functionality. izer has programmable spread spectrum, do not enable
spread for both at the same time or their interaction
Table 5. TP/Coax Drive Current (CMLLVL = 1000)

PREEMPHASIS PREEMP SETTING ICML SINGLE-ENDED VOLTAGE SWING
IPRE (mA)
LEVEL (dB)* (0x06, D[3:0]) (mA) MAX (mV) MIN (mV)
-6.0 0100 12 4 400 200
-4.1 0011 13 3 400 250
-2.5 0010 14 2 400 300
-1.2 0001 15 1 400 350
0
0000 16 0 400 400
(power-on default)
1.1 1000 16 1 425 375
2.2 1001 16 2 450 350
3.3 1010 16 3 475 325
4.4 1011 16 4 500 300
6.0 1100 15 5 500 250
8.0 1101 14 6 500 200
10.5 1110 13 7 500 150
14.0 1111 12 8 500 100
*Negative preemphasis levels denote deemphasis.
Maxim Integrated 31

MAX9273
STP Cable Drive
Table 6. Serial Output Spread
SS SPREAD (%)
000 No spread spectrum. Power-up default.
001 ±0.5% spread spectrum.
011 ±2% spread spectrum.
100 No spread spectrum.
Table 7. Spread Limitations

BWS = 0 MODE, PCLKIN BWS = 1 MODE PCLKIN SERIAL LINK BIT RATE AVAILABLE
FREQUENCY (MHz) FREQUENCY (MHz) (Mbps) SPREAD RATES
< 33.3 < 25
(DBL=0) (DBL = 0)
< 1000 All rates available
< 66.6 < 50
(DBL = 1) (DBL = 1)
33.3 to 50 25 to 37.5
(DBL = 0) (DBL = 0)
R 1000 1.5%, 1.0%, 0.5%
66.6 to 100 50 to 75
(DBL = 1) (DBL = 1)
cancels benefits. The deserializer tracks the serializer’s Manual Programming of the
spread and passes the spread to the deserializer output. Spread-Spectrum Divider
The programmable spread-spectrum amplitudes are The modulation rate relates to the PCLKIN frequency as
Q0.5%, Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 6). follows:
Some spread-spectrum amplitudes can only be used at
fPCLKIN
lower PCLKIN frequencies (Table 7). There is no PCLKIN fM= (1 + DRS)
frequency limit for the Q0.5% spread rate. MOD x SDIV
When the spread spectrum is turned on or off, the serial where:
link stops for several microseconds and then restarts in fM = Modulation frequency
order for the deserializer to lose and relock to the new DRS = DRS value (0 or 1)
serial-data stream. fPCLKIN = PCLKIN frequency
The serializer includes a sawtooth divider to control the MOD = Modulation coefficient given in Table 8
spread-modulation rate. Autodetection of the PCLKIN
SDIV = 6-bit SDIV setting, manually programmed by the FC
operation range guarantees a spread-spectrum modu-
lation frequency within 20kHz to 40kHz. Additionally, To program the SDIV setting, first look up the modula-
manual configuration of the sawtooth divider (SDIV: 0x03, tion coefficient according to the desired bus-width and
D[5:0]) allows the user to set a modulation frequency spread-spectrum settings. Solve the above equation for
according to the PCLKIN frequency. When ranges are SDIV using the desired pixel clock and modulation fre-
manually selected, program the SDIV value for a fixed quencies. If the calculated SDIV value is larger than the
modulation frequency around 20kHz. maximum allowed SDIV value in Table 8, set SDIV to the
maximum value.
Maxim Integrated 32

MAX9273
STP Cable Drive
Table 8. Modulation Coefficients and The parity bit is still added when CRC is enabled,
because it is used for word-boundary detection. When
Maximum SDIV Settings
CRC is enabled, each data word is scrambled and then
SPREAD- MODULATION the 6-bit CRC and 1-bit parity are added before the
SDIV UPPER 8b/10b encoding.
BWS SPECTRUM COEFFICIENT
LIMIT (dec)
SETTING (%) (dec) At the deserializer, the CRC code is recalculated. If the
1 104 40 recalculated CRC code does not match the received CRC
0.5 104 63 code, an error is flagged. This CRC error is reported to the
3 152 27 error counter.
1
1.5 152 54 Hamming Code
4 204 15 Hamming code is a simple and effective error-correction
2 204 30 code to detect and/or correct errors. The MAX9273 seri-
1 80 52 alizer (when used with the MAX9272 GMSL deserializer)
uses single-error correction/double-error detection per
0.5 80 63
pixel hamming-code scheme.
3 112 37
0 The serializer uses data interleaving for burst-error toler-
1.5 112 63
ance. Burst errors up to 11 consecutive bits on the serial
4 152 21
link are corrected, and burst errors up to 31 consecutive
2 152 42 bits are detected.
Hamming code adds overhead similar to CRC. See Table 2
Additional Error Detection and Correction for details regarding the available input word size.
In default mode (additional error detection and correction
disabled), data encoding/decoding is the same as in pre- HS/VS Encoding and/or Tracking
vious GMSL serializers/deserializers (parity only). At the HS/VS encoding by a GMSL serializer allows horizontal
serializer, the parallel input word is scrambled and a par- and vertical synchronization signals to be transmitted
ity bit added. The scrambled word is divided into 3 or 4 while conserving pixel data bandwidth. With HS/VS
bytes (depending on the BWS setting), 8b/10b encoded, encoding enabled, 10-bit pixel data with a clock up to
and then transmitted serially. At the deserializer, the same 100MHz can be transmitted using 1 pixel of data per HS/
operations are performed in reverse order. The parity bit VS transition, versus 8-bit data with a clock up to 100MHz
is used by the deserializer to find the word boundary and without HS/VS encoding. The deserializer performs HV
for error detection. Errors are counted in an error counter decoding, tracks the period of the HV signals, and uses
register and an error pin indicates errors. voting to filter HS/VS bit errors. When using HV encod-
The serializer can use of of two additional error-detection/ ing, use a minimum low-pulse duration of two PCLKIN
correction methods (selectable by register setting): cycles when DBL = 0 on the MAX9271/MAX9273. When
1) 6-bit cyclic redundancy check DBL = 1, use a minimum HS/VS low-pulse duration of
five PCLKIN cycles and a minimum high-pulse duration
2) 6-bit hamming code with 16-word interleaving
of two PCLKIN cycles. When using hamming code and
Cyclic Redundancy Check (CRC) HS/VS encoding, do not send more than two transitions
When CRC is enabled, the serializer adds 6 bits of CRC to every 16 PCLKIN cycles.
the input data. This reduces the available bits in the input
data word by 6, compared to the non-CRC case (see When the serializer uses double-input mode (DBL = 1),
Table 2 for details). For example, 16 bits are available for the active duration, plus the blanking duration of HS or
input data instead of 22 bits when BWS = 0, and 24 bits VS signals, should be an even number of PCLKIN cycles.
instead of 30 bits when BWS = 1. If HS/VS tracking is used without HV encoding, use DIN0
The CRC generator polynomial is x6
+ x + 1 (as used in for HSYNC and DIN1 for VSYNC. In this case, if DBL
the ITU-T G704 telecommunication standard). values on the serializer and the deserializer are different,
set the deserializer’s UNEQDBL register bit to 1. If the
Maxim Integrated 33

MAX9273
STP Cable Drive
serializer and deserializer have unequal DBL settings attached peripherals. Assign a unique device address to
and HVEN = 0, then HS/VS inversion should only be used send control data to one deserializer. Leave all unused
on the side that has DBL = 1. HS/VS encoding sends IN_ pins unconnected, or connect them to ground
packets when HSYNC or VSYNC is low, use HS/VS inver- through 50I and a capacitor for increased power-supply
sion register bits if the input HSYNC and VSYNC signals rejection. If OUT- is not used, connect OUT- to AVDD
use an active-low convention to send data packets dur- through a 50I resistor (Figure 32). When there are FCs
ing the inactive pixel clock periods. at the serializer, and at each deserializer, only one FC
can communicate at a time. Disable one splitter control-
Serial Output channel link to prevent contention. Use the DIS_REV_P or
The driver output is programmable for two types of cable: DIS_REV_N register bits to disable a control-channel link.
100I twisted pair and 50I coax (contact the factory for
serializers with 75I cable drive). Configuration Inputs (CONF1, CONF0)
CONF1 and CONF0 determine the power-up values of the
Coax-Mode Splitter serial output type, the input data latch, and the control-
In coax mode, OUT+ and OUT- are active. This enables channel interface type (Table 9). These functions can
use as a 1:2 splitter (Figure 31). In coax mode, connect be changed after power-up by writing to the appropriate
OUT+ to IN+ of the deserializer. Connect OUT- to IN- of register bits
the second deserializer. Control-channel data is broad-
cast from the serializer to both deserializers and their
MAX9273 GMSL
DESERIALIZER
MAX9273 GMSL
DESERIALIZER
OUT+ IN+
OUT- IN- OUT+ IN+
OUT- IN-
AVDD
GMSL
DESERIALIZER
50I
IN+
IN-
Figure 31. 2:1 Coax-Mode Splitter Connection Diagram Figure 32. Coax-Mode Connection Diagram
Table 9. Configuration Input Map

CXTP ES I2CSEL
CONF1 CONF0
(OUT+/OUT- OUTPUT TYPE) (PCLKIN LATCH EDGE) (CONTROL-CHANNEL TYPE)
Low Low 1 (coax) 1 (falling) 1 (I2C-to-I2C)
Low Mid 1 (coax) 1 (falling) 0 (UART-to-I2C/UART)
Low High 1 (coax) 0 (rising) 1 (I2C-to-I2C)
Mid Low 1 (coax) 0 (rising) 0 (UART-to-I2C/UART)
Mid Mid 0 (STP) 1 (falling) 1 (I2C-to-I2C)
Mid High 0 (STP) 1 (falling) 0 (UART-to-I2C/UART)
High Low 0 (STP) 0 (rising) 1 (I2C-to-I2C)
High Mid 0 (STP) 0 (rising) 0 (UART-to-I2C/UART)
High High Do not use Do not use Do not use
Maxim Integrated 34

MAX9273
STP Cable Drive
Sleep Mode disabled, the device can only be woken up from the local
The serializer includes a sleep mode to reduce power control channel. To wake up the device, send an arbitrary
consumption. The device enters or exits sleep mode by control-channel command to the serializer. Wait 5ms
a command from a local FC or a remote FC using the for the chip to power up and then write 0 to the SLEEP
control channel. Set the SLEEP bit to 1 to initiate sleep register bit to make the wake-up permanent.
mode. The serializer sleeps immediately after setting
Power-Down Mode
its SLEEP = 1. The OUT+ and OUT- serial outputs each
The serializer has a power-down mode that further reduc-
have wake-up receiver to accept wake-up commands
es power consumption compared to sleep mode. Set
from the attached deserializers. On power-up, the OUT+
PWDN low to enter power-down mode. In power-down
wake-up receiver is enabled and the OUT- wake-up
mode, the serial outputs are in high impedance. Entering
receiver is disabled. Disable the wake-up receivers
power-down resets the device’s registers. Upon exiting
(through ENWAKEP or ENWAKEN) if the devices are
power-down, the state of the MS, DRS, CONF0, CONF1,
disconnected or wake-up is not used in order to reduce
and AUTOS pins are latched.
sleep-mode current. If both wake-up receivers are
Table 10. Startup Procedure for Video-Display Applications

NO. µC SERIALIZER DESERIALIZER
Sets all configuration inputs. If any Sets all configuration inputs. If any
configuration inputs are available configuration inputs are available
— FC connected to serializer. on one end of the link but not on on one end of the link but not on
the other, always connects that the other, always connects that
configuration input low. configuration input low.
1 Powers up. Powers up and loads default settings. Powers up and loads default settings.
Enables configuration link by
setting CLINKEN = 1 (if not
2 enabled automatically) and gets Establishes configuration link. Locks to configuration link signal.
an acknowledge. Waits for link
to be established (~3ms).
Writes one link configuration
Configuration changed from default
bit (DRS, BWS, or EDC) in
3 — settings (loss-of-lock occurs if BWS or
the deserializer and gets an
EDC changes).
acknowledge.
Writes corresponding serializer
4 link configuration bit and gets Relocks to configuration link signal.
settings.
an acknowledge.
Waits for link to be established
(~3ms) and then repeats steps
5 — —
3 through 4 until all serial link
bits are configured.
Writes remaining configuration
Configuration changed from default Configuration changed from default
6 bits in the serializer/deserializer
settings. settings.
and gets an acknowledge.
Enables video link by setting
SEREN = 1 and gets an Locks to serial link signal and begins
7 Begins serializing data.
acknowledge. Waits for link to deserializing data.
be established (~3ms).
Maxim Integrated 35

MAX9273
STP Cable Drive
Table 11. Startup Procedure for Image-Sensing Applications
NO. µC SERIALIZER DESERIALIZER
Sets all configuration inputs. If any Sets all configuration inputs. If any
inputs are available on one chip but inputs are available on one chip but
— FC connected to deserializer.
not on the other, always connects not on the other, always connects
input low. input low.
Powers up and loads default settings. Powers up and loads default settings.
1 Powers up.
Establishes serial link. Locks to serial link signal.
Writes deserializer configuration
3 — settings (loss-of-lock occurs if BWS or
bits and gets an acknowledge.
EDC changes).
Writes serializer configuration

bits. Does not get an
4 acknowledge (or gets a dummy Relocks to serial link signal.
settings.
acknowledge) if loss-of-lock
occurred.
Enables video link by setting

SEREN = 1 (if not enabled
automatically). Cannot get an
Locks to serial link signal and begins
5 acknowledge (or gets a dummy Begins serializing data.
deserializing data.
acknowledge) if loss-of-lock
occurred. Waits for link to be
established (~3ms).
AUTOS PIN SEREN POWER-UP

SETTING VALUE
LOW 1
HIGH 0
CLINKEN = 0 OR
SEREN = 1
CLINKEN = 0 OR
SLEEP = 1 SEREN = 1 CONFIG LINK CONFIG LINK
FOR > 8ms SLEEP = 0, POWER-ON CONFIG UNLOCKED OPERATING
SLEEP WAKE-UP
SEREN = 0 IDLE CLINKEN = 1 LINK STARTED CONFIG LINK PROGRAM
LOCKED REGISTERS
WAKE-UP SIGNAL
SEREN = 1,
SEREN = 0 OR
SLEEP = 0, PCLKIN RUNNING
SLEEP = 1 NO PCLKIN
SEREN = 1
SEREN = 0 OR
NO PCLKIN
PWDN = HIGH, PRBSEN = 0
PWDN = LOW OR POWER-DOWN VIDEO LINK
POWER-ON VIDEO VIDEO LINK VIDEO LINK
ALL STATES OR
POWER-OFF AUTOS = LOW LINK LOCKING LOCKED OPERATING PRBSEN = 1 PRBS TEST
POWER-OFF
VIDEO LINK
PWDN = HIGH, UNLOCKED
POWER-ON
AUTOS = HIGH
Figure 33. State Diagram, All Applications
Maxim Integrated 36

MAX9273
STP Cable Drive
Configuration Link acknowledge frame is not generated when communica-
The control channel can operate in a low-speed mode tion fails due to contention. If communication across the
called configuration link in the absence of a clock input. serial link is not required, the FCs can disable the forward
This allows a microprocessor to program configura- and reverse control channel using the FWDCCEN and
tion registers before starting the video link. An internal REVCCEN bits (0x04, D[1:0]) in the serializer/deserial-
oscillator provides the clock for configuration link. Set izer. Communication across the serial link is stopped and
CLINKEN = 1 on the serializer to enable configuration contention between FCs cannot occur.
link. Configuration link is active until the video link is As an example of dual FC use in an image-sensing appli-
enabled. The video link overrides the configuration link cation, the serializer can be in sleep mode, waiting for
and attempts to lock when SEREN = 1. wake-up by the FC on the deserializer side. After wake-
up, the serializer-side FC assumes master control of the
Link Startup Procedure serializer’s registers.
Table 10 lists the start-up procedure for video-display
applications. Table 11 lists the startup procedure for Jitter-Filtering PLL
image-sensing applications. The control channel is avail- In some applications, the clock input (PCLKIN) includes
able after the video link or the configuration link is estab- noise, which reduces link reliability. The clock input has a
lished. If the deserializer powers up after the serializer, programmable narrowband jitter-filter PLL that attenuates
the control channel becomes unavailable until 2ms after frequencies higher than 100kHz (typ). Enable the jitter-
power-up. filter by setting ENJITFILT = 1 (0x05, D6).
Applications Information PCLKIN Spread Tracking

The serializer can operate with a spread PCLKIN signal.
When using a spread PCLKIN signal, disable the jitter-
PRBS Test
filter by setting ENJITFILT = 0 (0x05, D6). Do not exceed
The serializer includes a PRBS pattern generator that
the spread limitations in Table 7 and keep modulation
works with bit-error verification in the deserializer. To run
less than 40kHz. In addition, turn off spread spectrum
the PRBS test, set PRBSEN = 1 (0x04, D5) in the deserial-
in the serializer/deserializer. The serializer/deserializer
izer and then in the serializer. To exit the PRBS test, set track the spread on PCLKIN.
PRBSEN = 0 (0x04, D5) in the serializer.
Changing the Clock Frequency
Error Generator It is recommended that the serial link be enabled after
The serializer contains an error generator that enables the video clock (fPCLKIN) and the control-channel clock
repeatable testing of the error-detection/correction fea- (fUART/fI2C) are stable. When changing clock frequency,
tures of the GMSL link. Register 0x11 stores the configu- stop the video clock for 5Fs, apply the clock at the new
ration bits for the error generator. A FC sets the error- frequency, then restart the serial link or toggle SEREN.
generation rate, type of errors, and the total number of On-the-fly changes in clock frequency are possible if
errors. The error generator is off by default. the new frequency is immediately stable and without
Dual µC Control glitches. The reverse control channel remains unavail-
Usually systems have one FC to run the control channel, able for 350Fs after serial link start or stop. When using
located on the serializer side for video-display appli- the UART interface, limit on-the-fly changes in fUART to
cations or on the deserializer side for image-sensing factors of less than 3.5 at a time to ensure that the device
applications. However, a FC can reside on each side recognizes the UART sync pattern. For example, when
simultaneously and trade off running the control channel. lowering the UART frequency from 1Mbps to 100kbps,
In this case, each FC can communicate with the serializer first send data at 333kbps, then at 100kbps for reduction
and deserializer and any peripheral devices. ratios of 3 and 3.333, respectively.
Contention occurs if both FCs attempt to use the control Fast Detection of Loss-of-Synchronization
channel at the same time. It is up to the user to prevent A measure of link quality is the recovery time from loss-of-
this contention by implementing a higher-level protocol. synchronization. The host can be quickly notified of loss-
In addition, the control channel does not provide arbitra- of-lock by connecting the deserializer’s LOCK output to
tion between I2C masters on both sides of the link. An the deserializer’s GPI input. If LOCK is lost, GPO on the
Maxim Integrated 37

MAX9273
STP Cable Drive
serializer follows the transition of LOCK at GPI. If other corresponding register on the other device (register 0x00
sources also use the GPI input, the FC can implement of the deserializer for serializer device address change,
a routine to distinguish between interrupts from loss-of- or register 0x01 of the serializer for deserializer device
lock and normal interrupts. The control channel does not address change).
require an active video link and thus can always monitor
LOCK. LOCK asserts for a synchronized video link but Three-Level Configuration Inputs
not for the configuration link. CONF1 and CONF0 are three-level inputs that control
the serial interface configuration and power-up defaults.
Providing a Frame Sync Connect CONF1or CONF0 through a pullup resistor to
(Camera Applications) IOVDD to set a high level, a pulldown resistor to GND to
The GPI/GPO provides a simple solution for camera set a low level, or IOVDD/2 or open to set a midlevel. For
applications that require a frame sync signal from the digital control, use three-state logic to drive the three-
ECU (e.g., surround-view systems). Connect the ECU level logic inputs.
frame sync signal to the GPI input and connect the GPO
output to the camera frame sync input. GPI/GPO have a Configuration Blocking
typical delay of 275Fs. Skew between multiple GPI/GPO The serializer can block changes to registers. Set
channels is maximum 115Fs. If a lower skew signal is CFGBLOCK to make all registers read only. Once set, the
required, connect the camera’s frame sync input to one registers remain blocked until the supplies are removed
of the serializer’s GPIOs and use an I2C broadcast write or until PWDN is low.
command to change the GPIO output state. This has a
maximum skew of 1.5Fs, independent from the used I2C Compatibility with Other GMSL Devices
bit rate. The MAX9273 serializer is designed to pair with the
MAX9272 deserializer, but interoperates with any GMSL
Software Programming of the deserializer. See Table 12 for operating limitations.
Device Addresses
The serializer and deserializer have programmable device GPIOs
addresses. This allows multiple GMSL devices, along with The serializer has five open-drain GPIOs available when
I2C peripherals, to coexist on the same control channel. not used as data or configuration inputs. Setting the GPIO
The serializer device address is in register 0x00 of each enable bits (register 0x0E) to 1 enables the GPIOs and
device, while the deserializer device address is in register internally connects the respective data or configuration
0x01 of each device. To change a device address, first input low. Setting the GPIO output bits to 0 pulls the output
write to the device whose address changes (register 0x00 low, while setting the bits to 1 leaves the output undriven,
of the serializer for serializer device address change, or and pulled high through internal/external pullup resistors.
register 0x01 of the deserializer for deserializer device The GPIO input buffers are enabled when the GPIO is
address change). Then write the same address into the enabled. The input states are stored in register 0x10. Set
GPIO_OUT to 1 when using a GPIO_ as an input.
Table 12. MAX9273 Feature Compatibility

MAX9273 FEATURE GMSL DESERIALIZER
HSYNC/VSYNC encoding If feature not supported in deserializer, must be turned off in the serializer.
Hamming-code error
If feature not supported in deserializer, must be turned off in the serializer.
correction
I2C-to-I2C If feature not supported in deserializer, must use UART-to-I2C or UART-to-UART.
CRC error detection If feature not supported in deserializer, must be turned off in the serializer.
If feature not supported in deserializer, data is output as a single word at half the input
Double input
frequency.
If feature not supported in deserializer, must connect unused serial input through 200nF and
Coax
50I in series to AVDD and set the reverse control-channel amplitude to 100mV.
I2S encoding If supported in the deserializer, disable I2S in the deserializer.
Maxim Integrated 38

MAX9273
STP Cable Drive
Internal Input Pulldowns and the series AC-coupling capacitors (C). The RC time
The control and configuration inputs (except three-level constant for four equal-value series capacitors is (C x
inputs) include a pulldown resistor to GND. External pull- (RTD + RTR))/4. RTD and RTR are required to match the
down resistors are not needed. transmission line impedance (usually 100I differential,
50I single-ended). This leaves the capacitor selection
Choosing I2C/UART Pullup Resistors to change the system time constant. Use 0.2FF or larger
The I2C and UART open-drain lines require a pullup high-frequency surface-mount ceramic capacitors, with
resistor to provide a logic-high level. There are tradeoffs sufficient voltage rating to withstand a short to battery, to
between power dissipation and speed, and a compro- pass the lower speed reverse control-channel signal. Use
mise may be required when choosing pullup resistor capacitors with a case size less than 3.2mm x 1.6mm to
values. Every device connected to the bus introduces have lower parasitic effects to the high-speed signal.
some capacitance even when the device is not in opera-
tion. I2C specifies 300ns rise times (30% to 70%) for fast Power-Supply Circuits and Bypassing
mode, which is defined for data rates up to 400kbps (see The serializer uses an AVDD and DVDD of 1.7V to 1.9V.
the I2C specifications in the AC Electrical Characteristics All inputs and outputs, except for the serial output, derive
table for details). To meet the fast-mode rise-time require- power from an IOVDD of 1.7V to 3.6V that scales with
ment, choose the pullup resistors so that rise time tR = IOVDD. Proper voltage-supply bypassing is essential for
0.85 x RPULLUP x CBUS < 300ns. The waveforms are not high-frequency circuit stability.
recognized if the transition time becomes too slow. The
Power-Supply Table
serializer supports I2C/UART rates up to 1Mbps (UART-
Power-supply currents shown in the Electrical
to-I2C mode) and 400kbps (I2C-to-I2C mode).
Characteristics table are the sum of the currents from
AC-Coupling AVDD, DVDD, and IOVDD. Typical currents from the
AC-coupling isolates the receiver from DC voltages up individual power supplies are shown in Table 13.
to the voltage rating of the capacitor. Capacitors at the
Cables and Connectors
serializer output and at the deserializer input are needed
Interconnect for CML typically has a differential imped-
for proper link operation and to provide protection if
ance of 100I. Use cables and connectors that have
either end of the cable is shorted to battery. AC-coupling
matched differential impedance to minimize impedance
blocks low-frequency ground shifts and low-frequency
discontinuities. Coax cables typically have a characteristic
common-mode noise.
impedance of 50I (contact the factory for 75I operation).
Selection of AC-Coupling Capacitors Table 14 lists the suggested cables and connectors used
Voltage droop and the digital sum variation (DSV) of trans- in the GMSL link.
mitted symbols cause signal transitions to start from dif-
ferent voltage levels. Because the transition time is fixed, Table 13. Typical Power-Supply Currents
starting the signal transition from different voltage levels (Using Worst-Case Input Pattern)
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an PCLK AVDD DVDD IOVDD
acceptable level. The RC network for an AC-coupled link (MHz) (mA) (mA) (mA)
consists of the CML/coax receiver termination resistor 25 29.5 9.4 0.2
(RTR), the CML/coax driver termination resistor (RTD), 50 34.9 14.4 0.3
Table 14. Suggested Connectors and Cables for GMSL

SUPPLIER CONNECTOR CABLE TYPE
Rosenberger 59S2AX-400A5-Y RG174 Coax
JAE MX38-FF A-BW-Lxxxxx STP
Nissei GT11L-2S F-2WME AWG28 STP
Rosenberger D4S10A-40ML5-Z Dacar 538 STP
Maxim Integrated 39

MAX9273
STP Cable Drive
Board Layout do not have 100I differential impedance when brought
Separate the LVCMOS logic signals and CML/coax high- close together—the impedance goes down when the
speed signals to prevent crosstalk. Use a four-layer PCB traces are brought closer. Use a 50I trace for the single-
with separate layers for power, ground, CML/coax, and ended output when driving coax.
LVCMOS logic signals. Layout PCB traces close to each Route the PCB traces for differential CML in parallel to
other for a 100I differential characteristic impedance. maintain the differential characteristic impedance. Avoid
The trace dimensions depend on the type of trace used vias. Keep PCB traces that make up a differential pair
(microstrip or stripline). Note that two 50I PCB traces equal length to avoid skew within the differential pair.
ESD Protection
RD ESD tolerance is rated for Human Body Model, IEC
1MI 1.5kI
61000-4-2, and ISO 10605. The ISO 10605 and IEC
CHARGE-CURRENT- DISCHARGE 61000-4-2 standards specify ESD tolerance for electronic
LIMIT RESISTOR RESISTANCE systems. The serial outputs are rated for ISO 10605 ESD
HIGH-
VOLTAGE CS STORAGE DEVICE protection and IEC 61000-4-2 ESD protection. All pins
100pF CAPACITOR UNDER are tested for the Human Body Model. The Human Body
DC
TEST
SOURCE Model discharge components are CS = 100pF and RD =
1.5kI (Figure 34). The IEC 61000-4-2 discharge compo-
nents are CS = 150pF and RD = 330I (Figure 35). The
ISO 10605 discharge components are CS = 330pF and
Figure 34. Human Body Model ESD Test Circuit RD = 2kI (Figure 36).
RD RD
330I 2kI
CHARGE-CURRENT- DISCHARGE CHARGE-CURRENT- DISCHARGE

LIMIT RESISTOR RESISTANCE LIMIT RESISTOR RESISTANCE
HIGH- HIGH-
CS STORAGE DEVICE CS STORAGE DEVICE
VOLTAGE VOLTAGE
150pF CAPACITOR UNDER 330pF CAPACITOR UNDER
DC DC
TEST TEST
SOURCE SOURCE
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit Figure 36. ISO 10605 Contact Discharge ESD Test Circuit
Maxim Integrated 40

MAX9273
STP Cable Drive
Table 15. Register Table (see Table 1)
REGISTER DEFAULT
BITS NAME VALUE FUNCTION
ADDRESS VALUE
D[7:1] SERID XXXXXXX Serializer device address. 1000000
0x00 0 Normal operation.
D0 CFGBLOCK 0
1 Registers 0x00 to 0x1F are read only.
D[7:1] DESID XXXXXXX Deserializer device address. 1001000
0x01
D0 — 0 Reserved. 0
D[7:5] SS 000
0x02 D4 — 1 Reserved. 1
00 12.5MHz to 25MHz pixel clock.
01 25MHz to 50MHz pixel clock.
D[3:2] PRNG 11
10 Automatically detect the pixel clock range.
11 Automatically detect the pixel clock range.
00 0.5 to 1Gbps serial-bit rate.
01 1 to 2Gps serial-bit rate.
D[1:0] SRNG 11
10 Automatically detect serial-bit rate.
11 Automatically detect serial-bit rate.
Calibrate spread-modulation rate only once after
00
locking.
Calibrate spread-modulation rate every 2ms after
01
locking.
D[7:6] AUTOFM 00
10
0x03 locking.
11
locking.
000000 Autocalibrate sawtooth divider.
D[5:0] SDIV Manual SDIV setting. See the Manual Programming 000000
XXXXXX
of the Spread-Spectrum Divider section.
Maxim Integrated 41

MAX9273
STP Cable Drive
Table 15. Register Table (see Table 1) (continued)
REGISTER DEFAULT
ADDRESS VALUE
Disable serial link. Power-up default when AUTOS

= high. Reverse control-channel communication
0
remains unavailable for 350Fs after the serializer
starts/stops the serial link.
D7 SEREN 0, 1
Enable serial link. Power-up default when AUTOS
= low. Reverse control-channel communication
1
remains unavailable for 350Fs after the serializer
starts/stops the serial link.
0 Disable configuration link.
D6 CLINKEN 0
1 Enable configuration link.
0 Disable PRBS test.
D5 PRBSEN 0
1 Enable PRBS test.
0x04 0 Normal mode.
D4 SLEEP 0
1 Activate sleep mode.
00 Local control channel uses I2C when I2CSEL = 0.
D[3:2] INTTYPE 01 Local control channel uses UART when I2CSEL = 0. 00
10, 11 Local control channel disabled.
Disable reverse control channel from deserializer
0
(receiving).
D1 REVCCEN 1
Enable reverse control channel from deserializer
1
(receiving).
Disable forward control channel to deserializer
0
(sending).
D0 FWDCCEN 1
Enable forward control channel to deserializer
1
(sending).
I2C conversion sends the register address when
0
converting UART to I2C.
D7 I2CMETHOD Disable sending of I2C register address when 0
1 converting UART-to-I2C (command-byte
-only mode).
0 Jitter filter disabled.
D6 ENJITFILT 0
1 Jitter filter active.
00 Continuous PRBS length.
0x05
01 9.83Mbit PRBS length.
D[5:4] PRBSLEN 00
D[3:2] — 00 Reserved. 00
0 Disable wake-up receiver.
D1 ENWAKEN 0
1 Enable OUT- wake-up receiver during sleep mode.
0 Disable wake-up receiver.
D0 ENWAKEP 1
1 Enable OUT- wake-up receiver during sleep mode.
Maxim Integrated 42

MAX9273
STP Cable Drive
REGISTER DEFAULT
ADDRESS VALUE
0000 Do not use.
0001 Do not use.
0010 100mV output level.
0110 300mV output level
400mV output level. Power-up default when
D[7:4] CMLLVL 1000 1000, 1010
twisted-pair output is selected (Table 9).
1001 450mV output level
500mV output level. Power-up default when coax
1010
output is selected (Table 9).
1011 Do not use.
1100 Do not use.
1101 Do not use.
1110 Do not use.
0x06
1111 Do not use.
0000 Preemphasis off.
0001 -1.2dB preemphasis.
0101 Do not use.
0110 Do not use.
0111 Do not use.
D[3:0] PREEMP 0000
1000 1.1dB preemphasis.
Maxim Integrated 43

MAX9273
STP Cable Drive
REGISTER DEFAULT
ADDRESS VALUE
0 Single-input mode.
D7 DBL 0
1 Double-input mode.
0 High data-rate mode.
D6 DRS 0
1 Low data-rate mode.
0 24-bit mode.
D5 BWS 0
1 32-bit mode.
Input data latched on rising edge of PCLKIN.
Power-up default determined by CONF1 and
0
CONF0 (Table 9). Do not change this value while
the pixel clock is running.
D4 ES 0, 1
Input data latched on falling edge of PCLKIN.
0x07 Power-up default determined by CONF1 and
1
CONF0 (Table 9). Do not change this value while
the pixel clock is running.
0 HS/VS encoding disabled.
D2 HVEN 0
1 HS/VS encoding enabled.
1-bit parity error detection
00
(GMSL compatible).
01 6-bit CRC error detection.
D[1:0] EDC 00
6-bit hamming code (single-bit error correct,
10
double-bit error detect) and 16- word interleaving.
11 Do not use.
0 No VS or DIN0 inversion.
Invert VS when HVEN = 1.
D7 INVVS Invert DIN0 when HVEN = 0. 0
1
Do not use if DBL = 0 in the serializer and
DBL = 1 in the deserializer.
0x08 0 No HS or DIN1 inversion
Invert HS when HVEN = 1.
D6 INVHS Invert DIN1 when HVEN = 0. 0
1
Do not use if DBL = 0 in the serializer and
DBL = 1 in the deserializer.
D[5:0] — 000000 Reserved. 000000
D[7:1] I2CSRCA XXXXXXX I2C address translator source A. 0000000
0x09
D[7:1] I2CDSTA XXXXXXX I2C address translator destination A. 0000000
0x0A
D[7:1] I2CSRCB XXXXXXX I2C address translator source B. 0000000
0x0B
Maxim Integrated 44

MAX9273
STP Cable Drive
REGISTER DEFAULT
ADDRESS VALUE
D[7:1] I2CDSTB XXXXXXX I2C address translator destination B. 0000000
0x0C
Acknowledge not generated when forward channel
0
is not available.
D7 I2CLOCACK 1
I2C-to-I2C slave generates local acknowledge
1
when forward channel is not available.
00 352ns/117ns I2C setup/hold time.
D[6:5] I2CSLVSH 01
000 8.47kbps (typ) I2C-to-I2C master bit-rate setting.
0x0D
011 105kbps (typ) I2C-to-I2C master bit-rate setting.
D[4:2] I2CMSTBT 101
00 64Fs (typ) I2C-to-I2C slave remote timeout.
D[1:0] I2CSLVTO 10
11 No I2C-to-I2C slave remote timeout.
0 OUT+ reverse channel receiver enabled.
D7 DIS_REV_P 0
1 OUT+ reverse channel receiver disabled.
0 OUT- reverse channel receiver enabled.
D6 DIS_REV_N 1
1 OUT- reverse channel receiver disabled.
0 Disable GPIO5.
D5 GPIO5EN 0
1 Enable GPIO5.
0 Disable GPIO4.
D4 GPIO4EN 0
0x0E 1 Enable GPIO4.
0 Disable GPIO3.
D3 GPIO3EN 0
1 Enable GPIO3.
0 Disable GPIO2.
D2 GPIO2EN 0
1 Enable GPIO2.
0 Disable GPIO1.
D1 GPIO1EN 1
1 Enable GPIO1.
Maxim Integrated 45

MAX9273
STP Cable Drive
REGISTER DEFAULT
ADDRESS VALUE
D[7:6] — 11 Reserved. 11
0 Set GPIO5 low.
D5 GPIO5OUT 1
1 Set GPIO5 high.
0 Set GPIO4 low.
D4 GPIO4OUT 1
1 Set GPIO4 high.
0 Set GPIO3 low.
D3 GPIO3OUT 1
0x0F 1 Set GPIO3 high.
0 Set GPIO2 low.
D2 GPIO2OUT 1
1 Set GPIO2 high.
0 Set GPIO1 low.
D1 GPIO1OUT 1
1 Set GPIO1 high.
0 Set GPO low.
D0 SETGPO 0
1 Set GPO high.
D[7:6] — 00 Reserved. 00
0 GPIO5 is low. 1
D5 GPIO5IN
1 GPIO5 is high. (read only)
0 GPIO4 is low. 1
D4 GPIO4IN
0 GPIO3 is low. 1
D3 GPIO3IN
0x10 1 GPIO3 is high. (read only)
0 GPIO2 is low. 1
D2 GPIO2IN
0 GPIO1 is low. 1
D1 GPIO1IN
0 GPO is set low. 0
D0 GPO_L
1 GPO is set high. (read only)
00 Generate an error every 2560 bits.
01 Generate an error every 40,960 bits.
D[7:6] ERRGRATE 00
10 Generate an error every 655,360 bits.
11 Generate an error every 10,485,760 bits.
00 Generate single-bit errors.
01 Generate 2 (8b/10b) symbol errors.
D[5:4] ERRGTYPE 00
0x11
00 Continuously generate errors.
01 16 generated errors.
D[3:2] ERRGCNT 00
0 Disable periodic error generation.
D1 ERRGPER 0
1 Enable periodic error generation.
0 Disable error generator.
D0 ERRGEN 0
1 Enable error generator.
Maxim Integrated 46

MAX9273
STP Cable Drive
REGISTER DEFAULT
ADDRESS VALUE
0x12 D[7:0] — 01000000 Reserved. 01000000
0x13 D[7:0] — 00100010 Reserved 00100010
00000000
0x14 D[7:0] — XXXXXXXX Reserved.
(read only)
0 CXTP input is low. 0
D7 CXTP
1 CXTP input is high. (read only)
0 Input is high. 0
D6 I2CSEL
1 Input is low. (read only)
0 Input is high. 0
D5 LCCEN
1 Input is low. (read only)
0x15
000
D[4:2] — 000 Reserved.
(read only)
0 Output disabled. 0
D1 OUTPUTEN
1 Output enabled. (read only)
0 Valid PCLKIN detected. 0
D0 PCLKDET
1 Valid PCLKIN not detected. (read only)
00000000
(read only)
00000000
(read only)
00001011
0x1E D[7:0] ID 00001011 Device identifier (MAX9273 = 0x0B).
(read only)
000
D[7:5] — 000 Reserved.
(read only)
0x1F 0 Not HDCP capable. 0
D4 CAPS
1 HDCP capable. (read only)
D[3:0] REVISION XXXX Device revision. (read only)
Maxim Integrated 47

MAX9273
STP Cable Drive
Typical Application Circuit
PCLKIN PCLK
PCLK PCLKIN
DOUT0–DOUT21 RGBHV
RGBHV DIN0–DIN21
CONF1
CONF0
CX/TP
DISPLAY
GPU
MAX9273 MAX9272
ECU
TX RX/SDA
UART
RX TX/SCL TO PERIPHERALS
OUT+ IN+ GPI
OUT- IN- RX/SDA/EDC

INT GPO
MS MS TX/SCL/ES
LOCK
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
VIDEO-DISPLAY APPLICATION
Ordering Information Package Information

For the latest package outline information and land patterns (foot-
PART TEMP RANGE PIN-PACKAGE
prints), go to www.maximintegrated.com/packages. Note that a
MAX9273GTL+ -40NC to +105NC 40 TQFN-EP* “+”, “#”, or “-” in the package code indicates RoHS status only.
MAX9273GTL/V+** -40NC to +105NC 40 TQFN-EP* Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package. PACKAGE PACKAGE OUTLINE LAND
*EP = Exposed pad. TYPE CODE NO. PATTERN NO.
**Future product—contact factory for availability.
40 TQFN-EP T4066+3 21-0141 90-0054
Chip Information
PROCESS: CMOS
Maxim Integrated 48

MAX9273
STP Cable Drive
Revision History
REVISION REVISION PAGES

DESCRIPTION
NUMBER DATE CHANGED
0 6/12 Initial release —
1 11/12 Added nonautomotive package to Ordering Information. 48
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 49
© 2012 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.

MAX9273 22-Bit GMSL Serializer With Coax or STP Cable Drive: General Description Benefits and Features

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

MAX9273 22-Bit GMSL Serializer With Coax or STP Cable Drive: General Description Benefits and Features

Uploaded by

Copyright:

Available Formats

EVALUATION KIT AVAILABLE

Maxim Integrated 4

Maxim Integrated 5

Package Thermal Characteristics (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Maxim Integrated 6

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Maxim Integrated 7

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Maxim Integrated 8

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Maxim Integrated 9

OUTPUT POWER SPECTRUM (dBm)

SUPPLY CURRENT (mA)

-20 0.5% SPREAD

MAXIMUM PCLKIN FREQUENCY MAXIMUM PCLKIN FREQUENCY MAXIMUM PCLKIN FREQUENCY

OPTIMUM PE/EQ 10m STP CABLE OPTIMUM PE/EQ

PCLKIN FREQUENCY (MHz)

PCLKIN FREQUENCY (MHz)

6dB PE, EQ OFF 6dB PE, EQ OFF

Maxim Integrated 10

Maxim Integrated 11

Maxim Integrated 12

Maxim Integrated 13

DVOS = |VOS(+) - VOS(-)|

VOD(-) DVOD = |VOD(+) - VOD(-)| VOD(-)

Figure 1. Serial-Output Parameters

Figure 2. Output Waveforms at OUT+, OUT-

NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.

Figure 4. Worst-Case Pattern Input

Maxim Integrated 14

Figure 5. Parallel Clock Input Requirements

START BIT 7 STOP

tSU;STA tLOW tHIGH

tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO

Figure 6. I2C Timing Parameters

Figure 7. Differential Output Template

Maxim Integrated 15

VIH MIN VIH MIN

NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.

Figure 8. Input Setup and Hold Times

Figure 9. GPI-to-GPO Delay

Maxim Integrated 16

EXPANDED TIME SCALE

Figure 10. Serializer Delay

SERIAL LINK INACTIVE SERIAL LINK ACTIVE

REVERSE CONTROL CHANNEL CHANNEL REVERSE CONTROL CHANNEL

PWDN MUST BE HIGH

Figure 11. Link Startup Time

Maxim Integrated 17

REVERSE CONTROL REVERSE CONTROL REVERSE CONTROL REVERSE CONTROL

Figure 12. Power-Up Delay

Detailed Description Register Mapping

Maxim Integrated 18

Maxim Integrated 19

ERRGRATE = 00, generate an error every 2560 bits

Maxim Integrated 20

Table 2. Input Map

Maxim Integrated 21

DIN0–DIN21 FIRST WORD SECOND WORD THIRD WORD FOURTH WORD

LATCH A FIRST WORD SECOND WORD THIRD WORD FOURTH WORD

Figure 13. Single-Input Waveform (Latch on Rising Edge of PCLKIN Selected)