MAX9273 22-Bit GMSL Serializer With Coax or STP Cable Drive: General Description Benefits and Features
MAX9273 22-Bit GMSL Serializer With Coax or STP Cable Drive: General Description Benefits and Features
MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
General Description Benefits and Features
The MAX9273 compact serializer is designed to drive S Ideal for Camera Applications
50I coax or 100I shielded twisted-pair (STP) cable. Drives Low-Cost 50I Coax Cable and FAKRA
The device pairs with the MAX9272 deserializer. The Connectors or 100I STP
parallel input is programmable for single or double input. Error Detection/Correction
Double input allows higher pixel clock input frequency by 9.6kbps to 1Mbps Control Channel in I2C-to-I2C
registering two pixels of typical image-sensor video data Mode with Clock Stretch Capability
before serializing. This doubles the maximum pixel clock Best-in-Class Supply Current: 75mA (max)
frequency compared to single input. Double-Rate Clock for Megapixel Cameras
The device features an embedded control channel that Serializer Pre/Deemphasis Allows 15m Cable at
Full Speed
operates at 9.6kbps to 1Mbps in UART and mixed UART/
40-Pin (6mm x 6mm) TQFN Package with 0.5mm
I2C modes, and up to 400kbps in I2C mode. Using the
Lead Pitch
control channel, a microcontroller (FC) is capable of
programming serializer, deserializer, and camera (or any S High-Speed Data Serialization for Megapixel
peripheral) registers at any time, independent of video Cameras
timing. There is one dedicated GPIO, four optional GPIOs, Up to 1.5Gbps Serial-Bit Rate with Single or
and a GPO output, allowing remote power-up of a camera Double Input: 6.25MHz to 100MHz Clock
module, camera frame synchronization, and other uses. S Multiple Control-Channel Modes for System
Error-detection and correction coding are programmable. Flexibility
For driving longer cables, the serializer has program- 9.6kbps to 1Mbps Control Channel in UART-to-
mable pre/deemphasis. Programmable spread spectrum UART or UART-to-I2C Modes
is available on the serial output. The serial output meets S Reduces EMI and Shielding Requirements
ISO 10605 and IEC 61000-4-2 ESD standards. The core
supply range is 1.7V to 1.9V and the I/O supply range is Output Programmable for 100mV to 500mV
Single-Ended or 100mV to 400mV Differential
1.7V to 3.6V. The device is available in a 40-pin (6mm x
Programmable Spread Spectrum on the Serial
6mm) TQFN-EP package with 0.5mm lead pitch and oper-
Output Reduces EMI
ates over the -40NC to +105NC temperature range.
Bypassable Input PLL for Parallel Clock Jitter
Attenuation
Applications Tracks Spread Spectrum on Parallel Input
Automotive Camera Systems S Peripheral Features for Camera Power-Up and
Verification
Navigation Displays
Built-In PRBS Generator for BER Testing of the
Serial Link
Up to Five GPIO Ports
Dedicated “Up/Down” GPO for Camera Frame
Sync Trigger and Other Uses
S Reduces Power Requirements
Remote/Local Wake-Up from Sleep Mode
Ordering Information appears at end of data sheet.
S Meets Rigorous Automotive and Industrial
Typical Application Circuit appears at end of data sheet. Requirements
-40NC to +105NC Operating Temperature
For related parts and recommended products to use with this part, ±8kV Contact and ±15kV Air ISO 10605 and
refer to www.maximintegrated.com/MAX9273.related. IEC 61000-4-2 ESD Protection
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-6384; Rev 1; 11/12
MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Link Signaling and Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reverse Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data-Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interfacing Command-Byte-Only I2C Devices with UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Format for Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C Communication with Remote-Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Control-Channel Broadcast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pre/Deemphasis Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Manual Programming of the Spread-Spectrum Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Additional Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Maxim Integrated 2
MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
TABLE OF CONTENTS (continued)
Hamming Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
HS/VS Encoding and/or Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Coax-Mode Splitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Configuration Inputs (CONF1, CONF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Link Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PRBS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Error Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Dual µC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Jitter-Filtering PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PCLKIN Spread Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Changing the Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Fast Detection of Loss-of-Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Providing a Frame Sync (Camera Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Software Programming of the Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Three-Level Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Compatibility with Other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Choosing I2C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Selection of AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power-Supply Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Maxim Integrated 3
MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
LIST OF FIGURES
Figure 1. Serial-Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. Output Waveforms at OUT+, OUT- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. Single-Ended Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Worst-Case Pattern Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Parallel Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. I2C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Differential Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Input Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Serializer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Link Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Single-Input Waveform (Latch on Rising Edge of PCLKIN Selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Single-Input Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Double-Input Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Double-Input Waveform (Latch on Rising Edge of PCLKIN Selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Serial-Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18. GMSL UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. GMSL UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. SYNC Byte (0x79) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. ACK Byte (0xC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 22. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0) . . . . . . . . . 26
Figure 23. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1) . . . . . . . . . 27
Figure 24. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 25. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 26. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 27. Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 28. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 29. Format for Write to Multiple Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 30. Format for I2C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 31. 2:1 Coax-Mode Splitter Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 32. Coax-Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 33. State Diagram, All Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 34. Human Body Model ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 36. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC Electrical Characteristics
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL= 100I ±1% (differential), EP connected to PCB ground (GND),
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.)
0.35 x
Low-Level Input Voltage VIL1 V
VIOVDD
Input Current IIN1 VIN = 0V to VIOVDD -10 +20 FA
three-level logic inputs (CONF0, CONF1)
0.7 x
High-Level Input Voltage VIH V
VIOVDD
0.3 x
Low-Level Input Voltage VIL V
VIOVDD
Midlevel Input Current IINM (Note 2) -10 +10 FA
Input Current IIN -150 +150 FA
SINGLE-ENDED OUTPUT (GPO)
VIOVDD
High-Level Output Voltage VOH1 IOUT = -2mA V
- 0.2
Low-Level Output Voltage VOL1 IOUT = 2mA 0.2 V
VIOVDD = 3.0V to 3.6V 16 35 64
Output Short-Circuit Current IOS VO = 0V mA
VIOVDD = 1.7V to 1.9V 3 12 21
0.3 x
Low- Level Input Voltage VIL2 V
VIOVDD
RX/SDA, TX/SCL -110 +1
Input Current IIN2 (Note 3) FA
GPIO_ -80 +1
VIOVDD = 1.7V to 1.9V 0.4
Low-Level Output Voltage VOL2 IOUT = 3mA V
VIOVDD = 3.0V to 3.6V 0.3
Differential serial OutputS (OUT+, OUT-)
Preemphasis off (Figure 1) 300 400 500
Differential Output Voltage VOD 3.3dB preemphasis setting (Figure 2) 350 610 mV
3.3dB deemphasis setting (Figure 2) 240 425
Change in VOD Between
DVOD 25 mV
Complementary Output States
Output Offset Voltage
VOS Preemphasis off 1.1 1.4 1.56 V
(VOUT+ + VOUT-)/2 = VOS
Change in VOS Between
DVOS 25 mV
Complementary Output States
VOUT+ or VOUT- = 0V -62
Output Short-Circuit Current IOS mA
VOUT+ or VOUT- = 1.9V 25
Magnitude of Differential Output
IOSD VOD = 0V 25 mA
Short-Circuit Current
Output Termination Resistance
RO From VOUT+, VOUT- to VAVDD 45 54 63 I
(Internal)
SINGLE-ENDED SERIAL OUTPUTS (OUT+, OUT-)
Preemphasis off, high drive (Figure 3) 375 500 625
3.3dB preemphasis setting, high drive
435 765
Single-Ended Output Voltage VOD (Figure 2) mV
3.3dB deemphasis setting, high drive
300 535
(Figure 2)
VOUT+ or VOUT- = 0V -69
Output Short-Circuit Current IOS mA
VOUT+ or VOUT- = 1.9V 32
Output Termination Resistance
RO From VOUT+ or VOUT- to VAVDD 45 54 63 I
(Internal)
AC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground (GND),
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC)
Note 2: To provide a midlevel, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than Q10µA.
Note 3: IIN min due to voltage drop across the internal pullup resistor.
Note 4: Specified pin to ground.
Note 5: Specified pin to all supply/ground.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured in serial link bit times. Bit time = 1/(30 x fPCLKIN) for BWS = 0. Bit time = 1/(40 x fPCLKIN) for BWS = 1.
MAX9273 toc03
MAX9273 toc01
MAX9273 toc02
PRBS ON, PRBS ON, fPCLKIN = 20MHz
COAX MODE PREEMPHASIS = COAX MODE -10
65 65
60 60 0% 0.5%
-30 SPREAD SPREAD
55 55 -40
50 50 -50
-60
45 45
PREEMPHASIS = 1%
PREEMPHASIS = -70
0x01 TO 0x04 SPREAD
40 0x01 TO 0x04 40
-80 4% SPREAD
PREEMPHASIS = 0x00 PREEMPHASIS = 0x00 2% SPREAD
35 35 -90
5 10 15 20 25 30 35 40 45 50 5 10 15 20 25 30 35 40 18.5 19.0 19.5 20.0 20.5 21.0 21.5
PCLKIN FREQUENCY (MHz) PCLKIN FREQUENCY (MHz) PCLKIN FREQUENCY (MHz)
SERIAL LINK SWITCHING PATTERN SERIAL LINK SWITCHING PATTERN
OUTPUT POWER SPECTRUM vs. PCLKIN WITH 6dB PREEMPHASIS (PARALLEL BIT WITH 6dB PREEMPHASIS (PARALLEL BIT
FREQUENCY (VARIOUS SPREAD) RATE = 50MHz, 10m STP CABLE) RATE = 50MHz, 20m COAX CABLE)
MAX9273 toc05 MAX9273 toc06
0
MAX9273 toc04
fPCLKIN = 50MHz
-10
0% SPREAD
OUTPUT POWER SPECTRUM (dBm)
-30
-40
-50
-60
-70 1%
-80 SPREAD
4% SPREAD
-90 2% SPREAD
-100
47 48 49 50 51 52 53 50mV/div 200ps/div 1.5Gbps 50mV/div 200ps/div 1.5Gbps
PCLKIN FREQUENCY (MHz)
MAX9273 toc08
MAX9273 toc09
TOP VIEW
RX/SDA
TX/SCL
AUTOS
CONF1
CONF0
PWDN
AVDD
OUT+
OUT-
DRS
30 29 28 27 26 25 24 23 22 21
PCLKIN 31 20 MS
DIN0 32 19 GPIO1
DIN1 33 18 GPO
DIN2 34 17 DIN21
DVDD 35 16 DIN20
MAX9273
DIN3 36 15 IOVDD
DIN4 37 14 DIN19/VS
DIN5 38 13 DIN18/VS
IOVDD 39 EP* 12 DIN17/GPIO5
+
DIN6 40 11 DIN16/GPIO4
1 2 3 4 5 6 7 8 9 10
DIN7
DIN8
DIN9
AVDD
DIN10
DIN11
DIN12
DIN13
DIN14/GPIO2
DIN15/GPIO3
TQFN
(6mm x 6mm x 0.75mm)
CONNECT EP TO GROUND PLANE
Pin Description
PIN NAME FUNCTION
1, 2, 3, 5–8,
16, 17, 32, DIN0–DIN13,
Parallel Data Inputs with Internal Pulldown to EP
33, 34, 36, DIN20, DIN21
37, 38
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1FF and 0.001FF capacitors as close
4, 27 AVDD
as possible to the device with the smaller capacitor closest to AVDD.
Parallel Data Inputs/GPIO. Defaults to parallel data input on power-up.
DIN14/
Parallel data input has internal pulldown to EP.
9–12 GPIO2–DIN17/
GPIO_ has an open-drain output with internal 60kI pullup to IOVDD. See register table
GPIO5
for programming details.
Parallel Data Input/Horizontal Sync with Internal Pulldown to EP. Defaults to parallel data input
13 DIN18/HS on power-up.
Horizontal sync input when VS/HS encoding is enabled (Table 2).
Parallel Data Input/Vertical Sync with Internal Pulldown to EP. Defaults to parallel data input on
14 DIN19/VS power-up.
Vertical sync input when VS/HS encoding is enabled (Table 2).
UART Transmit or I2C Serial-Clock Input/Output with Internal 30kI Pullup to IOVDD. In UART
mode, TX/SCL is the Tx output of the serializer’s UART. In the I2C mode, TX/SCL is the SCL
29 TX/SCL
input/output of the serializer’s I2C master/slave. TX/SCL has an open-drain driver and requires
a pullup resistor.
Autostart Input with Internal Pulldown to EP. AUTOS = low enables serialization upon power-
30 AUTOS up and automatic frequency range selection of PCLKIN. AUTOS = high puts the part in sleep
mode upon power-up.
Parallel Clock Input with Internal Pulldown to EP. Latches parallel data inputs and provides
31 PCLKIN
the PLL reference clock.
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1FF and 0.001FF capacitors as close
35 DVDD
as possible to the device with the smaller value capacitor closest to DVDD.
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB
— EP
ground plane through an array of vias for proper thermal and electrical performance.
SSPLL
PCLKIN FILTER
PLL MAX9273
CLKDIV
DIN0–DIN13
DIN14/GPIO2 OUT+
PARALLEL
DIN15/GPIO3 TO SERIAL OUT-
DIN16/GPIO4 CML TX
DIN17/GPIO5 SCRAMBLE/
SINGLE-/
CRC/
DOUBLE-
FIFO HAMMING/ RX
INPUT
8b/10b
GPO LATCH
ENCODE
REVERSE
GPIO1
CONTROL
CHANNEL
FCC
GPIO
DIN18/HS
DIN19/VS
UART/I2C
DIN20, DIN21
TX/SCL RX/SDA
VOD
VOS
OUT-
RL/2
GND
((OUT+) + (OUT-))/2
OUT-
VOS(-) VOS(+) VOS(-)
OUT+
VOD(+)
VOD = 0V
(OUT+) - (OUT-)
OUT+
OUT+ VO/2 VO VO/2 VO
VOD(P) VOD(D) OR
VOS
OUT-
OUT-
Figure 3. Single-Ended Output Template
SERIAL-BIT
TIME
PCLKIN
DIN_
VIH MIN
PCLKIN tHIGH
VIL MAX
tF tR tLOW
SCL
tBUF tSP
tr tf
SDA
800mVP-P
t TSOJ1 t TSOJ1
2 2
VIH MIN
PCLKIN
VIL MAX
tSET tHOLD
VIH_MIN
DESERIALIZER
GPI
VIL_MAX
tGPIO tGPIO
VOH_MIN
SERIALIZER
GPO
VOL_MAX
DIN_
N N+1 N+2 N+3 N+4
PCLKIN
N-1 N
OUT+/-
tSD
FIRST BIT LAST BIT
PCLKIN
tLOCK
350Fs
VIH1
PWDN
tPU
POWERED UP,
POWERED DOWN SERIAL LINK INACTIVE POWERED UP, SERIAL LINK ACTIVE
350µs
RESERVED = 00
GPIO5IN = 1, GPIO5 is input high
GPIO4IN = 1, GPIO4 is input high
0x10 0x3E GPIO3IN = 1, GPIO3 is input high
GPIO2IN = 1, GPIO2 is input high
GPIO1IN = 1, GPIO1 is input high
GPO_L = 0, GPO set low
PCLKIN
MAX9273
DIN0–DIN14
INPUT
DIN0–DIN21 OR
LATCH B
DIN0–DIN10 INPUT
LATCH B
INPUT
LATCH A
MAX9273
÷2
PCLKIN
PCLKIN
Figure 14. Single-Input Function Block Figure 15. Double-Input Function Block
PCLKIN
÷2
DIN0–DIN14
OR FIRST WORD SECOND WORD THIRD WORD FOURTH WORD
DIN0–DIN10
Serial Link Signaling and Data Format Control Channel and Register Programming
The serializer uses differential CML signaling to drive The control channel is available for the FC to send and
twisted-pair cable and single-ended CML to drive coaxial receive control data over the serial link simultaneously
cable. The output amplitude is programmable. with the high-speed data. The FC controls the link from
Input data is scrambled and then 8b/10b coded. The either the serializer or deserializer side. The control chan-
deserializer recovers the embedded serial clock, then nel between the FC and serializer or deserializer runs in
samples, decodes, and descrambles the data. In 24-bit base mode or bypass mode, according to the mode-
or 32-bit mode, 22 or 30 bits contain the video data selection (MS) input of the device connected to the FC.
and/or error correction bits, if used. The 23rd or 31st bit Base mode is a half-duplex control channel and bypass
carries the forward control-channel data. The last bit is mode is a full-duplex control channel.
the parity bit of the previous 23 or 31 bits (Figure 17).
UART Interface
Reverse Control Channel In base mode, the FC is the host and can access the
The serializer uses the reverse control channel to receive registers of both the serializer and deserializer from
I2C/UART and GPO signals from the deserializer in the either side of the link using the GMSL UART protocol.
opposite direction of the video stream. The reverse The FC can also program the peripherals on the remote
control channel and forward video data coexist on side by sending the UART packets to the serializer or
the same serial cable forming a bidirectional link. The deserializer, with the UART packets converted to I2C
reverse control channel operates independently from the by the device on the remote side of the link. The FC
forward control channel. The reverse control channel is communicates with a UART peripheral in base mode
available 2ms after power-up. The serializer temporarily (through INTTYPE register settings), using the half-duplex
disables the reverse control channel for 350Fs after start- default GMSL UART protocol of the serializer/deserial-
ing/stopping the forward serial link. izer. The device addresses of the serializer/deserializer in
base mode are programmable. The default value is 0x80
Data-Rate Selection
for the serializer and 0x90 for the deserializer.
The serializer/deserializer use DRS, DBL, and BWS to set
the PCLKIN frequency range (Table 3). Set DRS = 1 for When the peripheral interface is I2C, the serializer/
a PCLKIN frequency range of 6.25MHz to 12.5MHz (32- deserializer convert UART packets to I2C that have
bit, single-input mode) or 8.33MHz to 16.66MHz (24-bit, device addresses different from those of the serializer or
single-input mode). Set DRS = 0 for normal operation. deserializer. The converted I2C bit rate is the same as the
It is not recommended to use double-input mode when original UART bit rate.
DRS = 1.
Maxim Integrated 23
MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
24 BITS 32 BITS
FORWARD FORWARD
VIDEO AND ERROR- VIDEO AND ERROR-
CONTROL- CONTROL-
CORRECTION DATA CORRECTION DATA
CHANNEL BIT CHANNEL BIT
PACKET PACKET
PARITY PARITY
CHECK BIT CHECK BIT
NOTE: SERIAL DATA SHOWN BEFORE SCRAMBLING AND 8b/10b ENCODING
The deserializer uses differential line coding to send izer registers do not take effect until after the acknowl-
signals over the reverse channel to the serializer. The edge byte is sent. This allows the FC to verify that write
bit rate of the control channel is 9.6kbps to 1Mbps in commands are received without error, even if the result
both directions. The serializer/deserializer automatically of the write command directly affects the serial link. The
detect the control-channel bit rate in base mode. Packet slave uses the SYNC byte to synchronize with the host
bit-rate changes can be made in steps of up to 3.5 UART’s data rate. If the GPI or MS/HVEN inputs of the
times higher or lower than the previous bit rate. See the deserializer toggle while there is control-channel com-
Changing the Clock Frequency section for more informa- munication, or if a line fault occurs, the control-channel
tion on changing the control-channel bit rate. communication is corrupted. In the event of a missed
Figure 19 shows the UART data format. Figure 20 and or delayed acknowledge (~1ms due to control-channel
Figure 21 detail the formats of the SYNC byte (0x79) timeout), the FC should assume there was an error in the
and the ACK byte (0xC3). The FC and the connected packet when the slave device received it, or that an error
slave chip generate the SYNC byte and ACK byte, occurred during the response from the slave device. In
respectively. Events such as device wake-up and GPI base mode, the FC must keep the UART Tx/Rx lines high
generate transitions on the control channel that can be for 16 bit times before starting to send a new packet.
ignored by the FC. Data written to the serializer/deserial-
SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N
1 UART FRAME
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
START 1 0 0 1 1 1 1 0 PARITY STOP START 1 1 0 0 0 0 1 1 PARITY STOP
Figure 20. SYNC Byte (0x79) Figure 21. ACK Byte (0xC3)
SERIALIZER/DESERIALIZER PERIPHERAL
1 7 1 1 8 1 8 1 8 1 1
S DEV ID W A REG ADDR A DATA 0 A DATA N A P
SERIALIZER/DESERIALIZER PERIPHERAL
1 7 1 1 8 1 1 7 1 1 8 1 8 1 1
S DEV ID W A REG ADDR A S DEV ID R A DATA 0 A DATA N A P
Figure 22. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
SERIALIZER/DESERIALIZER PERIPHERAL
1 7 1 1 8 1 8 1 1
S DEV ID W A DATA 0 A DATA N A P
SERIALIZER/DESERIALIZER PERIPHERAL
1 7 1 1 8 1 8 1 1
S DEV ID R A DATA 0 A DATA N A P
Figure 23. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1)
SDA
SCL
S P
START STOP
CONDITION CONDITION
SDA
SCL
1 2 8 9
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
0 = WRITE
ADDRESS = 0x80 REGISTER ADDRESS = 0x00 REGISTER 0x00 WRITE DATA
S 1 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 A D7 D6 D5 D4 D3 D2 D1 D0 A P
S = START BIT
P = STOP BIT
A = ACK
D_ = DATA BIT
0 = WRITE
ADDRESS = 0x80 REGISTER ADDRESS = 0x00
S 1 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 A
S = START BIT
P = STOP BIT
REGISTER 0x00 WRITE DATA REGISTER 0x01 WRITE DATA A = ACK
N = NACK
D_ = DATA BIT
D7 D6 D5 D4 D3 D2 D1 D0 A D7 D6 D5 D4 D3 D2 D1 D0 N P
0 = WRITE
ADDRESS = 0x80 REGISTER ADDRESS = 0x00
S 1 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 0 A
S = START BIT
1 = READ P = STOP BIT
ADDRESS = 0x81 REGISTER 0x00 READ DATA A = ACK
REPEATED START N = NACK
D_ = DATA BIT
S 1 0 0 0 0 0 0 1 A D7 D6 D5 D4 D3 D2 D1 D0 N P
cancels benefits. The deserializer tracks the serializer’s Manual Programming of the
spread and passes the spread to the deserializer output. Spread-Spectrum Divider
The programmable spread-spectrum amplitudes are The modulation rate relates to the PCLKIN frequency as
Q0.5%, Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 6). follows:
Some spread-spectrum amplitudes can only be used at
fPCLKIN
lower PCLKIN frequencies (Table 7). There is no PCLKIN fM= (1 + DRS)
frequency limit for the Q0.5% spread rate. MOD x SDIV
When the spread spectrum is turned on or off, the serial where:
link stops for several microseconds and then restarts in fM = Modulation frequency
order for the deserializer to lose and relock to the new DRS = DRS value (0 or 1)
serial-data stream. fPCLKIN = PCLKIN frequency
The serializer includes a sawtooth divider to control the MOD = Modulation coefficient given in Table 8
spread-modulation rate. Autodetection of the PCLKIN
SDIV = 6-bit SDIV setting, manually programmed by the FC
operation range guarantees a spread-spectrum modu-
lation frequency within 20kHz to 40kHz. Additionally, To program the SDIV setting, first look up the modula-
manual configuration of the sawtooth divider (SDIV: 0x03, tion coefficient according to the desired bus-width and
D[5:0]) allows the user to set a modulation frequency spread-spectrum settings. Solve the above equation for
according to the PCLKIN frequency. When ranges are SDIV using the desired pixel clock and modulation fre-
manually selected, program the SDIV value for a fixed quencies. If the calculated SDIV value is larger than the
modulation frequency around 20kHz. maximum allowed SDIV value in Table 8, set SDIV to the
maximum value.
MAX9273 GMSL
DESERIALIZER
MAX9273 GMSL
DESERIALIZER
OUT+ IN+
OUT- IN-
AVDD
GMSL
DESERIALIZER
50I
IN+
IN-
Figure 31. 2:1 Coax-Mode Splitter Connection Diagram Figure 32. Coax-Mode Connection Diagram
CLINKEN = 0 OR
SEREN = 1
CLINKEN = 0 OR
SLEEP = 1 SEREN = 1 CONFIG LINK CONFIG LINK
FOR > 8ms SLEEP = 0, POWER-ON CONFIG UNLOCKED OPERATING
SLEEP WAKE-UP
SEREN = 0 IDLE CLINKEN = 1 LINK STARTED CONFIG LINK PROGRAM
LOCKED REGISTERS
WAKE-UP SIGNAL
SEREN = 1,
SEREN = 0 OR
SLEEP = 0, PCLKIN RUNNING
SLEEP = 1 NO PCLKIN
SEREN = 1
SEREN = 0 OR
NO PCLKIN
PWDN = HIGH, PRBSEN = 0
PWDN = LOW OR POWER-DOWN VIDEO LINK
POWER-ON VIDEO VIDEO LINK VIDEO LINK
ALL STATES OR
POWER-OFF AUTOS = LOW LINK LOCKING LOCKED OPERATING PRBSEN = 1 PRBS TEST
POWER-OFF
VIDEO LINK
PWDN = HIGH, UNLOCKED
POWER-ON
AUTOS = HIGH
RD RD
330I 2kI
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit Figure 36. ISO 10605 Contact Discharge ESD Test Circuit
PCLKIN PCLK
PCLK PCLKIN
DOUT0–DOUT21 RGBHV
RGBHV DIN0–DIN21
CONF1
CONF0
CX/TP
DISPLAY
GPU
MAX9273 MAX9272
ECU
TX RX/SDA
UART
RX TX/SCL TO PERIPHERALS
OUT+ IN+ GPI
LOCK
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
VIDEO-DISPLAY APPLICATION
Chip Information
PROCESS: CMOS
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 49
© 2012 Maxim Integrated The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.