A Novel Application Data Coordinator for Mobile Computing Systems

Wenping Zhu *, Leibo Liu, Shouyi Yin, Eugene. Y. Tang, Jiqiang Song, Qian Huang, Shaojun Wei
Research Center for Mobile Computing, Tsinghua University
Institute of Microelectronics, Tsinghua University
Tsinghua National Laboratory for Information Science and Technology, Beijing 100084, China
* Email: zhuwp08@mails.tsinghua.edu.cn

Abstract: Recent developments and technological transfer methods to reduce the wireless transmission
advances in information and communication bandwidth.
technologies are leading to an increasing availability and There has been a large body of work related to
functionality of portable devices, with improved QoS application service delivery in mobile computing
(Quality of Service) of wireless connections together environments. Conventionally, application data transfer
with decreasing costs. As a consequence, the power is entirely carried out by software. Due to the large
consumption of the portable device and the required amount of CPU computations and memory access
transmission bandwidth are rapidly increasing. This operations, this approach turns out to be unrealistic for
paper proposes a novel architecture named FAST (Fast mobile devices, because of the unacceptable power
Application Service Transfer) coordinator, which aims at consumption. Although DMA (Direct Memory Access)
extending the battery lifetime of portable devices and can be used in some cases to accelerate data transfer, but
adaptively regulating the network bandwidth of wireless almost all the processes above the IP (Internet Protocol)
communications in mobile computing environments. As layer require the involvement of CPU. A significant
a coprocessor capable of application-aware transfer amount of research has sought to improve transport-layer
acceleration with little involvement of the CPU, the performance over wireless data networks [2-6], but most
architecture provides a direct and fast interface between of these works involve the CPU in the data transfer as
the application software and the communication network. well, which makes the power consumption unacceptable.
This coordinator has been implemented on an Furthermore, the improved transport layer protocols are
FPGA-based prototype platform. Emulation showed that typically application-unaware, which results in
the CPU usage was reduced nearly 90% in the target unrealistic dynamic partitioning of computing-intensive
client system (Atom Z500 processor @800 MHz) by tasks and the adaptive bandwidth modulation. There are
partitioning most of the computing-intensive tasks into also some hardware implementations [7-9] of the TCP
the proposed coordinator. Moreover, the transmission /IP (Transmission Control Protocol/Internet Protocol)
data rate was reduced from 9.8Mbps to 2.4Mbps. With stacks, which have incorporated the Ethernet card onto
these improvements, the FAST coordinator can be chips but they only implement the protocol stacks
widely used in a range of applications, including between the transport layer and the physical layer,
multimedia service delivery, web browsing, and without directly answering requests from the application
collaborative computing. software or processing data.
Keyword: application data; FAST coordinator; mobile This paper presents an FAST coordinator which works
computing; transfer acceleration as a generic architecture to enable mobile clients to fit
1. Introduction well into wireless communication world. Being
Recent advances in wireless communications, computer application-aware, the FAST coordinator takes care of all
technologies and portable information appliances have application data transmission tasks in the transport layer
engendered a new paradigm of computing, called mobile of the OSI (Open System Interconnection) model, with
computing [1], in which users carrying portable devices little involvement of the CPU. Some data transformation
have access to data and information services regardless can also be performed by the coordinator, which is more
of their physical location or movement behavior. As the efficient and faster than the CPU. According to the data
functionality and capability of battery-operated portable type and timing requirement, the FAST coordinator can
devices increase, their power consumption requirements rearrange the sending sequence to prioritize several
increase as well. Undoubtedly, maximizing battery application tasks, and delay the actual sending time to
lifetime is desirable for the users’ convenience. However, the network interface whenever possible to form a burst
the small form factor of portable devices limits battery of data. Also, since the intermediate data in each stage is
size and capacity. Meanwhile, emerging rich-media preserved in the coordinator, the power consumption is
application services on mobile devices featuring large further reduced by less memory access operations. The
amount of data transfer demand high network bandwidth. coordinator has been implemented on a FPGA-based
This seriously congests wireless access network, and (Xilinx Virtex-5 XC5VLX220T) mobile computing
therefore motivates the seeking of innovative data prototype. Emulation on a MID (Mobile Internet Device)

978-1-4244-5798-4/10/$26.00 ©2010 IEEE

showed that the CPU usage was reduced to 12% in the multimedia services still require the use of RTP over
client (Atom Z500 @ 800 MHz), while the client failed UDP/IP to provide acceptable QoS. Data packer applies
to process the same media data without FAST the RTP to protect the compressed data, packets the data
coordinator even though its processor was fully occupied. under the UDP/IP protocol, and then transfers the data to
Moreover, the transmission data rate was reduced from the network interface.
9.8Mbps to 2.4Mbps. 2.4. Storage components
2. FAST architecture The data buffer stories intermediate data or control
This section describes the architecture of the FAST information between adjacent functional components in
coordinator. Figure 1 shows the major components of the the FAST coordinator. The storage is implemented as a
FAST coordinator, which can be divided into the task SRAM. The task list is the storage module of all the
manager, interface controllers, functional components FAST-related commands sent out by the CPU. This
and storage components. module is a memory block with a number of fixed-size
entries, which is implemented as a register file.
N 3. Emulation environment
Data Data Data Data Data
slicer buffer com buffer packer
E Hardware of the mobile client prototype (shown in
B T
U W
Figure 2) has been developed, which consists of two
S Task O main parts: a Menlow Board (MB) and a FPGA board.
Task management module
list R MB, incorporating Atom processor Z5XX series and
I K Intel System Controller Hub US15W on board, is a
F Data
Data Data Data Data versatile platform developed for numerous embedded
Assem I
buffer decom buffer unpacker
-bler F applications including interactive client, medical and
Figure 1. FAST coordinator architecture industrial control. The FPGA board is regarded as a
peripheral device in the system where the FAST
2.1 Task manager coordinator resides in. The coordinator is responsible for
The task manager, which consists of the task receiving data from Wi-Fi module and finally writing the
management module and the task list, is responsible for result into SDRAM, which acts as storage memory for
scanning the command section in the shared memory and FAST. MB uses PCIe as its system bus, therefore the
managing the task list in the coordinator. The task FPGA board exchanges data with MB via a PCIe/AHB
management module maintains the task list and controls bridge, which has also been implemented in the FPGA.
data flow in the FAST coordinator. The task list stores all The FAST coordinator was realized in Verilog HDL and
the FAST-related commands sent out by the CPU. successfully synthesized using ISE on a Xilinx Virtex-5
2.2 Interface controllers FPGA. The implementation result is shown in Table 1.
A local interface is employed to provide support for the
system bus protocol as the communication channel
between the FAST coordinator and other system
components.
The network interface controller is the interface used
by the FAST coordinator to communicate with other
mobile clients or servers in the network environment.
2.3 Functional components
The functional components are the key part that releases Figure 2. Hardware of mobile client prototype
the CPU from frequent memory accesses and
computations. All the data processes are optional, Table 1. FAST Coordinator Implementation Result on
depending on the configuration information in the task FPGA
manager. Metric Result
As shown in Figure 1, the functional components FPGA Xilinx Virtex-5
consist of two channels, receiving channel and XC5VLX220T
transmitting channel respectively. Next, the process flow Synthesis software Xilinx ISE 9.2i
is illustrated by taking transmitting channel as an Total LUT number 94064
example. Firstly, the data slicer splits the block data Operating frequency 62.5 MHz
loaded from memory into slices appropriate for network
transmission, and stores the result into the data buffer for 4. Performance evaluation
further processing. Secondly, the data is compressed by This section presents an experiment to evaluate the
the data compressor to reduce the required network FAST coordinator’s performance on a MID. The
bandwidth if necessary. However a number of real-time performance of the FAST coordinator has been evaluated
by playing a video clip (2012.mp4) on the same platform application-aware coordinator, the battery life can be
(Atom Z500 processor @800 MHz) with and without the extended substantially. Furthermore, network bandwidth
involvement of FAST. As shown in figure 3, the average requirement is also alleviated by the bandwidth adaptive
CPU usage is 12% on the developed system. However, it modulation technique. This proposed solution can be
fails to play the same video on the MID without the widely used in portable devices to meet the requirements
involvement of FAST. of emerging application services, including video
conferencing, IPTV, multimedia service delivery etc.
100%
Based on the current prototype, some experiments will
90% be launched to verify the performance improvement
80%
70%
achieved by the proposed coordinator. Further research
60% Fail to work will be invested in optimization and improvement
50% play!
40%
on global performance by investigating research efforts
30% within the domain of low-power design.
20%
10%
0% References
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‹‰—”‡ͶǤƒ–ƒ”ƒ–‡…‘’ƒ”‹•‘
5. Conclusion
In this article, a novel architecture of the FAST
coordinator is proposed to enable mobile clients to fit
well in the mobile computing world. With this