Ee240 Lecture1
Ee240 Lecture1
Ee240 Lecture1
Spring 2011
Şenol Mutlu
a x
b
c ENTITY
d mux
s0
s1
The keyword ENTITY starts the entity statement. The name of the
entity is mux. Six ports are of mode of IN and one port is of mode
OUT. The four data input ports (a,b,c,d) are of type BIT. The two
multiplexer select inputs, s0 and s1 are also of type BIT. The output
port is of type BIT. END keyword ends the entity. A lot more
information can be put into an entity
Adapted from (D.L. Perry, VHDL Programming by Example). Copyright 2002 McGraw-Hill
Şenol Mutlu, EE240, Digital Design 3
Ports
PORT (in1,in2: IN BIT; out1,out2:OUT BIT);
Port Declaration constitutes the primary content of the Entity Declaration. Each port
represents either external pins of the device, or wires connecting two or more entities
within a complete device. Each port has Port names, Mode (direction), and Type
(kind of values possible).
IN: data flows only INTO this entity, driven by another entity used on right side of assignments.
(z <= a NAND inport_name)
OUT: data flows only OUT of this entity into other entities. It can not be read by its entity (no
internal feedback). It is used on left side of assignments. (outport_name <= x OR y)
BUFFER: data flows only OUT of the entity, into other entities. It can be read by its entity. It
can only have one driver. It can be used on both sides of assignments. (bufport <= z;
IF bufport=„1‟ THEN…)
INOUT: data can flow bidirectionally, either in or out or both. It can be read by its entity. It can
also be driven by external driver. It can be used on both sides of assignments.
Types useful for synthesis and simulation : bit, bit_vector, std_logic, std_logic_vector,
std_ulogic, std_ulogic_vector, boolean, integer
BODY
Concurrent Sequential
Identifiers
Identifiers are the names of things you
create:
signals, variables, constants
architecture names, entity names,
process names, component names
Rules:
Cannot be reserved words First character is letter
Uppercase and lowercase equivalent First and last character NOT underscore
Only letters, numbers, and underscore _ Two underscores in succession illegal
Adapted from (D.L. Perry, VHDL Programming by Example). Copyright 2002 McGraw-Hill
Şenol Mutlu, EE240, Digital Design 11
VHDL Predefined Types
Predefined integer type: Predefined physical type:
TYPE integer IS RANGE –2147483648 TO 2147483647; TYPE time IS RANGE -2**31-1 TO 2**31-1
UNITS
Predefined floating point type: fs; --femtosecond =10-15 sec
TYPE real IS RANGE -1.0E38 TO 1.0E38; ps = 1000 fs; --picosecond =10-12 sec
ns = 1000 ps; --nanosecond =10-9 sec
Predefined enumeration types: us = 1000 ns; --microsecond =10-6 sec
TYPE bit IS (`0','1'); ms = 1000 us; --millisecond =10-3 sec
TYPE boolean IS (false,true); sec =1000 ms; --second
TYPE severity_level IS (note,warning,error,failure); min =60 sec; --minute
TYPE character IS (`a','b','c',...); hr =60 min; --hour
END UNITS;
Predefined array types:
TYPE string IS ARRAY (positive RANGE <>) OF character;
TYPE bit_vector IS ARRAY (natural RANGE <>) OF bit;
STD and IEEE libraries have more defined operators and types.
STD_LOGIC ('U','X','0','1','Z','W','L','H','-') where:
'U' means uninitialized, 'X' means unknown , '0' means low , '1' means high, 'Z' means high impedance,
'W' means weak unknown, 'L' means weak low, 'H' means weak high, '-' means don't care
For XST synthesis, the '0' and 'L' values are treated identically, as are '1' and 'H'. The 'X', and '-' values are
treated as don't care. The 'U' and 'W' values are not accepted by XST. The 'Z' value is treated as high
impedance.
Şenol Mutlu, EE240, Digital Design 12
VHDL Operators
VHDL can use most of the
operators used in software
languages.
c1 c2
internal_line z_out
enable en clock_ ck clk z
component fsm_
x_in x component
y_in y
Şenol Mutlu, EE240, Digital Design 15
Packages
Used for grouping elements like components, subprograms, types so that they can be
shared globally by the design units that specify the usage of that package. It consists
of package declaration and package body. Items declared in the package declaration
section are visible to any design unit that uses the package with a USE clause.
Package declaration: The package declaration can
PACKAGE std_logic_1164 IS contain the following declarations:
TYPE std_ulogic IS ......; Subprogram declaration
FUNCTION resolved (....) RETURN std_logic Type, subtype declaration
... Constant, deferred constant
END std_logic_1164; declaration
Signal declaration creates a global
Package body: signal
PACKAGE BODY std_logic_1164 IS File declaration
TYPE stdlogic_1d IS ARRAY (std_logic) OF std_ulogic; Alias declaration
CONSTANT .....; Component declaration
FUNCTION resolved (...) RETURN std_logic IS Attribute declaration, a user-
function description defined attribute
END resolved; Attribute specification
... Disconnection specification
END std_logic_1164; Use clause
Data in
Register Register
Data out
Register
Combinational Transfer Level
logic
CLK CLK
(RTL)
Clock description
Şenol Mutlu, EE240, Digital Design Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill 21
Conditional Signal Assignment
Şenol Mutlu, EE240, Digital Design Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill 23
Syntax of Selected Signal Assignment
The WITH keyword
starts the construct. All
possibilities must be
included. OTHERS
eliminates the need to
individually write all
possibilities.
Şenol Mutlu, EE240, Digital Design Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill 24
3-to8 Decoder Example: Select Signal Assignment
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dcd_3_to_8 IS
PORT (adr : IN std_logic_vector (2 DOWNTO 0);
so : OUT std_logic_vector (7 DOWNTO 0));
END dcd_3_to_8;
--
ARCHITECTURE dataflow OF dcd_3_to_8 IS
BEGIN
WITH adr SELECT
so <= "00000001" AFTER 2 NS WHEN "000",
"00000010" AFTER 2 NS WHEN "00Z" | "001",
"00000100" AFTER 2 NS WHEN "0Z0" | "010",
"00001000" AFTER 2 NS WHEN "0ZZ" | "0Z1" | "01Z" | "011",
"00010000" AFTER 2 NS WHEN "100" | "Z00",
"00100000" AFTER 2 NS WHEN "Z0Z" | "Z01" | "10Z" | "101",
"01000000" AFTER 2 NS WHEN "ZZ0" | "Z10" | "1Z0" | "110",
"10000000" AFTER 2 NS WHEN "ZZZ" | "ZZ1" | "Z1Z" | "Z11" |
"1ZZ" | "1Z1" | "11Z" | "111",
"XXXXXXXX" WHEN OTHERS;
END dataflow;
Şenol Mutlu, EE240, Digital Design Adapted from (Navabi, VHDL). Copyright 1993 McGraw-Hill 25
Vector Operations
If signals are defined as follows:
ENTITY myadder16 IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;
Cout, Overflow : OUT STD_LOGIC ) ;
END myadder16 ;
entity mymultiply is
port(
a : in STD_LOGIC_VECTOR(15 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
mult : out STD_LOGIC_VECTOR(23 downto 0);
);
end mymultiply;
mult <= a * b;
end dataflow;