MODULE 5: BASIC PROCESSING UNIT

I ) FUNDAMENTAL CONCEPTS OF PROCESSOR

To execute a program the processor fetches one instruction at a time from the memory and performs the
operation specified in the instruction. instructions are fetched from successive memory locations until a
branch or jump instruction is encountered .

Processor uses program counter (PC) to store the address of the next instruction, to be fetched for the
execution, after fetching the instruction the contents of the PC is updated to point next instruction in the
sequence .whenever branch instruction is encountered processor will store different value into the PC.

To execute an instruction, processor has to perform following 3 steps:

1) Fetch contents of memory-location pointed to by PC. Content of this location is an instruction to be

executed. The instructions are loaded into IR, Symbolically, this operation is written as:

IR[[PC]]

2) Increment PC by 4.

PC [PC] +4

3) Carry out the actions specified by instruction (in the IR).

The first 2 steps are referred to as Fetch Phase. Step 3 is referred to as Execution Phase.

NOTE :

when a instruction occupies more than one word then step 1 and step 2 must be repeated as many
times as necessary to fetch the complete instruction.

To study these operations in detail we need to understand internal organization of the Processor.

Internal Organization of the processor or Single Bus Organization

Basic organization structure of the processor consist of single processor bus, we are using single
processor bus(internal bus) to interconnect internal components of the processor such as Control Unit,
Registers, Arithmetic Logic unit as shown in the below figure 5.1. we can also interconnect external
devices such as memory and I/O devices to the processor using external bus.

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 figure 5.1 Single bus Organization of the datapath inside a processor

Data & address lines of the external memory-bus is connected to the internal processor-bus via MDR &
MAR respectively. (MDR Memory Data Register, MAR Memory Address Register).

▪ MDR has 2 inputs and 2 outputs. Data may be loaded into MDR either from memory-bus
(external) or from processor-bus (internal).

▪ MARin input is connected to internal-bus; MARout output is connected to external bus.

▪ Instruction Decoder & Control Unit is responsible for issuing the control-signals to all the units
inside the processor and implementing the actions specified by the Instruction (loaded in the
IR).
▪ Register R0 through R(n-1) are the Processor Registers.

The programmer can access these registers for general-purpose use. Only processor can access these 3
registers Y, Z & Temp for temporary storage during program-execution,the programmer cannot access
these 3 registers.

▪ ALU takes two operand as input, one Operand A as input gets from the output of the
multiplexer (MUX) and another Operand B as input gets from the operand directly from the
processor-bus and performs the arithmetic and logical type of operation specified in a
instruction.

• There are 2 options provided for operand A as input of the ALU i.e, Multiplexer MUX selects one of
the 2 inputs either output of Register Y or constant-value 4( which is used to increment PC content).

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Whenever ALU executes a instruction it has to perform the one or more following operations in some
specified sequence.

1) Transfer a word of data from one register to another or to the ALU.

2) Perform arithmetic or a logic operation and store the result in a register.
3) Fetch the contents of a given memory-location and load them into a register.
4) Store a word of data from a register into a given memory-location.

Disadvantage of Single Bus Organization : Only one data item can be transferred over the bus in a
clock cycle, so needs many number of steps.

Solution: Provide multiple internal-paths. Multiple paths allow several data-transfers to take place in
Parallel within in one clock cycle.

1) REGISTER TRANSFERS
Whenever processor wants to execute a instruction it required a sequence of steps in which data
are transferred from one register to another.

▪ For each register, two control-signals are used: Riin & Riout. These are called Gating Signals.
▪ R1in=1 data on processor bus is loaded into R1 Register
▪ R1out=1 content of Register R1 is placed on processor bus.

For example, Move R1, R2;

This transfers the contents of register R1 to register R2. This can be accomplished as follows:

1) Enable the output of registers R1 by setting R1out to 1 This places the contents of R1 on
processor-bus.

2) Enable the input of register R2 by setting R2out to 1. This loads data from processor-bus into register
R4.

• All operations and data transfers within the processor take place within time-periods defined by
the processor-clock.

• The control-signals that govern a particular transfer are asserted at the start of the clock cycle.

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2) PERFORMING AN ARITHMETIC OR LOGIC OPERATION
▪ The ALU is a combinational circuit that has no internal storage.
▪ The ALU performs arithmetic operations on the 2 operands applied to its A and B inputs.
▪ One of the operands is output of MUX & the other operand is obtained directly from bus.
▪ The result (produced by the ALU) is stored temporarily in register Z.

The sequence of operations to add content of Register R1 and R2 and storing result in Register R3
[R3][R1]+[R2] is as follows.

1) R1out, Yin //transfer the contents of R1 to Y register

2) R2out, SelectY, Add, Zin //R2 contents are transferred directly to B input of ALU.
// The numbers of added. Sum stored in register Z
3) Zout, R3in //sum is transferred to register R3

• The signals are activated for the duration of the clock cycle corresponding to that step. All other
Signals are inactive.

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3) FETCHING A WORD FROM MEMORY
▪ To fetch instruction/data from memory, processor transfers required address to MAR (whose
output is connected to address-lines of memory-bus). at the same time, processor issues Read
signal on control-lines of memory-bus.
▪ When requested-data are received from memory, they are stored in MDR. From MDR, they are
transferred to other registers.
▪ MFC (Memory Function Completed): Addressed-device sets MFC to 1 to indicate that the
contents of the specified location have been read & are available on data-lines of memory-bus.

The connections for register MDR is illustrates in the following diagram

It consist of four control signals: MDRin and MDRout control the connection to the internal bus, and
MDRin E and MDRoutE control the connection to the external bus.

During memory Read and Write operations, the timing of internal processor operations must be
coordinated with response of the addressed device on the memory bus.

Example: consider a instruction Move (R1),R2 to perform READ operation

Processor needs following sequence of steps or action to execute Move (R1),R2 instruction

1) R1out, MARin, Read desired address is loaded into MAR & Read command is issued
2) MDRinE, WMFC load MDR from memory bus & Wait for MFC response from memory
3) MDRout, R2in load R2 from MDR

where WMFC=control signal that causes processor's control circuitry to wait for arrival of MFC signal

NOTE:
Each action or step can be completed in only one clock cycle, except step2 which requires one or
more clock cycles, depending on the speed of the addressed device.

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Timing diagram to perform memory read operation (Move (R1),R2 )

4) Storing a Word in Memory

To write a word into memory location, processor has to load desired memory location address into MAR
then the data to be written are loaded into MDR and a Write Control signal is activated.

Example: consider a instruction Move R2,(R1) to perform WRITE operation

To execute Move R2,(R1) this instruction processor needs following sequence of execution steps.

1) R1out, MARin //desired address is loaded into MAR

2) R2out, MDRin, Write //data to be written are loaded into MDR & Write command is issued
3) MDRoutE, WMFC //load data into memory location pointed by R1 from MDR

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II) EXECUTION OF A COMPLETE INSTRUCTION

Consider the instruction Add (R3),R1 which adds the contents of a memory-location pointed by R3
to register R1. Executing this instruction requires the following actions:

1) Fetch the instruction.

2) Fetch the first operand.
3) Perform the addition.
4) Load the result into R1.

Processor uses these are the sequence of control steps required to perform addition of two given
operands using single bus architecture.

Control sequence for execution of Add (R3),R1 instruction is as follows

1) PCout, MARin, Read, Select4, Add, Zin
2) Zout, PCin, Yin, WMFC
3) MDRout, IRin
4) R3out, MARin, Read
5) R1out, Yin, WMFC
6) MDRout, SelectY, Add, Zin
7) Zout, R1in, End.
Instruction execution proceeds as follows:
Step 1: The instruction-fetch operation is initiated by loading contents of PC into MAR & sending a
Read request to memory. The Select signal is set to Select4, which causes the Mux to select
constant 4. This value is added to operand at input B (PC‟s content), and the result is stored in Z

Step 2: Updated value in Z is moved to PC.

Step 3: Fetched instruction is moved into MDR and then to IR.

Step 4: Contents of R3 are loaded into MAR & a memory read signal is issued.

Step 5: Contents of R1 are transferred to Y to prepare for addition.

Step 6 : When Read operation is completed, memory-operand is available in MDR, and the addition is
performed.
Step 7: Sum is stored in Z, then transferred to R1.The End signal causes a new instruction
fetch cycle to begin by returning to step1.
NOTE: step no 1 to 3 represents fetch phase , it is common to all the instructions .
Step no 4 to 7 represents execution phase.

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III) BRANCHING INSTRUCTIONS
A branch instruction replaces the contents of the PC with the branch target address, this address is
usually obtained by adding an offset X, which is given in the branch instruction, to the updated value of
the PC.

Control sequence for an unconditional branch instruction is as follows:

1) PCout, MARin, Read, Select4, Add, Zin

2) Zout, PCin, Yin, WMFC
3) MDRout, IRin
4) Offset-field-of-IRout, Add, Zin
5) Zout, PCin, End
The processing starts, as usual, the fetch phase ends in step3. In step 4, the offset-value is extracted from
IR by instruction-decoding circuit. Since the updated value of PC is already available in register Y, the
offset X is gated onto the bus, and an addition operation is performed. In step 5, the result, which is the
branch-address, is loaded into the PC.

The offset X used in a branch instruction is usually the difference between the branch target - address and
the address immediately following the branch instruction. (For example, if the branch instruction is at
location 2000 and branch target-address is 2050, then the value of X must be 46, since the PC will be
containing the address 2004 after fetching the instruction at location 2050).

In case of conditional branch, we need to check the status of the condition-codes before loading a
new value into the PC.

Example : Offset-field-of-IRout, Add, Zin, If N=0 then End If N=0, processor returns to step 1
immediately after step 4. If N=1, step 5 is performed to load a new value into PC.

IV) MULTIPLE BUS ORGANIZATION

Multiple Bus Organization structure is used to reduce the number of execution steps needed to transfer
the data items over the single bus, in case of multiple bus organization structure processor can transfer
multiple data items in parallel over the bus.
The below figure depicts a three bus structure used to connect the registers and the ALU of a processor.

Register File: All the general purpose registers are combined into a single block called as a Register File.
It has 3 ports , Two output-ports allow the contents of 2 different registers to be simultaneously placed
on buses A & B, and Third input-port allows data on bus C to be loaded into a third register during the
same clock-cycle.
Buses A and B are used to transfer source-operands to A & B inputs of ALU and Result is transferred to
destination over bus C.

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Incrementer-unit is used to increment PC by 4.

Control sequence for the instruction Add R4,R5,R6 is as follows :

1) PCout, R=B, MARin, Read, IncPC
2) WMFC
3) MDRout, R=B, IRin
4) R4outA, R5outB, SelectA, Add, R6in, End.

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Instruction execution proceeds as follows:
Step 1: Contents of PC are passed through ALU using R=B control-signal and loaded into MAR to start
a memory Read operation. At the same time, PC is incremented by 4.

Step 2 : Processor waits for MFC signal from memory.

Step 3: Processor loads requested-data into MDR, and then transfers them to IR.
Step 4: The instruction is decoded and add operation take place in a single step.

NOTE: Step number 1 to 3 Represents Fetch Phase and Step number 4 represents Execution Phase ,in
Multiple Bus Organization Execution Phase needs only one control step to complete the
Execution of the instruction
Advantage of Multiple Bus Organization:

It provides multiple paths to transfer data over the bus hence it reduces number of instruction
Execution steps so ultimately processor reduces number of clock cycles needed to execute an a
Instruction.

V) Design of Control Unit

To execute instructions, the processor must have some means of generating the control signals needed in
the proper sequence.
There are two approaches for this purpose:

1) Hardwired control
2) Microprogrammed control.

1) Hardwired control
In this method processor can generate the control-signals using step counter and Decoder/Encoder
circuit .

Control sequence for execution of this instruction is as follows

1) PCout, MARin, Read, Select4, Add, Zin

2) Zout, PCin, Yin, WMFC
3) MDRout, IRin
4) R3out, MARin, Read
5) R1out, Yin, WMFC

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6) MDRout, SelectY, Add, Zin
7) Zout, R1in, End.
These are the few examples of Control signals generated by the control unit to execute an
Add (R3),R1 instruction using single bus structure, where each step in this sequence is completed
in one clock cycle.

The below figure shows the Organization of Control unit.

Decoder/Encoder Block is a combinational-circuit that generates required control-outputs

depending on state of all its inputs.

The Required control signals are determined by the following information.

1. Contents of the control step counter

2. contents of the instruction register
3. contents of the external inputs
4. contents of the condition codes

Step-Decoder : provides a separate signal line for each step or time slot in the control sequence.
Instruction Decoder: The output of the instruction decoder consist of a separate line for each machine
instruction .
• It decodes the instruction loaded in the IR.
• If IR is an 8 bit register, then instruction decoder generates 28(256 lines); one for each
instruction.
• It consists of a separate output-lines INS1 through INSm for each machine instruction.
• According to code in the IR, one of the output-lines INS1 through INSm is set to 1, and all
other lines are set to 0.

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Encoder
It gets the input from instruction decoder, step decoder, external inputs and condition codes.
It uses all these inputs to generate individual control-signals: Yin, PCout, Add, End and so on.

For example Zin=T1+T6.ADD+T4.BR

This signal is asserted during time-slot T1 for all instructions during T6 for an Add instruction.
during T4 for unconditional branch instruction.

Separation of the Decoding and Encoding Functions

In this diagram we are using two special type of control signals to control the execution of each
instruction
1) RUN Control Signal
2) RESET Control Signal
When RUN=1, counter is incremented by 1 at the end of every clock cycle. When RUN=0, counter stops
counting.
After execution of each instruction, end signal is generated. End signal resets step counter, Sequence of
operations carried out by this machine is determined by wiring of logic circuits, hence
the name “hardwired”.

Advantage: Can operate at high speed.

Disadvantages:
1) Since no. of instructions/control-lines is often in hundreds, the complexity of control unit
is very high.
2) It is costly and difficult to design.
3) The control unit is inflexible because it is difficult to change the design.

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2) MICROPROGRAMMED CONTROL.
In this method processor can generate the control-signals using Programs which is similar to
machine language programs.

Control sequence for execution of this instruction is as follows

1) PCout, MARin, Read, Select4, Add, Zin

2) Zout, PCin, Yin, WMFC
3) MDRout, IRin
4) R3out, MARin, Read
5) R1out, Yin, WMFC
6) MDRout, SelectY, Add, Zin
7) Zout, R1in, End.

This diagram indicates how we can generate control signals using

microprogrammed method.

Terms Related to micro programmed method:

Control Word(CW): is a word whose individual bits represent various control-signals (like Add,PCin).
Each of the control-steps in control sequence of an instruction defines a unique
combination of 1s & 0s in CW.

Microinstructions: Individual control-words in microroutine are referred to as microinstructions

Microroutine : A sequence of CWs corresponding to control-sequence of a machine instruction

constitutes the microroutine.

control store(CS): The microroutines for all instructions in the instruction-set of a computer are stored in

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 a special memory called the control store(CS)
BASIC ORGANIZATION OF CONTROL UNIT

The control unit can generate the control signals for any instruction by sequentially reading the control
words of the corresponding micro routine from the control store.

Whenever processor wants to execute an instruction, it fetches the instruction from the memory and loads
into Instruction register for the execution and these instruction address is stored into starting address
generator circuit and in turn it is loaded into micro program counter.
Processor uses content of the micro program counter address of the desired instruction and reads the
control words sequentially from the control store .
The content of the micro program counter is incremented automatically by the clock to fetch next
successive micro instruction in the program.

ORGANIZATION OF MICROPROGRAMMED CONTROL UNIT TO SUPPORT

CONDITIONAL BRANCHING

Drawback of previous Microprogram control:

It cannot handle the situation when the control unit is required to check the status of the condition codes
or external inputs to choose between alternative courses of action . i.e it cannot handle Branching
Instruction.

Solution:

Use conditional branch microinstruction. In case of conditional branching, microinstructions specify

which of the external inputs, condition codes should be checked as a condition for branching to take
place.

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To allow implementation of a conditional branch, inputs to this block consist of external inputs and
condition-codes & contents of IR.

μPC is incremented every time a new microinstruction is fetched from microprogram memory except
in following situations:

1) When a new instruction is loaded into IR, μPC is loaded with starting-address of microroutine
for that instruction.

2) When a Branch microinstruction is encountered and branch condition is satisfied, μPC is

loaded with branch-address.

3) When an End microinstruction is encountered, μPC is loaded with address of first CW in

microroutine for instruction fetch cycle.

Drawbacks of microprogrammed control:

1) Assigning individual bits to each control-signal results in long microinstructions because the number
of required signals is usually large.

2) Available bit-space is poorly used because only a few bits are set to 1 in any given microinstruction.

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 Microroutine for the Instruction Branch<0
Processor needs following Control Sequences to execute a instruction Branch<0

HARDWIRED CONTROL VS MICROPROGRAMMED CONTROL

Sl. No. HARDWIRED CONTROL MICROPROGRAMMED CONTROL
1 In this method processor can generate the In this method processor can generate the control-
control-signals using step counter and signals using Programs which is similar to
Decoder/Encoder circuit . machine language programs

2 It is Faster It is slower
3 Control Functions are implemented using Control Functions are implemented using Software
Hardware
4 Difficult to Handle Large or Complex Easy to Handle Large or Complex instruction set
instruction set
5 Not flexible to accommodate new system More flexible to accommodate new system
specifications or new instructions. specifications or new instructions.

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