Power Management and Sleep Modes
Power Management and Sleep Modes
Power Management and Sleep Modes
Table 9-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Timer Oscillator
Source Enabled
SPM/EEPROM
TWI Address
BOD Disable
Pin Change
Main Clock
Software
Enabled
clkFLASH
Other/O
Timer2
Ready
clkADC
Match
clkCPU
clkASY
WDT
ADC
clkIO
Sleep Mode
Idle X X X X X(2) X X X X X X X
ADC noise
X X X X(2) X(3) X X(2) X X X
Reduction
Power-down X(3) X X X
(2) (3)
Power-save X X X X X X X
Standby(1) X X(3) X X X
Extended
X(2) X X(2) X(3) X X X X
Standby
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT1 and INT0, only level interrupt.
To enter any of the six sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be
executed. The SM2, SM1, and SM0 bits in the SMCR register select which sleep mode (idle, ADC noise reduction, power-
down, power-save, standby, or extended standby) will be activated by the SLEEP instruction. See Table 9-2 on page 38 for a
summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles
in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP.
The contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during
sleep mode, the MCU wakes up and executes from the reset vector.
34 ATmega328P [DATASHEET]
7810D–AVR–01/15